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i386: voyager: use __maybe_unused
[linux-2.6/mini2440.git] / sound / pci / maestro3.c
blob4526904e3f86df587fe37eb1ad9783c64c3bef25
1 /*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <sound/driver.h>
35 #include <asm/io.h>
36 #include <linux/delay.h>
37 #include <linux/interrupt.h>
38 #include <linux/init.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/moduleparam.h>
44 #include <linux/firmware.h>
45 #include <sound/core.h>
46 #include <sound/info.h>
47 #include <sound/control.h>
48 #include <sound/pcm.h>
49 #include <sound/mpu401.h>
50 #include <sound/ac97_codec.h>
51 #include <sound/initval.h>
52 #include <asm/byteorder.h>
53
54 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
55 MODULE_DESCRIPTION("ESS Maestro3 PCI");
56 MODULE_LICENSE("GPL");
57 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
58 "{ESS,ES1988},"
59 "{ESS,Allegro PCI},"
60 "{ESS,Allegro-1 PCI},"
61 "{ESS,Canyon3D-2/LE PCI}}");
62
63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
65 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
66 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
67 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
68
69 module_param_array(index, int, NULL, 0444);
70 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
71 module_param_array(id, charp, NULL, 0444);
72 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
73 module_param_array(enable, bool, NULL, 0444);
74 MODULE_PARM_DESC(enable, "Enable this soundcard.");
75 module_param_array(external_amp, bool, NULL, 0444);
76 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
77 module_param_array(amp_gpio, int, NULL, 0444);
78 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
79
80 #define MAX_PLAYBACKS 2
81 #define MAX_CAPTURES 1
82 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
83
84
85 /*
86 * maestro3 registers
87 */
88
89 /* Allegro PCI configuration registers */
90 #define PCI_LEGACY_AUDIO_CTRL 0x40
91 #define SOUND_BLASTER_ENABLE 0x00000001
92 #define FM_SYNTHESIS_ENABLE 0x00000002
93 #define GAME_PORT_ENABLE 0x00000004
94 #define MPU401_IO_ENABLE 0x00000008
95 #define MPU401_IRQ_ENABLE 0x00000010
96 #define ALIAS_10BIT_IO 0x00000020
97 #define SB_DMA_MASK 0x000000C0
98 #define SB_DMA_0 0x00000040
99 #define SB_DMA_1 0x00000040
100 #define SB_DMA_R 0x00000080
101 #define SB_DMA_3 0x000000C0
102 #define SB_IRQ_MASK 0x00000700
103 #define SB_IRQ_5 0x00000000
104 #define SB_IRQ_7 0x00000100
105 #define SB_IRQ_9 0x00000200
106 #define SB_IRQ_10 0x00000300
107 #define MIDI_IRQ_MASK 0x00003800
108 #define SERIAL_IRQ_ENABLE 0x00004000
109 #define DISABLE_LEGACY 0x00008000
110
111 #define PCI_ALLEGRO_CONFIG 0x50
112 #define SB_ADDR_240 0x00000004
113 #define MPU_ADDR_MASK 0x00000018
114 #define MPU_ADDR_330 0x00000000
115 #define MPU_ADDR_300 0x00000008
116 #define MPU_ADDR_320 0x00000010
117 #define MPU_ADDR_340 0x00000018
118 #define USE_PCI_TIMING 0x00000040
119 #define POSTED_WRITE_ENABLE 0x00000080
120 #define DMA_POLICY_MASK 0x00000700
121 #define DMA_DDMA 0x00000000
122 #define DMA_TDMA 0x00000100
123 #define DMA_PCPCI 0x00000200
124 #define DMA_WBDMA16 0x00000400
125 #define DMA_WBDMA4 0x00000500
126 #define DMA_WBDMA2 0x00000600
127 #define DMA_WBDMA1 0x00000700
128 #define DMA_SAFE_GUARD 0x00000800
129 #define HI_PERF_GP_ENABLE 0x00001000
130 #define PIC_SNOOP_MODE_0 0x00002000
131 #define PIC_SNOOP_MODE_1 0x00004000
132 #define SOUNDBLASTER_IRQ_MASK 0x00008000
133 #define RING_IN_ENABLE 0x00010000
134 #define SPDIF_TEST_MODE 0x00020000
135 #define CLK_MULT_MODE_SELECT_2 0x00040000
136 #define EEPROM_WRITE_ENABLE 0x00080000
137 #define CODEC_DIR_IN 0x00100000
138 #define HV_BUTTON_FROM_GD 0x00200000
139 #define REDUCED_DEBOUNCE 0x00400000
140 #define HV_CTRL_ENABLE 0x00800000
141 #define SPDIF_ENABLE 0x01000000
142 #define CLK_DIV_SELECT 0x06000000
143 #define CLK_DIV_BY_48 0x00000000
144 #define CLK_DIV_BY_49 0x02000000
145 #define CLK_DIV_BY_50 0x04000000
146 #define CLK_DIV_RESERVED 0x06000000
147 #define PM_CTRL_ENABLE 0x08000000
148 #define CLK_MULT_MODE_SELECT 0x30000000
149 #define CLK_MULT_MODE_SHIFT 28
150 #define CLK_MULT_MODE_0 0x00000000
151 #define CLK_MULT_MODE_1 0x10000000
152 #define CLK_MULT_MODE_2 0x20000000
153 #define CLK_MULT_MODE_3 0x30000000
154 #define INT_CLK_SELECT 0x40000000
155 #define INT_CLK_MULT_RESET 0x80000000
156
157 /* M3 */
158 #define INT_CLK_SRC_NOT_PCI 0x00100000
159 #define INT_CLK_MULT_ENABLE 0x80000000
160
161 #define PCI_ACPI_CONTROL 0x54
162 #define PCI_ACPI_D0 0x00000000
163 #define PCI_ACPI_D1 0xB4F70000
164 #define PCI_ACPI_D2 0xB4F7B4F7
165
166 #define PCI_USER_CONFIG 0x58
167 #define EXT_PCI_MASTER_ENABLE 0x00000001
168 #define SPDIF_OUT_SELECT 0x00000002
169 #define TEST_PIN_DIR_CTRL 0x00000004
170 #define AC97_CODEC_TEST 0x00000020
171 #define TRI_STATE_BUFFER 0x00000080
172 #define IN_CLK_12MHZ_SELECT 0x00000100
173 #define MULTI_FUNC_DISABLE 0x00000200
174 #define EXT_MASTER_PAIR_SEL 0x00000400
175 #define PCI_MASTER_SUPPORT 0x00000800
176 #define STOP_CLOCK_ENABLE 0x00001000
177 #define EAPD_DRIVE_ENABLE 0x00002000
178 #define REQ_TRI_STATE_ENABLE 0x00004000
179 #define REQ_LOW_ENABLE 0x00008000
180 #define MIDI_1_ENABLE 0x00010000
181 #define MIDI_2_ENABLE 0x00020000
182 #define SB_AUDIO_SYNC 0x00040000
183 #define HV_CTRL_TEST 0x00100000
184 #define SOUNDBLASTER_TEST 0x00400000
185
186 #define PCI_USER_CONFIG_C 0x5C
187
188 #define PCI_DDMA_CTRL 0x60
189 #define DDMA_ENABLE 0x00000001
190
191
192 /* Allegro registers */
193 #define HOST_INT_CTRL 0x18
194 #define SB_INT_ENABLE 0x0001
195 #define MPU401_INT_ENABLE 0x0002
196 #define ASSP_INT_ENABLE 0x0010
197 #define RING_INT_ENABLE 0x0020
198 #define HV_INT_ENABLE 0x0040
199 #define CLKRUN_GEN_ENABLE 0x0100
200 #define HV_CTRL_TO_PME 0x0400
201 #define SOFTWARE_RESET_ENABLE 0x8000
202
203 /*
204 * should be using the above defines, probably.
205 */
206 #define REGB_ENABLE_RESET 0x01
207 #define REGB_STOP_CLOCK 0x10
208
209 #define HOST_INT_STATUS 0x1A
210 #define SB_INT_PENDING 0x01
211 #define MPU401_INT_PENDING 0x02
212 #define ASSP_INT_PENDING 0x10
213 #define RING_INT_PENDING 0x20
214 #define HV_INT_PENDING 0x40
215
216 #define HARDWARE_VOL_CTRL 0x1B
217 #define SHADOW_MIX_REG_VOICE 0x1C
218 #define HW_VOL_COUNTER_VOICE 0x1D
219 #define SHADOW_MIX_REG_MASTER 0x1E
220 #define HW_VOL_COUNTER_MASTER 0x1F
221
222 #define CODEC_COMMAND 0x30
223 #define CODEC_READ_B 0x80
224
225 #define CODEC_STATUS 0x30
226 #define CODEC_BUSY_B 0x01
227
228 #define CODEC_DATA 0x32
229
230 #define RING_BUS_CTRL_A 0x36
231 #define RAC_PME_ENABLE 0x0100
232 #define RAC_SDFS_ENABLE 0x0200
233 #define LAC_PME_ENABLE 0x0400
234 #define LAC_SDFS_ENABLE 0x0800
235 #define SERIAL_AC_LINK_ENABLE 0x1000
236 #define IO_SRAM_ENABLE 0x2000
237 #define IIS_INPUT_ENABLE 0x8000
238
239 #define RING_BUS_CTRL_B 0x38
240 #define SECOND_CODEC_ID_MASK 0x0003
241 #define SPDIF_FUNC_ENABLE 0x0010
242 #define SECOND_AC_ENABLE 0x0020
243 #define SB_MODULE_INTF_ENABLE 0x0040
244 #define SSPE_ENABLE 0x0040
245 #define M3I_DOCK_ENABLE 0x0080
246
247 #define SDO_OUT_DEST_CTRL 0x3A
248 #define COMMAND_ADDR_OUT 0x0003
249 #define PCM_LR_OUT_LOCAL 0x0000
250 #define PCM_LR_OUT_REMOTE 0x0004
251 #define PCM_LR_OUT_MUTE 0x0008
252 #define PCM_LR_OUT_BOTH 0x000C
253 #define LINE1_DAC_OUT_LOCAL 0x0000
254 #define LINE1_DAC_OUT_REMOTE 0x0010
255 #define LINE1_DAC_OUT_MUTE 0x0020
256 #define LINE1_DAC_OUT_BOTH 0x0030
257 #define PCM_CLS_OUT_LOCAL 0x0000
258 #define PCM_CLS_OUT_REMOTE 0x0040
259 #define PCM_CLS_OUT_MUTE 0x0080
260 #define PCM_CLS_OUT_BOTH 0x00C0
261 #define PCM_RLF_OUT_LOCAL 0x0000
262 #define PCM_RLF_OUT_REMOTE 0x0100
263 #define PCM_RLF_OUT_MUTE 0x0200
264 #define PCM_RLF_OUT_BOTH 0x0300
265 #define LINE2_DAC_OUT_LOCAL 0x0000
266 #define LINE2_DAC_OUT_REMOTE 0x0400
267 #define LINE2_DAC_OUT_MUTE 0x0800
268 #define LINE2_DAC_OUT_BOTH 0x0C00
269 #define HANDSET_OUT_LOCAL 0x0000
270 #define HANDSET_OUT_REMOTE 0x1000
271 #define HANDSET_OUT_MUTE 0x2000
272 #define HANDSET_OUT_BOTH 0x3000
273 #define IO_CTRL_OUT_LOCAL 0x0000
274 #define IO_CTRL_OUT_REMOTE 0x4000
275 #define IO_CTRL_OUT_MUTE 0x8000
276 #define IO_CTRL_OUT_BOTH 0xC000
277
278 #define SDO_IN_DEST_CTRL 0x3C
279 #define STATUS_ADDR_IN 0x0003
280 #define PCM_LR_IN_LOCAL 0x0000
281 #define PCM_LR_IN_REMOTE 0x0004
282 #define PCM_LR_RESERVED 0x0008
283 #define PCM_LR_IN_BOTH 0x000C
284 #define LINE1_ADC_IN_LOCAL 0x0000
285 #define LINE1_ADC_IN_REMOTE 0x0010
286 #define LINE1_ADC_IN_MUTE 0x0020
287 #define MIC_ADC_IN_LOCAL 0x0000
288 #define MIC_ADC_IN_REMOTE 0x0040
289 #define MIC_ADC_IN_MUTE 0x0080
290 #define LINE2_DAC_IN_LOCAL 0x0000
291 #define LINE2_DAC_IN_REMOTE 0x0400
292 #define LINE2_DAC_IN_MUTE 0x0800
293 #define HANDSET_IN_LOCAL 0x0000
294 #define HANDSET_IN_REMOTE 0x1000
295 #define HANDSET_IN_MUTE 0x2000
296 #define IO_STATUS_IN_LOCAL 0x0000
297 #define IO_STATUS_IN_REMOTE 0x4000
298
299 #define SPDIF_IN_CTRL 0x3E
300 #define SPDIF_IN_ENABLE 0x0001
301
302 #define GPIO_DATA 0x60
303 #define GPIO_DATA_MASK 0x0FFF
304 #define GPIO_HV_STATUS 0x3000
305 #define GPIO_PME_STATUS 0x4000
306
307 #define GPIO_MASK 0x64
308 #define GPIO_DIRECTION 0x68
309 #define GPO_PRIMARY_AC97 0x0001
310 #define GPI_LINEOUT_SENSE 0x0004
311 #define GPO_SECONDARY_AC97 0x0008
312 #define GPI_VOL_DOWN 0x0010
313 #define GPI_VOL_UP 0x0020
314 #define GPI_IIS_CLK 0x0040
315 #define GPI_IIS_LRCLK 0x0080
316 #define GPI_IIS_DATA 0x0100
317 #define GPI_DOCKING_STATUS 0x0100
318 #define GPI_HEADPHONE_SENSE 0x0200
319 #define GPO_EXT_AMP_SHUTDOWN 0x1000
320
321 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
322 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
323
324 /* M3 */
325 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
326
327 #define ASSP_INDEX_PORT 0x80
328 #define ASSP_MEMORY_PORT 0x82
329 #define ASSP_DATA_PORT 0x84
330
331 #define MPU401_DATA_PORT 0x98
332 #define MPU401_STATUS_PORT 0x99
333
334 #define CLK_MULT_DATA_PORT 0x9C
335
336 #define ASSP_CONTROL_A 0xA2
337 #define ASSP_0_WS_ENABLE 0x01
338 #define ASSP_CTRL_A_RESERVED1 0x02
339 #define ASSP_CTRL_A_RESERVED2 0x04
340 #define ASSP_CLK_49MHZ_SELECT 0x08
341 #define FAST_PLU_ENABLE 0x10
342 #define ASSP_CTRL_A_RESERVED3 0x20
343 #define DSP_CLK_36MHZ_SELECT 0x40
344
345 #define ASSP_CONTROL_B 0xA4
346 #define RESET_ASSP 0x00
347 #define RUN_ASSP 0x01
348 #define ENABLE_ASSP_CLOCK 0x00
349 #define STOP_ASSP_CLOCK 0x10
350 #define RESET_TOGGLE 0x40
351
352 #define ASSP_CONTROL_C 0xA6
353 #define ASSP_HOST_INT_ENABLE 0x01
354 #define FM_ADDR_REMAP_DISABLE 0x02
355 #define HOST_WRITE_PORT_ENABLE 0x08
356
357 #define ASSP_HOST_INT_STATUS 0xAC
358 #define DSP2HOST_REQ_PIORECORD 0x01
359 #define DSP2HOST_REQ_I2SRATE 0x02
360 #define DSP2HOST_REQ_TIMER 0x04
361
362 /* AC97 registers */
363 /* XXX fix this crap up */
364 /*#define AC97_RESET 0x00*/
365
366 #define AC97_VOL_MUTE_B 0x8000
367 #define AC97_VOL_M 0x1F
368 #define AC97_LEFT_VOL_S 8
369
370 #define AC97_MASTER_VOL 0x02
371 #define AC97_LINE_LEVEL_VOL 0x04
372 #define AC97_MASTER_MONO_VOL 0x06
373 #define AC97_PC_BEEP_VOL 0x0A
374 #define AC97_PC_BEEP_VOL_M 0x0F
375 #define AC97_SROUND_MASTER_VOL 0x38
376 #define AC97_PC_BEEP_VOL_S 1
377
378 /*#define AC97_PHONE_VOL 0x0C
379 #define AC97_MIC_VOL 0x0E*/
380 #define AC97_MIC_20DB_ENABLE 0x40
381
382 /*#define AC97_LINEIN_VOL 0x10
383 #define AC97_CD_VOL 0x12
384 #define AC97_VIDEO_VOL 0x14
385 #define AC97_AUX_VOL 0x16*/
386 #define AC97_PCM_OUT_VOL 0x18
387 /*#define AC97_RECORD_SELECT 0x1A*/
388 #define AC97_RECORD_MIC 0x00
389 #define AC97_RECORD_CD 0x01
390 #define AC97_RECORD_VIDEO 0x02
391 #define AC97_RECORD_AUX 0x03
392 #define AC97_RECORD_MONO_MUX 0x02
393 #define AC97_RECORD_DIGITAL 0x03
394 #define AC97_RECORD_LINE 0x04
395 #define AC97_RECORD_STEREO 0x05
396 #define AC97_RECORD_MONO 0x06
397 #define AC97_RECORD_PHONE 0x07
398
399 /*#define AC97_RECORD_GAIN 0x1C*/
400 #define AC97_RECORD_VOL_M 0x0F
401
402 /*#define AC97_GENERAL_PURPOSE 0x20*/
403 #define AC97_POWER_DOWN_CTRL 0x26
404 #define AC97_ADC_READY 0x0001
405 #define AC97_DAC_READY 0x0002
406 #define AC97_ANALOG_READY 0x0004
407 #define AC97_VREF_ON 0x0008
408 #define AC97_PR0 0x0100
409 #define AC97_PR1 0x0200
410 #define AC97_PR2 0x0400
411 #define AC97_PR3 0x0800
412 #define AC97_PR4 0x1000
413
414 #define AC97_RESERVED1 0x28
415
416 #define AC97_VENDOR_TEST 0x5A
417
418 #define AC97_CLOCK_DELAY 0x5C
419 #define AC97_LINEOUT_MUX_SEL 0x0001
420 #define AC97_MONO_MUX_SEL 0x0002
421 #define AC97_CLOCK_DELAY_SEL 0x1F
422 #define AC97_DAC_CDS_SHIFT 6
423 #define AC97_ADC_CDS_SHIFT 11
424
425 #define AC97_MULTI_CHANNEL_SEL 0x74
426
427 /*#define AC97_VENDOR_ID1 0x7C
428 #define AC97_VENDOR_ID2 0x7E*/
429
430 /*
431 * ASSP control regs
432 */
433 #define DSP_PORT_TIMER_COUNT 0x06
434
435 #define DSP_PORT_MEMORY_INDEX 0x80
436
437 #define DSP_PORT_MEMORY_TYPE 0x82
438 #define MEMTYPE_INTERNAL_CODE 0x0002
439 #define MEMTYPE_INTERNAL_DATA 0x0003
440 #define MEMTYPE_MASK 0x0003
441
442 #define DSP_PORT_MEMORY_DATA 0x84
443
444 #define DSP_PORT_CONTROL_REG_A 0xA2
445 #define DSP_PORT_CONTROL_REG_B 0xA4
446 #define DSP_PORT_CONTROL_REG_C 0xA6
447
448 #define REV_A_CODE_MEMORY_BEGIN 0x0000
449 #define REV_A_CODE_MEMORY_END 0x0FFF
450 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
451 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
452
453 #define REV_B_CODE_MEMORY_BEGIN 0x0000
454 #define REV_B_CODE_MEMORY_END 0x0BFF
455 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
456 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
457
458 #define REV_A_DATA_MEMORY_BEGIN 0x1000
459 #define REV_A_DATA_MEMORY_END 0x2FFF
460 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
461 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
462
463 #define REV_B_DATA_MEMORY_BEGIN 0x1000
464 #define REV_B_DATA_MEMORY_END 0x2BFF
465 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
466 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
467
468
469 #define NUM_UNITS_KERNEL_CODE 16
470 #define NUM_UNITS_KERNEL_DATA 2
471
472 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
473 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
474
475 /*
476 * Kernel data layout
477 */
478
479 #define DP_SHIFT_COUNT 7
480
481 #define KDATA_BASE_ADDR 0x1000
482 #define KDATA_BASE_ADDR2 0x1080
483
484 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
485 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
486 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
487 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
488 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
489 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
490 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
491 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
492 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
493
494 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
495 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
496
497 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
498 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
499 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
500 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
501 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
502 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
503 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
504 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
505 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
506 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
507
508 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
509 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
510
511 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
512 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
513
514 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
515 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
516
517 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
518 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
519 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
520
521 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
522 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
523 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
524 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
525 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
526
527 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
528 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
529 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
530
531 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
532 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
533 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
534
535 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
536 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
537 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
538 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
539 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
540 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
541 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
542 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
543 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
544 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
545
546 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
547 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
548 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
549
550 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
551 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
552
553 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
554 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
555 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
556
557 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
558 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
559 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
560 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
561 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
562 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
563
564 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
565 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
566 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
567 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
568 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
569 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
570
571 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
572 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
573 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
574 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
575 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
576 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
577
578 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
579 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
580 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
581 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
582
583 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
584 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
585
586 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
587 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
588
589 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
590 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
591 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
592 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
593 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
594
595 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
596 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
597
598 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
599 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
600 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
601
602 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
603 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
604
605 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
606
607 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
608 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
609 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
610 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
611 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
612 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
613 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
614 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
615 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
616 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
617 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
618 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
619
620 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
621 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
622 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
623 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
624
625 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
626 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
627
628 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
629 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
630 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
631 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
632
633 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
634 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
635 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
636 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
637 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
638
639 /*
640 * second 'segment' (?) reserved for mixer
641 * buffers..
642 */
643
644 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
645 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
646 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
647 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
648 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
649 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
650 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
651 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
652 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
653 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
654 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
655 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
656 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
657 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
658 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
659 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
660
661 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
662 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
663 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
664 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
665 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
666 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
667 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
668 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
669 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
670 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
671 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
672
673 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
674 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
675 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
676 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
677 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
678 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
679
680 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
681 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
682 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
683 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
684
685 /*
686 * client data area offsets
687 */
688 #define CDATA_INSTANCE_READY 0x00
689
690 #define CDATA_HOST_SRC_ADDRL 0x01
691 #define CDATA_HOST_SRC_ADDRH 0x02
692 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
693 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
694 #define CDATA_HOST_SRC_CURRENTL 0x05
695 #define CDATA_HOST_SRC_CURRENTH 0x06
696
697 #define CDATA_IN_BUF_CONNECT 0x07
698 #define CDATA_OUT_BUF_CONNECT 0x08
699
700 #define CDATA_IN_BUF_BEGIN 0x09
701 #define CDATA_IN_BUF_END_PLUS_1 0x0A
702 #define CDATA_IN_BUF_HEAD 0x0B
703 #define CDATA_IN_BUF_TAIL 0x0C
704 #define CDATA_OUT_BUF_BEGIN 0x0D
705 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
706 #define CDATA_OUT_BUF_HEAD 0x0F
707 #define CDATA_OUT_BUF_TAIL 0x10
708
709 #define CDATA_DMA_CONTROL 0x11
710 #define CDATA_RESERVED 0x12
711
712 #define CDATA_FREQUENCY 0x13
713 #define CDATA_LEFT_VOLUME 0x14
714 #define CDATA_RIGHT_VOLUME 0x15
715 #define CDATA_LEFT_SUR_VOL 0x16
716 #define CDATA_RIGHT_SUR_VOL 0x17
717
718 #define CDATA_HEADER_LEN 0x18
719
720 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
721 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
722 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
723 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
724 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
725 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
726 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
727 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
728
729 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
730 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
731 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
732 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
733 #define MINISRC_BIQUAD_STAGE 2
734 #define MINISRC_COEF_LOC 0x175
735
736 #define DMACONTROL_BLOCK_MASK 0x000F
737 #define DMAC_BLOCK0_SELECTOR 0x0000
738 #define DMAC_BLOCK1_SELECTOR 0x0001
739 #define DMAC_BLOCK2_SELECTOR 0x0002
740 #define DMAC_BLOCK3_SELECTOR 0x0003
741 #define DMAC_BLOCK4_SELECTOR 0x0004
742 #define DMAC_BLOCK5_SELECTOR 0x0005
743 #define DMAC_BLOCK6_SELECTOR 0x0006
744 #define DMAC_BLOCK7_SELECTOR 0x0007
745 #define DMAC_BLOCK8_SELECTOR 0x0008
746 #define DMAC_BLOCK9_SELECTOR 0x0009
747 #define DMAC_BLOCKA_SELECTOR 0x000A
748 #define DMAC_BLOCKB_SELECTOR 0x000B
749 #define DMAC_BLOCKC_SELECTOR 0x000C
750 #define DMAC_BLOCKD_SELECTOR 0x000D
751 #define DMAC_BLOCKE_SELECTOR 0x000E
752 #define DMAC_BLOCKF_SELECTOR 0x000F
753 #define DMACONTROL_PAGE_MASK 0x00F0
754 #define DMAC_PAGE0_SELECTOR 0x0030
755 #define DMAC_PAGE1_SELECTOR 0x0020
756 #define DMAC_PAGE2_SELECTOR 0x0010
757 #define DMAC_PAGE3_SELECTOR 0x0000
758 #define DMACONTROL_AUTOREPEAT 0x1000
759 #define DMACONTROL_STOPPED 0x2000
760 #define DMACONTROL_DIRECTION 0x0100
761
762 /*
763 * an arbitrary volume we set the internal
764 * volume settings to so that the ac97 volume
765 * range is a little less insane. 0x7fff is
766 * max.
767 */
768 #define ARB_VOLUME ( 0x6800 )
769
770 /*
771 */
772
773 struct m3_list {
774 int curlen;
775 int mem_addr;
776 int max;
777 };
778
779 struct m3_dma {
780
781 int number;
782 struct snd_pcm_substream *substream;
783
784 struct assp_instance {
785 unsigned short code, data;
786 } inst;
787
788 int running;
789 int opened;
790
791 unsigned long buffer_addr;
792 int dma_size;
793 int period_size;
794 unsigned int hwptr;
795 int count;
796
797 int index[3];
798 struct m3_list *index_list[3];
799
800 int in_lists;
801
802 struct list_head list;
803
804 };
805
806 struct snd_m3 {
807
808 struct snd_card *card;
809
810 unsigned long iobase;
811
812 int irq;
813 unsigned int allegro_flag : 1;
814
815 struct snd_ac97 *ac97;
816
817 struct snd_pcm *pcm;
818
819 struct pci_dev *pci;
820
821 int dacs_active;
822 int timer_users;
823
824 struct m3_list msrc_list;
825 struct m3_list mixer_list;
826 struct m3_list adc1_list;
827 struct m3_list dma_list;
828
829 /* for storing reset state..*/
830 u8 reset_state;
831
832 int external_amp;
833 int amp_gpio; /* gpio pin # for external amp, -1 = default */
834 unsigned int hv_config; /* hardware-volume config bits */
835 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
836 (e.g. for IrDA on Dell Inspirons) */
837 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
838
839 /* midi */
840 struct snd_rawmidi *rmidi;
841
842 /* pcm streams */
843 int num_substreams;
844 struct m3_dma *substreams;
845
846 spinlock_t reg_lock;
847 spinlock_t ac97_lock;
848
849 struct snd_kcontrol *master_switch;
850 struct snd_kcontrol *master_volume;
851 struct tasklet_struct hwvol_tq;
852
853 #ifdef CONFIG_PM
854 u16 *suspend_mem;
855 #endif
856
857 const struct firmware *assp_kernel_image;
858 const struct firmware *assp_minisrc_image;
859 };
860
861 /*
862 * pci ids
863 */
864 static struct pci_device_id snd_m3_ids[] = {
865 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
866 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
867 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
868 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
869 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
870 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
871 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
872 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
873 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
874 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
875 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
876 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
877 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
878 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
879 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
880 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
881 {0,},
882 };
883
884 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
885
886 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
887 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
888 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
889 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
890 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
891 { } /* END */
892 };
893
894 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
895 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
896 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
897 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
898 { } /* END */
899 };
900
901 /* hardware volume quirks */
902 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
903 /* Allegro chips */
904 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
905 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
906 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
907 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
908 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
930 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
931 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
932 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
933 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
934 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
935 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
936 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
937 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
938 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
940 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
942 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
944 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
946 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
948 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
950 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
952 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
954 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
955 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
956 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
957 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
958 /* Maestro3 chips */
959 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
960 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
961 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
962 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
963 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
966 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
967 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
973 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
974 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
975 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
976 { } /* END */
977 };
978
979 /* HP Omnibook quirks */
980 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
981 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
982 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
983 { } /* END */
984 };
985
986 /*
987 * lowlevel functions
988 */
989
990 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
991 {
992 outw(value, chip->iobase + reg);
993 }
994
995 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
996 {
997 return inw(chip->iobase + reg);
998 }
999
1000 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1001 {
1002 outb(value, chip->iobase + reg);
1003 }
1004
1005 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1006 {
1007 return inb(chip->iobase + reg);
1008 }
1009
1010 /*
1011 * access 16bit words to the code or data regions of the dsp's memory.
1012 * index addresses 16bit words.
1013 */
1014 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1015 {
1016 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1017 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1018 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1019 }
1020
1021 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1022 {
1023 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1024 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1025 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1026 }
1027
1028 static void snd_m3_assp_halt(struct snd_m3 *chip)
1029 {
1030 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1031 msleep(10);
1032 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1033 }
1034
1035 static void snd_m3_assp_continue(struct snd_m3 *chip)
1036 {
1037 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1038 }
1039
1040
1041 /*
1042 * This makes me sad. the maestro3 has lists
1043 * internally that must be packed.. 0 terminates,
1044 * apparently, or maybe all unused entries have
1045 * to be 0, the lists have static lengths set
1046 * by the binary code images.
1047 */
1048
1049 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1050 {
1051 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1052 list->mem_addr + list->curlen,
1053 val);
1054 return list->curlen++;
1055 }
1056
1057 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1058 {
1059 u16 val;
1060 int lastindex = list->curlen - 1;
1061
1062 if (index != lastindex) {
1063 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1064 list->mem_addr + lastindex);
1065 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1066 list->mem_addr + index,
1067 val);
1068 }
1069
1070 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1071 list->mem_addr + lastindex,
1072 0);
1073
1074 list->curlen--;
1075 }
1076
1077 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1078 {
1079 chip->timer_users++;
1080 if (chip->timer_users != 1)
1081 return;
1082
1083 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084 KDATA_TIMER_COUNT_RELOAD,
1085 240);
1086
1087 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1088 KDATA_TIMER_COUNT_CURRENT,
1089 240);
1090
1091 snd_m3_outw(chip,
1092 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1093 HOST_INT_CTRL);
1094 }
1095
1096 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1097 {
1098 chip->timer_users--;
1099 if (chip->timer_users > 0)
1100 return;
1101
1102 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1103 KDATA_TIMER_COUNT_RELOAD,
1104 0);
1105
1106 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1107 KDATA_TIMER_COUNT_CURRENT,
1108 0);
1109
1110 snd_m3_outw(chip,
1111 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1112 HOST_INT_CTRL);
1113 }
1114
1115 /*
1116 * start/stop
1117 */
1118
1119 /* spinlock held! */
1120 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1121 struct snd_pcm_substream *subs)
1122 {
1123 if (! s || ! subs)
1124 return -EINVAL;
1125
1126 snd_m3_inc_timer_users(chip);
1127 switch (subs->stream) {
1128 case SNDRV_PCM_STREAM_PLAYBACK:
1129 chip->dacs_active++;
1130 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1131 s->inst.data + CDATA_INSTANCE_READY, 1);
1132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1133 KDATA_MIXER_TASK_NUMBER,
1134 chip->dacs_active);
1135 break;
1136 case SNDRV_PCM_STREAM_CAPTURE:
1137 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1138 KDATA_ADC1_REQUEST, 1);
1139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1140 s->inst.data + CDATA_INSTANCE_READY, 1);
1141 break;
1142 }
1143 return 0;
1144 }
1145
1146 /* spinlock held! */
1147 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1148 struct snd_pcm_substream *subs)
1149 {
1150 if (! s || ! subs)
1151 return -EINVAL;
1152
1153 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1154 s->inst.data + CDATA_INSTANCE_READY, 0);
1155 snd_m3_dec_timer_users(chip);
1156 switch (subs->stream) {
1157 case SNDRV_PCM_STREAM_PLAYBACK:
1158 chip->dacs_active--;
1159 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1160 KDATA_MIXER_TASK_NUMBER,
1161 chip->dacs_active);
1162 break;
1163 case SNDRV_PCM_STREAM_CAPTURE:
1164 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1165 KDATA_ADC1_REQUEST, 0);
1166 break;
1167 }
1168 return 0;
1169 }
1170
1171 static int
1172 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1173 {
1174 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1175 struct m3_dma *s = subs->runtime->private_data;
1176 int err = -EINVAL;
1177
1178 snd_assert(s != NULL, return -ENXIO);
1179
1180 spin_lock(&chip->reg_lock);
1181 switch (cmd) {
1182 case SNDRV_PCM_TRIGGER_START:
1183 case SNDRV_PCM_TRIGGER_RESUME:
1184 if (s->running)
1185 err = -EBUSY;
1186 else {
1187 s->running = 1;
1188 err = snd_m3_pcm_start(chip, s, subs);
1189 }
1190 break;
1191 case SNDRV_PCM_TRIGGER_STOP:
1192 case SNDRV_PCM_TRIGGER_SUSPEND:
1193 if (! s->running)
1194 err = 0; /* should return error? */
1195 else {
1196 s->running = 0;
1197 err = snd_m3_pcm_stop(chip, s, subs);
1198 }
1199 break;
1200 }
1201 spin_unlock(&chip->reg_lock);
1202 return err;
1203 }
1204
1205 /*
1206 * setup
1207 */
1208 static void
1209 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1210 {
1211 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1212 struct snd_pcm_runtime *runtime = subs->runtime;
1213
1214 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1215 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1216 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1217 } else {
1218 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1219 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1220 }
1221 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1222 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1223
1224 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1225 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1226 s->hwptr = 0;
1227 s->count = 0;
1228
1229 #define LO(x) ((x) & 0xffff)
1230 #define HI(x) LO((x) >> 16)
1231
1232 /* host dma buffer pointers */
1233 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1234 s->inst.data + CDATA_HOST_SRC_ADDRL,
1235 LO(s->buffer_addr));
1236
1237 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1238 s->inst.data + CDATA_HOST_SRC_ADDRH,
1239 HI(s->buffer_addr));
1240
1241 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1242 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1243 LO(s->buffer_addr + s->dma_size));
1244
1245 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1246 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1247 HI(s->buffer_addr + s->dma_size));
1248
1249 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1250 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1251 LO(s->buffer_addr));
1252
1253 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1254 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1255 HI(s->buffer_addr));
1256 #undef LO
1257 #undef HI
1258
1259 /* dsp buffers */
1260
1261 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1262 s->inst.data + CDATA_IN_BUF_BEGIN,
1263 dsp_in_buffer);
1264
1265 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1266 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1267 dsp_in_buffer + (dsp_in_size / 2));
1268
1269 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1270 s->inst.data + CDATA_IN_BUF_HEAD,
1271 dsp_in_buffer);
1272
1273 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1274 s->inst.data + CDATA_IN_BUF_TAIL,
1275 dsp_in_buffer);
1276
1277 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1278 s->inst.data + CDATA_OUT_BUF_BEGIN,
1279 dsp_out_buffer);
1280
1281 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1282 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1283 dsp_out_buffer + (dsp_out_size / 2));
1284
1285 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1286 s->inst.data + CDATA_OUT_BUF_HEAD,
1287 dsp_out_buffer);
1288
1289 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1290 s->inst.data + CDATA_OUT_BUF_TAIL,
1291 dsp_out_buffer);
1292 }
1293
1294 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1295 struct snd_pcm_runtime *runtime)
1296 {
1297 u32 freq;
1298
1299 /*
1300 * put us in the lists if we're not already there
1301 */
1302 if (! s->in_lists) {
1303 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1304 s->inst.data >> DP_SHIFT_COUNT);
1305 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1306 s->inst.data >> DP_SHIFT_COUNT);
1307 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1308 s->inst.data >> DP_SHIFT_COUNT);
1309 s->in_lists = 1;
1310 }
1311
1312 /* write to 'mono' word */
1313 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1314 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1315 runtime->channels == 2 ? 0 : 1);
1316 /* write to '8bit' word */
1317 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1319 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1320
1321 /* set up dac/adc rate */
1322 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1323 if (freq)
1324 freq--;
1325
1326 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1327 s->inst.data + CDATA_FREQUENCY,
1328 freq);
1329 }
1330
1331
1332 static const struct play_vals {
1333 u16 addr, val;
1334 } pv[] = {
1335 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1336 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1337 {SRC3_DIRECTION_OFFSET, 0} ,
1338 /* +1, +2 are stereo/16 bit */
1339 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1340 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1341 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1342 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1343 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1344 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1345 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1346 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1347 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1348 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1349 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1350 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1351 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1352 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1353 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1354 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1355 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1356 };
1357
1358
1359 /* the mode passed should be already shifted and masked */
1360 static void
1361 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1362 struct snd_pcm_substream *subs)
1363 {
1364 unsigned int i;
1365
1366 /*
1367 * some per client initializers
1368 */
1369
1370 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1371 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1372 s->inst.data + 40 + 8);
1373
1374 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1375 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1376 s->inst.code + MINISRC_COEF_LOC);
1377
1378 /* enable or disable low pass filter? */
1379 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1380 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1381 subs->runtime->rate > 45000 ? 0xff : 0);
1382
1383 /* tell it which way dma is going? */
1384 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1385 s->inst.data + CDATA_DMA_CONTROL,
1386 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1387
1388 /*
1389 * set an armload of static initializers
1390 */
1391 for (i = 0; i < ARRAY_SIZE(pv); i++)
1392 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1393 s->inst.data + pv[i].addr, pv[i].val);
1394 }
1395
1396 /*
1397 * Native record driver
1398 */
1399 static const struct rec_vals {
1400 u16 addr, val;
1401 } rv[] = {
1402 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1403 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1404 {SRC3_DIRECTION_OFFSET, 1} ,
1405 /* +1, +2 are stereo/16 bit */
1406 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1407 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1408 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1409 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1410 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1411 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1412 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1413 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1414 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1415 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1416 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1417 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1418 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1419 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1420 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1421 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1422 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1423 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1424 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1425 };
1426
1427 static void
1428 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1429 {
1430 unsigned int i;
1431
1432 /*
1433 * some per client initializers
1434 */
1435
1436 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1437 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1438 s->inst.data + 40 + 8);
1439
1440 /* tell it which way dma is going? */
1441 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1442 s->inst.data + CDATA_DMA_CONTROL,
1443 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1444 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1445
1446 /*
1447 * set an armload of static initializers
1448 */
1449 for (i = 0; i < ARRAY_SIZE(rv); i++)
1450 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1451 s->inst.data + rv[i].addr, rv[i].val);
1452 }
1453
1454 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1455 struct snd_pcm_hw_params *hw_params)
1456 {
1457 struct m3_dma *s = substream->runtime->private_data;
1458 int err;
1459
1460 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1461 return err;
1462 /* set buffer address */
1463 s->buffer_addr = substream->runtime->dma_addr;
1464 if (s->buffer_addr & 0x3) {
1465 snd_printk(KERN_ERR "oh my, not aligned\n");
1466 s->buffer_addr = s->buffer_addr & ~0x3;
1467 }
1468 return 0;
1469 }
1470
1471 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1472 {
1473 struct m3_dma *s;
1474
1475 if (substream->runtime->private_data == NULL)
1476 return 0;
1477 s = substream->runtime->private_data;
1478 snd_pcm_lib_free_pages(substream);
1479 s->buffer_addr = 0;
1480 return 0;
1481 }
1482
1483 static int
1484 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1485 {
1486 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1487 struct snd_pcm_runtime *runtime = subs->runtime;
1488 struct m3_dma *s = runtime->private_data;
1489
1490 snd_assert(s != NULL, return -ENXIO);
1491
1492 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1493 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1494 return -EINVAL;
1495 if (runtime->rate > 48000 ||
1496 runtime->rate < 8000)
1497 return -EINVAL;
1498
1499 spin_lock_irq(&chip->reg_lock);
1500
1501 snd_m3_pcm_setup1(chip, s, subs);
1502
1503 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1504 snd_m3_playback_setup(chip, s, subs);
1505 else
1506 snd_m3_capture_setup(chip, s, subs);
1507
1508 snd_m3_pcm_setup2(chip, s, runtime);
1509
1510 spin_unlock_irq(&chip->reg_lock);
1511
1512 return 0;
1513 }
1514
1515 /*
1516 * get current pointer
1517 */
1518 static unsigned int
1519 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1520 {
1521 u16 hi = 0, lo = 0;
1522 int retry = 10;
1523 u32 addr;
1524
1525 /*
1526 * try and get a valid answer
1527 */
1528 while (retry--) {
1529 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1530 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1531
1532 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1533 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1534
1535 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1536 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1537 break;
1538 }
1539 addr = lo | ((u32)hi<<16);
1540 return (unsigned int)(addr - s->buffer_addr);
1541 }
1542
1543 static snd_pcm_uframes_t
1544 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1545 {
1546 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1547 unsigned int ptr;
1548 struct m3_dma *s = subs->runtime->private_data;
1549 snd_assert(s != NULL, return 0);
1550
1551 spin_lock(&chip->reg_lock);
1552 ptr = snd_m3_get_pointer(chip, s, subs);
1553 spin_unlock(&chip->reg_lock);
1554 return bytes_to_frames(subs->runtime, ptr);
1555 }
1556
1557
1558 /* update pointer */
1559 /* spinlock held! */
1560 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1561 {
1562 struct snd_pcm_substream *subs = s->substream;
1563 unsigned int hwptr;
1564 int diff;
1565
1566 if (! s->running)
1567 return;
1568
1569 hwptr = snd_m3_get_pointer(chip, s, subs);
1570
1571 /* try to avoid expensive modulo divisions */
1572 if (hwptr >= s->dma_size)
1573 hwptr %= s->dma_size;
1574
1575 diff = s->dma_size + hwptr - s->hwptr;
1576 if (diff >= s->dma_size)
1577 diff %= s->dma_size;
1578
1579 s->hwptr = hwptr;
1580 s->count += diff;
1581
1582 if (s->count >= (signed)s->period_size) {
1583
1584 if (s->count < 2 * (signed)s->period_size)
1585 s->count -= (signed)s->period_size;
1586 else
1587 s->count %= s->period_size;
1588
1589 spin_unlock(&chip->reg_lock);
1590 snd_pcm_period_elapsed(subs);
1591 spin_lock(&chip->reg_lock);
1592 }
1593 }
1594
1595 static void snd_m3_update_hw_volume(unsigned long private_data)
1596 {
1597 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1598 int x, val;
1599 unsigned long flags;
1600
1601 /* Figure out which volume control button was pushed,
1602 based on differences from the default register
1603 values. */
1604 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1605
1606 /* Reset the volume control registers. */
1607 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1608 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1609 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1610 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1611
1612 if (!chip->master_switch || !chip->master_volume)
1613 return;
1614
1615 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1616 spin_lock_irqsave(&chip->ac97_lock, flags);
1617
1618 val = chip->ac97->regs[AC97_MASTER_VOL];
1619 switch (x) {
1620 case 0x88:
1621 /* mute */
1622 val ^= 0x8000;
1623 chip->ac97->regs[AC97_MASTER_VOL] = val;
1624 outw(val, chip->iobase + CODEC_DATA);
1625 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1626 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1627 &chip->master_switch->id);
1628 break;
1629 case 0xaa:
1630 /* volume up */
1631 if ((val & 0x7f) > 0)
1632 val--;
1633 if ((val & 0x7f00) > 0)
1634 val -= 0x0100;
1635 chip->ac97->regs[AC97_MASTER_VOL] = val;
1636 outw(val, chip->iobase + CODEC_DATA);
1637 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1638 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1639 &chip->master_volume->id);
1640 break;
1641 case 0x66:
1642 /* volume down */
1643 if ((val & 0x7f) < 0x1f)
1644 val++;
1645 if ((val & 0x7f00) < 0x1f00)
1646 val += 0x0100;
1647 chip->ac97->regs[AC97_MASTER_VOL] = val;
1648 outw(val, chip->iobase + CODEC_DATA);
1649 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1650 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1651 &chip->master_volume->id);
1652 break;
1653 }
1654 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1655 }
1656
1657 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1658 {
1659 struct snd_m3 *chip = dev_id;
1660 u8 status;
1661 int i;
1662
1663 status = inb(chip->iobase + HOST_INT_STATUS);
1664
1665 if (status == 0xff)
1666 return IRQ_NONE;
1667
1668 if (status & HV_INT_PENDING)
1669 tasklet_hi_schedule(&chip->hwvol_tq);
1670
1671 /*
1672 * ack an assp int if its running
1673 * and has an int pending
1674 */
1675 if (status & ASSP_INT_PENDING) {
1676 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1677 if (!(ctl & STOP_ASSP_CLOCK)) {
1678 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1679 if (ctl & DSP2HOST_REQ_TIMER) {
1680 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1681 /* update adc/dac info if it was a timer int */
1682 spin_lock(&chip->reg_lock);
1683 for (i = 0; i < chip->num_substreams; i++) {
1684 struct m3_dma *s = &chip->substreams[i];
1685 if (s->running)
1686 snd_m3_update_ptr(chip, s);
1687 }
1688 spin_unlock(&chip->reg_lock);
1689 }
1690 }
1691 }
1692
1693 #if 0 /* TODO: not supported yet */
1694 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1695 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1696 #endif
1697
1698 /* ack ints */
1699 outb(status, chip->iobase + HOST_INT_STATUS);
1700
1701 return IRQ_HANDLED;
1702 }
1703
1704
1705 /*
1706 */
1707
1708 static struct snd_pcm_hardware snd_m3_playback =
1709 {
1710 .info = (SNDRV_PCM_INFO_MMAP |
1711 SNDRV_PCM_INFO_INTERLEAVED |
1712 SNDRV_PCM_INFO_MMAP_VALID |
1713 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1714 /*SNDRV_PCM_INFO_PAUSE |*/
1715 SNDRV_PCM_INFO_RESUME),
1716 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1717 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1718 .rate_min = 8000,
1719 .rate_max = 48000,
1720 .channels_min = 1,
1721 .channels_max = 2,
1722 .buffer_bytes_max = (512*1024),
1723 .period_bytes_min = 64,
1724 .period_bytes_max = (512*1024),
1725 .periods_min = 1,
1726 .periods_max = 1024,
1727 };
1728
1729 static struct snd_pcm_hardware snd_m3_capture =
1730 {
1731 .info = (SNDRV_PCM_INFO_MMAP |
1732 SNDRV_PCM_INFO_INTERLEAVED |
1733 SNDRV_PCM_INFO_MMAP_VALID |
1734 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1735 /*SNDRV_PCM_INFO_PAUSE |*/
1736 SNDRV_PCM_INFO_RESUME),
1737 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1738 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1739 .rate_min = 8000,
1740 .rate_max = 48000,
1741 .channels_min = 1,
1742 .channels_max = 2,
1743 .buffer_bytes_max = (512*1024),
1744 .period_bytes_min = 64,
1745 .period_bytes_max = (512*1024),
1746 .periods_min = 1,
1747 .periods_max = 1024,
1748 };
1749
1750
1751 /*
1752 */
1753
1754 static int
1755 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1756 {
1757 int i;
1758 struct m3_dma *s;
1759
1760 spin_lock_irq(&chip->reg_lock);
1761 for (i = 0; i < chip->num_substreams; i++) {
1762 s = &chip->substreams[i];
1763 if (! s->opened)
1764 goto __found;
1765 }
1766 spin_unlock_irq(&chip->reg_lock);
1767 return -ENOMEM;
1768 __found:
1769 s->opened = 1;
1770 s->running = 0;
1771 spin_unlock_irq(&chip->reg_lock);
1772
1773 subs->runtime->private_data = s;
1774 s->substream = subs;
1775
1776 /* set list owners */
1777 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1778 s->index_list[0] = &chip->mixer_list;
1779 } else
1780 s->index_list[0] = &chip->adc1_list;
1781 s->index_list[1] = &chip->msrc_list;
1782 s->index_list[2] = &chip->dma_list;
1783
1784 return 0;
1785 }
1786
1787 static void
1788 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1789 {
1790 struct m3_dma *s = subs->runtime->private_data;
1791
1792 if (s == NULL)
1793 return; /* not opened properly */
1794
1795 spin_lock_irq(&chip->reg_lock);
1796 if (s->substream && s->running)
1797 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1798 if (s->in_lists) {
1799 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1800 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1801 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1802 s->in_lists = 0;
1803 }
1804 s->running = 0;
1805 s->opened = 0;
1806 spin_unlock_irq(&chip->reg_lock);
1807 }
1808
1809 static int
1810 snd_m3_playback_open(struct snd_pcm_substream *subs)
1811 {
1812 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1813 struct snd_pcm_runtime *runtime = subs->runtime;
1814 int err;
1815
1816 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1817 return err;
1818
1819 runtime->hw = snd_m3_playback;
1820 snd_pcm_set_sync(subs);
1821
1822 return 0;
1823 }
1824
1825 static int
1826 snd_m3_playback_close(struct snd_pcm_substream *subs)
1827 {
1828 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1829
1830 snd_m3_substream_close(chip, subs);
1831 return 0;
1832 }
1833
1834 static int
1835 snd_m3_capture_open(struct snd_pcm_substream *subs)
1836 {
1837 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1838 struct snd_pcm_runtime *runtime = subs->runtime;
1839 int err;
1840
1841 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1842 return err;
1843
1844 runtime->hw = snd_m3_capture;
1845 snd_pcm_set_sync(subs);
1846
1847 return 0;
1848 }
1849
1850 static int
1851 snd_m3_capture_close(struct snd_pcm_substream *subs)
1852 {
1853 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1854
1855 snd_m3_substream_close(chip, subs);
1856 return 0;
1857 }
1858
1859 /*
1860 * create pcm instance
1861 */
1862
1863 static struct snd_pcm_ops snd_m3_playback_ops = {
1864 .open = snd_m3_playback_open,
1865 .close = snd_m3_playback_close,
1866 .ioctl = snd_pcm_lib_ioctl,
1867 .hw_params = snd_m3_pcm_hw_params,
1868 .hw_free = snd_m3_pcm_hw_free,
1869 .prepare = snd_m3_pcm_prepare,
1870 .trigger = snd_m3_pcm_trigger,
1871 .pointer = snd_m3_pcm_pointer,
1872 };
1873
1874 static struct snd_pcm_ops snd_m3_capture_ops = {
1875 .open = snd_m3_capture_open,
1876 .close = snd_m3_capture_close,
1877 .ioctl = snd_pcm_lib_ioctl,
1878 .hw_params = snd_m3_pcm_hw_params,
1879 .hw_free = snd_m3_pcm_hw_free,
1880 .prepare = snd_m3_pcm_prepare,
1881 .trigger = snd_m3_pcm_trigger,
1882 .pointer = snd_m3_pcm_pointer,
1883 };
1884
1885 static int __devinit
1886 snd_m3_pcm(struct snd_m3 * chip, int device)
1887 {
1888 struct snd_pcm *pcm;
1889 int err;
1890
1891 err = snd_pcm_new(chip->card, chip->card->driver, device,
1892 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1893 if (err < 0)
1894 return err;
1895
1896 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1897 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1898
1899 pcm->private_data = chip;
1900 pcm->info_flags = 0;
1901 strcpy(pcm->name, chip->card->driver);
1902 chip->pcm = pcm;
1903
1904 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1905 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1906
1907 return 0;
1908 }
1909
1910
1911 /*
1912 * ac97 interface
1913 */
1914
1915 /*
1916 * Wait for the ac97 serial bus to be free.
1917 * return nonzero if the bus is still busy.
1918 */
1919 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1920 {
1921 int i = 10000;
1922
1923 do {
1924 if (! (snd_m3_inb(chip, 0x30) & 1))
1925 return 0;
1926 cpu_relax();
1927 } while (i-- > 0);
1928
1929 snd_printk(KERN_ERR "ac97 serial bus busy\n");
1930 return 1;
1931 }
1932
1933 static unsigned short
1934 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1935 {
1936 struct snd_m3 *chip = ac97->private_data;
1937 unsigned long flags;
1938 unsigned short data = 0xffff;
1939
1940 if (snd_m3_ac97_wait(chip))
1941 goto fail;
1942 spin_lock_irqsave(&chip->ac97_lock, flags);
1943 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1944 if (snd_m3_ac97_wait(chip))
1945 goto fail_unlock;
1946 data = snd_m3_inw(chip, CODEC_DATA);
1947 fail_unlock:
1948 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1949 fail:
1950 return data;
1951 }
1952
1953 static void
1954 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1955 {
1956 struct snd_m3 *chip = ac97->private_data;
1957 unsigned long flags;
1958
1959 if (snd_m3_ac97_wait(chip))
1960 return;
1961 spin_lock_irqsave(&chip->ac97_lock, flags);
1962 snd_m3_outw(chip, val, CODEC_DATA);
1963 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1964 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1965 }
1966
1967
1968 static void snd_m3_remote_codec_config(int io, int isremote)
1969 {
1970 isremote = isremote ? 1 : 0;
1971
1972 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1973 io + RING_BUS_CTRL_B);
1974 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1975 io + SDO_OUT_DEST_CTRL);
1976 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1977 io + SDO_IN_DEST_CTRL);
1978 }
1979
1980 /*
1981 * hack, returns non zero on err
1982 */
1983 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1984 {
1985 u16 ret;
1986
1987 if (snd_m3_ac97_wait(chip))
1988 return 1;
1989
1990 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1991
1992 if (snd_m3_ac97_wait(chip))
1993 return 1;
1994
1995 ret = snd_m3_inw(chip, 0x32);
1996
1997 return (ret == 0) || (ret == 0xffff);
1998 }
1999
2000 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2001 {
2002 u16 dir;
2003 int delay1 = 0, delay2 = 0, i;
2004 int io = chip->iobase;
2005
2006 if (chip->allegro_flag) {
2007 /*
2008 * the onboard codec on the allegro seems
2009 * to want to wait a very long time before
2010 * coming back to life
2011 */
2012 delay1 = 50;
2013 delay2 = 800;
2014 } else {
2015 /* maestro3 */
2016 delay1 = 20;
2017 delay2 = 500;
2018 }
2019
2020 for (i = 0; i < 5; i++) {
2021 dir = inw(io + GPIO_DIRECTION);
2022 if (!chip->irda_workaround)
2023 dir |= 0x10; /* assuming pci bus master? */
2024
2025 snd_m3_remote_codec_config(io, 0);
2026
2027 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2028 udelay(20);
2029
2030 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2031 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2032 outw(0, io + GPIO_DATA);
2033 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2034
2035 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2036
2037 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2038 udelay(5);
2039 /* ok, bring back the ac-link */
2040 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2041 outw(~0, io + GPIO_MASK);
2042
2043 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2044
2045 if (! snd_m3_try_read_vendor(chip))
2046 break;
2047
2048 delay1 += 10;
2049 delay2 += 100;
2050
2051 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2052 delay1, delay2);
2053 }
2054
2055 #if 0
2056 /* more gung-ho reset that doesn't
2057 * seem to work anywhere :)
2058 */
2059 tmp = inw(io + RING_BUS_CTRL_A);
2060 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2061 msleep(20);
2062 outw(tmp, io + RING_BUS_CTRL_A);
2063 msleep(50);
2064 #endif
2065 }
2066
2067 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2068 {
2069 struct snd_ac97_bus *pbus;
2070 struct snd_ac97_template ac97;
2071 struct snd_ctl_elem_id id;
2072 int err;
2073 static struct snd_ac97_bus_ops ops = {
2074 .write = snd_m3_ac97_write,
2075 .read = snd_m3_ac97_read,
2076 };
2077
2078 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2079 return err;
2080
2081 memset(&ac97, 0, sizeof(ac97));
2082 ac97.private_data = chip;
2083 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2084 return err;
2085
2086 /* seems ac97 PCM needs initialization.. hack hack.. */
2087 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2088 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2089 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2090
2091 memset(&id, 0, sizeof(id));
2092 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2093 strcpy(id.name, "Master Playback Switch");
2094 chip->master_switch = snd_ctl_find_id(chip->card, &id);
2095 memset(&id, 0, sizeof(id));
2096 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2097 strcpy(id.name, "Master Playback Volume");
2098 chip->master_volume = snd_ctl_find_id(chip->card, &id);
2099
2100 return 0;
2101 }
2102
2103
2104 #define FIRMWARE_IN_THE_KERNEL
2105
2106 #ifdef FIRMWARE_IN_THE_KERNEL
2107
2108 /*
2109 * DSP Code images
2110 */
2111
2112 static const u16 assp_kernel_image[] = {
2113 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2114 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2115 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2116 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2117 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2118 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2119 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2120 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2121 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2122 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2123 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2124 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2125 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2126 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2127 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2128 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2129 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2130 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2131 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2132 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2133 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2134 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2135 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2136 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2137 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2138 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2139 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2140 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2141 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2142 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2143 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2144 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2145 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2146 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2147 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2148 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2149 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2150 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2151 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2152 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2153 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2154 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2155 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2156 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2157 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2158 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2159 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2160 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2161 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2162 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2163 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2164 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2165 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2166 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2167 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2168 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2169 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2170 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2171 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2172 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2173 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2174 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2175 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2176 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2177 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2178 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2179 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2180 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2181 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2182 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2183 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2184 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2185 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2186 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2187 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2188 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2189 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2190 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2191 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2192 0xBE3A,
2193 };
2194
2195 /*
2196 * Mini sample rate converter code image
2197 * that is to be loaded at 0x400 on the DSP.
2198 */
2199 static const u16 assp_minisrc_image[] = {
2200
2201 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2202 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2203 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2204 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2205 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2206 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2207 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2208 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2209 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2210 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2211 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2212 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2213 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2214 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2215 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2216 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2217 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2218 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2219 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2220 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2221 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2222 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2223 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2224 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2225 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2226 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2227 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2228 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2229 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2230 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2231 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2232 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2233 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2234 };
2235
2236 static const struct firmware assp_kernel = {
2237 .data = (u8 *)assp_kernel_image,
2238 .size = sizeof assp_kernel_image
2239 };
2240 static const struct firmware assp_minisrc = {
2241 .data = (u8 *)assp_minisrc_image,
2242 .size = sizeof assp_minisrc_image
2243 };
2244
2245 #endif /* FIRMWARE_IN_THE_KERNEL */
2246
2247 #ifdef __LITTLE_ENDIAN
2248 static inline void snd_m3_convert_from_le(const struct firmware *fw) { }
2249 #else
2250 static void snd_m3_convert_from_le(const struct firmware *fw)
2251 {
2252 int i;
2253 u16 *data = (u16 *)fw->data;
2254
2255 for (i = 0; i < fw->size / 2; ++i)
2256 le16_to_cpus(&data[i]);
2257 }
2258 #endif
2259
2260
2261 /*
2262 * initialize ASSP
2263 */
2264
2265 #define MINISRC_LPF_LEN 10
2266 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2267 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2268 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2269 };
2270
2271 static void snd_m3_assp_init(struct snd_m3 *chip)
2272 {
2273 unsigned int i;
2274 u16 *data;
2275
2276 /* zero kernel data */
2277 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2278 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2279 KDATA_BASE_ADDR + i, 0);
2280
2281 /* zero mixer data? */
2282 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2283 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2284 KDATA_BASE_ADDR2 + i, 0);
2285
2286 /* init dma pointer */
2287 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2288 KDATA_CURRENT_DMA,
2289 KDATA_DMA_XFER0);
2290
2291 /* write kernel into code memory.. */
2292 data = (u16 *)chip->assp_kernel_image->data;
2293 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2294 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2295 REV_B_CODE_MEMORY_BEGIN + i, data[i]);
2296 }
2297
2298 /*
2299 * We only have this one client and we know that 0x400
2300 * is free in our kernel's mem map, so lets just
2301 * drop it there. It seems that the minisrc doesn't
2302 * need vectors, so we won't bother with them..
2303 */
2304 data = (u16 *)chip->assp_minisrc_image->data;
2305 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2306 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2307 0x400 + i, data[i]);
2308 }
2309
2310 /*
2311 * write the coefficients for the low pass filter?
2312 */
2313 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2314 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2315 0x400 + MINISRC_COEF_LOC + i,
2316 minisrc_lpf[i]);
2317 }
2318
2319 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2320 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2321 0x8000);
2322
2323 /*
2324 * the minisrc is the only thing on
2325 * our task list..
2326 */
2327 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2328 KDATA_TASK0,
2329 0x400);
2330
2331 /*
2332 * init the mixer number..
2333 */
2334
2335 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2336 KDATA_MIXER_TASK_NUMBER,0);
2337
2338 /*
2339 * EXTREME KERNEL MASTER VOLUME
2340 */
2341 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2342 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2343 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2344 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2345
2346 chip->mixer_list.curlen = 0;
2347 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2348 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2349 chip->adc1_list.curlen = 0;
2350 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2351 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2352 chip->dma_list.curlen = 0;
2353 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2354 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2355 chip->msrc_list.curlen = 0;
2356 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2357 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2358 }
2359
2360
2361 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2362 {
2363 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2364 MINISRC_IN_BUFFER_SIZE / 2 +
2365 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2366 int address, i;
2367
2368 /*
2369 * the revb memory map has 0x1100 through 0x1c00
2370 * free.
2371 */
2372
2373 /*
2374 * align instance address to 256 bytes so that its
2375 * shifted list address is aligned.
2376 * list address = (mem address >> 1) >> 7;
2377 */
2378 data_bytes = ALIGN(data_bytes, 256);
2379 address = 0x1100 + ((data_bytes/2) * index);
2380
2381 if ((address + (data_bytes/2)) >= 0x1c00) {
2382 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2383 data_bytes, index, address);
2384 return -ENOMEM;
2385 }
2386
2387 s->number = index;
2388 s->inst.code = 0x400;
2389 s->inst.data = address;
2390
2391 for (i = data_bytes / 2; i > 0; address++, i--) {
2392 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2393 address, 0);
2394 }
2395
2396 return 0;
2397 }
2398
2399
2400 /*
2401 * this works for the reference board, have to find
2402 * out about others
2403 *
2404 * this needs more magic for 4 speaker, but..
2405 */
2406 static void
2407 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2408 {
2409 int io = chip->iobase;
2410 u16 gpo, polarity;
2411
2412 if (! chip->external_amp)
2413 return;
2414
2415 polarity = enable ? 0 : 1;
2416 polarity = polarity << chip->amp_gpio;
2417 gpo = 1 << chip->amp_gpio;
2418
2419 outw(~gpo, io + GPIO_MASK);
2420
2421 outw(inw(io + GPIO_DIRECTION) | gpo,
2422 io + GPIO_DIRECTION);
2423
2424 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2425 io + GPIO_DATA);
2426
2427 outw(0xffff, io + GPIO_MASK);
2428 }
2429
2430 static int
2431 snd_m3_chip_init(struct snd_m3 *chip)
2432 {
2433 struct pci_dev *pcidev = chip->pci;
2434 unsigned long io = chip->iobase;
2435 u32 n;
2436 u16 w;
2437 u8 t; /* makes as much sense as 'n', no? */
2438
2439 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2440 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2441 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2442 DISABLE_LEGACY);
2443 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2444
2445 if (chip->is_omnibook) {
2446 /*
2447 * Volume buttons on some HP OmniBook laptops don't work
2448 * correctly. This makes them work for the most part.
2449 *
2450 * Volume up and down buttons on the laptop side work.
2451 * Fn+cursor_up (volme up) works.
2452 * Fn+cursor_down (volume down) doesn't work.
2453 * Fn+F7 (mute) works acts as volume up.
2454 */
2455 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2456 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2457 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2458 outw(0xffff, io + GPIO_MASK);
2459 }
2460 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2461 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2462 n |= chip->hv_config;
2463 /* For some reason we must always use reduced debounce. */
2464 n |= REDUCED_DEBOUNCE;
2465 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2466 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2467
2468 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2469 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2470 n &= ~INT_CLK_SELECT;
2471 if (!chip->allegro_flag) {
2472 n &= ~INT_CLK_MULT_ENABLE;
2473 n |= INT_CLK_SRC_NOT_PCI;
2474 }
2475 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2476 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2477
2478 if (chip->allegro_flag) {
2479 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2480 n |= IN_CLK_12MHZ_SELECT;
2481 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2482 }
2483
2484 t = inb(chip->iobase + ASSP_CONTROL_A);
2485 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2486 t |= ASSP_CLK_49MHZ_SELECT;
2487 t |= ASSP_0_WS_ENABLE;
2488 outb(t, chip->iobase + ASSP_CONTROL_A);
2489
2490 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2491 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2492
2493 outb(0x00, io + HARDWARE_VOL_CTRL);
2494 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2495 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2496 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2497 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2498
2499 return 0;
2500 }
2501
2502 static void
2503 snd_m3_enable_ints(struct snd_m3 *chip)
2504 {
2505 unsigned long io = chip->iobase;
2506 unsigned short val;
2507
2508 /* TODO: MPU401 not supported yet */
2509 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2510 if (chip->hv_config & HV_CTRL_ENABLE)
2511 val |= HV_INT_ENABLE;
2512 outw(val, io + HOST_INT_CTRL);
2513 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2514 io + ASSP_CONTROL_C);
2515 }
2516
2517
2518 /*
2519 */
2520
2521 static int snd_m3_free(struct snd_m3 *chip)
2522 {
2523 struct m3_dma *s;
2524 int i;
2525
2526 if (chip->substreams) {
2527 spin_lock_irq(&chip->reg_lock);
2528 for (i = 0; i < chip->num_substreams; i++) {
2529 s = &chip->substreams[i];
2530 /* check surviving pcms; this should not happen though.. */
2531 if (s->substream && s->running)
2532 snd_m3_pcm_stop(chip, s, s->substream);
2533 }
2534 spin_unlock_irq(&chip->reg_lock);
2535 kfree(chip->substreams);
2536 }
2537 if (chip->iobase) {
2538 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2539 }
2540
2541 #ifdef CONFIG_PM
2542 vfree(chip->suspend_mem);
2543 #endif
2544
2545 if (chip->irq >= 0) {
2546 synchronize_irq(chip->irq);
2547 free_irq(chip->irq, chip);
2548 }
2549
2550 if (chip->iobase)
2551 pci_release_regions(chip->pci);
2552
2553 #ifdef FIRMWARE_IN_THE_KERNEL
2554 if (chip->assp_kernel_image != &assp_kernel)
2555 #endif
2556 release_firmware(chip->assp_kernel_image);
2557 #ifdef FIRMWARE_IN_THE_KERNEL
2558 if (chip->assp_minisrc_image != &assp_minisrc)
2559 #endif
2560 release_firmware(chip->assp_minisrc_image);
2561
2562 pci_disable_device(chip->pci);
2563 kfree(chip);
2564 return 0;
2565 }
2566
2567
2568 /*
2569 * APM support
2570 */
2571 #ifdef CONFIG_PM
2572 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2573 {
2574 struct snd_card *card = pci_get_drvdata(pci);
2575 struct snd_m3 *chip = card->private_data;
2576 int i, index;
2577
2578 if (chip->suspend_mem == NULL)
2579 return 0;
2580
2581 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2582 snd_pcm_suspend_all(chip->pcm);
2583 snd_ac97_suspend(chip->ac97);
2584
2585 msleep(10); /* give the assp a chance to idle.. */
2586
2587 snd_m3_assp_halt(chip);
2588
2589 /* save dsp image */
2590 index = 0;
2591 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2592 chip->suspend_mem[index++] =
2593 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2594 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2595 chip->suspend_mem[index++] =
2596 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2597
2598 pci_disable_device(pci);
2599 pci_save_state(pci);
2600 pci_set_power_state(pci, pci_choose_state(pci, state));
2601 return 0;
2602 }
2603
2604 static int m3_resume(struct pci_dev *pci)
2605 {
2606 struct snd_card *card = pci_get_drvdata(pci);
2607 struct snd_m3 *chip = card->private_data;
2608 int i, index;
2609
2610 if (chip->suspend_mem == NULL)
2611 return 0;
2612
2613 pci_set_power_state(pci, PCI_D0);
2614 pci_restore_state(pci);
2615 if (pci_enable_device(pci) < 0) {
2616 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2617 "disabling device\n");
2618 snd_card_disconnect(card);
2619 return -EIO;
2620 }
2621 pci_set_master(pci);
2622
2623 /* first lets just bring everything back. .*/
2624 snd_m3_outw(chip, 0, 0x54);
2625 snd_m3_outw(chip, 0, 0x56);
2626
2627 snd_m3_chip_init(chip);
2628 snd_m3_assp_halt(chip);
2629 snd_m3_ac97_reset(chip);
2630
2631 /* restore dsp image */
2632 index = 0;
2633 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2634 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2635 chip->suspend_mem[index++]);
2636 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2637 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2638 chip->suspend_mem[index++]);
2639
2640 /* tell the dma engine to restart itself */
2641 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2642 KDATA_DMA_ACTIVE, 0);
2643
2644 /* restore ac97 registers */
2645 snd_ac97_resume(chip->ac97);
2646
2647 snd_m3_assp_continue(chip);
2648 snd_m3_enable_ints(chip);
2649 snd_m3_amp_enable(chip, 1);
2650
2651 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2652 return 0;
2653 }
2654 #endif /* CONFIG_PM */
2655
2656
2657 /*
2658 */
2659
2660 static int snd_m3_dev_free(struct snd_device *device)
2661 {
2662 struct snd_m3 *chip = device->device_data;
2663 return snd_m3_free(chip);
2664 }
2665
2666 static int __devinit
2667 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2668 int enable_amp,
2669 int amp_gpio,
2670 struct snd_m3 **chip_ret)
2671 {
2672 struct snd_m3 *chip;
2673 int i, err;
2674 const struct snd_pci_quirk *quirk;
2675 static struct snd_device_ops ops = {
2676 .dev_free = snd_m3_dev_free,
2677 };
2678
2679 *chip_ret = NULL;
2680
2681 if (pci_enable_device(pci))
2682 return -EIO;
2683
2684 /* check, if we can restrict PCI DMA transfers to 28 bits */
2685 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2686 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2687 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2688 pci_disable_device(pci);
2689 return -ENXIO;
2690 }
2691
2692 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2693 if (chip == NULL) {
2694 pci_disable_device(pci);
2695 return -ENOMEM;
2696 }
2697
2698 spin_lock_init(&chip->reg_lock);
2699 spin_lock_init(&chip->ac97_lock);
2700
2701 switch (pci->device) {
2702 case PCI_DEVICE_ID_ESS_ALLEGRO:
2703 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2704 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2705 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2706 chip->allegro_flag = 1;
2707 break;
2708 }
2709
2710 chip->card = card;
2711 chip->pci = pci;
2712 chip->irq = -1;
2713
2714 chip->external_amp = enable_amp;
2715 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2716 chip->amp_gpio = amp_gpio;
2717 else {
2718 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2719 if (quirk) {
2720 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2721 "for '%s'\n", quirk->name);
2722 chip->amp_gpio = quirk->value;
2723 } else if (chip->allegro_flag)
2724 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2725 else /* presumably this is for all 'maestro3's.. */
2726 chip->amp_gpio = GPO_EXT_AMP_M3;
2727 }
2728
2729 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2730 if (quirk) {
2731 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2732 "for '%s'\n", quirk->name);
2733 chip->irda_workaround = 1;
2734 }
2735 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2736 if (quirk)
2737 chip->hv_config = quirk->value;
2738 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2739 chip->is_omnibook = 1;
2740
2741 chip->num_substreams = NR_DSPS;
2742 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2743 GFP_KERNEL);
2744 if (chip->substreams == NULL) {
2745 kfree(chip);
2746 pci_disable_device(pci);
2747 return -ENOMEM;
2748 }
2749
2750 err = request_firmware(&chip->assp_kernel_image,
2751 "ess/maestro3_assp_kernel.fw", &pci->dev);
2752 if (err < 0) {
2753 #ifdef FIRMWARE_IN_THE_KERNEL
2754 chip->assp_kernel_image = &assp_kernel;
2755 #else
2756 snd_m3_free(chip);
2757 return err;
2758 #endif
2759 } else
2760 snd_m3_convert_from_le(chip->assp_kernel_image);
2761
2762 err = request_firmware(&chip->assp_minisrc_image,
2763 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2764 if (err < 0) {
2765 #ifdef FIRMWARE_IN_THE_KERNEL
2766 chip->assp_minisrc_image = &assp_minisrc;
2767 #else
2768 snd_m3_free(chip);
2769 return err;
2770 #endif
2771 } else
2772 snd_m3_convert_from_le(chip->assp_minisrc_image);
2773
2774 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2775 snd_m3_free(chip);
2776 return err;
2777 }
2778 chip->iobase = pci_resource_start(pci, 0);
2779
2780 /* just to be sure */
2781 pci_set_master(pci);
2782
2783 snd_m3_chip_init(chip);
2784 snd_m3_assp_halt(chip);
2785
2786 snd_m3_ac97_reset(chip);
2787
2788 snd_m3_amp_enable(chip, 1);
2789
2790 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2791
2792 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2793 card->driver, chip)) {
2794 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2795 snd_m3_free(chip);
2796 return -ENOMEM;
2797 }
2798 chip->irq = pci->irq;
2799
2800 #ifdef CONFIG_PM
2801 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2802 if (chip->suspend_mem == NULL)
2803 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2804 #endif
2805
2806 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2807 snd_m3_free(chip);
2808 return err;
2809 }
2810
2811 if ((err = snd_m3_mixer(chip)) < 0)
2812 return err;
2813
2814 for (i = 0; i < chip->num_substreams; i++) {
2815 struct m3_dma *s = &chip->substreams[i];
2816 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2817 return err;
2818 }
2819
2820 if ((err = snd_m3_pcm(chip, 0)) < 0)
2821 return err;
2822
2823 snd_m3_enable_ints(chip);
2824 snd_m3_assp_continue(chip);
2825
2826 snd_card_set_dev(card, &pci->dev);
2827
2828 *chip_ret = chip;
2829
2830 return 0;
2831 }
2832
2833 /*
2834 */
2835 static int __devinit
2836 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2837 {
2838 static int dev;
2839 struct snd_card *card;
2840 struct snd_m3 *chip;
2841 int err;
2842
2843 /* don't pick up modems */
2844 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2845 return -ENODEV;
2846
2847 if (dev >= SNDRV_CARDS)
2848 return -ENODEV;
2849 if (!enable[dev]) {
2850 dev++;
2851 return -ENOENT;
2852 }
2853
2854 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2855 if (card == NULL)
2856 return -ENOMEM;
2857
2858 switch (pci->device) {
2859 case PCI_DEVICE_ID_ESS_ALLEGRO:
2860 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2861 strcpy(card->driver, "Allegro");
2862 break;
2863 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2864 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2865 strcpy(card->driver, "Canyon3D-2");
2866 break;
2867 default:
2868 strcpy(card->driver, "Maestro3");
2869 break;
2870 }
2871
2872 if ((err = snd_m3_create(card, pci,
2873 external_amp[dev],
2874 amp_gpio[dev],
2875 &chip)) < 0) {
2876 snd_card_free(card);
2877 return err;
2878 }
2879 card->private_data = chip;
2880
2881 sprintf(card->shortname, "ESS %s PCI", card->driver);
2882 sprintf(card->longname, "%s at 0x%lx, irq %d",
2883 card->shortname, chip->iobase, chip->irq);
2884
2885 if ((err = snd_card_register(card)) < 0) {
2886 snd_card_free(card);
2887 return err;
2888 }
2889
2890 #if 0 /* TODO: not supported yet */
2891 /* TODO enable MIDI IRQ and I/O */
2892 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2893 chip->iobase + MPU401_DATA_PORT,
2894 MPU401_INFO_INTEGRATED,
2895 chip->irq, 0, &chip->rmidi);
2896 if (err < 0)
2897 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2898 #endif
2899
2900 pci_set_drvdata(pci, card);
2901 dev++;
2902 return 0;
2903 }
2904
2905 static void __devexit snd_m3_remove(struct pci_dev *pci)
2906 {
2907 snd_card_free(pci_get_drvdata(pci));
2908 pci_set_drvdata(pci, NULL);
2909 }
2910
2911 static struct pci_driver driver = {
2912 .name = "Maestro3",
2913 .id_table = snd_m3_ids,
2914 .probe = snd_m3_probe,
2915 .remove = __devexit_p(snd_m3_remove),
2916 #ifdef CONFIG_PM
2917 .suspend = m3_suspend,
2918 .resume = m3_resume,
2919 #endif
2920 };
2921
2922 static int __init alsa_card_m3_init(void)
2923 {
2924 return pci_register_driver(&driver);
2925 }
2926
2927 static void __exit alsa_card_m3_exit(void)
2928 {
2929 pci_unregister_driver(&driver);
2930 }
2931
2932 module_init(alsa_card_m3_init)
2933 module_exit(alsa_card_m3_exit)
Support for the Chinese Samsung S3C2440 based development boards