drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39
  40 #include "../pci.h"
  41 #include "pciehp.h"
  42
  43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
  44
  45 struct ctrl_reg {
  46         u8 cap_id;
  47         u8 nxt_ptr;
  48         u16 cap_reg;
  49         u32 dev_cap;
  50         u16 dev_ctrl;
  51         u16 dev_status;
  52         u32 lnk_cap;
  53         u16 lnk_ctrl;
  54         u16 lnk_status;
  55         u32 slot_cap;
  56         u16 slot_ctrl;
  57         u16 slot_status;
  58         u16 root_ctrl;
  59         u16 rsvp;
  60         u32 root_status;
  61 } __attribute__ ((packed));
  62
  63 /* offsets to the controller registers based on the above structure layout */
  64 enum ctrl_offsets {
  65         PCIECAPID       =       offsetof(struct ctrl_reg, cap_id),
  66         NXTCAPPTR       =       offsetof(struct ctrl_reg, nxt_ptr),
  67         CAPREG          =       offsetof(struct ctrl_reg, cap_reg),
  68         DEVCAP          =       offsetof(struct ctrl_reg, dev_cap),
  69         DEVCTRL         =       offsetof(struct ctrl_reg, dev_ctrl),
  70         DEVSTATUS       =       offsetof(struct ctrl_reg, dev_status),
  71         LNKCAP          =       offsetof(struct ctrl_reg, lnk_cap),
  72         LNKCTRL         =       offsetof(struct ctrl_reg, lnk_ctrl),
  73         LNKSTATUS       =       offsetof(struct ctrl_reg, lnk_status),
  74         SLOTCAP         =       offsetof(struct ctrl_reg, slot_cap),
  75         SLOTCTRL        =       offsetof(struct ctrl_reg, slot_ctrl),
  76         SLOTSTATUS      =       offsetof(struct ctrl_reg, slot_status),
  77         ROOTCTRL        =       offsetof(struct ctrl_reg, root_ctrl),
  78         ROOTSTATUS      =       offsetof(struct ctrl_reg, root_status),
  79 };
  80
  81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  82 {
  83         struct pci_dev *dev = ctrl->pci_dev;
  84         return pci_read_config_word(dev, ctrl->cap_base + reg, value);
  85 }
  86
  87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  88 {
  89         struct pci_dev *dev = ctrl->pci_dev;
  90         return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
  91 }
  92
  93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  94 {
  95         struct pci_dev *dev = ctrl->pci_dev;
  96         return pci_write_config_word(dev, ctrl->cap_base + reg, value);
  97 }
  98
  99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
 100 {
 101         struct pci_dev *dev = ctrl->pci_dev;
 102         return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
 103 }
 104
 105 /* Field definitions in PCI Express Capabilities Register */
 106 #define CAP_VER                 0x000F
 107 #define DEV_PORT_TYPE           0x00F0
 108 #define SLOT_IMPL               0x0100
 109 #define MSG_NUM                 0x3E00
 110
 111 /* Device or Port Type */
 112 #define NAT_ENDPT               0x00
 113 #define LEG_ENDPT               0x01
 114 #define ROOT_PORT               0x04
 115 #define UP_STREAM               0x05
 116 #define DN_STREAM               0x06
 117 #define PCIE_PCI_BRDG           0x07
 118 #define PCI_PCIE_BRDG           0x10
 119
 120 /* Field definitions in Device Capabilities Register */
 121 #define DATTN_BUTTN_PRSN        0x1000
 122 #define DATTN_LED_PRSN          0x2000
 123 #define DPWR_LED_PRSN           0x4000
 124
 125 /* Field definitions in Link Capabilities Register */
 126 #define MAX_LNK_SPEED           0x000F
 127 #define MAX_LNK_WIDTH           0x03F0
 128
 129 /* Link Width Encoding */
 130 #define LNK_X1          0x01
 131 #define LNK_X2          0x02
 132 #define LNK_X4          0x04
 133 #define LNK_X8          0x08
 134 #define LNK_X12         0x0C
 135 #define LNK_X16         0x10
 136 #define LNK_X32         0x20
 137
 138 /*Field definitions of Link Status Register */
 139 #define LNK_SPEED       0x000F
 140 #define NEG_LINK_WD     0x03F0
 141 #define LNK_TRN_ERR     0x0400
 142 #define LNK_TRN         0x0800
 143 #define SLOT_CLK_CONF   0x1000
 144
 145 /* Field definitions in Slot Capabilities Register */
 146 #define ATTN_BUTTN_PRSN 0x00000001
 147 #define PWR_CTRL_PRSN   0x00000002
 148 #define MRL_SENS_PRSN   0x00000004
 149 #define ATTN_LED_PRSN   0x00000008
 150 #define PWR_LED_PRSN    0x00000010
 151 #define HP_SUPR_RM_SUP  0x00000020
 152 #define HP_CAP          0x00000040
 153 #define SLOT_PWR_VALUE  0x000003F8
 154 #define SLOT_PWR_LIMIT  0x00000C00
 155 #define PSN             0xFFF80000      /* PSN: Physical Slot Number */
 156
 157 /* Field definitions in Slot Control Register */
 158 #define ATTN_BUTTN_ENABLE               0x0001
 159 #define PWR_FAULT_DETECT_ENABLE         0x0002
 160 #define MRL_DETECT_ENABLE               0x0004
 161 #define PRSN_DETECT_ENABLE              0x0008
 162 #define CMD_CMPL_INTR_ENABLE            0x0010
 163 #define HP_INTR_ENABLE                  0x0020
 164 #define ATTN_LED_CTRL                   0x00C0
 165 #define PWR_LED_CTRL                    0x0300
 166 #define PWR_CTRL                        0x0400
 167 #define EMI_CTRL                        0x0800
 168
 169 /* Attention indicator and Power indicator states */
 170 #define LED_ON          0x01
 171 #define LED_BLINK       0x10
 172 #define LED_OFF         0x11
 173
 174 /* Power Control Command */
 175 #define POWER_ON        0
 176 #define POWER_OFF       0x0400
 177
 178 /* EMI Status defines */
 179 #define EMI_DISENGAGED  0
 180 #define EMI_ENGAGED     1
 181
 182 /* Field definitions in Slot Status Register */
 183 #define ATTN_BUTTN_PRESSED      0x0001
 184 #define PWR_FAULT_DETECTED      0x0002
 185 #define MRL_SENS_CHANGED        0x0004
 186 #define PRSN_DETECT_CHANGED     0x0008
 187 #define CMD_COMPLETED           0x0010
 188 #define MRL_STATE               0x0020
 189 #define PRSN_STATE              0x0040
 190 #define EMI_STATE               0x0080
 191 #define EMI_STATUS_BIT          7
 192
 193 static irqreturn_t pcie_isr(int irq, void *dev_id);
 194 static void start_int_poll_timer(struct controller *ctrl, int sec);
 195
 196 /* This is the interrupt polling timeout function. */
 197 static void int_poll_timeout(unsigned long data)
 198 {
 199         struct controller *ctrl = (struct controller *)data;
 200
 201         /* Poll for interrupt events.  regs == NULL => polling */
 202         pcie_isr(0, ctrl);
 203
 204         init_timer(&ctrl->poll_timer);
 205         if (!pciehp_poll_time)
 206                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
 207
 208         start_int_poll_timer(ctrl, pciehp_poll_time);
 209 }
 210
 211 /* This function starts the interrupt polling timer. */
 212 static void start_int_poll_timer(struct controller *ctrl, int sec)
 213 {
 214         /* Clamp to sane value */
 215         if ((sec <= 0) || (sec > 60))
 216                 sec = 2;
 217
 218         ctrl->poll_timer.function = &int_poll_timeout;
 219         ctrl->poll_timer.data = (unsigned long)ctrl;
 220         ctrl->poll_timer.expires = jiffies + sec * HZ;
 221         add_timer(&ctrl->poll_timer);
 222 }
 223
 224 static inline int pcie_wait_cmd(struct controller *ctrl)
 225 {
 226         int retval = 0;
 227         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 228         unsigned long timeout = msecs_to_jiffies(msecs);
 229         int rc;
 230
 231         rc = wait_event_interruptible_timeout(ctrl->queue,
 232                                               !ctrl->cmd_busy, timeout);
 233         if (!rc)
 234                 dbg("Command not completed in 1000 msec\n");
 235         else if (rc < 0) {
 236                 retval = -EINTR;
 237                 info("Command was interrupted by a signal\n");
 238         }
 239
 240         return retval;
 241 }
 242
 243 /**
 244  * pcie_write_cmd - Issue controller command
 245  * @ctrl: controller to which the command is issued
 246  * @cmd:  command value written to slot control register
 247  * @mask: bitmask of slot control register to be modified
 248  */
 249 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 250 {
 251         int retval = 0;
 252         u16 slot_status;
 253         u16 slot_ctrl;
 254
 255         mutex_lock(&ctrl->ctrl_lock);
 256
 257         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 258         if (retval) {
 259                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 260                 goto out;
 261         }
 262
 263         if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
 264                 /* After 1 sec and CMD_COMPLETED still not set, just
 265                    proceed forward to issue the next command according
 266                    to spec.  Just print out the error message */
 267                 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
 268                     __func__);
 269         }
 270
 271         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 272         if (retval) {
 273                 err("%s: Cannot read SLOTCTRL register\n", __func__);
 274                 goto out;
 275         }
 276
 277         slot_ctrl &= ~mask;
 278         slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
 279
 280         ctrl->cmd_busy = 1;
 281         smp_mb();
 282         retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
 283         if (retval)
 284                 err("%s: Cannot write to SLOTCTRL register\n", __func__);
 285
 286         /*
 287          * Wait for command completion.
 288          */
 289         if (!retval)
 290                 retval = pcie_wait_cmd(ctrl);
 291  out:
 292         mutex_unlock(&ctrl->ctrl_lock);
 293         return retval;
 294 }
 295
 296 static int hpc_check_lnk_status(struct controller *ctrl)
 297 {
 298         u16 lnk_status;
 299         int retval = 0;
 300
 301         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 302         if (retval) {
 303                 err("%s: Cannot read LNKSTATUS register\n", __func__);
 304                 return retval;
 305         }
 306
 307         dbg("%s: lnk_status = %x\n", __func__, lnk_status);
 308         if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
 309                 !(lnk_status & NEG_LINK_WD)) {
 310                 err("%s : Link Training Error occurs \n", __func__);
 311                 retval = -1;
 312                 return retval;
 313         }
 314
 315         return retval;
 316 }
 317
 318 static int hpc_get_attention_status(struct slot *slot, u8 *status)
 319 {
 320         struct controller *ctrl = slot->ctrl;
 321         u16 slot_ctrl;
 322         u8 atten_led_state;
 323         int retval = 0;
 324
 325         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 326         if (retval) {
 327                 err("%s: Cannot read SLOTCTRL register\n", __func__);
 328                 return retval;
 329         }
 330
 331         dbg("%s: SLOTCTRL %x, value read %x\n",
 332             __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
 333
 334         atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
 335
 336         switch (atten_led_state) {
 337         case 0:
 338                 *status = 0xFF; /* Reserved */
 339                 break;
 340         case 1:
 341                 *status = 1;    /* On */
 342                 break;
 343         case 2:
 344                 *status = 2;    /* Blink */
 345                 break;
 346         case 3:
 347                 *status = 0;    /* Off */
 348                 break;
 349         default:
 350                 *status = 0xFF;
 351                 break;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static int hpc_get_power_status(struct slot *slot, u8 *status)
 358 {
 359         struct controller *ctrl = slot->ctrl;
 360         u16 slot_ctrl;
 361         u8 pwr_state;
 362         int     retval = 0;
 363
 364         retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
 365         if (retval) {
 366                 err("%s: Cannot read SLOTCTRL register\n", __func__);
 367                 return retval;
 368         }
 369         dbg("%s: SLOTCTRL %x value read %x\n",
 370             __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
 371
 372         pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
 373
 374         switch (pwr_state) {
 375         case 0:
 376                 *status = 1;
 377                 break;
 378         case 1:
 379                 *status = 0;
 380                 break;
 381         default:
 382                 *status = 0xFF;
 383                 break;
 384         }
 385
 386         return retval;
 387 }
 388
 389 static int hpc_get_latch_status(struct slot *slot, u8 *status)
 390 {
 391         struct controller *ctrl = slot->ctrl;
 392         u16 slot_status;
 393         int retval = 0;
 394
 395         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 396         if (retval) {
 397                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 398                 return retval;
 399         }
 400
 401         *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
 402
 403         return 0;
 404 }
 405
 406 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
 407 {
 408         struct controller *ctrl = slot->ctrl;
 409         u16 slot_status;
 410         u8 card_state;
 411         int retval = 0;
 412
 413         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 414         if (retval) {
 415                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 416                 return retval;
 417         }
 418         card_state = (u8)((slot_status & PRSN_STATE) >> 6);
 419         *status = (card_state == 1) ? 1 : 0;
 420
 421         return 0;
 422 }
 423
 424 static int hpc_query_power_fault(struct slot *slot)
 425 {
 426         struct controller *ctrl = slot->ctrl;
 427         u16 slot_status;
 428         u8 pwr_fault;
 429         int retval = 0;
 430
 431         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 432         if (retval) {
 433                 err("%s: Cannot check for power fault\n", __func__);
 434                 return retval;
 435         }
 436         pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
 437
 438         return pwr_fault;
 439 }
 440
 441 static int hpc_get_emi_status(struct slot *slot, u8 *status)
 442 {
 443         struct controller *ctrl = slot->ctrl;
 444         u16 slot_status;
 445         int retval = 0;
 446
 447         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 448         if (retval) {
 449                 err("%s : Cannot check EMI status\n", __func__);
 450                 return retval;
 451         }
 452         *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
 453
 454         return retval;
 455 }
 456
 457 static int hpc_toggle_emi(struct slot *slot)
 458 {
 459         u16 slot_cmd;
 460         u16 cmd_mask;
 461         int rc;
 462
 463         slot_cmd = EMI_CTRL;
 464         cmd_mask = EMI_CTRL;
 465         if (!pciehp_poll_mode) {
 466                 slot_cmd = slot_cmd | HP_INTR_ENABLE;
 467                 cmd_mask = cmd_mask | HP_INTR_ENABLE;
 468         }
 469
 470         rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
 471         slot->last_emi_toggle = get_seconds();
 472
 473         return rc;
 474 }
 475
 476 static int hpc_set_attention_status(struct slot *slot, u8 value)
 477 {
 478         struct controller *ctrl = slot->ctrl;
 479         u16 slot_cmd;
 480         u16 cmd_mask;
 481         int rc;
 482
 483         cmd_mask = ATTN_LED_CTRL;
 484         switch (value) {
 485                 case 0 :        /* turn off */
 486                         slot_cmd = 0x00C0;
 487                         break;
 488                 case 1:         /* turn on */
 489                         slot_cmd = 0x0040;
 490                         break;
 491                 case 2:         /* turn blink */
 492                         slot_cmd = 0x0080;
 493                         break;
 494                 default:
 495                         return -1;
 496         }
 497         if (!pciehp_poll_mode) {
 498                 slot_cmd = slot_cmd | HP_INTR_ENABLE;
 499                 cmd_mask = cmd_mask | HP_INTR_ENABLE;
 500         }
 501
 502         rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 503         dbg("%s: SLOTCTRL %x write cmd %x\n",
 504             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 505
 506         return rc;
 507 }
 508
 509 static void hpc_set_green_led_on(struct slot *slot)
 510 {
 511         struct controller *ctrl = slot->ctrl;
 512         u16 slot_cmd;
 513         u16 cmd_mask;
 514
 515         slot_cmd = 0x0100;
 516         cmd_mask = PWR_LED_CTRL;
 517         if (!pciehp_poll_mode) {
 518                 slot_cmd = slot_cmd | HP_INTR_ENABLE;
 519                 cmd_mask = cmd_mask | HP_INTR_ENABLE;
 520         }
 521
 522         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 523
 524         dbg("%s: SLOTCTRL %x write cmd %x\n",
 525             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 526 }
 527
 528 static void hpc_set_green_led_off(struct slot *slot)
 529 {
 530         struct controller *ctrl = slot->ctrl;
 531         u16 slot_cmd;
 532         u16 cmd_mask;
 533
 534         slot_cmd = 0x0300;
 535         cmd_mask = PWR_LED_CTRL;
 536         if (!pciehp_poll_mode) {
 537                 slot_cmd = slot_cmd | HP_INTR_ENABLE;
 538                 cmd_mask = cmd_mask | HP_INTR_ENABLE;
 539         }
 540
 541         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 542         dbg("%s: SLOTCTRL %x write cmd %x\n",
 543             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 544 }
 545
 546 static void hpc_set_green_led_blink(struct slot *slot)
 547 {
 548         struct controller *ctrl = slot->ctrl;
 549         u16 slot_cmd;
 550         u16 cmd_mask;
 551
 552         slot_cmd = 0x0200;
 553         cmd_mask = PWR_LED_CTRL;
 554         if (!pciehp_poll_mode) {
 555                 slot_cmd = slot_cmd | HP_INTR_ENABLE;
 556                 cmd_mask = cmd_mask | HP_INTR_ENABLE;
 557         }
 558
 559         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 560
 561         dbg("%s: SLOTCTRL %x write cmd %x\n",
 562             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 563 }
 564
 565 static void hpc_release_ctlr(struct controller *ctrl)
 566 {
 567         if (pciehp_poll_mode)
 568                 del_timer(&ctrl->poll_timer);
 569         else
 570                 free_irq(ctrl->pci_dev->irq, ctrl);
 571
 572         /*
 573          * If this is the last controller to be released, destroy the
 574          * pciehp work queue
 575          */
 576         if (atomic_dec_and_test(&pciehp_num_controllers))
 577                 destroy_workqueue(pciehp_wq);
 578 }
 579
 580 static int hpc_power_on_slot(struct slot * slot)
 581 {
 582         struct controller *ctrl = slot->ctrl;
 583         u16 slot_cmd;
 584         u16 cmd_mask;
 585         u16 slot_status;
 586         int retval = 0;
 587
 588         dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 589
 590         /* Clear sticky power-fault bit from previous power failures */
 591         retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
 592         if (retval) {
 593                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
 594                 return retval;
 595         }
 596         slot_status &= PWR_FAULT_DETECTED;
 597         if (slot_status) {
 598                 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
 599                 if (retval) {
 600                         err("%s: Cannot write to SLOTSTATUS register\n",
 601                             __func__);
 602                         return retval;
 603                 }
 604         }
 605
 606         slot_cmd = POWER_ON;
 607         cmd_mask = PWR_CTRL;
 608         /* Enable detection that we turned off at slot power-off time */
 609         if (!pciehp_poll_mode) {
 610                 slot_cmd = slot_cmd |
 611                            PWR_FAULT_DETECT_ENABLE |
 612                            MRL_DETECT_ENABLE |
 613                            PRSN_DETECT_ENABLE |
 614                            HP_INTR_ENABLE;
 615                 cmd_mask = cmd_mask |
 616                            PWR_FAULT_DETECT_ENABLE |
 617                            MRL_DETECT_ENABLE |
 618                            PRSN_DETECT_ENABLE |
 619                            HP_INTR_ENABLE;
 620         }
 621
 622         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 623
 624         if (retval) {
 625                 err("%s: Write %x command failed!\n", __func__, slot_cmd);
 626                 return -1;
 627         }
 628         dbg("%s: SLOTCTRL %x write cmd %x\n",
 629             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 630
 631         return retval;
 632 }
 633
 634 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
 635 {
 636         struct pci_dev *dev = ctrl->pci_dev;
 637         int pos;
 638         u32 reg;
 639
 640         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 641         if (!pos)
 642                 return 0;
 643         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 644         if (reg & PCI_ERR_COR_BAD_DLLP)
 645                 return 0;
 646         reg |= PCI_ERR_COR_BAD_DLLP;
 647         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 648         return 1;
 649 }
 650
 651 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
 652 {
 653         struct pci_dev *dev = ctrl->pci_dev;
 654         u32 reg;
 655         int pos;
 656
 657         pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 658         if (!pos)
 659                 return;
 660         pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
 661         if (!(reg & PCI_ERR_COR_BAD_DLLP))
 662                 return;
 663         reg &= ~PCI_ERR_COR_BAD_DLLP;
 664         pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
 665 }
 666
 667 static int hpc_power_off_slot(struct slot * slot)
 668 {
 669         struct controller *ctrl = slot->ctrl;
 670         u16 slot_cmd;
 671         u16 cmd_mask;
 672         int retval = 0;
 673         int changed;
 674
 675         dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
 676
 677         /*
 678          * Set Bad DLLP Mask bit in Correctable Error Mask
 679          * Register. This is the workaround against Bad DLLP error
 680          * that sometimes happens during turning power off the slot
 681          * which conforms to PCI Express 1.0a spec.
 682          */
 683         changed = pcie_mask_bad_dllp(ctrl);
 684
 685         slot_cmd = POWER_OFF;
 686         cmd_mask = PWR_CTRL;
 687         /*
 688          * If we get MRL or presence detect interrupts now, the isr
 689          * will notice the sticky power-fault bit too and issue power
 690          * indicator change commands. This will lead to an endless loop
 691          * of command completions, since the power-fault bit remains on
 692          * till the slot is powered on again.
 693          */
 694         if (!pciehp_poll_mode) {
 695                 slot_cmd = (slot_cmd &
 696                             ~PWR_FAULT_DETECT_ENABLE &
 697                             ~MRL_DETECT_ENABLE &
 698                             ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
 699                 cmd_mask = cmd_mask |
 700                            PWR_FAULT_DETECT_ENABLE |
 701                            MRL_DETECT_ENABLE |
 702                            PRSN_DETECT_ENABLE |
 703                            HP_INTR_ENABLE;
 704         }
 705
 706         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 707         if (retval) {
 708                 err("%s: Write command failed!\n", __func__);
 709                 retval = -1;
 710                 goto out;
 711         }
 712         dbg("%s: SLOTCTRL %x write cmd %x\n",
 713             __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
 714
 715         /*
 716          * After turning power off, we must wait for at least 1 second
 717          * before taking any action that relies on power having been
 718          * removed from the slot/adapter.
 719          */
 720         msleep(1000);
 721  out:
 722         if (changed)
 723                 pcie_unmask_bad_dllp(ctrl);
 724
 725         return retval;
 726 }
 727
 728 static irqreturn_t pcie_isr(int irq, void *dev_id)
 729 {
 730         struct controller *ctrl = (struct controller *)dev_id;
 731         u16 detected, intr_loc;
 732
 733         /*
 734          * In order to guarantee that all interrupt events are
 735          * serviced, we need to re-inspect Slot Status register after
 736          * clearing what is presumed to be the last pending interrupt.
 737          */
 738         intr_loc = 0;
 739         do {
 740                 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
 741                         err("%s: Cannot read SLOTSTATUS\n", __func__);
 742                         return IRQ_NONE;
 743                 }
 744
 745                 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
 746                              MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
 747                              CMD_COMPLETED);
 748                 intr_loc |= detected;
 749                 if (!intr_loc)
 750                         return IRQ_NONE;
 751                 if (pciehp_writew(ctrl, SLOTSTATUS, detected)) {
 752                         err("%s: Cannot write to SLOTSTATUS\n", __func__);
 753                         return IRQ_NONE;
 754                 }
 755         } while (detected);
 756
 757         dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
 758
 759         /* Check Command Complete Interrupt Pending */
 760         if (intr_loc & CMD_COMPLETED) {
 761                 ctrl->cmd_busy = 0;
 762                 smp_mb();
 763                 wake_up_interruptible(&ctrl->queue);
 764         }
 765
 766         /* Check MRL Sensor Changed */
 767         if (intr_loc & MRL_SENS_CHANGED)
 768                 pciehp_handle_switch_change(0, ctrl);
 769
 770         /* Check Attention Button Pressed */
 771         if (intr_loc & ATTN_BUTTN_PRESSED)
 772                 pciehp_handle_attention_button(0, ctrl);
 773
 774         /* Check Presence Detect Changed */
 775         if (intr_loc & PRSN_DETECT_CHANGED)
 776                 pciehp_handle_presence_change(0, ctrl);
 777
 778         /* Check Power Fault Detected */
 779         if (intr_loc & PWR_FAULT_DETECTED)
 780                 pciehp_handle_power_fault(0, ctrl);
 781
 782         return IRQ_HANDLED;
 783 }
 784
 785 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 786 {
 787         struct controller *ctrl = slot->ctrl;
 788         enum pcie_link_speed lnk_speed;
 789         u32     lnk_cap;
 790         int retval = 0;
 791
 792         retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
 793         if (retval) {
 794                 err("%s: Cannot read LNKCAP register\n", __func__);
 795                 return retval;
 796         }
 797
 798         switch (lnk_cap & 0x000F) {
 799         case 1:
 800                 lnk_speed = PCIE_2PT5GB;
 801                 break;
 802         default:
 803                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 804                 break;
 805         }
 806
 807         *value = lnk_speed;
 808         dbg("Max link speed = %d\n", lnk_speed);
 809
 810         return retval;
 811 }
 812
 813 static int hpc_get_max_lnk_width(struct slot *slot,
 814                                  enum pcie_link_width *value)
 815 {
 816         struct controller *ctrl = slot->ctrl;
 817         enum pcie_link_width lnk_wdth;
 818         u32     lnk_cap;
 819         int retval = 0;
 820
 821         retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
 822         if (retval) {
 823                 err("%s: Cannot read LNKCAP register\n", __func__);
 824                 return retval;
 825         }
 826
 827         switch ((lnk_cap & 0x03F0) >> 4){
 828         case 0:
 829                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 830                 break;
 831         case 1:
 832                 lnk_wdth = PCIE_LNK_X1;
 833                 break;
 834         case 2:
 835                 lnk_wdth = PCIE_LNK_X2;
 836                 break;
 837         case 4:
 838                 lnk_wdth = PCIE_LNK_X4;
 839                 break;
 840         case 8:
 841                 lnk_wdth = PCIE_LNK_X8;
 842                 break;
 843         case 12:
 844                 lnk_wdth = PCIE_LNK_X12;
 845                 break;
 846         case 16:
 847                 lnk_wdth = PCIE_LNK_X16;
 848                 break;
 849         case 32:
 850                 lnk_wdth = PCIE_LNK_X32;
 851                 break;
 852         default:
 853                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 854                 break;
 855         }
 856
 857         *value = lnk_wdth;
 858         dbg("Max link width = %d\n", lnk_wdth);
 859
 860         return retval;
 861 }
 862
 863 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
 864 {
 865         struct controller *ctrl = slot->ctrl;
 866         enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
 867         int retval = 0;
 868         u16 lnk_status;
 869
 870         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 871         if (retval) {
 872                 err("%s: Cannot read LNKSTATUS register\n", __func__);
 873                 return retval;
 874         }
 875
 876         switch (lnk_status & 0x0F) {
 877         case 1:
 878                 lnk_speed = PCIE_2PT5GB;
 879                 break;
 880         default:
 881                 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
 882                 break;
 883         }
 884
 885         *value = lnk_speed;
 886         dbg("Current link speed = %d\n", lnk_speed);
 887
 888         return retval;
 889 }
 890
 891 static int hpc_get_cur_lnk_width(struct slot *slot,
 892                                  enum pcie_link_width *value)
 893 {
 894         struct controller *ctrl = slot->ctrl;
 895         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 896         int retval = 0;
 897         u16 lnk_status;
 898
 899         retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
 900         if (retval) {
 901                 err("%s: Cannot read LNKSTATUS register\n", __func__);
 902                 return retval;
 903         }
 904
 905         switch ((lnk_status & 0x03F0) >> 4){
 906         case 0:
 907                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 908                 break;
 909         case 1:
 910                 lnk_wdth = PCIE_LNK_X1;
 911                 break;
 912         case 2:
 913                 lnk_wdth = PCIE_LNK_X2;
 914                 break;
 915         case 4:
 916                 lnk_wdth = PCIE_LNK_X4;
 917                 break;
 918         case 8:
 919                 lnk_wdth = PCIE_LNK_X8;
 920                 break;
 921         case 12:
 922                 lnk_wdth = PCIE_LNK_X12;
 923                 break;
 924         case 16:
 925                 lnk_wdth = PCIE_LNK_X16;
 926                 break;
 927         case 32:
 928                 lnk_wdth = PCIE_LNK_X32;
 929                 break;
 930         default:
 931                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 932                 break;
 933         }
 934
 935         *value = lnk_wdth;
 936         dbg("Current link width = %d\n", lnk_wdth);
 937
 938         return retval;
 939 }
 940
 941 static struct hpc_ops pciehp_hpc_ops = {
 942         .power_on_slot                  = hpc_power_on_slot,
 943         .power_off_slot                 = hpc_power_off_slot,
 944         .set_attention_status           = hpc_set_attention_status,
 945         .get_power_status               = hpc_get_power_status,
 946         .get_attention_status           = hpc_get_attention_status,
 947         .get_latch_status               = hpc_get_latch_status,
 948         .get_adapter_status             = hpc_get_adapter_status,
 949         .get_emi_status                 = hpc_get_emi_status,
 950         .toggle_emi                     = hpc_toggle_emi,
 951
 952         .get_max_bus_speed              = hpc_get_max_lnk_speed,
 953         .get_cur_bus_speed              = hpc_get_cur_lnk_speed,
 954         .get_max_lnk_width              = hpc_get_max_lnk_width,
 955         .get_cur_lnk_width              = hpc_get_cur_lnk_width,
 956
 957         .query_power_fault              = hpc_query_power_fault,
 958         .green_led_on                   = hpc_set_green_led_on,
 959         .green_led_off                  = hpc_set_green_led_off,
 960         .green_led_blink                = hpc_set_green_led_blink,
 961
 962         .release_ctlr                   = hpc_release_ctlr,
 963         .check_lnk_status               = hpc_check_lnk_status,
 964 };
 965
 966 #ifdef CONFIG_ACPI
 967 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
 968 {
 969         acpi_status status;
 970         acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
 971         struct pci_dev *pdev = dev;
 972         struct pci_bus *parent;
 973         struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
 974
 975         /*
 976          * Per PCI firmware specification, we should run the ACPI _OSC
 977          * method to get control of hotplug hardware before using it.
 978          * If an _OSC is missing, we look for an OSHP to do the same thing.
 979          * To handle different BIOS behavior, we look for _OSC and OSHP
 980          * within the scope of the hotplug controller and its parents, upto
 981          * the host bridge under which this controller exists.
 982          */
 983         while (!handle) {
 984                 /*
 985                  * This hotplug controller was not listed in the ACPI name
 986                  * space at all. Try to get acpi handle of parent pci bus.
 987                  */
 988                 if (!pdev || !pdev->bus->parent)
 989                         break;
 990                 parent = pdev->bus->parent;
 991                 dbg("Could not find %s in acpi namespace, trying parent\n",
 992                                 pci_name(pdev));
 993                 if (!parent->self)
 994                         /* Parent must be a host bridge */
 995                         handle = acpi_get_pci_rootbridge_handle(
 996                                         pci_domain_nr(parent),
 997                                         parent->number);
 998                 else
 999                         handle = DEVICE_ACPI_HANDLE(
1000                                         &(parent->self->dev));
1001                 pdev = parent->self;
1002         }
1003
1004         while (handle) {
1005                 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1006                 dbg("Trying to get hotplug control for %s \n",
1007                         (char *)string.pointer);
1008                 status = pci_osc_control_set(handle,
1009                                 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1010                                 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1011                 if (status == AE_NOT_FOUND)
1012                         status = acpi_run_oshp(handle);
1013                 if (ACPI_SUCCESS(status)) {
1014                         dbg("Gained control for hotplug HW for pci %s (%s)\n",
1015                                 pci_name(dev), (char *)string.pointer);
1016                         kfree(string.pointer);
1017                         return 0;
1018                 }
1019                 if (acpi_root_bridge(handle))
1020                         break;
1021                 chandle = handle;
1022                 status = acpi_get_parent(chandle, &handle);
1023                 if (ACPI_FAILURE(status))
1024                         break;
1025         }
1026
1027         err("Cannot get control of hotplug hardware for pci %s\n",
1028                         pci_name(dev));
1029
1030         kfree(string.pointer);
1031         return -1;
1032 }
1033 #endif
1034
1035 static int pcie_init_hardware_part1(struct controller *ctrl,
1036                                     struct pcie_device *dev)
1037 {
1038         /* Mask Hot-plug Interrupt Enable */
1039         if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) {
1040                 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
1041                 return -1;
1042         }
1043         return 0;
1044 }
1045
1046 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1047 {
1048         u16 cmd, mask;
1049
1050         /*
1051          * We need to clear all events before enabling hotplug interrupt
1052          * notification mechanism in order for hotplug controler to
1053          * generate interrupts.
1054          */
1055         if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) {
1056                 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1057                 return -1;
1058         }
1059
1060         cmd = PRSN_DETECT_ENABLE;
1061         if (ATTN_BUTTN(ctrl))
1062                 cmd |= ATTN_BUTTN_ENABLE;
1063         if (POWER_CTRL(ctrl))
1064                 cmd |= PWR_FAULT_DETECT_ENABLE;
1065         if (MRL_SENS(ctrl))
1066                 cmd |= MRL_DETECT_ENABLE;
1067         if (!pciehp_poll_mode)
1068                 cmd |= HP_INTR_ENABLE;
1069
1070         mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE |
1071                 PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE;
1072
1073         if (pcie_write_cmd(ctrl, cmd, mask)) {
1074                 err("%s: Cannot enable software notification\n", __func__);
1075                 goto abort;
1076         }
1077
1078         if (pciehp_force)
1079                 dbg("Bypassing BIOS check for pciehp use on %s\n",
1080                                 pci_name(ctrl->pci_dev));
1081         else if (pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev))
1082                 goto abort_disable_intr;
1083
1084         return 0;
1085
1086         /* We end up here for the many possible ways to fail this API. */
1087 abort_disable_intr:
1088         if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE))
1089                 err("%s : disabling interrupts failed\n", __func__);
1090 abort:
1091         return -1;
1092 }
1093
1094 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1095 {
1096         int rc;
1097         u16 cap_reg;
1098         u32 slot_cap;
1099         int cap_base;
1100         u16 slot_status, slot_ctrl;
1101         struct pci_dev *pdev;
1102
1103         pdev = dev->port;
1104         ctrl->pci_dev = pdev;   /* save pci_dev in context */
1105
1106         dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1107                         __func__, pdev->vendor, pdev->device);
1108
1109         cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1110         if (cap_base == 0) {
1111                 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__);
1112                 goto abort;
1113         }
1114
1115         ctrl->cap_base = cap_base;
1116
1117         dbg("%s: pcie_cap_base %x\n", __func__, cap_base);
1118
1119         rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1120         if (rc) {
1121                 err("%s: Cannot read CAPREG register\n", __func__);
1122                 goto abort;
1123         }
1124         dbg("%s: CAPREG offset %x cap_reg %x\n",
1125             __func__, ctrl->cap_base + CAPREG, cap_reg);
1126
1127         if (((cap_reg & SLOT_IMPL) == 0) ||
1128             (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1129                 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1130                 dbg("%s : This is not a root port or the port is not "
1131                     "connected to a slot\n", __func__);
1132                 goto abort;
1133         }
1134
1135         rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1136         if (rc) {
1137                 err("%s: Cannot read SLOTCAP register\n", __func__);
1138                 goto abort;
1139         }
1140         dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1141             __func__, ctrl->cap_base + SLOTCAP, slot_cap);
1142
1143         if (!(slot_cap & HP_CAP)) {
1144                 dbg("%s : This slot is not hot-plug capable\n", __func__);
1145                 goto abort;
1146         }
1147         /* For debugging purpose */
1148         rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1149         if (rc) {
1150                 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1151                 goto abort;
1152         }
1153         dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1154             __func__, ctrl->cap_base + SLOTSTATUS, slot_status);
1155
1156         rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1157         if (rc) {
1158                 err("%s: Cannot read SLOTCTRL register\n", __func__);
1159                 goto abort;
1160         }
1161         dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1162             __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1163
1164         for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1165                 if (pci_resource_len(pdev, rc) > 0)
1166                         dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1167                             (unsigned long long)pci_resource_start(pdev, rc),
1168                             (unsigned long long)pci_resource_len(pdev, rc));
1169
1170         info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1171              pdev->vendor, pdev->device,
1172              pdev->subsystem_vendor, pdev->subsystem_device);
1173
1174         mutex_init(&ctrl->crit_sect);
1175         mutex_init(&ctrl->ctrl_lock);
1176
1177         /* setup wait queue */
1178         init_waitqueue_head(&ctrl->queue);
1179
1180         /* return PCI Controller Info */
1181         ctrl->slot_device_offset = 0;
1182         ctrl->num_slots = 1;
1183         ctrl->first_slot = slot_cap >> 19;
1184         ctrl->slot_cap = slot_cap;
1185
1186         rc = pcie_init_hardware_part1(ctrl, dev);
1187         if (rc)
1188                 goto abort;
1189
1190         if (pciehp_poll_mode) {
1191                 /* Install interrupt polling timer. Start with 10 sec delay */
1192                 init_timer(&ctrl->poll_timer);
1193                 start_int_poll_timer(ctrl, 10);
1194         } else {
1195                 /* Installs the interrupt handler */
1196                 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1197                                  MY_NAME, (void *)ctrl);
1198                 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1199                     __func__, ctrl->pci_dev->irq,
1200                     atomic_read(&pciehp_num_controllers), rc);
1201                 if (rc) {
1202                         err("Can't get irq %d for the hotplug controller\n",
1203                             ctrl->pci_dev->irq);
1204                         goto abort;
1205                 }
1206         }
1207         dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1208                 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1209
1210         /*
1211          * If this is the first controller to be initialized,
1212          * initialize the pciehp work queue
1213          */
1214         if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1215                 pciehp_wq = create_singlethread_workqueue("pciehpd");
1216                 if (!pciehp_wq) {
1217                         rc = -ENOMEM;
1218                         goto abort_free_irq;
1219                 }
1220         }
1221
1222         rc = pcie_init_hardware_part2(ctrl, dev);
1223         if (rc == 0) {
1224                 ctrl->hpc_ops = &pciehp_hpc_ops;
1225                 return 0;
1226         }
1227 abort_free_irq:
1228         if (pciehp_poll_mode)
1229                 del_timer_sync(&ctrl->poll_timer);
1230         else
1231                 free_irq(ctrl->pci_dev->irq, ctrl);
1232 abort:
1233         return -1;
1234 }