include/asm-arm/arch-s3c2410/map.h

   1 /* linux/include/asm-arm/arch-s3c2410/map.h
   2  *
   3  * Copyright (c) 2003 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 - Memory map definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_MAP_H
  14 #define __ASM_ARCH_MAP_H
  15
  16 /* we have a bit of a tight squeeze to fit all our registers from
  17  * 0xF00000000 upwards, since we use all of the nGCS space in some
  18  * capacity, and also need to fit the S3C2410 registers in as well...
  19  *
  20  * we try to ensure stuff like the IRQ registers are available for
  21  * an single MOVS instruction (ie, only 8 bits of set data)
  22  *
  23  * Note, we are trying to remove some of these from the implementation
  24  * as they are only useful to certain drivers...
  25  */
  26
  27 #ifndef __ASSEMBLY__
  28 #define S3C2410_ADDR(x)   ((void __iomem __force *)0xF0000000 + (x))
  29 #else
  30 #define S3C2410_ADDR(x)   (0xF0000000 + (x))
  31 #endif
  32
  33 /* interrupt controller is the first thing we put in, to make
  34  * the assembly code for the irq detection easier
  35  */
  36 #define S3C24XX_VA_IRQ     S3C2410_ADDR(0x00000000)
  37 #define S3C2410_PA_IRQ     (0x4A000000)
  38 #define S3C24XX_SZ_IRQ     SZ_1M
  39
  40 /* memory controller registers */
  41 #define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
  42 #define S3C2410_PA_MEMCTRL (0x48000000)
  43 #define S3C24XX_SZ_MEMCTRL SZ_1M
  44
  45 /* USB host controller */
  46 #define S3C2410_PA_USBHOST (0x49000000)
  47 #define S3C24XX_SZ_USBHOST SZ_1M
  48
  49 /* DMA controller */
  50 #define S3C2410_PA_DMA     (0x4B000000)
  51 #define S3C24XX_SZ_DMA     SZ_1M
  52
  53 /* Clock and Power management */
  54 #define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00200000)
  55 #define S3C2410_PA_CLKPWR  (0x4C000000)
  56 #define S3C24XX_SZ_CLKPWR  SZ_1M
  57
  58 /* LCD controller */
  59 #define S3C24XX_VA_LCD     S3C2410_ADDR(0x00300000)
  60 #define S3C2410_PA_LCD     (0x4D000000)
  61 #define S3C24XX_SZ_LCD     SZ_1M
  62
  63 /* NAND flash controller */
  64 #define S3C2410_PA_NAND    (0x4E000000)
  65 #define S3C24XX_SZ_NAND    SZ_1M
  66
  67 /* UARTs */
  68 #define S3C24XX_VA_UART    S3C2410_ADDR(0x00400000)
  69 #define S3C2410_PA_UART    (0x50000000)
  70 #define S3C24XX_SZ_UART    SZ_1M
  71
  72 /* Timers */
  73 #define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00500000)
  74 #define S3C2410_PA_TIMER   (0x51000000)
  75 #define S3C24XX_SZ_TIMER   SZ_1M
  76
  77 /* USB Device port */
  78 #define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00600000)
  79 #define S3C2410_PA_USBDEV  (0x52000000)
  80 #define S3C24XX_SZ_USBDEV  SZ_1M
  81
  82 /* Watchdog */
  83 #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
  84 #define S3C2410_PA_WATCHDOG (0x53000000)
  85 #define S3C24XX_SZ_WATCHDOG SZ_1M
  86
  87 /* IIC hardware controller */
  88 #define S3C2410_PA_IIC     (0x54000000)
  89 #define S3C24XX_SZ_IIC     SZ_1M
  90
  91 /* IIS controller */
  92 #define S3C2410_PA_IIS     (0x55000000)
  93 #define S3C24XX_SZ_IIS     SZ_1M
  94
  95 /* GPIO ports */
  96
  97 /* the calculation for the VA of this must ensure that
  98  * it is the same distance apart from the UART in the
  99  * phsyical address space, as the initial mapping for the IO
 100  * is done as a 1:1 maping. This puts it (currently) at
 101  * 0xF6800000, which is not in the way of any current mapping
 102  * by the base system.
 103 */
 104
 105 #define S3C2410_PA_GPIO    (0x56000000)
 106 #define S3C24XX_VA_GPIO    ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
 107 #define S3C24XX_SZ_GPIO    SZ_1M
 108
 109 /* RTC */
 110 #define S3C2410_PA_RTC     (0x57000000)
 111 #define S3C24XX_SZ_RTC     SZ_1M
 112
 113 /* ADC */
 114 #define S3C2410_PA_ADC     (0x58000000)
 115 #define S3C24XX_SZ_ADC     SZ_1M
 116
 117 /* SPI */
 118 #define S3C2410_PA_SPI     (0x59000000)
 119 #define S3C24XX_SZ_SPI     SZ_1M
 120
 121 /* SDI */
 122 #define S3C2410_PA_SDI     (0x5A000000)
 123 #define S3C24XX_SZ_SDI     SZ_1M
 124
 125 /* CAMIF */
 126 #define S3C2440_PA_CAMIF   (0x4F000000)
 127 #define S3C2440_SZ_CAMIF   SZ_1M
 128
 129 /* AC97 */
 130
 131 #define S3C2440_PA_AC97    (0x5B000000)
 132 #define S3C2440_SZ_AC97    SZ_1M
 133
 134 /* S3C2443 High-speed SD/MMC */
 135 #define S3C2443_PA_HSMMC   (0x4A800000)
 136 #define S3C2443_SZ_HSMMC   (256)
 137
 138 /* ISA style IO, for each machine to sort out mappings for, if it
 139  * implements it. We reserve two 16M regions for ISA.
 140  */
 141
 142 #define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
 143 #define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
 144
 145 /* physical addresses of all the chip-select areas */
 146
 147 #define S3C2410_CS0 (0x00000000)
 148 #define S3C2410_CS1 (0x08000000)
 149 #define S3C2410_CS2 (0x10000000)
 150 #define S3C2410_CS3 (0x18000000)
 151 #define S3C2410_CS4 (0x20000000)
 152 #define S3C2410_CS5 (0x28000000)
 153 #define S3C2410_CS6 (0x30000000)
 154 #define S3C2410_CS7 (0x38000000)
 155
 156 #define S3C2410_SDRAM_PA    (S3C2410_CS6)
 157
 158
 159 /* Use a single interface for common resources between S3C24XX cpus */
 160
 161 #define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
 162 #define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
 163 #define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
 164 #define S3C24XX_PA_DMA      S3C2410_PA_DMA
 165 #define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
 166 #define S3C24XX_PA_LCD      S3C2410_PA_LCD
 167 #define S3C24XX_PA_UART     S3C2410_PA_UART
 168 #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
 169 #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
 170 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
 171 #define S3C24XX_PA_IIC      S3C2410_PA_IIC
 172 #define S3C24XX_PA_IIS      S3C2410_PA_IIS
 173 #define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
 174 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 175 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 176 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
 177
 178 /* deal with the registers that move under the 2412/2413 */
 179
 180 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 181 #ifndef __ASSEMBLY__
 182 extern void __iomem *s3c24xx_va_gpio2;
 183 #endif
 184 #ifdef CONFIG_CPU_S3C2412_ONLY
 185 #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
 186 #else
 187 #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
 188 #endif
 189 #else
 190 #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
 191 #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
 192 #endif
 193
 194 #endif /* __ASM_ARCH_MAP_H */