drivers/serial/sh-sci.h

   1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
   2  *
   3  *  linux/drivers/serial/sh-sci.h
   4  *
   5  *  SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   6  *  Copyright (C) 1999, 2000  Niibe Yutaka
   7  *  Copyright (C) 2000  Greg Banks
   8  *  Copyright (C) 2002, 2003  Paul Mundt
   9  *  Modified to support multiple serial ports. Stuart Menefy (May 2000).
  10  *  Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
  11  *  Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
  12  */
  13 #include <linux/serial_core.h>
  14 #include <asm/io.h>
  15
  16 #if defined(__H8300H__) || defined(__H8300S__)
  17 #include <asm/gpio.h>
  18 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  19 #include <asm/regs306x.h>
  20 #endif
  21 #if defined(CONFIG_H8S2678)
  22 #include <asm/regs267x.h>
  23 #endif
  24 #endif
  25
  26 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
  27 # define SCSPTR 0xffffff7c /* 8 bit */
  28 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  29 # define SCI_ONLY
  30 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  31       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  32       defined(CONFIG_CPU_SUBTYPE_SH7706)
  33 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  34 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  35 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  36 # define SCI_AND_SCIF
  37 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  38 # define SCIF0          0xA4400000
  39 # define SCIF2          0xA4410000
  40 # define SCSMR_Ir       0xA44A0000
  41 # define IRDA_SCIF      SCIF0
  42 # define SCPCR 0xA4000116
  43 # define SCPDR 0xA4000136
  44
  45 /* Set the clock source,
  46  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  47  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  48  */
  49 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  50 # define SCIF_ONLY
  51 #elif defined(CONFIG_SH_RTS7751R2D)
  52 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  53 # define SCIF_ORER 0x0001   /* overrun error bit */
  54 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  55 # define SCIF_ONLY
  56 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
  57       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  58       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  59       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
  60       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
  61       defined(CONFIG_CPU_SUBTYPE_SH7751R)
  62 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  63 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  64 # define SCIF_ORER 0x0001   /* overrun error bit */
  65 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  66         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  67         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  68 # define SCI_AND_SCIF
  69 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  70 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  71 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  72 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  73 # define SCIF_ORER 0x0001  /* overrun error bit */
  74 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  75 # define SCIF_ONLY
  76 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
  77 # define SCPCR  0xA4050116        /* 16 bit SCIF */
  78 # define SCPDR  0xA4050136        /* 16 bit SCIF */
  79 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  80 # define SCIF_ONLY
  81 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  82 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  83 # define SCI_NPORTS 2
  84 # define SCIF_ORER 0x0001   /* overrun error bit */
  85 # define PACR 0xa4050100
  86 # define PBCR 0xa4050102
  87 # define SCSCR_INIT(port)          0x3B
  88 # define SCIF_ONLY
  89 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
  90 # define SCPDR  0xA4050138        /* 16 bit SCIF */
  91 # define SCSPTR2 SCPDR
  92 # define SCIF_ORER 0x0001   /* overrun error bit */
  93 # define SCSCR_INIT(port)  0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
  94 # define SCIF_ONLY
  95 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  96 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  97 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  98 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  99 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
 100 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
 101 # define SCIF_ONLY
 102 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 103 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
 104 # define SCSPTR0                SCPDR0
 105 # define SCIF_ORER              0x0001  /* overrun error bit */
 106 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 107 # define SCIF_ONLY
 108 # define PORT_PSCR              0xA405011E
 109 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 110 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 111 # define SCIF_ORER 0x0001   /* overrun error bit */
 112 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 113 # define SCIF_ONLY
 114 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 115 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
 116 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 117 # define SCIF_ORER 0x0001   /* overrun error bit */
 118 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 119 # define SCIF_ONLY
 120 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 121 # include <asm/hardware.h>
 122 # define SCIF_BASE_ADDR    0x01030000
 123 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 124 # define SCIF_PTR2_OFFS    0x0000020
 125 # define SCIF_LSR2_OFFS    0x0000024
 126 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 127 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 128 # define SCSCR_INIT(port)  0x38                           /* TIE=0,RIE=0,
 129                                                              TE=1,RE=1,REIE=1 */
 130 # define SCIF_ONLY
 131 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 132 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 133 # define SCI_ONLY
 134 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 135 #elif defined(CONFIG_H8S2678)
 136 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 137 # define SCI_ONLY
 138 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 139 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 140 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 141 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 142 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 143 # define SCIF_ORER 0x0001  /* overrun error bit */
 144 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 145 # define SCIF_ONLY
 146 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 147 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 148 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 149 # define SCIF_ORER      0x0001          /* Overrun error bit */
 150 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 151 # define SCIF_ONLY
 152 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 153 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 154 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 155 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 156 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 157 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 158 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 159 # define SCIF_OPER      0x0001          /* Overrun error bit */
 160 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 161 # define SCIF_ONLY
 162 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
 163 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 164 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 165 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 166 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 167 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 168 # define SCIF_ONLY
 169 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 170 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 171 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 172 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 173 # define SCIF_ORER 0x0001  /* overrun error bit */
 174 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 175 # define SCIF_ONLY
 176 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 177 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 178 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
 179 # define SCSPTR2 0xffc50020             /* 16 bit SCIF */
 180 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 181 # define SCIF_ORER 0x0001               /* Overrun error bit */
 182 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 183 # define SCIF_ONLY
 184 #else
 185 # error CPU subtype not defined
 186 #endif
 187
 188 /* SCSCR */
 189 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 190 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 191 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 192 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 193 #if defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 194     defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 195     defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 196     defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 197     defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 198     defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 199     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
 200     defined(CONFIG_CPU_SUBTYPE_SH7785)  || \
 201     defined(CONFIG_CPU_SUBTYPE_SHX3)
 202 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 203 #else
 204 #define SCI_CTRL_FLAGS_REIE 0
 205 #endif
 206 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 207 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 208 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 209 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 210
 211 /* SCxSR SCI */
 212 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 213 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 214 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 215 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 216 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 217 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 218 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 219 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 220
 221 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 222
 223 /* SCxSR SCIF */
 224 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 225 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 226 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 227 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 228 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 229 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 230 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 231 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 232
 233 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 234 #define SCIF_ORER    0x0200
 235 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 236 #define SCIF_RFDC_MASK 0x007f
 237 #define SCIF_TXROOM_MAX 64
 238 #else
 239 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 240 #define SCIF_RFDC_MASK 0x001f
 241 #define SCIF_TXROOM_MAX 16
 242 #endif
 243
 244 #if defined(SCI_ONLY)
 245 # define SCxSR_TEND(port)               SCI_TEND
 246 # define SCxSR_ERRORS(port)             SCI_ERRORS
 247 # define SCxSR_RDxF(port)               SCI_RDRF
 248 # define SCxSR_TDxE(port)               SCI_TDRE
 249 # define SCxSR_ORER(port)               SCI_ORER
 250 # define SCxSR_FER(port)                SCI_FER
 251 # define SCxSR_PER(port)                SCI_PER
 252 # define SCxSR_BRK(port)                0x00
 253 # define SCxSR_RDxF_CLEAR(port)         0xbc
 254 # define SCxSR_ERROR_CLEAR(port)        0xc4
 255 # define SCxSR_TDxE_CLEAR(port)         0x78
 256 # define SCxSR_BREAK_CLEAR(port)        0xc4
 257 #elif defined(SCIF_ONLY)
 258 # define SCxSR_TEND(port)               SCIF_TEND
 259 # define SCxSR_ERRORS(port)             SCIF_ERRORS
 260 # define SCxSR_RDxF(port)               SCIF_RDF
 261 # define SCxSR_TDxE(port)               SCIF_TDFE
 262 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 263 # define SCxSR_ORER(port)               SCIF_ORER
 264 #else
 265 # define SCxSR_ORER(port)               0x0000
 266 #endif
 267 # define SCxSR_FER(port)                SCIF_FER
 268 # define SCxSR_PER(port)                SCIF_PER
 269 # define SCxSR_BRK(port)                SCIF_BRK
 270 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 271 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 272 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 273 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 274 # define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
 275 #else
 276 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
 277 # define SCxSR_RDxF_CLEAR(port)         0x00fc
 278 # define SCxSR_ERROR_CLEAR(port)        0x0073
 279 # define SCxSR_TDxE_CLEAR(port)         0x00df
 280 # define SCxSR_BREAK_CLEAR(port)        0x00e3
 281 #endif
 282 #else
 283 # define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 284 # define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 285 # define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 286 # define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 287 # define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
 288 # define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 289 # define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 290 # define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 291 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 292 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 293 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 294 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 295 #endif
 296
 297 /* SCFCR */
 298 #define SCFCR_RFRST 0x0002
 299 #define SCFCR_TFRST 0x0004
 300 #define SCFCR_TCRST 0x4000
 301 #define SCFCR_MCE   0x0008
 302
 303 #define SCI_MAJOR               204
 304 #define SCI_MINOR_START         8
 305
 306 /* Generic serial flags */
 307 #define SCI_RX_THROTTLE         0x0000001
 308
 309 #define SCI_MAGIC 0xbabeface
 310
 311 /*
 312  * Events are used to schedule things to happen at timer-interrupt
 313  * time, instead of at rs interrupt time.
 314  */
 315 #define SCI_EVENT_WRITE_WAKEUP  0
 316
 317 #define SCI_IN(size, offset)                                    \
 318   unsigned int addr = port->mapbase + (offset);                 \
 319   if ((size) == 8) {                                            \
 320     return ctrl_inb(addr);                                      \
 321   } else {                                                      \
 322     return ctrl_inw(addr);                                      \
 323   }
 324 #define SCI_OUT(size, offset, value)                            \
 325   unsigned int addr = port->mapbase + (offset);                 \
 326   if ((size) == 8) {                                            \
 327     ctrl_outb(value, addr);                                     \
 328   } else {                                                      \
 329     ctrl_outw(value, addr);                                     \
 330   }
 331
 332 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 333   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 334   {                                                                     \
 335     if (port->type == PORT_SCI) {                                       \
 336       SCI_IN(sci_size, sci_offset)                                      \
 337     } else {                                                            \
 338       SCI_IN(scif_size, scif_offset);                                   \
 339     }                                                                   \
 340   }                                                                     \
 341   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 342   {                                                                     \
 343     if (port->type == PORT_SCI) {                                       \
 344       SCI_OUT(sci_size, sci_offset, value)                              \
 345     } else {                                                            \
 346       SCI_OUT(scif_size, scif_offset, value);                           \
 347     }                                                                   \
 348   }
 349
 350 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 351   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 352   {                                                                     \
 353     SCI_IN(scif_size, scif_offset);                                     \
 354   }                                                                     \
 355   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 356   {                                                                     \
 357     SCI_OUT(scif_size, scif_offset, value);                             \
 358   }
 359
 360 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 361   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 362   {                                                                     \
 363     SCI_IN(sci_size, sci_offset);                                       \
 364   }                                                                     \
 365   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 366   {                                                                     \
 367     SCI_OUT(sci_size, sci_offset, value);                               \
 368   }
 369
 370 #ifdef CONFIG_CPU_SH3
 371 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 372 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 373                                 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 374                                  h8_sci_offset, h8_sci_size) \
 375   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 376 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 377           CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 378 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 379     defined(CONFIG_CPU_SUBTYPE_SH7705)
 380 #define SCIF_FNS(name, scif_offset, scif_size) \
 381   CPU_SCIF_FNS(name, scif_offset, scif_size)
 382 #else
 383 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 384                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 385                  h8_sci_offset, h8_sci_size) \
 386   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 387 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 388   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 389 #endif
 390 #elif defined(__H8300H__) || defined(__H8300S__)
 391 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 392                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 393                  h8_sci_offset, h8_sci_size) \
 394   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 395 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 396 #else
 397 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 398                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 399                  h8_sci_offset, h8_sci_size) \
 400   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 401 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 402   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 403 #endif
 404
 405 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 406     defined(CONFIG_CPU_SUBTYPE_SH7705)
 407
 408 SCIF_FNS(SCSMR,  0x00, 16)
 409 SCIF_FNS(SCBRR,  0x04,  8)
 410 SCIF_FNS(SCSCR,  0x08, 16)
 411 SCIF_FNS(SCTDSR, 0x0c,  8)
 412 SCIF_FNS(SCFER,  0x10, 16)
 413 SCIF_FNS(SCxSR,  0x14, 16)
 414 SCIF_FNS(SCFCR,  0x18, 16)
 415 SCIF_FNS(SCFDR,  0x1c, 16)
 416 SCIF_FNS(SCxTDR, 0x20,  8)
 417 SCIF_FNS(SCxRDR, 0x24,  8)
 418 SCIF_FNS(SCLSR,  0x24, 16)
 419 #else
 420 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 421 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 422 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 423 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 424 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 425 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 426 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 427 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 428 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 429 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
 430     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 431     defined(CONFIG_CPU_SUBTYPE_SH7785)
 432 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 433 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 434 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 435 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 436 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 437 #else
 438 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 439 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 440 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 441 #endif
 442 #endif
 443 #define sci_in(port, reg) sci_##reg##_in(port)
 444 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 445
 446 /* H8/300 series SCI pins assignment */
 447 #if defined(__H8300H__) || defined(__H8300S__)
 448 static const struct __attribute__((packed)) {
 449         int port;             /* GPIO port no */
 450         unsigned short rx,tx; /* GPIO bit no */
 451 } h8300_sci_pins[] = {
 452 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 453         {    /* SCI0 */
 454                 .port = H8300_GPIO_P9,
 455                 .rx   = H8300_GPIO_B2,
 456                 .tx   = H8300_GPIO_B0,
 457         },
 458         {    /* SCI1 */
 459                 .port = H8300_GPIO_P9,
 460                 .rx   = H8300_GPIO_B3,
 461                 .tx   = H8300_GPIO_B1,
 462         },
 463         {    /* SCI2 */
 464                 .port = H8300_GPIO_PB,
 465                 .rx   = H8300_GPIO_B7,
 466                 .tx   = H8300_GPIO_B6,
 467         }
 468 #elif defined(CONFIG_H8S2678)
 469         {    /* SCI0 */
 470                 .port = H8300_GPIO_P3,
 471                 .rx   = H8300_GPIO_B2,
 472                 .tx   = H8300_GPIO_B0,
 473         },
 474         {    /* SCI1 */
 475                 .port = H8300_GPIO_P3,
 476                 .rx   = H8300_GPIO_B3,
 477                 .tx   = H8300_GPIO_B1,
 478         },
 479         {    /* SCI2 */
 480                 .port = H8300_GPIO_P5,
 481                 .rx   = H8300_GPIO_B1,
 482                 .tx   = H8300_GPIO_B0,
 483         }
 484 #endif
 485 };
 486 #endif
 487
 488 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
 489 static inline int sci_rxd_in(struct uart_port *port)
 490 {
 491         if (port->mapbase == 0xfffffe80)
 492                 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
 493         return 1;
 494 }
 495 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 496       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 497       defined(CONFIG_CPU_SUBTYPE_SH7706)
 498 static inline int sci_rxd_in(struct uart_port *port)
 499 {
 500         if (port->mapbase == 0xfffffe80)
 501                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 502         if (port->mapbase == 0xa4000150)
 503                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 504         if (port->mapbase == 0xa4000140)
 505                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 506         return 1;
 507 }
 508 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 509 static inline int sci_rxd_in(struct uart_port *port)
 510 {
 511         if (port->mapbase == SCIF0)
 512                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 513         if (port->mapbase == SCIF2)
 514                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 515         return 1;
 516 }
 517 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 518 static inline int sci_rxd_in(struct uart_port *port)
 519 {
 520           return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
 521 }
 522 static inline void set_sh771x_scif_pfc(struct uart_port *port)
 523 {
 524         if (port->mapbase == 0xA4400000){
 525                 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
 526                 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
 527                 return;
 528         }
 529         if (port->mapbase == 0xA4410000){
 530                 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
 531                 return;
 532         }
 533 }
 534
 535 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 536       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 537       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 538       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 539       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 540       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 541       defined(CONFIG_CPU_SUBTYPE_SH4_202)
 542 static inline int sci_rxd_in(struct uart_port *port)
 543 {
 544 #ifndef SCIF_ONLY
 545         if (port->mapbase == 0xffe00000)
 546                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 547 #endif
 548 #ifndef SCI_ONLY
 549         if (port->mapbase == 0xffe80000)
 550                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 551 #endif
 552         return 1;
 553 }
 554 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 555 static inline int sci_rxd_in(struct uart_port *port)
 556 {
 557         if (port->mapbase == 0xfe600000)
 558                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 559         if (port->mapbase == 0xfe610000)
 560                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 561         if (port->mapbase == 0xfe620000)
 562                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 563         return 1;
 564 }
 565 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
 566 static inline int sci_rxd_in(struct uart_port *port)
 567 {
 568         if (port->mapbase == 0xa4430000)
 569                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 570         return 1;
 571 }
 572 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
 573 static inline int sci_rxd_in(struct uart_port *port)
 574 {
 575         return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 576 }
 577 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 578 static inline int sci_rxd_in(struct uart_port *port)
 579 {
 580         if (port->mapbase == 0xffe00000)
 581                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 582         if (port->mapbase == 0xffe10000)
 583                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 584         if (port->mapbase == 0xffe20000)
 585                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 586         if (port->mapbase == 0xffe30000)
 587                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 588         return 1;
 589 }
 590 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 591 static inline int sci_rxd_in(struct uart_port *port)
 592 {
 593         if (port->mapbase == 0xffe00000)
 594                 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
 595         return 1;
 596 }
 597 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 598 static inline int sci_rxd_in(struct uart_port *port)
 599 {
 600         if (port->mapbase == 0xffe00000)
 601                 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
 602         else
 603                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 604
 605 }
 606 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 607 static inline int sci_rxd_in(struct uart_port *port)
 608 {
 609          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 610 }
 611 #elif defined(__H8300H__) || defined(__H8300S__)
 612 static inline int sci_rxd_in(struct uart_port *port)
 613 {
 614         int ch = (port->mapbase - SMR0) >> 3;
 615         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 616 }
 617 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 618 static inline int sci_rxd_in(struct uart_port *port)
 619 {
 620         if (port->mapbase == 0xff923000)
 621                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 622         if (port->mapbase == 0xff924000)
 623                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 624         if (port->mapbase == 0xff925000)
 625                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 626         return 1;
 627 }
 628 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 629 static inline int sci_rxd_in(struct uart_port *port)
 630 {
 631         if (port->mapbase == 0xffe00000)
 632                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 633         if (port->mapbase == 0xffe10000)
 634                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 635         return 1;
 636 }
 637 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 638 static inline int sci_rxd_in(struct uart_port *port)
 639 {
 640         if (port->mapbase == 0xffea0000)
 641                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 642         if (port->mapbase == 0xffeb0000)
 643                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 644         if (port->mapbase == 0xffec0000)
 645                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 646         if (port->mapbase == 0xffed0000)
 647                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 648         if (port->mapbase == 0xffee0000)
 649                 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
 650         if (port->mapbase == 0xffef0000)
 651                 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
 652         return 1;
 653 }
 654 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
 655 static inline int sci_rxd_in(struct uart_port *port)
 656 {
 657         if (port->mapbase == 0xfffe8000)
 658                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 659         if (port->mapbase == 0xfffe8800)
 660                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 661         if (port->mapbase == 0xfffe9000)
 662                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 663         if (port->mapbase == 0xfffe9800)
 664                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 665         return 1;
 666 }
 667 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 668 static inline int sci_rxd_in(struct uart_port *port)
 669 {
 670         if (port->mapbase == 0xf8400000)
 671                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 672         if (port->mapbase == 0xf8410000)
 673                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 674         if (port->mapbase == 0xf8420000)
 675                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 676         return 1;
 677 }
 678 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 679 static inline int sci_rxd_in(struct uart_port *port)
 680 {
 681         if (port->mapbase == 0xffc30000)
 682                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 683         if (port->mapbase == 0xffc40000)
 684                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 685         if (port->mapbase == 0xffc50000)
 686                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 687         if (port->mapbase == 0xffc60000)
 688                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 689 }
 690 #endif
 691
 692 /*
 693  * Values for the BitRate Register (SCBRR)
 694  *
 695  * The values are actually divisors for a frequency which can
 696  * be internal to the SH3 (14.7456MHz) or derived from an external
 697  * clock source.  This driver assumes the internal clock is used;
 698  * to support using an external clock source, config options or
 699  * possibly command-line options would need to be added.
 700  *
 701  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 702  * the SCSMR register would also need to be set to non-zero values.
 703  *
 704  * -- Greg Banks 27Feb2000
 705  *
 706  * Answer: The SCBRR register is only eight bits, and the value in
 707  * it gets larger with lower baud rates. At around 2400 (depending on
 708  * the peripherial module clock) you run out of bits. However the
 709  * lower two bits of SCSMR allow the module clock to be divided down,
 710  * scaling the value which is needed in SCBRR.
 711  *
 712  * -- Stuart Menefy - 23 May 2000
 713  *
 714  * I meant, why would anyone bother with bitrates below 2400.
 715  *
 716  * -- Greg Banks - 7Jul2000
 717  *
 718  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 719  * tape reader as a console!
 720  *
 721  * -- Mitch Davis - 15 Jul 2000
 722  */
 723
 724 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 725     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 726     defined(CONFIG_CPU_SUBTYPE_SH7785)
 727 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 728 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 729 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 730 #elif defined(__H8300H__) || defined(__H8300S__)
 731 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
 732 #elif defined(CONFIG_SUPERH64)
 733 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
 734 #else /* Generic SH */
 735 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 736 #endif