drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include <linux/io-mapping.h>
  35
  36 /* General customization:
  37  */
  38
  39 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  40
  41 #define DRIVER_NAME             "i915"
  42 #define DRIVER_DESC             "Intel Graphics"
  43 #define DRIVER_DATE             "20080730"
  44
  45 enum pipe {
  46         PIPE_A = 0,
  47         PIPE_B,
  48 };
  49
  50 #define I915_NUM_PIPE   2
  51
  52 /* Interface history:
  53  *
  54  * 1.1: Original.
  55  * 1.2: Add Power Management
  56  * 1.3: Add vblank support
  57  * 1.4: Fix cmdbuffer path, add heap destroy
  58  * 1.5: Add vblank pipe configuration
  59  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  60  *      - Support vertical blank on secondary display pipe
  61  */
  62 #define DRIVER_MAJOR            1
  63 #define DRIVER_MINOR            6
  64 #define DRIVER_PATCHLEVEL       0
  65
  66 #define WATCH_COHERENCY 0
  67 #define WATCH_BUF       0
  68 #define WATCH_EXEC      0
  69 #define WATCH_LRU       0
  70 #define WATCH_RELOC     0
  71 #define WATCH_INACTIVE  0
  72 #define WATCH_PWRITE    0
  73
  74 typedef struct _drm_i915_ring_buffer {
  75         int tail_mask;
  76         unsigned long Size;
  77         u8 *virtual_start;
  78         int head;
  79         int tail;
  80         int space;
  81         drm_local_map_t map;
  82         struct drm_gem_object *ring_obj;
  83 } drm_i915_ring_buffer_t;
  84
  85 struct mem_block {
  86         struct mem_block *next;
  87         struct mem_block *prev;
  88         int start;
  89         int size;
  90         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  91 };
  92
  93 struct opregion_header;
  94 struct opregion_acpi;
  95 struct opregion_swsci;
  96 struct opregion_asle;
  97
  98 struct intel_opregion {
  99         struct opregion_header *header;
 100         struct opregion_acpi *acpi;
 101         struct opregion_swsci *swsci;
 102         struct opregion_asle *asle;
 103         int enabled;
 104 };
 105
 106 typedef struct drm_i915_private {
 107         struct drm_device *dev;
 108
 109         int has_gem;
 110
 111         void __iomem *regs;
 112         drm_local_map_t *sarea;
 113
 114         drm_i915_sarea_t *sarea_priv;
 115         drm_i915_ring_buffer_t ring;
 116
 117         drm_dma_handle_t *status_page_dmah;
 118         void *hw_status_page;
 119         dma_addr_t dma_status_page;
 120         uint32_t counter;
 121         unsigned int status_gfx_addr;
 122         drm_local_map_t hws_map;
 123         struct drm_gem_object *hws_obj;
 124
 125         unsigned int cpp;
 126         int back_offset;
 127         int front_offset;
 128         int current_page;
 129         int page_flipping;
 130
 131         wait_queue_head_t irq_queue;
 132         atomic_t irq_received;
 133         /** Protects user_irq_refcount and irq_mask_reg */
 134         spinlock_t user_irq_lock;
 135         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 136         int user_irq_refcount;
 137         /** Cached value of IMR to avoid reads in updating the bitfield */
 138         u32 irq_mask_reg;
 139         u32 pipestat[2];
 140
 141         int tex_lru_log_granularity;
 142         int allow_batchbuffer;
 143         struct mem_block *agp_heap;
 144         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 145         int vblank_pipe;
 146
 147         struct intel_opregion opregion;
 148
 149         /* Register state */
 150         u8 saveLBB;
 151         u32 saveDSPACNTR;
 152         u32 saveDSPBCNTR;
 153         u32 saveDSPARB;
 154         u32 saveRENDERSTANDBY;
 155         u32 saveHWS;
 156         u32 savePIPEACONF;
 157         u32 savePIPEBCONF;
 158         u32 savePIPEASRC;
 159         u32 savePIPEBSRC;
 160         u32 saveFPA0;
 161         u32 saveFPA1;
 162         u32 saveDPLL_A;
 163         u32 saveDPLL_A_MD;
 164         u32 saveHTOTAL_A;
 165         u32 saveHBLANK_A;
 166         u32 saveHSYNC_A;
 167         u32 saveVTOTAL_A;
 168         u32 saveVBLANK_A;
 169         u32 saveVSYNC_A;
 170         u32 saveBCLRPAT_A;
 171         u32 savePIPEASTAT;
 172         u32 saveDSPASTRIDE;
 173         u32 saveDSPASIZE;
 174         u32 saveDSPAPOS;
 175         u32 saveDSPAADDR;
 176         u32 saveDSPASURF;
 177         u32 saveDSPATILEOFF;
 178         u32 savePFIT_PGM_RATIOS;
 179         u32 saveBLC_PWM_CTL;
 180         u32 saveBLC_PWM_CTL2;
 181         u32 saveFPB0;
 182         u32 saveFPB1;
 183         u32 saveDPLL_B;
 184         u32 saveDPLL_B_MD;
 185         u32 saveHTOTAL_B;
 186         u32 saveHBLANK_B;
 187         u32 saveHSYNC_B;
 188         u32 saveVTOTAL_B;
 189         u32 saveVBLANK_B;
 190         u32 saveVSYNC_B;
 191         u32 saveBCLRPAT_B;
 192         u32 savePIPEBSTAT;
 193         u32 saveDSPBSTRIDE;
 194         u32 saveDSPBSIZE;
 195         u32 saveDSPBPOS;
 196         u32 saveDSPBADDR;
 197         u32 saveDSPBSURF;
 198         u32 saveDSPBTILEOFF;
 199         u32 saveVGA0;
 200         u32 saveVGA1;
 201         u32 saveVGA_PD;
 202         u32 saveVGACNTRL;
 203         u32 saveADPA;
 204         u32 saveLVDS;
 205         u32 savePP_ON_DELAYS;
 206         u32 savePP_OFF_DELAYS;
 207         u32 saveDVOA;
 208         u32 saveDVOB;
 209         u32 saveDVOC;
 210         u32 savePP_ON;
 211         u32 savePP_OFF;
 212         u32 savePP_CONTROL;
 213         u32 savePP_DIVISOR;
 214         u32 savePFIT_CONTROL;
 215         u32 save_palette_a[256];
 216         u32 save_palette_b[256];
 217         u32 saveFBC_CFB_BASE;
 218         u32 saveFBC_LL_BASE;
 219         u32 saveFBC_CONTROL;
 220         u32 saveFBC_CONTROL2;
 221         u32 saveIER;
 222         u32 saveIIR;
 223         u32 saveIMR;
 224         u32 saveCACHE_MODE_0;
 225         u32 saveD_STATE;
 226         u32 saveCG_2D_DIS;
 227         u32 saveMI_ARB_STATE;
 228         u32 saveSWF0[16];
 229         u32 saveSWF1[16];
 230         u32 saveSWF2[3];
 231         u8 saveMSR;
 232         u8 saveSR[8];
 233         u8 saveGR[25];
 234         u8 saveAR_INDEX;
 235         u8 saveAR[21];
 236         u8 saveDACMASK;
 237         u8 saveDACDATA[256*3]; /* 256 3-byte colors */
 238         u8 saveCR[37];
 239
 240         struct {
 241                 struct drm_mm gtt_space;
 242
 243                 struct io_mapping *gtt_mapping;
 244
 245                 /**
 246                  * List of objects currently involved in rendering from the
 247                  * ringbuffer.
 248                  *
 249                  * Includes buffers having the contents of their GPU caches
 250                  * flushed, not necessarily primitives.  last_rendering_seqno
 251                  * represents when the rendering involved will be completed.
 252                  *
 253                  * A reference is held on the buffer while on this list.
 254                  */
 255                 struct list_head active_list;
 256
 257                 /**
 258                  * List of objects which are not in the ringbuffer but which
 259                  * still have a write_domain which needs to be flushed before
 260                  * unbinding.
 261                  *
 262                  * last_rendering_seqno is 0 while an object is in this list.
 263                  *
 264                  * A reference is held on the buffer while on this list.
 265                  */
 266                 struct list_head flushing_list;
 267
 268                 /**
 269                  * LRU list of objects which are not in the ringbuffer and
 270                  * are ready to unbind, but are still in the GTT.
 271                  *
 272                  * last_rendering_seqno is 0 while an object is in this list.
 273                  *
 274                  * A reference is not held on the buffer while on this list,
 275                  * as merely being GTT-bound shouldn't prevent its being
 276                  * freed, and we'll pull it off the list in the free path.
 277                  */
 278                 struct list_head inactive_list;
 279
 280                 /**
 281                  * List of breadcrumbs associated with GPU requests currently
 282                  * outstanding.
 283                  */
 284                 struct list_head request_list;
 285
 286                 /**
 287                  * We leave the user IRQ off as much as possible,
 288                  * but this means that requests will finish and never
 289                  * be retired once the system goes idle. Set a timer to
 290                  * fire periodically while the ring is running. When it
 291                  * fires, go retire requests.
 292                  */
 293                 struct delayed_work retire_work;
 294
 295                 uint32_t next_gem_seqno;
 296
 297                 /**
 298                  * Waiting sequence number, if any
 299                  */
 300                 uint32_t waiting_gem_seqno;
 301
 302                 /**
 303                  * Last seq seen at irq time
 304                  */
 305                 uint32_t irq_gem_seqno;
 306
 307                 /**
 308                  * Flag if the X Server, and thus DRM, is not currently in
 309                  * control of the device.
 310                  *
 311                  * This is set between LeaveVT and EnterVT.  It needs to be
 312                  * replaced with a semaphore.  It also needs to be
 313                  * transitioned away from for kernel modesetting.
 314                  */
 315                 int suspended;
 316
 317                 /**
 318                  * Flag if the hardware appears to be wedged.
 319                  *
 320                  * This is set when attempts to idle the device timeout.
 321                  * It prevents command submission from occuring and makes
 322                  * every pending request fail
 323                  */
 324                 int wedged;
 325
 326                 /** Bit 6 swizzling required for X tiling */
 327                 uint32_t bit_6_swizzle_x;
 328                 /** Bit 6 swizzling required for Y tiling */
 329                 uint32_t bit_6_swizzle_y;
 330         } mm;
 331 } drm_i915_private_t;
 332
 333 /** driver private structure attached to each drm_gem_object */
 334 struct drm_i915_gem_object {
 335         struct drm_gem_object *obj;
 336
 337         /** Current space allocated to this object in the GTT, if any. */
 338         struct drm_mm_node *gtt_space;
 339
 340         /** This object's place on the active/flushing/inactive lists */
 341         struct list_head list;
 342
 343         /**
 344          * This is set if the object is on the active or flushing lists
 345          * (has pending rendering), and is not set if it's on inactive (ready
 346          * to be unbound).
 347          */
 348         int active;
 349
 350         /**
 351          * This is set if the object has been written to since last bound
 352          * to the GTT
 353          */
 354         int dirty;
 355
 356         /** AGP memory structure for our GTT binding. */
 357         DRM_AGP_MEM *agp_mem;
 358
 359         struct page **page_list;
 360
 361         /**
 362          * Current offset of the object in GTT space.
 363          *
 364          * This is the same as gtt_space->start
 365          */
 366         uint32_t gtt_offset;
 367
 368         /** Boolean whether this object has a valid gtt offset. */
 369         int gtt_bound;
 370
 371         /** How many users have pinned this object in GTT space */
 372         int pin_count;
 373
 374         /** Breadcrumb of last rendering to the buffer. */
 375         uint32_t last_rendering_seqno;
 376
 377         /** Current tiling mode for the object. */
 378         uint32_t tiling_mode;
 379
 380         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 381         uint32_t agp_type;
 382
 383         /**
 384          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 385          * flags which individual pages are valid.
 386          */
 387         uint8_t *page_cpu_valid;
 388 };
 389
 390 /**
 391  * Request queue structure.
 392  *
 393  * The request queue allows us to note sequence numbers that have been emitted
 394  * and may be associated with active buffers to be retired.
 395  *
 396  * By keeping this list, we can avoid having to do questionable
 397  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 398  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 399  */
 400 struct drm_i915_gem_request {
 401         /** GEM sequence number associated with this request. */
 402         uint32_t seqno;
 403
 404         /** Time at which this request was emitted, in jiffies. */
 405         unsigned long emitted_jiffies;
 406
 407         struct list_head list;
 408 };
 409
 410 struct drm_i915_file_private {
 411         struct {
 412                 uint32_t last_gem_seqno;
 413                 uint32_t last_gem_throttle_seqno;
 414         } mm;
 415 };
 416
 417 extern struct drm_ioctl_desc i915_ioctls[];
 418 extern int i915_max_ioctl;
 419
 420                                 /* i915_dma.c */
 421 extern void i915_kernel_lost_context(struct drm_device * dev);
 422 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 423 extern int i915_driver_unload(struct drm_device *);
 424 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 425 extern void i915_driver_lastclose(struct drm_device * dev);
 426 extern void i915_driver_preclose(struct drm_device *dev,
 427                                  struct drm_file *file_priv);
 428 extern void i915_driver_postclose(struct drm_device *dev,
 429                                   struct drm_file *file_priv);
 430 extern int i915_driver_device_is_agp(struct drm_device * dev);
 431 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 432                               unsigned long arg);
 433 extern int i915_emit_box(struct drm_device *dev,
 434                          struct drm_clip_rect __user *boxes,
 435                          int i, int DR1, int DR4);
 436
 437 /* i915_irq.c */
 438 extern int i915_irq_emit(struct drm_device *dev, void *data,
 439                          struct drm_file *file_priv);
 440 extern int i915_irq_wait(struct drm_device *dev, void *data,
 441                          struct drm_file *file_priv);
 442 void i915_user_irq_get(struct drm_device *dev);
 443 void i915_user_irq_put(struct drm_device *dev);
 444
 445 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 446 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 447 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 448 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 449 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 450                                 struct drm_file *file_priv);
 451 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 452                                 struct drm_file *file_priv);
 453 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 454 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 455 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 456 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 457                             struct drm_file *file_priv);
 458 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 459
 460 void
 461 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 462
 463 void
 464 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 465
 466
 467 /* i915_mem.c */
 468 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 469                           struct drm_file *file_priv);
 470 extern int i915_mem_free(struct drm_device *dev, void *data,
 471                          struct drm_file *file_priv);
 472 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 473                               struct drm_file *file_priv);
 474 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 475                                  struct drm_file *file_priv);
 476 extern void i915_mem_takedown(struct mem_block **heap);
 477 extern void i915_mem_release(struct drm_device * dev,
 478                              struct drm_file *file_priv, struct mem_block *heap);
 479 /* i915_gem.c */
 480 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 481                         struct drm_file *file_priv);
 482 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 483                           struct drm_file *file_priv);
 484 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 485                          struct drm_file *file_priv);
 486 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 487                           struct drm_file *file_priv);
 488 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 489                         struct drm_file *file_priv);
 490 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 491                               struct drm_file *file_priv);
 492 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 493                              struct drm_file *file_priv);
 494 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 495                         struct drm_file *file_priv);
 496 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 497                        struct drm_file *file_priv);
 498 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 499                          struct drm_file *file_priv);
 500 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 501                         struct drm_file *file_priv);
 502 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 503                             struct drm_file *file_priv);
 504 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 505                            struct drm_file *file_priv);
 506 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 507                            struct drm_file *file_priv);
 508 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 509                         struct drm_file *file_priv);
 510 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 511                         struct drm_file *file_priv);
 512 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 513                                 struct drm_file *file_priv);
 514 void i915_gem_load(struct drm_device *dev);
 515 int i915_gem_proc_init(struct drm_minor *minor);
 516 void i915_gem_proc_cleanup(struct drm_minor *minor);
 517 int i915_gem_init_object(struct drm_gem_object *obj);
 518 void i915_gem_free_object(struct drm_gem_object *obj);
 519 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 520 void i915_gem_object_unpin(struct drm_gem_object *obj);
 521 void i915_gem_lastclose(struct drm_device *dev);
 522 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 523 void i915_gem_retire_requests(struct drm_device *dev);
 524 void i915_gem_retire_work_handler(struct work_struct *work);
 525 void i915_gem_clflush_object(struct drm_gem_object *obj);
 526
 527 /* i915_gem_tiling.c */
 528 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 529
 530 /* i915_gem_debug.c */
 531 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 532                           const char *where, uint32_t mark);
 533 #if WATCH_INACTIVE
 534 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 535 #else
 536 #define i915_verify_inactive(dev, file, line)
 537 #endif
 538 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 539 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 540                           const char *where, uint32_t mark);
 541 void i915_dump_lru(struct drm_device *dev, const char *where);
 542
 543 /* i915_suspend.c */
 544 extern int i915_save_state(struct drm_device *dev);
 545 extern int i915_restore_state(struct drm_device *dev);
 546
 547 /* i915_suspend.c */
 548 extern int i915_save_state(struct drm_device *dev);
 549 extern int i915_restore_state(struct drm_device *dev);
 550
 551 #ifdef CONFIG_ACPI
 552 /* i915_opregion.c */
 553 extern int intel_opregion_init(struct drm_device *dev);
 554 extern void intel_opregion_free(struct drm_device *dev);
 555 extern void opregion_asle_intr(struct drm_device *dev);
 556 extern void opregion_enable_asle(struct drm_device *dev);
 557 #else
 558 static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
 559 static inline void intel_opregion_free(struct drm_device *dev) { return; }
 560 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 561 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 562 #endif
 563
 564 /**
 565  * Lock test for when it's just for synchronization of ring access.
 566  *
 567  * In that case, we don't need to do it when GEM is initialized as nobody else
 568  * has access to the ring.
 569  */
 570 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 571         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 572                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 573 } while (0)
 574
 575 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 576 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 577 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 578 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 579 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 580 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 581
 582 #define I915_VERBOSE 0
 583
 584 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 585                         volatile char *virt;
 586
 587 #define BEGIN_LP_RING(n) do {                           \
 588         if (I915_VERBOSE)                               \
 589                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
 590         if (dev_priv->ring.space < (n)*4)               \
 591                 i915_wait_ring(dev, (n)*4, __func__);           \
 592         outcount = 0;                                   \
 593         outring = dev_priv->ring.tail;                  \
 594         ringmask = dev_priv->ring.tail_mask;            \
 595         virt = dev_priv->ring.virtual_start;            \
 596 } while (0)
 597
 598 #define OUT_RING(n) do {                                        \
 599         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 600         *(volatile unsigned int *)(virt + outring) = (n);       \
 601         outcount++;                                             \
 602         outring += 4;                                           \
 603         outring &= ringmask;                                    \
 604 } while (0)
 605
 606 #define ADVANCE_LP_RING() do {                                          \
 607         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 608         dev_priv->ring.tail = outring;                                  \
 609         dev_priv->ring.space -= outcount * 4;                           \
 610         I915_WRITE(PRB0_TAIL, outring);                 \
 611 } while(0)
 612
 613 /**
 614  * Reads a dword out of the status page, which is written to from the command
 615  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 616  * MI_STORE_DATA_IMM.
 617  *
 618  * The following dwords have a reserved meaning:
 619  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 620  * 0x04: ring 0 head pointer
 621  * 0x05: ring 1 head pointer (915-class)
 622  * 0x06: ring 2 head pointer (915-class)
 623  * 0x10-0x1b: Context status DWords (GM45)
 624  * 0x1f: Last written status offset. (GM45)
 625  *
 626  * The area from dword 0x20 to 0x3ff is available for driver usage.
 627  */
 628 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 629 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 630 #define I915_GEM_HWS_INDEX              0x20
 631 #define I915_BREADCRUMB_INDEX           0x21
 632
 633 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 634
 635 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 636 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 637 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 638 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 639 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 640
 641 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 642 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 643 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 644 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 645                         (dev)->pci_device == 0x27AE)
 646 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 647                        (dev)->pci_device == 0x2982 || \
 648                        (dev)->pci_device == 0x2992 || \
 649                        (dev)->pci_device == 0x29A2 || \
 650                        (dev)->pci_device == 0x2A02 || \
 651                        (dev)->pci_device == 0x2A12 || \
 652                        (dev)->pci_device == 0x2A42 || \
 653                        (dev)->pci_device == 0x2E02 || \
 654                        (dev)->pci_device == 0x2E12 || \
 655                        (dev)->pci_device == 0x2E22)
 656
 657 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 658
 659 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 660
 661 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 662                      (dev)->pci_device == 0x2E12 || \
 663                      (dev)->pci_device == 0x2E22)
 664
 665 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 666                         (dev)->pci_device == 0x29B2 ||  \
 667                         (dev)->pci_device == 0x29D2)
 668
 669 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 670                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 671
 672 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 673                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
 674
 675 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
 676
 677 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 678
 679 #endif