include/asm-powerpc/cpm1.h

   1 /*
   2  * MPC8xx Communication Processor Module.
   3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4  *
   5  * This file contains structures and information for the communication
   6  * processor channels.  Some CPM control and status is available
   7  * throught the MPC8xx internal memory map.  See immap.h for details.
   8  * This file only contains what I need for the moment, not the total
   9  * CPM capabilities.  I (or someone else) will add definitions as they
  10  * are needed.  -- Dan
  11  *
  12  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  13  * bytes of the DP RAM and relocates the I2C parameter area to the
  14  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  15  * or other use.
  16  */
  17 #ifndef __CPM1__
  18 #define __CPM1__
  19
  20 #include <asm/8xx_immap.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/cpm.h>
  23
  24 /* CPM Command register.
  25 */
  26 #define CPM_CR_RST      ((ushort)0x8000)
  27 #define CPM_CR_OPCODE   ((ushort)0x0f00)
  28 #define CPM_CR_CHAN     ((ushort)0x00f0)
  29 #define CPM_CR_FLG      ((ushort)0x0001)
  30
  31 /* Channel numbers.
  32 */
  33 #define CPM_CR_CH_SCC1          ((ushort)0x0000)
  34 #define CPM_CR_CH_I2C           ((ushort)0x0001)        /* I2C and IDMA1 */
  35 #define CPM_CR_CH_SCC2          ((ushort)0x0004)
  36 #define CPM_CR_CH_SPI           ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
  37 #define CPM_CR_CH_TIMER         CPM_CR_CH_SPI
  38 #define CPM_CR_CH_SCC3          ((ushort)0x0008)
  39 #define CPM_CR_CH_SMC1          ((ushort)0x0009)        /* SMC1 / DSP1 */
  40 #define CPM_CR_CH_SCC4          ((ushort)0x000c)
  41 #define CPM_CR_CH_SMC2          ((ushort)0x000d)        /* SMC2 / DSP2 */
  42
  43 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  44
  45 #ifndef CONFIG_PPC_CPM_NEW_BINDING
  46 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  47  * being) used for microcode.  There is an area that can only be used
  48  * as data ram for buffer descriptors, which is all we use right now.
  49  * Currently the first 512 and last 256 bytes are used for microcode.
  50  */
  51 #define CPM_DATAONLY_BASE       ((uint)0x0800)
  52 #define CPM_DATAONLY_SIZE       ((uint)0x0700)
  53 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  54 #endif
  55
  56 /* Export the base address of the communication processor registers
  57  * and dual port ram.
  58  */
  59 extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
  60
  61 #ifdef CONFIG_PPC_CPM_NEW_BINDING
  62 #define cpm_dpalloc cpm_muram_alloc
  63 #define cpm_dpfree cpm_muram_free
  64 #define cpm_dpram_addr cpm_muram_addr
  65 #define cpm_dpram_phys cpm_muram_dma
  66 #else
  67 extern unsigned long cpm_dpalloc(uint size, uint align);
  68 extern int cpm_dpfree(unsigned long offset);
  69 extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
  70 extern void cpm_dpdump(void);
  71 extern void *cpm_dpram_addr(unsigned long offset);
  72 extern uint cpm_dpram_phys(u8 *addr);
  73 #endif
  74
  75 extern void cpm_setbrg(uint brg, uint rate);
  76
  77 extern void cpm_load_patch(cpm8xx_t *cp);
  78
  79 extern void cpm_reset(void);
  80
  81 /* Parameter RAM offsets.
  82 */
  83 #define PROFF_SCC1      ((uint)0x0000)
  84 #define PROFF_IIC       ((uint)0x0080)
  85 #define PROFF_SCC2      ((uint)0x0100)
  86 #define PROFF_SPI       ((uint)0x0180)
  87 #define PROFF_SCC3      ((uint)0x0200)
  88 #define PROFF_SMC1      ((uint)0x0280)
  89 #define PROFF_SCC4      ((uint)0x0300)
  90 #define PROFF_SMC2      ((uint)0x0380)
  91
  92 /* Define enough so I can at least use the serial port as a UART.
  93  * The MBX uses SMC1 as the host serial port.
  94  */
  95 typedef struct smc_uart {
  96         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
  97         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
  98         u_char  smc_rfcr;       /* Rx function code */
  99         u_char  smc_tfcr;       /* Tx function code */
 100         ushort  smc_mrblr;      /* Max receive buffer length */
 101         uint    smc_rstate;     /* Internal */
 102         uint    smc_idp;        /* Internal */
 103         ushort  smc_rbptr;      /* Internal */
 104         ushort  smc_ibc;        /* Internal */
 105         uint    smc_rxtmp;      /* Internal */
 106         uint    smc_tstate;     /* Internal */
 107         uint    smc_tdp;        /* Internal */
 108         ushort  smc_tbptr;      /* Internal */
 109         ushort  smc_tbc;        /* Internal */
 110         uint    smc_txtmp;      /* Internal */
 111         ushort  smc_maxidl;     /* Maximum idle characters */
 112         ushort  smc_tmpidl;     /* Temporary idle counter */
 113         ushort  smc_brklen;     /* Last received break length */
 114         ushort  smc_brkec;      /* rcv'd break condition counter */
 115         ushort  smc_brkcr;      /* xmt break count register */
 116         ushort  smc_rmask;      /* Temporary bit mask */
 117         char    res1[8];        /* Reserved */
 118         ushort  smc_rpbase;     /* Relocation pointer */
 119 } smc_uart_t;
 120
 121 /* Function code bits.
 122 */
 123 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 124
 125 /* SMC uart mode register.
 126 */
 127 #define SMCMR_REN       ((ushort)0x0001)
 128 #define SMCMR_TEN       ((ushort)0x0002)
 129 #define SMCMR_DM        ((ushort)0x000c)
 130 #define SMCMR_SM_GCI    ((ushort)0x0000)
 131 #define SMCMR_SM_UART   ((ushort)0x0020)
 132 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 133 #define SMCMR_SM_MASK   ((ushort)0x0030)
 134 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 135 #define SMCMR_REVD      SMCMR_PM_EVEN
 136 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 137 #define SMCMR_BS        SMCMR_PEN
 138 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 139 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 140 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 141
 142 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 143  * it can only receive or transmit.  The parameter ram values for
 144  * each direction are either unique or properly overlap, so we can
 145  * include them in one structure.
 146  */
 147 typedef struct smc_centronics {
 148         ushort  scent_rbase;
 149         ushort  scent_tbase;
 150         u_char  scent_cfcr;
 151         u_char  scent_smask;
 152         ushort  scent_mrblr;
 153         uint    scent_rstate;
 154         uint    scent_r_ptr;
 155         ushort  scent_rbptr;
 156         ushort  scent_r_cnt;
 157         uint    scent_rtemp;
 158         uint    scent_tstate;
 159         uint    scent_t_ptr;
 160         ushort  scent_tbptr;
 161         ushort  scent_t_cnt;
 162         uint    scent_ttemp;
 163         ushort  scent_max_sl;
 164         ushort  scent_sl_cnt;
 165         ushort  scent_character1;
 166         ushort  scent_character2;
 167         ushort  scent_character3;
 168         ushort  scent_character4;
 169         ushort  scent_character5;
 170         ushort  scent_character6;
 171         ushort  scent_character7;
 172         ushort  scent_character8;
 173         ushort  scent_rccm;
 174         ushort  scent_rccr;
 175 } smc_cent_t;
 176
 177 /* Centronics Status Mask Register.
 178 */
 179 #define SMC_CENT_F      ((u_char)0x08)
 180 #define SMC_CENT_PE     ((u_char)0x04)
 181 #define SMC_CENT_S      ((u_char)0x02)
 182
 183 /* SMC Event and Mask register.
 184 */
 185 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 186 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 187 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 188 #define SMCM_BSY        ((unsigned char)0x04)
 189 #define SMCM_TX         ((unsigned char)0x02)
 190 #define SMCM_RX         ((unsigned char)0x01)
 191
 192 /* Baud rate generators.
 193 */
 194 #define CPM_BRG_RST             ((uint)0x00020000)
 195 #define CPM_BRG_EN              ((uint)0x00010000)
 196 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 197 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 198 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 199 #define CPM_BRG_ATB             ((uint)0x00002000)
 200 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 201 #define CPM_BRG_DIV16           ((uint)0x00000001)
 202
 203 /* SI Clock Route Register
 204 */
 205 #define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 206 #define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 207 #define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 208 #define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 209 #define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 210 #define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 211 #define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 212 #define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 213
 214 /* SCCs.
 215 */
 216 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 217 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 218 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 219 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 220 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 221 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 222 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 223 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 224 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 225 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 226 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 227 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 228 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 229 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 230 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 231 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 232 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 233 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 234 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 235 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 236
 237 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 238 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 239 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 240 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 241 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 242 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 243 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 244 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 245 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 246 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 247 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 248 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 249 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 250 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 251 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 252 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 253 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 254 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 255 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 256 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 257 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 258 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 259 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 260 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 261 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 262 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 263 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 264 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 265 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 266 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 267 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 268 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 269 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 270 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 271 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 272 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 273 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 274 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 275 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 276 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 277 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 278 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 279 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 280 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 281 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 282 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 283 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 284 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 285 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 286 #define SCC_GSMRL_MODE_QMC      ((uint)0x0000000a)
 287 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 288 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 289 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 290 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 291 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 292 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 293 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 294 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 295 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 296
 297 #define SCC_TODR_TOD            ((ushort)0x8000)
 298
 299 /* SCC Event and Mask register.
 300 */
 301 #define SCCM_TXE        ((unsigned char)0x10)
 302 #define SCCM_BSY        ((unsigned char)0x04)
 303 #define SCCM_TX         ((unsigned char)0x02)
 304 #define SCCM_RX         ((unsigned char)0x01)
 305
 306 typedef struct scc_param {
 307         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 308         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 309         u_char  scc_rfcr;       /* Rx function code */
 310         u_char  scc_tfcr;       /* Tx function code */
 311         ushort  scc_mrblr;      /* Max receive buffer length */
 312         uint    scc_rstate;     /* Internal */
 313         uint    scc_idp;        /* Internal */
 314         ushort  scc_rbptr;      /* Internal */
 315         ushort  scc_ibc;        /* Internal */
 316         uint    scc_rxtmp;      /* Internal */
 317         uint    scc_tstate;     /* Internal */
 318         uint    scc_tdp;        /* Internal */
 319         ushort  scc_tbptr;      /* Internal */
 320         ushort  scc_tbc;        /* Internal */
 321         uint    scc_txtmp;      /* Internal */
 322         uint    scc_rcrc;       /* Internal */
 323         uint    scc_tcrc;       /* Internal */
 324 } sccp_t;
 325
 326 /* Function code bits.
 327 */
 328 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 329
 330 /* CPM Ethernet through SCCx.
 331  */
 332 typedef struct scc_enet {
 333         sccp_t  sen_genscc;
 334         uint    sen_cpres;      /* Preset CRC */
 335         uint    sen_cmask;      /* Constant mask for CRC */
 336         uint    sen_crcec;      /* CRC Error counter */
 337         uint    sen_alec;       /* alignment error counter */
 338         uint    sen_disfc;      /* discard frame counter */
 339         ushort  sen_pads;       /* Tx short frame pad character */
 340         ushort  sen_retlim;     /* Retry limit threshold */
 341         ushort  sen_retcnt;     /* Retry limit counter */
 342         ushort  sen_maxflr;     /* maximum frame length register */
 343         ushort  sen_minflr;     /* minimum frame length register */
 344         ushort  sen_maxd1;      /* maximum DMA1 length */
 345         ushort  sen_maxd2;      /* maximum DMA2 length */
 346         ushort  sen_maxd;       /* Rx max DMA */
 347         ushort  sen_dmacnt;     /* Rx DMA counter */
 348         ushort  sen_maxb;       /* Max BD byte count */
 349         ushort  sen_gaddr1;     /* Group address filter */
 350         ushort  sen_gaddr2;
 351         ushort  sen_gaddr3;
 352         ushort  sen_gaddr4;
 353         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 354         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 355         uint    sen_tbuf0rba;   /* Internal */
 356         uint    sen_tbuf0crc;   /* Internal */
 357         ushort  sen_tbuf0bcnt;  /* Internal */
 358         ushort  sen_paddrh;     /* physical address (MSB) */
 359         ushort  sen_paddrm;
 360         ushort  sen_paddrl;     /* physical address (LSB) */
 361         ushort  sen_pper;       /* persistence */
 362         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 363         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 364         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 365         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 366         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 367         uint    sen_tbuf1rba;   /* Internal */
 368         uint    sen_tbuf1crc;   /* Internal */
 369         ushort  sen_tbuf1bcnt;  /* Internal */
 370         ushort  sen_txlen;      /* Tx Frame length counter */
 371         ushort  sen_iaddr1;     /* Individual address filter */
 372         ushort  sen_iaddr2;
 373         ushort  sen_iaddr3;
 374         ushort  sen_iaddr4;
 375         ushort  sen_boffcnt;    /* Backoff counter */
 376
 377         /* NOTE: Some versions of the manual have the following items
 378          * incorrectly documented.  Below is the proper order.
 379          */
 380         ushort  sen_taddrh;     /* temp address (MSB) */
 381         ushort  sen_taddrm;
 382         ushort  sen_taddrl;     /* temp address (LSB) */
 383 } scc_enet_t;
 384
 385 /* SCC Event register as used by Ethernet.
 386 */
 387 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 388 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 389 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 390 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 391 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 392 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 393
 394 /* SCC Mode Register (PMSR) as used by Ethernet.
 395 */
 396 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 397 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 398 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 399 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 400 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 401 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 402 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 403 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 404 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 405 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 406 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 407 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 408 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 409
 410 /* SCC as UART
 411 */
 412 typedef struct scc_uart {
 413         sccp_t  scc_genscc;
 414         char    res1[8];        /* Reserved */
 415         ushort  scc_maxidl;     /* Maximum idle chars */
 416         ushort  scc_idlc;       /* temp idle counter */
 417         ushort  scc_brkcr;      /* Break count register */
 418         ushort  scc_parec;      /* receive parity error counter */
 419         ushort  scc_frmec;      /* receive framing error counter */
 420         ushort  scc_nosec;      /* receive noise counter */
 421         ushort  scc_brkec;      /* receive break condition counter */
 422         ushort  scc_brkln;      /* last received break length */
 423         ushort  scc_uaddr1;     /* UART address character 1 */
 424         ushort  scc_uaddr2;     /* UART address character 2 */
 425         ushort  scc_rtemp;      /* Temp storage */
 426         ushort  scc_toseq;      /* Transmit out of sequence char */
 427         ushort  scc_char1;      /* control character 1 */
 428         ushort  scc_char2;      /* control character 2 */
 429         ushort  scc_char3;      /* control character 3 */
 430         ushort  scc_char4;      /* control character 4 */
 431         ushort  scc_char5;      /* control character 5 */
 432         ushort  scc_char6;      /* control character 6 */
 433         ushort  scc_char7;      /* control character 7 */
 434         ushort  scc_char8;      /* control character 8 */
 435         ushort  scc_rccm;       /* receive control character mask */
 436         ushort  scc_rccr;       /* receive control character register */
 437         ushort  scc_rlbc;       /* receive last break character */
 438 } scc_uart_t;
 439
 440 /* SCC Event and Mask registers when it is used as a UART.
 441 */
 442 #define UART_SCCM_GLR           ((ushort)0x1000)
 443 #define UART_SCCM_GLT           ((ushort)0x0800)
 444 #define UART_SCCM_AB            ((ushort)0x0200)
 445 #define UART_SCCM_IDL           ((ushort)0x0100)
 446 #define UART_SCCM_GRA           ((ushort)0x0080)
 447 #define UART_SCCM_BRKE          ((ushort)0x0040)
 448 #define UART_SCCM_BRKS          ((ushort)0x0020)
 449 #define UART_SCCM_CCR           ((ushort)0x0008)
 450 #define UART_SCCM_BSY           ((ushort)0x0004)
 451 #define UART_SCCM_TX            ((ushort)0x0002)
 452 #define UART_SCCM_RX            ((ushort)0x0001)
 453
 454 /* The SCC PMSR when used as a UART.
 455 */
 456 #define SCU_PSMR_FLC            ((ushort)0x8000)
 457 #define SCU_PSMR_SL             ((ushort)0x4000)
 458 #define SCU_PSMR_CL             ((ushort)0x3000)
 459 #define SCU_PSMR_UM             ((ushort)0x0c00)
 460 #define SCU_PSMR_FRZ            ((ushort)0x0200)
 461 #define SCU_PSMR_RZS            ((ushort)0x0100)
 462 #define SCU_PSMR_SYN            ((ushort)0x0080)
 463 #define SCU_PSMR_DRT            ((ushort)0x0040)
 464 #define SCU_PSMR_PEN            ((ushort)0x0010)
 465 #define SCU_PSMR_RPM            ((ushort)0x000c)
 466 #define SCU_PSMR_REVP           ((ushort)0x0008)
 467 #define SCU_PSMR_TPM            ((ushort)0x0003)
 468 #define SCU_PSMR_TEVP           ((ushort)0x0002)
 469
 470 /* CPM Transparent mode SCC.
 471  */
 472 typedef struct scc_trans {
 473         sccp_t  st_genscc;
 474         uint    st_cpres;       /* Preset CRC */
 475         uint    st_cmask;       /* Constant mask for CRC */
 476 } scc_trans_t;
 477
 478 /* IIC parameter RAM.
 479 */
 480 typedef struct iic {
 481         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
 482         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
 483         u_char  iic_rfcr;       /* Rx function code */
 484         u_char  iic_tfcr;       /* Tx function code */
 485         ushort  iic_mrblr;      /* Max receive buffer length */
 486         uint    iic_rstate;     /* Internal */
 487         uint    iic_rdp;        /* Internal */
 488         ushort  iic_rbptr;      /* Internal */
 489         ushort  iic_rbc;        /* Internal */
 490         uint    iic_rxtmp;      /* Internal */
 491         uint    iic_tstate;     /* Internal */
 492         uint    iic_tdp;        /* Internal */
 493         ushort  iic_tbptr;      /* Internal */
 494         ushort  iic_tbc;        /* Internal */
 495         uint    iic_txtmp;      /* Internal */
 496         char    res1[4];        /* Reserved */
 497         ushort  iic_rpbase;     /* Relocation pointer */
 498         char    res2[2];        /* Reserved */
 499 } iic_t;
 500
 501 /* SPI parameter RAM.
 502 */
 503 typedef struct spi {
 504         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
 505         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
 506         u_char  spi_rfcr;       /* Rx function code */
 507         u_char  spi_tfcr;       /* Tx function code */
 508         ushort  spi_mrblr;      /* Max receive buffer length */
 509         uint    spi_rstate;     /* Internal */
 510         uint    spi_rdp;        /* Internal */
 511         ushort  spi_rbptr;      /* Internal */
 512         ushort  spi_rbc;        /* Internal */
 513         uint    spi_rxtmp;      /* Internal */
 514         uint    spi_tstate;     /* Internal */
 515         uint    spi_tdp;        /* Internal */
 516         ushort  spi_tbptr;      /* Internal */
 517         ushort  spi_tbc;        /* Internal */
 518         uint    spi_txtmp;      /* Internal */
 519         uint    spi_res;
 520         ushort  spi_rpbase;     /* Relocation pointer */
 521         ushort  spi_res2;
 522 } spi_t;
 523
 524 /* SPI Mode register.
 525 */
 526 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
 527 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
 528 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
 529 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
 530 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
 531 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
 532 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
 533 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
 534 #define SPMODE_LEN4     ((ushort)0x0030)        /*  4 bits per char */
 535 #define SPMODE_LEN8     ((ushort)0x0070)        /*  8 bits per char */
 536 #define SPMODE_LEN16    ((ushort)0x00f0)        /* 16 bits per char */
 537 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
 538
 539 /* SPIE fields */
 540 #define SPIE_MME        0x20
 541 #define SPIE_TXE        0x10
 542 #define SPIE_BSY        0x04
 543 #define SPIE_TXB        0x02
 544 #define SPIE_RXB        0x01
 545
 546 /*
 547  * RISC Controller Configuration Register definitons
 548  */
 549 #define RCCR_TIME       0x8000                  /* RISC Timer Enable */
 550 #define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)       /* RISC Timer Period */
 551 #define RCCR_TIME_MASK  0x00FF                  /* not RISC Timer related bits */
 552
 553 /* RISC Timer Parameter RAM offset */
 554 #define PROFF_RTMR      ((uint)0x01B0)
 555
 556 typedef struct risc_timer_pram {
 557         unsigned short  tm_base;        /* RISC Timer Table Base Address */
 558         unsigned short  tm_ptr;         /* RISC Timer Table Pointer (internal) */
 559         unsigned short  r_tmr;          /* RISC Timer Mode Register */
 560         unsigned short  r_tmv;          /* RISC Timer Valid Register */
 561         unsigned long   tm_cmd;         /* RISC Timer Command Register */
 562         unsigned long   tm_cnt;         /* RISC Timer Internal Count */
 563 } rt_pram_t;
 564
 565 /* Bits in RISC Timer Command Register */
 566 #define TM_CMD_VALID    0x80000000      /* Valid - Enables the timer */
 567 #define TM_CMD_RESTART  0x40000000      /* Restart - for automatic restart */
 568 #define TM_CMD_PWM      0x20000000      /* Run in Pulse Width Modulation Mode */
 569 #define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
 570 #define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
 571
 572 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 573  * channels or devices.  All of these are presented to the PPC core
 574  * as a single interrupt.  The CPM interrupt handler dispatches its
 575  * own handlers, in a similar fashion to the PPC core handler.  We
 576  * use the table as defined in the manuals (i.e. no special high
 577  * priority and SCC1 == SCCa, etc...).
 578  */
 579 #define CPMVEC_NR               32
 580 #define CPMVEC_PIO_PC15         ((ushort)0x1f)
 581 #define CPMVEC_SCC1             ((ushort)0x1e)
 582 #define CPMVEC_SCC2             ((ushort)0x1d)
 583 #define CPMVEC_SCC3             ((ushort)0x1c)
 584 #define CPMVEC_SCC4             ((ushort)0x1b)
 585 #define CPMVEC_PIO_PC14         ((ushort)0x1a)
 586 #define CPMVEC_TIMER1           ((ushort)0x19)
 587 #define CPMVEC_PIO_PC13         ((ushort)0x18)
 588 #define CPMVEC_PIO_PC12         ((ushort)0x17)
 589 #define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
 590 #define CPMVEC_IDMA1            ((ushort)0x15)
 591 #define CPMVEC_IDMA2            ((ushort)0x14)
 592 #define CPMVEC_TIMER2           ((ushort)0x12)
 593 #define CPMVEC_RISCTIMER        ((ushort)0x11)
 594 #define CPMVEC_I2C              ((ushort)0x10)
 595 #define CPMVEC_PIO_PC11         ((ushort)0x0f)
 596 #define CPMVEC_PIO_PC10         ((ushort)0x0e)
 597 #define CPMVEC_TIMER3           ((ushort)0x0c)
 598 #define CPMVEC_PIO_PC9          ((ushort)0x0b)
 599 #define CPMVEC_PIO_PC8          ((ushort)0x0a)
 600 #define CPMVEC_PIO_PC7          ((ushort)0x09)
 601 #define CPMVEC_TIMER4           ((ushort)0x07)
 602 #define CPMVEC_PIO_PC6          ((ushort)0x06)
 603 #define CPMVEC_SPI              ((ushort)0x05)
 604 #define CPMVEC_SMC1             ((ushort)0x04)
 605 #define CPMVEC_SMC2             ((ushort)0x03)
 606 #define CPMVEC_PIO_PC5          ((ushort)0x02)
 607 #define CPMVEC_PIO_PC4          ((ushort)0x01)
 608 #define CPMVEC_ERROR            ((ushort)0x00)
 609
 610 /* CPM interrupt configuration vector.
 611 */
 612 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
 613 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 614 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 615 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
 616 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
 617 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
 618 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
 619 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
 620
 621 #define IMAP_ADDR               (get_immrbase())
 622
 623 #define CPM_PIN_INPUT     0
 624 #define CPM_PIN_OUTPUT    1
 625 #define CPM_PIN_PRIMARY   0
 626 #define CPM_PIN_SECONDARY 2
 627 #define CPM_PIN_GPIO      4
 628 #define CPM_PIN_OPENDRAIN 8
 629
 630 enum cpm_port {
 631         CPM_PORTA,
 632         CPM_PORTB,
 633         CPM_PORTC,
 634         CPM_PORTD,
 635         CPM_PORTE,
 636 };
 637
 638 void cpm1_set_pin(enum cpm_port port, int pin, int flags);
 639
 640 enum cpm_clk_dir {
 641         CPM_CLK_RX,
 642         CPM_CLK_TX,
 643         CPM_CLK_RTX
 644 };
 645
 646 enum cpm_clk_target {
 647         CPM_CLK_SCC1,
 648         CPM_CLK_SCC2,
 649         CPM_CLK_SCC3,
 650         CPM_CLK_SCC4,
 651         CPM_CLK_SMC1,
 652         CPM_CLK_SMC2,
 653 };
 654
 655 enum cpm_clk {
 656         CPM_BRG1,       /* Baud Rate Generator  1 */
 657         CPM_BRG2,       /* Baud Rate Generator  2 */
 658         CPM_BRG3,       /* Baud Rate Generator  3 */
 659         CPM_BRG4,       /* Baud Rate Generator  4 */
 660         CPM_CLK1,       /* Clock  1 */
 661         CPM_CLK2,       /* Clock  2 */
 662         CPM_CLK3,       /* Clock  3 */
 663         CPM_CLK4,       /* Clock  4 */
 664         CPM_CLK5,       /* Clock  5 */
 665         CPM_CLK6,       /* Clock  6 */
 666         CPM_CLK7,       /* Clock  7 */
 667         CPM_CLK8,       /* Clock  8 */
 668 };
 669
 670 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
 671
 672 #endif /* __CPM1__ */