2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kobject.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
33 #include <asm/processor.h>
34 #include <asm/uaccess.h>
40 #define MISC_MCELOG_MINOR 227
44 static int mce_dont_init
;
48 * 0: always panic on uncorrected errors, log corrected errors
49 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
50 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
51 * 3: never panic or SIGBUS, log all errors (for testing only)
53 static int tolerant
= 1;
56 static unsigned long notify_user
;
58 static int mce_bootlog
= -1;
59 static atomic_t mce_events
;
61 static char trigger
[128];
62 static char *trigger_argv
[2] = { trigger
, NULL
};
64 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
66 /* MCA banks polled by the period polling timer for corrected events */
67 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
68 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
71 /* Do initial initialization of a struct mce */
72 void mce_setup(struct mce
*m
)
74 memset(m
, 0, sizeof(struct mce
));
75 m
->cpu
= smp_processor_id();
80 * Lockless MCE logging infrastructure.
81 * This avoids deadlocks on printk locks without having to break locks. Also
82 * separate MCEs from kernel messages to avoid bogus bug reports.
85 static struct mce_log mcelog
= {
90 void mce_log(struct mce
*mce
)
94 atomic_inc(&mce_events
);
98 entry
= rcu_dereference(mcelog
.next
);
101 * When the buffer fills up discard new entries.
102 * Assume that the earlier errors are the more
105 if (entry
>= MCE_LOG_LEN
) {
106 set_bit(MCE_OVERFLOW
, (unsigned long *)&mcelog
.flags
);
109 /* Old left over entry. Skip: */
110 if (mcelog
.entry
[entry
].finished
) {
118 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
121 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
123 mcelog
.entry
[entry
].finished
= 1;
126 set_bit(0, ¬ify_user
);
129 static void print_mce(struct mce
*m
)
131 printk(KERN_EMERG
"\n"
132 KERN_EMERG
"HARDWARE ERROR\n"
134 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
135 m
->cpu
, m
->mcgstatus
, m
->bank
, m
->status
);
137 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
138 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
140 if (m
->cs
== __KERNEL_CS
)
141 print_symbol("{%s}", m
->ip
);
144 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
146 printk("ADDR %llx ", m
->addr
);
148 printk("MISC %llx ", m
->misc
);
150 printk(KERN_EMERG
"This is not a software problem!\n");
151 printk(KERN_EMERG
"Run through mcelog --ascii to decode "
152 "and contact your hardware vendor\n");
155 static void mce_panic(char *msg
, struct mce
*backup
, unsigned long start
)
160 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
161 unsigned long tsc
= mcelog
.entry
[i
].tsc
;
163 if (time_before(tsc
, start
))
165 print_mce(&mcelog
.entry
[i
]);
166 if (backup
&& mcelog
.entry
[i
].tsc
== backup
->tsc
)
174 int mce_available(struct cpuinfo_x86
*c
)
178 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
181 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
183 if (regs
&& (m
->mcgstatus
& MCG_STATUS_RIPV
)) {
191 /* Assume the RIP in the MSR is exact. Is this true? */
192 m
->mcgstatus
|= MCG_STATUS_EIPV
;
193 rdmsrl(rip_msr
, m
->ip
);
199 * Poll for corrected events or events that happened before reset.
200 * Those are just logged through /dev/mcelog.
202 * This is executed in standard interrupt context.
204 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
211 rdmsrl(MSR_IA32_MCG_STATUS
, m
.mcgstatus
);
212 for (i
= 0; i
< banks
; i
++) {
213 if (!bank
[i
] || !test_bit(i
, *b
))
222 rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4, m
.status
);
223 if (!(m
.status
& MCI_STATUS_VAL
))
227 * Uncorrected events are handled by the exception handler
228 * when it is enabled. But when the exception is disabled log
231 * TBD do the same check for MCI_STATUS_EN here?
233 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
236 if (m
.status
& MCI_STATUS_MISCV
)
237 rdmsrl(MSR_IA32_MC0_MISC
+ i
*4, m
.misc
);
238 if (m
.status
& MCI_STATUS_ADDRV
)
239 rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4, m
.addr
);
241 if (!(flags
& MCP_TIMESTAMP
))
244 * Don't get the IP here because it's unlikely to
245 * have anything to do with the actual error location.
247 if (!(flags
& MCP_DONTLOG
)) {
249 add_taint(TAINT_MACHINE_CHECK
);
253 * Clear state for this bank.
255 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
259 * Don't clear MCG_STATUS here because it's only defined for
265 * The actual machine check handler. This only handles real
266 * exceptions when something got corrupted coming in through int 18.
268 * This is executed in NMI context not subject to normal locking rules. This
269 * implies that most kernel services cannot be safely used. Don't even
270 * think about putting a printk in there!
272 void do_machine_check(struct pt_regs
*regs
, long error_code
)
274 struct mce m
, panicm
;
275 int panicm_found
= 0;
279 * If no_way_out gets set, there is no safe way to recover from this
280 * MCE. If tolerant is cranked up, we'll try anyway.
284 * If kill_it gets set, there might be a way to recover from this
288 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
290 atomic_inc(&mce_entry
);
292 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
293 18, SIGKILL
) == NOTIFY_STOP
)
300 rdmsrl(MSR_IA32_MCG_STATUS
, m
.mcgstatus
);
302 /* if the restart IP is not valid, we're done for */
303 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
309 for (i
= 0; i
< banks
; i
++) {
310 __clear_bit(i
, toclear
);
318 rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4, m
.status
);
319 if ((m
.status
& MCI_STATUS_VAL
) == 0)
323 * Non uncorrected errors are handled by machine_check_poll
326 if ((m
.status
& MCI_STATUS_UC
) == 0)
330 * Set taint even when machine check was not enabled.
332 add_taint(TAINT_MACHINE_CHECK
);
334 __set_bit(i
, toclear
);
336 if (m
.status
& MCI_STATUS_EN
) {
337 /* if PCC was set, there's no way out */
338 no_way_out
|= !!(m
.status
& MCI_STATUS_PCC
);
340 * If this error was uncorrectable and there was
341 * an overflow, we're in trouble. If no overflow,
342 * we might get away with just killing a task.
344 if (m
.status
& MCI_STATUS_UC
) {
345 if (tolerant
< 1 || m
.status
& MCI_STATUS_OVER
)
351 * Machine check event was not enabled. Clear, but
357 if (m
.status
& MCI_STATUS_MISCV
)
358 rdmsrl(MSR_IA32_MC0_MISC
+ i
*4, m
.misc
);
359 if (m
.status
& MCI_STATUS_ADDRV
)
360 rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4, m
.addr
);
362 mce_get_rip(&m
, regs
);
366 * Did this bank cause the exception?
368 * Assume that the bank with uncorrectable errors did it,
369 * and that there is only a single one:
371 if ((m
.status
& MCI_STATUS_UC
) &&
372 (m
.status
& MCI_STATUS_EN
)) {
379 * If we didn't find an uncorrectable error, pick
380 * the last one (shouldn't happen, just being safe).
386 * If we have decided that we just CAN'T continue, and the user
387 * has not set tolerant to an insane level, give up and die.
389 if (no_way_out
&& tolerant
< 3)
390 mce_panic("Machine check", &panicm
, mcestart
);
393 * If the error seems to be unrecoverable, something should be
394 * done. Try to kill as little as possible. If we can kill just
395 * one task, do that. If the user has set the tolerance very
396 * high, don't try to do anything at all.
398 if (kill_it
&& tolerant
< 3) {
402 * If the EIPV bit is set, it means the saved IP is the
403 * instruction which caused the MCE.
405 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
406 user_space
= panicm
.ip
&& (panicm
.cs
& 3);
409 * If we know that the error was in user space, send a
410 * SIGBUS. Otherwise, panic if tolerance is low.
412 * force_sig() takes an awful lot of locks and has a slight
413 * risk of deadlocking.
416 force_sig(SIGBUS
, current
);
417 } else if (panic_on_oops
|| tolerant
< 2) {
418 mce_panic("Uncorrected machine check",
423 /* notify userspace ASAP */
424 set_thread_flag(TIF_MCE_NOTIFY
);
426 /* the last thing we do is clear state */
427 for (i
= 0; i
< banks
; i
++) {
428 if (test_bit(i
, toclear
))
429 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
431 wrmsrl(MSR_IA32_MCG_STATUS
, 0);
433 atomic_dec(&mce_entry
);
436 #ifdef CONFIG_X86_MCE_INTEL
438 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
439 * @cpu: The CPU on which the event occurred.
440 * @status: Event status information
442 * This function should be called by the thermal interrupt after the
443 * event has been processed and the decision was made to log the event
446 * The status parameter will be saved to the 'status' field of 'struct mce'
447 * and historically has been the register value of the
448 * MSR_IA32_THERMAL_STATUS (Intel) msr.
450 void mce_log_therm_throt_event(__u64 status
)
455 m
.bank
= MCE_THERMAL_BANK
;
459 #endif /* CONFIG_X86_MCE_INTEL */
462 * Periodic polling timer for "silent" machine check errors. If the
463 * poller finds an MCE, poll 2x faster. When the poller finds no more
464 * errors, poll 2x slower (up to check_interval seconds).
466 static int check_interval
= 5 * 60; /* 5 minutes */
468 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
469 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
471 static void mcheck_timer(unsigned long data
)
473 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
476 WARN_ON(smp_processor_id() != data
);
478 if (mce_available(¤t_cpu_data
)) {
479 machine_check_poll(MCP_TIMESTAMP
,
480 &__get_cpu_var(mce_poll_banks
));
484 * Alert userspace if needed. If we logged an MCE, reduce the
485 * polling interval, otherwise increase the polling interval.
487 n
= &__get_cpu_var(next_interval
);
488 if (mce_notify_user()) {
489 *n
= max(*n
/2, HZ
/100);
491 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
494 t
->expires
= jiffies
+ *n
;
498 static void mce_do_trigger(struct work_struct
*work
)
500 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
503 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
506 * Notify the user(s) about new machine check events.
507 * Can be called from interrupt context, but not from machine check/NMI
510 int mce_notify_user(void)
512 /* Not more than two messages every minute */
513 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
515 clear_thread_flag(TIF_MCE_NOTIFY
);
517 if (test_and_clear_bit(0, ¬ify_user
)) {
518 wake_up_interruptible(&mce_wait
);
521 * There is no risk of missing notifications because
522 * work_pending is always cleared before the function is
525 if (trigger
[0] && !work_pending(&mce_trigger_work
))
526 schedule_work(&mce_trigger_work
);
528 if (__ratelimit(&ratelimit
))
529 printk(KERN_INFO
"Machine check events logged\n");
536 /* see if the idle task needs to notify userspace: */
538 mce_idle_callback(struct notifier_block
*nfb
, unsigned long action
,
541 /* IDLE_END should be safe - interrupts are back on */
542 if (action
== IDLE_END
&& test_thread_flag(TIF_MCE_NOTIFY
))
548 static struct notifier_block mce_idle_notifier
= {
549 .notifier_call
= mce_idle_callback
,
552 static __init
int periodic_mcheck_init(void)
554 idle_notifier_register(&mce_idle_notifier
);
557 __initcall(periodic_mcheck_init
);
560 * Initialize Machine Checks for a CPU.
562 static int mce_cap_init(void)
567 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
569 if (b
> MAX_NR_BANKS
) {
571 "MCE: Using only %u machine check banks out of %u\n",
576 /* Don't support asymmetric configurations today */
577 WARN_ON(banks
!= 0 && b
!= banks
);
580 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
583 memset(bank
, 0xff, banks
* sizeof(u64
));
586 /* Use accurate RIP reporting if available. */
587 if ((cap
& (1<<9)) && ((cap
>> 16) & 0xff) >= 9)
588 rip_msr
= MSR_IA32_MCG_EIP
;
593 static void mce_init(void *dummy
)
595 mce_banks_t all_banks
;
600 * Log the machine checks left over from the previous reset.
602 bitmap_fill(all_banks
, MAX_NR_BANKS
);
603 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
605 set_in_cr4(X86_CR4_MCE
);
607 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
609 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
611 for (i
= 0; i
< banks
; i
++) {
612 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
613 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
617 /* Add per CPU specific workarounds here */
618 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
620 /* This should be disabled by the BIOS, but isn't always */
621 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
622 if (c
->x86
== 15 && banks
> 4) {
624 * disable GART TBL walk error reporting, which
625 * trips off incorrectly with the IOMMU & 3ware
628 clear_bit(10, (unsigned long *)&bank
[4]);
630 if (c
->x86
<= 17 && mce_bootlog
< 0) {
632 * Lots of broken BIOS around that don't clear them
633 * by default and leave crap in there. Don't log:
641 static void mce_cpu_features(struct cpuinfo_x86
*c
)
643 switch (c
->x86_vendor
) {
644 case X86_VENDOR_INTEL
:
645 mce_intel_feature_init(c
);
648 mce_amd_feature_init(c
);
655 static void mce_init_timer(void)
657 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
658 int *n
= &__get_cpu_var(next_interval
);
660 *n
= check_interval
* HZ
;
663 setup_timer(t
, mcheck_timer
, smp_processor_id());
664 t
->expires
= round_jiffies(jiffies
+ *n
);
669 * Called for each booted CPU to set up machine checks.
670 * Must be called with preempt off:
672 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
674 if (!mce_available(c
))
677 if (mce_cap_init() < 0) {
689 * Character device to read and clear the MCE log.
692 static DEFINE_SPINLOCK(mce_state_lock
);
693 static int open_count
; /* #times opened */
694 static int open_exclu
; /* already open exclusive? */
696 static int mce_open(struct inode
*inode
, struct file
*file
)
699 spin_lock(&mce_state_lock
);
701 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
702 spin_unlock(&mce_state_lock
);
708 if (file
->f_flags
& O_EXCL
)
712 spin_unlock(&mce_state_lock
);
715 return nonseekable_open(inode
, file
);
718 static int mce_release(struct inode
*inode
, struct file
*file
)
720 spin_lock(&mce_state_lock
);
725 spin_unlock(&mce_state_lock
);
730 static void collect_tscs(void *data
)
732 unsigned long *cpu_tsc
= (unsigned long *)data
;
734 rdtscll(cpu_tsc
[smp_processor_id()]);
737 static DEFINE_MUTEX(mce_read_mutex
);
739 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
742 char __user
*buf
= ubuf
;
743 unsigned long *cpu_tsc
;
747 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
751 mutex_lock(&mce_read_mutex
);
752 next
= rcu_dereference(mcelog
.next
);
754 /* Only supports full reads right now */
755 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
756 mutex_unlock(&mce_read_mutex
);
765 for (i
= prev
; i
< next
; i
++) {
766 unsigned long start
= jiffies
;
768 while (!mcelog
.entry
[i
].finished
) {
769 if (time_after_eq(jiffies
, start
+ 2)) {
770 memset(mcelog
.entry
+ i
, 0,
777 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
779 buf
+= sizeof(struct mce
);
784 memset(mcelog
.entry
+ prev
, 0,
785 (next
- prev
) * sizeof(struct mce
));
787 next
= cmpxchg(&mcelog
.next
, prev
, 0);
788 } while (next
!= prev
);
793 * Collect entries that were still getting written before the
796 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
798 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
799 if (mcelog
.entry
[i
].finished
&&
800 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
801 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
804 buf
+= sizeof(struct mce
);
805 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
808 mutex_unlock(&mce_read_mutex
);
811 return err
? -EFAULT
: buf
- ubuf
;
814 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
816 poll_wait(file
, &mce_wait
, wait
);
817 if (rcu_dereference(mcelog
.next
))
818 return POLLIN
| POLLRDNORM
;
822 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
824 int __user
*p
= (int __user
*)arg
;
826 if (!capable(CAP_SYS_ADMIN
))
830 case MCE_GET_RECORD_LEN
:
831 return put_user(sizeof(struct mce
), p
);
832 case MCE_GET_LOG_LEN
:
833 return put_user(MCE_LOG_LEN
, p
);
834 case MCE_GETCLEAR_FLAGS
: {
838 flags
= mcelog
.flags
;
839 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
841 return put_user(flags
, p
);
848 static const struct file_operations mce_chrdev_ops
= {
850 .release
= mce_release
,
853 .unlocked_ioctl
= mce_ioctl
,
856 static struct miscdevice mce_log_device
= {
863 * Old style boot options parsing. Only for compatibility.
865 static int __init
mcheck_disable(char *str
)
870 __setup("nomce", mcheck_disable
);
873 * mce=off disables machine check
874 * mce=TOLERANCELEVEL (number, see above)
875 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
876 * mce=nobootlog Don't log MCEs from before booting.
878 static int __init
mcheck_enable(char *str
)
880 if (!strcmp(str
, "off"))
882 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
883 mce_bootlog
= (str
[0] == 'b');
884 else if (isdigit(str
[0]))
885 get_option(&str
, &tolerant
);
887 printk(KERN_INFO
"mce= argument %s ignored. Please use /sys\n",
893 __setup("mce=", mcheck_enable
);
900 * Disable machine checks on suspend and shutdown. We can't really handle
903 static int mce_disable(void)
907 for (i
= 0; i
< banks
; i
++)
908 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
912 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
914 return mce_disable();
917 static int mce_shutdown(struct sys_device
*dev
)
919 return mce_disable();
923 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
924 * Only one CPU is active at this time, the others get re-added later using
927 static int mce_resume(struct sys_device
*dev
)
930 mce_cpu_features(¤t_cpu_data
);
935 static void mce_cpu_restart(void *data
)
937 del_timer_sync(&__get_cpu_var(mce_timer
));
938 if (mce_available(¤t_cpu_data
))
943 /* Reinit MCEs after user configuration changes */
944 static void mce_restart(void)
946 on_each_cpu(mce_cpu_restart
, NULL
, 1);
949 static struct sysdev_class mce_sysclass
= {
950 .suspend
= mce_suspend
,
951 .shutdown
= mce_shutdown
,
952 .resume
= mce_resume
,
953 .name
= "machinecheck",
956 DEFINE_PER_CPU(struct sys_device
, device_mce
);
959 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
961 /* Why are there no generic functions for this? */
962 #define ACCESSOR(name, var, start) \
963 static ssize_t show_ ## name(struct sys_device *s, \
964 struct sysdev_attribute *attr, \
966 return sprintf(buf, "%lx\n", (unsigned long)var); \
968 static ssize_t set_ ## name(struct sys_device *s, \
969 struct sysdev_attribute *attr, \
970 const char *buf, size_t siz) { \
972 unsigned long new = simple_strtoul(buf, &end, 0); \
981 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
983 static struct sysdev_attribute
*bank_attrs
;
985 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
988 u64 b
= bank
[attr
- bank_attrs
];
990 return sprintf(buf
, "%llx\n", b
);
993 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
994 const char *buf
, size_t siz
)
997 u64
new = simple_strtoull(buf
, &end
, 0);
1002 bank
[attr
- bank_attrs
] = new;
1009 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1011 strcpy(buf
, trigger
);
1013 return strlen(trigger
) + 1;
1016 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1017 const char *buf
, size_t siz
)
1022 strncpy(trigger
, buf
, sizeof(trigger
));
1023 trigger
[sizeof(trigger
)-1] = 0;
1024 len
= strlen(trigger
);
1025 p
= strchr(trigger
, '\n');
1033 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1034 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1036 ACCESSOR(check_interval
, check_interval
, mce_restart())
1038 static struct sysdev_attribute
*mce_attributes
[] = {
1039 &attr_tolerant
.attr
, &attr_check_interval
, &attr_trigger
,
1043 static cpumask_var_t mce_device_initialized
;
1045 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1046 static __cpuinit
int mce_create_device(unsigned int cpu
)
1051 if (!mce_available(&boot_cpu_data
))
1054 memset(&per_cpu(device_mce
, cpu
).kobj
, 0, sizeof(struct kobject
));
1055 per_cpu(device_mce
, cpu
).id
= cpu
;
1056 per_cpu(device_mce
, cpu
).cls
= &mce_sysclass
;
1058 err
= sysdev_register(&per_cpu(device_mce
, cpu
));
1062 for (i
= 0; mce_attributes
[i
]; i
++) {
1063 err
= sysdev_create_file(&per_cpu(device_mce
, cpu
),
1068 for (i
= 0; i
< banks
; i
++) {
1069 err
= sysdev_create_file(&per_cpu(device_mce
, cpu
),
1074 cpumask_set_cpu(cpu
, mce_device_initialized
);
1079 sysdev_remove_file(&per_cpu(device_mce
, cpu
),
1084 sysdev_remove_file(&per_cpu(device_mce
, cpu
),
1087 sysdev_unregister(&per_cpu(device_mce
, cpu
));
1092 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1096 if (!cpumask_test_cpu(cpu
, mce_device_initialized
))
1099 for (i
= 0; mce_attributes
[i
]; i
++)
1100 sysdev_remove_file(&per_cpu(device_mce
, cpu
),
1102 for (i
= 0; i
< banks
; i
++)
1103 sysdev_remove_file(&per_cpu(device_mce
, cpu
),
1105 sysdev_unregister(&per_cpu(device_mce
, cpu
));
1106 cpumask_clear_cpu(cpu
, mce_device_initialized
);
1109 /* Make sure there are no machine checks on offlined CPUs. */
1110 static void mce_disable_cpu(void *h
)
1113 unsigned long action
= *(unsigned long *)h
;
1115 if (!mce_available(¤t_cpu_data
))
1117 if (!(action
& CPU_TASKS_FROZEN
))
1119 for (i
= 0; i
< banks
; i
++)
1120 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1123 static void mce_reenable_cpu(void *h
)
1125 unsigned long action
= *(unsigned long *)h
;
1128 if (!mce_available(¤t_cpu_data
))
1131 if (!(action
& CPU_TASKS_FROZEN
))
1133 for (i
= 0; i
< banks
; i
++)
1134 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1137 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1138 static int __cpuinit
1139 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1141 unsigned int cpu
= (unsigned long)hcpu
;
1142 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1146 case CPU_ONLINE_FROZEN
:
1147 mce_create_device(cpu
);
1148 if (threshold_cpu_callback
)
1149 threshold_cpu_callback(action
, cpu
);
1152 case CPU_DEAD_FROZEN
:
1153 if (threshold_cpu_callback
)
1154 threshold_cpu_callback(action
, cpu
);
1155 mce_remove_device(cpu
);
1157 case CPU_DOWN_PREPARE
:
1158 case CPU_DOWN_PREPARE_FROZEN
:
1160 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1162 case CPU_DOWN_FAILED
:
1163 case CPU_DOWN_FAILED_FROZEN
:
1164 t
->expires
= round_jiffies(jiffies
+
1165 __get_cpu_var(next_interval
));
1166 add_timer_on(t
, cpu
);
1167 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1170 /* intentionally ignoring frozen here */
1171 cmci_rediscover(cpu
);
1177 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1178 .notifier_call
= mce_cpu_callback
,
1181 static __init
int mce_init_banks(void)
1185 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1190 for (i
= 0; i
< banks
; i
++) {
1191 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1193 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1197 a
->attr
.mode
= 0644;
1198 a
->show
= show_bank
;
1199 a
->store
= set_bank
;
1205 kfree(bank_attrs
[i
].attr
.name
);
1212 static __init
int mce_init_device(void)
1217 if (!mce_available(&boot_cpu_data
))
1220 alloc_cpumask_var(&mce_device_initialized
, GFP_KERNEL
);
1222 err
= mce_init_banks();
1226 err
= sysdev_class_register(&mce_sysclass
);
1230 for_each_online_cpu(i
) {
1231 err
= mce_create_device(i
);
1236 register_hotcpu_notifier(&mce_cpu_notifier
);
1237 misc_register(&mce_log_device
);
1242 device_initcall(mce_init_device
);
1244 #ifdef CONFIG_X86_32
1249 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1251 /* Handle unconfigured int18 (should never happen) */
1252 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1254 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1255 smp_processor_id());
1258 /* Call the installed machine check handler for this CPU setup. */
1259 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1260 unexpected_machine_check
;
1262 /* This has to be run for each processor */
1263 void mcheck_init(struct cpuinfo_x86
*c
)
1265 if (mce_disabled
== 1)
1268 switch (c
->x86_vendor
) {
1269 case X86_VENDOR_AMD
:
1273 case X86_VENDOR_INTEL
:
1275 intel_p5_mcheck_init(c
);
1277 intel_p6_mcheck_init(c
);
1279 intel_p4_mcheck_init(c
);
1282 case X86_VENDOR_CENTAUR
:
1284 winchip_mcheck_init(c
);
1292 static int __init
mcheck_disable(char *str
)
1298 static int __init
mcheck_enable(char *str
)
1304 __setup("nomce", mcheck_disable
);
1305 __setup("mce", mcheck_enable
);
1307 #endif /* CONFIG_X86_32 */