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ACPICA: Add support to externally execute _OSI method
[linux-2.6/mini2440.git] / drivers / net / gianfar.c
blobc4af949bf860d81ffd69ce6ff6eceb9cf0c8a69a
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
32 * day be supported.
33 *
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
39 *
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. This method will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
55 * skb.
56 *
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
65 */
66
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
80 #include <linux/mm.h>
81 #include <linux/platform_device.h>
82 #include <linux/ip.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
85 #include <linux/in.h>
86
87 #include <asm/io.h>
88 #include <asm/irq.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
95
96 #include "gianfar.h"
97 #include "gianfar_mii.h"
98
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct platform_device *pdev);
123 static int gfar_remove(struct platform_device *pdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
135 static void gfar_vlan_rx_register(struct net_device *netdev,
136 struct vlan_group *grp);
137 void gfar_halt(struct net_device *dev);
138 static void gfar_halt_nodisable(struct net_device *dev);
139 void gfar_start(struct net_device *dev);
140 static void gfar_clear_exact_match(struct net_device *dev);
141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
142
143 extern const struct ethtool_ops gfar_ethtool_ops;
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 /* Returns 1 if incoming frames use an FCB */
150 static inline int gfar_uses_fcb(struct gfar_private *priv)
151 {
152 return (priv->vlan_enable || priv->rx_csum_enable);
153 }
154
155 /* Set up the ethernet device structure, private data,
156 * and anything else we need before we start */
157 static int gfar_probe(struct platform_device *pdev)
158 {
159 u32 tempval;
160 struct net_device *dev = NULL;
161 struct gfar_private *priv = NULL;
162 struct gianfar_platform_data *einfo;
163 struct resource *r;
164 int err = 0, irq;
165 DECLARE_MAC_BUF(mac);
166
167 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
168
169 if (NULL == einfo) {
170 printk(KERN_ERR "gfar %d: Missing additional data!\n",
171 pdev->id);
172
173 return -ENODEV;
174 }
175
176 /* Create an ethernet device instance */
177 dev = alloc_etherdev(sizeof (*priv));
178
179 if (NULL == dev)
180 return -ENOMEM;
181
182 priv = netdev_priv(dev);
183 priv->dev = dev;
184
185 /* Set the info in the priv to the current info */
186 priv->einfo = einfo;
187
188 /* fill out IRQ fields */
189 if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
190 irq = platform_get_irq_byname(pdev, "tx");
191 if (irq < 0)
192 goto regs_fail;
193 priv->interruptTransmit = irq;
194
195 irq = platform_get_irq_byname(pdev, "rx");
196 if (irq < 0)
197 goto regs_fail;
198 priv->interruptReceive = irq;
199
200 irq = platform_get_irq_byname(pdev, "error");
201 if (irq < 0)
202 goto regs_fail;
203 priv->interruptError = irq;
204 } else {
205 irq = platform_get_irq(pdev, 0);
206 if (irq < 0)
207 goto regs_fail;
208 priv->interruptTransmit = irq;
209 }
210
211 /* get a pointer to the register memory */
212 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
213 priv->regs = ioremap(r->start, sizeof (struct gfar));
214
215 if (NULL == priv->regs) {
216 err = -ENOMEM;
217 goto regs_fail;
218 }
219
220 spin_lock_init(&priv->txlock);
221 spin_lock_init(&priv->rxlock);
222 spin_lock_init(&priv->bflock);
223 INIT_WORK(&priv->reset_task, gfar_reset_task);
224
225 platform_set_drvdata(pdev, dev);
226
227 /* Stop the DMA engine now, in case it was running before */
228 /* (The firmware could have used it, and left it running). */
229 /* To do this, we write Graceful Receive Stop and Graceful */
230 /* Transmit Stop, and then wait until the corresponding bits */
231 /* in IEVENT indicate the stops have completed. */
232 tempval = gfar_read(&priv->regs->dmactrl);
233 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
234 gfar_write(&priv->regs->dmactrl, tempval);
235
236 tempval = gfar_read(&priv->regs->dmactrl);
237 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
238 gfar_write(&priv->regs->dmactrl, tempval);
239
240 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
241 cpu_relax();
242
243 /* Reset MAC layer */
244 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
245
246 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
247 gfar_write(&priv->regs->maccfg1, tempval);
248
249 /* Initialize MACCFG2. */
250 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
251
252 /* Initialize ECNTRL */
253 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
254
255 /* Copy the station address into the dev structure, */
256 memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
257
258 /* Set the dev->base_addr to the gfar reg region */
259 dev->base_addr = (unsigned long) (priv->regs);
260
261 SET_NETDEV_DEV(dev, &pdev->dev);
262
263 /* Fill in the dev structure */
264 dev->open = gfar_enet_open;
265 dev->hard_start_xmit = gfar_start_xmit;
266 dev->tx_timeout = gfar_timeout;
267 dev->watchdog_timeo = TX_TIMEOUT;
268 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
269 #ifdef CONFIG_NET_POLL_CONTROLLER
270 dev->poll_controller = gfar_netpoll;
271 #endif
272 dev->stop = gfar_close;
273 dev->change_mtu = gfar_change_mtu;
274 dev->mtu = 1500;
275 dev->set_multicast_list = gfar_set_multi;
276
277 dev->ethtool_ops = &gfar_ethtool_ops;
278
279 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
280 priv->rx_csum_enable = 1;
281 dev->features |= NETIF_F_IP_CSUM;
282 } else
283 priv->rx_csum_enable = 0;
284
285 priv->vlgrp = NULL;
286
287 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
288 dev->vlan_rx_register = gfar_vlan_rx_register;
289
290 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
291
292 priv->vlan_enable = 1;
293 }
294
295 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
296 priv->extended_hash = 1;
297 priv->hash_width = 9;
298
299 priv->hash_regs[0] = &priv->regs->igaddr0;
300 priv->hash_regs[1] = &priv->regs->igaddr1;
301 priv->hash_regs[2] = &priv->regs->igaddr2;
302 priv->hash_regs[3] = &priv->regs->igaddr3;
303 priv->hash_regs[4] = &priv->regs->igaddr4;
304 priv->hash_regs[5] = &priv->regs->igaddr5;
305 priv->hash_regs[6] = &priv->regs->igaddr6;
306 priv->hash_regs[7] = &priv->regs->igaddr7;
307 priv->hash_regs[8] = &priv->regs->gaddr0;
308 priv->hash_regs[9] = &priv->regs->gaddr1;
309 priv->hash_regs[10] = &priv->regs->gaddr2;
310 priv->hash_regs[11] = &priv->regs->gaddr3;
311 priv->hash_regs[12] = &priv->regs->gaddr4;
312 priv->hash_regs[13] = &priv->regs->gaddr5;
313 priv->hash_regs[14] = &priv->regs->gaddr6;
314 priv->hash_regs[15] = &priv->regs->gaddr7;
315
316 } else {
317 priv->extended_hash = 0;
318 priv->hash_width = 8;
319
320 priv->hash_regs[0] = &priv->regs->gaddr0;
321 priv->hash_regs[1] = &priv->regs->gaddr1;
322 priv->hash_regs[2] = &priv->regs->gaddr2;
323 priv->hash_regs[3] = &priv->regs->gaddr3;
324 priv->hash_regs[4] = &priv->regs->gaddr4;
325 priv->hash_regs[5] = &priv->regs->gaddr5;
326 priv->hash_regs[6] = &priv->regs->gaddr6;
327 priv->hash_regs[7] = &priv->regs->gaddr7;
328 }
329
330 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
331 priv->padding = DEFAULT_PADDING;
332 else
333 priv->padding = 0;
334
335 if (dev->features & NETIF_F_IP_CSUM)
336 dev->hard_header_len += GMAC_FCB_LEN;
337
338 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
339 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
340 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
341
342 priv->txcoalescing = DEFAULT_TX_COALESCE;
343 priv->txcount = DEFAULT_TXCOUNT;
344 priv->txtime = DEFAULT_TXTIME;
345 priv->rxcoalescing = DEFAULT_RX_COALESCE;
346 priv->rxcount = DEFAULT_RXCOUNT;
347 priv->rxtime = DEFAULT_RXTIME;
348
349 /* Enable most messages by default */
350 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
351
352 /* Carrier starts down, phylib will bring it up */
353 netif_carrier_off(dev);
354
355 err = register_netdev(dev);
356
357 if (err) {
358 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
359 dev->name);
360 goto register_fail;
361 }
362
363 /* Create all the sysfs files */
364 gfar_init_sysfs(dev);
365
366 /* Print out the device info */
367 printk(KERN_INFO DEVICE_NAME "%s\n",
368 dev->name, print_mac(mac, dev->dev_addr));
369
370 /* Even more device info helps when determining which kernel */
371 /* provided which set of benchmarks. */
372 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
373 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
374 dev->name, priv->rx_ring_size, priv->tx_ring_size);
375
376 return 0;
377
378 register_fail:
379 iounmap(priv->regs);
380 regs_fail:
381 free_netdev(dev);
382 return err;
383 }
384
385 static int gfar_remove(struct platform_device *pdev)
386 {
387 struct net_device *dev = platform_get_drvdata(pdev);
388 struct gfar_private *priv = netdev_priv(dev);
389
390 platform_set_drvdata(pdev, NULL);
391
392 iounmap(priv->regs);
393 free_netdev(dev);
394
395 return 0;
396 }
397
398 #ifdef CONFIG_PM
399 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
400 {
401 struct net_device *dev = platform_get_drvdata(pdev);
402 struct gfar_private *priv = netdev_priv(dev);
403 unsigned long flags;
404 u32 tempval;
405
406 int magic_packet = priv->wol_en &&
407 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
408
409 netif_device_detach(dev);
410
411 if (netif_running(dev)) {
412 spin_lock_irqsave(&priv->txlock, flags);
413 spin_lock(&priv->rxlock);
414
415 gfar_halt_nodisable(dev);
416
417 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
418 tempval = gfar_read(&priv->regs->maccfg1);
419
420 tempval &= ~MACCFG1_TX_EN;
421
422 if (!magic_packet)
423 tempval &= ~MACCFG1_RX_EN;
424
425 gfar_write(&priv->regs->maccfg1, tempval);
426
427 spin_unlock(&priv->rxlock);
428 spin_unlock_irqrestore(&priv->txlock, flags);
429
430 napi_disable(&priv->napi);
431
432 if (magic_packet) {
433 /* Enable interrupt on Magic Packet */
434 gfar_write(&priv->regs->imask, IMASK_MAG);
435
436 /* Enable Magic Packet mode */
437 tempval = gfar_read(&priv->regs->maccfg2);
438 tempval |= MACCFG2_MPEN;
439 gfar_write(&priv->regs->maccfg2, tempval);
440 } else {
441 phy_stop(priv->phydev);
442 }
443 }
444
445 return 0;
446 }
447
448 static int gfar_resume(struct platform_device *pdev)
449 {
450 struct net_device *dev = platform_get_drvdata(pdev);
451 struct gfar_private *priv = netdev_priv(dev);
452 unsigned long flags;
453 u32 tempval;
454 int magic_packet = priv->wol_en &&
455 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
456
457 if (!netif_running(dev)) {
458 netif_device_attach(dev);
459 return 0;
460 }
461
462 if (!magic_packet && priv->phydev)
463 phy_start(priv->phydev);
464
465 /* Disable Magic Packet mode, in case something
466 * else woke us up.
467 */
468
469 spin_lock_irqsave(&priv->txlock, flags);
470 spin_lock(&priv->rxlock);
471
472 tempval = gfar_read(&priv->regs->maccfg2);
473 tempval &= ~MACCFG2_MPEN;
474 gfar_write(&priv->regs->maccfg2, tempval);
475
476 gfar_start(dev);
477
478 spin_unlock(&priv->rxlock);
479 spin_unlock_irqrestore(&priv->txlock, flags);
480
481 netif_device_attach(dev);
482
483 napi_enable(&priv->napi);
484
485 return 0;
486 }
487 #else
488 #define gfar_suspend NULL
489 #define gfar_resume NULL
490 #endif
491
492 /* Reads the controller's registers to determine what interface
493 * connects it to the PHY.
494 */
495 static phy_interface_t gfar_get_interface(struct net_device *dev)
496 {
497 struct gfar_private *priv = netdev_priv(dev);
498 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
499
500 if (ecntrl & ECNTRL_SGMII_MODE)
501 return PHY_INTERFACE_MODE_SGMII;
502
503 if (ecntrl & ECNTRL_TBI_MODE) {
504 if (ecntrl & ECNTRL_REDUCED_MODE)
505 return PHY_INTERFACE_MODE_RTBI;
506 else
507 return PHY_INTERFACE_MODE_TBI;
508 }
509
510 if (ecntrl & ECNTRL_REDUCED_MODE) {
511 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
512 return PHY_INTERFACE_MODE_RMII;
513 else {
514 phy_interface_t interface = priv->einfo->interface;
515
516 /*
517 * This isn't autodetected right now, so it must
518 * be set by the device tree or platform code.
519 */
520 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
521 return PHY_INTERFACE_MODE_RGMII_ID;
522
523 return PHY_INTERFACE_MODE_RGMII;
524 }
525 }
526
527 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
528 return PHY_INTERFACE_MODE_GMII;
529
530 return PHY_INTERFACE_MODE_MII;
531 }
532
533
534 /* Initializes driver's PHY state, and attaches to the PHY.
535 * Returns 0 on success.
536 */
537 static int init_phy(struct net_device *dev)
538 {
539 struct gfar_private *priv = netdev_priv(dev);
540 uint gigabit_support =
541 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
542 SUPPORTED_1000baseT_Full : 0;
543 struct phy_device *phydev;
544 char phy_id[BUS_ID_SIZE];
545 phy_interface_t interface;
546
547 priv->oldlink = 0;
548 priv->oldspeed = 0;
549 priv->oldduplex = -1;
550
551 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
552
553 interface = gfar_get_interface(dev);
554
555 phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
556
557 if (interface == PHY_INTERFACE_MODE_SGMII)
558 gfar_configure_serdes(dev);
559
560 if (IS_ERR(phydev)) {
561 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
562 return PTR_ERR(phydev);
563 }
564
565 /* Remove any features not supported by the controller */
566 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
567 phydev->advertising = phydev->supported;
568
569 priv->phydev = phydev;
570
571 return 0;
572 }
573
574 /*
575 * Initialize TBI PHY interface for communicating with the
576 * SERDES lynx PHY on the chip. We communicate with this PHY
577 * through the MDIO bus on each controller, treating it as a
578 * "normal" PHY at the address found in the TBIPA register. We assume
579 * that the TBIPA register is valid. Either the MDIO bus code will set
580 * it to a value that doesn't conflict with other PHYs on the bus, or the
581 * value doesn't matter, as there are no other PHYs on the bus.
582 */
583 static void gfar_configure_serdes(struct net_device *dev)
584 {
585 struct gfar_private *priv = netdev_priv(dev);
586 struct gfar_mii __iomem *regs =
587 (void __iomem *)&priv->regs->gfar_mii_regs;
588 int tbipa = gfar_read(&priv->regs->tbipa);
589 struct mii_bus *bus = gfar_get_miibus(priv);
590
591 if (bus)
592 mutex_lock(&bus->mdio_lock);
593
594 /* If the link is already up, we must already be ok, and don't need to
595 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
596 * everything for us? Resetting it takes the link down and requires
597 * several seconds for it to come back.
598 */
599 if (gfar_local_mdio_read(regs, tbipa, MII_BMSR) & BMSR_LSTATUS)
600 goto done;
601
602 /* Single clk mode, mii mode off(for serdes communication) */
603 gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
604
605 gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
606 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
607 ADVERTISE_1000XPSE_ASYM);
608
609 gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
610 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
611
612 done:
613 if (bus)
614 mutex_unlock(&bus->mdio_lock);
615 }
616
617 static void init_registers(struct net_device *dev)
618 {
619 struct gfar_private *priv = netdev_priv(dev);
620
621 /* Clear IEVENT */
622 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
623
624 /* Initialize IMASK */
625 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
626
627 /* Init hash registers to zero */
628 gfar_write(&priv->regs->igaddr0, 0);
629 gfar_write(&priv->regs->igaddr1, 0);
630 gfar_write(&priv->regs->igaddr2, 0);
631 gfar_write(&priv->regs->igaddr3, 0);
632 gfar_write(&priv->regs->igaddr4, 0);
633 gfar_write(&priv->regs->igaddr5, 0);
634 gfar_write(&priv->regs->igaddr6, 0);
635 gfar_write(&priv->regs->igaddr7, 0);
636
637 gfar_write(&priv->regs->gaddr0, 0);
638 gfar_write(&priv->regs->gaddr1, 0);
639 gfar_write(&priv->regs->gaddr2, 0);
640 gfar_write(&priv->regs->gaddr3, 0);
641 gfar_write(&priv->regs->gaddr4, 0);
642 gfar_write(&priv->regs->gaddr5, 0);
643 gfar_write(&priv->regs->gaddr6, 0);
644 gfar_write(&priv->regs->gaddr7, 0);
645
646 /* Zero out the rmon mib registers if it has them */
647 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
648 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
649
650 /* Mask off the CAM interrupts */
651 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
652 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
653 }
654
655 /* Initialize the max receive buffer length */
656 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
657
658 /* Initialize the Minimum Frame Length Register */
659 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
660 }
661
662
663 /* Halt the receive and transmit queues */
664 static void gfar_halt_nodisable(struct net_device *dev)
665 {
666 struct gfar_private *priv = netdev_priv(dev);
667 struct gfar __iomem *regs = priv->regs;
668 u32 tempval;
669
670 /* Mask all interrupts */
671 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
672
673 /* Clear all interrupts */
674 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
675
676 /* Stop the DMA, and wait for it to stop */
677 tempval = gfar_read(&priv->regs->dmactrl);
678 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
679 != (DMACTRL_GRS | DMACTRL_GTS)) {
680 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
681 gfar_write(&priv->regs->dmactrl, tempval);
682
683 while (!(gfar_read(&priv->regs->ievent) &
684 (IEVENT_GRSC | IEVENT_GTSC)))
685 cpu_relax();
686 }
687 }
688
689 /* Halt the receive and transmit queues */
690 void gfar_halt(struct net_device *dev)
691 {
692 struct gfar_private *priv = netdev_priv(dev);
693 struct gfar __iomem *regs = priv->regs;
694 u32 tempval;
695
696 gfar_halt_nodisable(dev);
697
698 /* Disable Rx and Tx */
699 tempval = gfar_read(&regs->maccfg1);
700 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
701 gfar_write(&regs->maccfg1, tempval);
702 }
703
704 void stop_gfar(struct net_device *dev)
705 {
706 struct gfar_private *priv = netdev_priv(dev);
707 struct gfar __iomem *regs = priv->regs;
708 unsigned long flags;
709
710 phy_stop(priv->phydev);
711
712 /* Lock it down */
713 spin_lock_irqsave(&priv->txlock, flags);
714 spin_lock(&priv->rxlock);
715
716 gfar_halt(dev);
717
718 spin_unlock(&priv->rxlock);
719 spin_unlock_irqrestore(&priv->txlock, flags);
720
721 /* Free the IRQs */
722 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
723 free_irq(priv->interruptError, dev);
724 free_irq(priv->interruptTransmit, dev);
725 free_irq(priv->interruptReceive, dev);
726 } else {
727 free_irq(priv->interruptTransmit, dev);
728 }
729
730 free_skb_resources(priv);
731
732 dma_free_coherent(&dev->dev,
733 sizeof(struct txbd8)*priv->tx_ring_size
734 + sizeof(struct rxbd8)*priv->rx_ring_size,
735 priv->tx_bd_base,
736 gfar_read(&regs->tbase0));
737 }
738
739 /* If there are any tx skbs or rx skbs still around, free them.
740 * Then free tx_skbuff and rx_skbuff */
741 static void free_skb_resources(struct gfar_private *priv)
742 {
743 struct rxbd8 *rxbdp;
744 struct txbd8 *txbdp;
745 int i;
746
747 /* Go through all the buffer descriptors and free their data buffers */
748 txbdp = priv->tx_bd_base;
749
750 for (i = 0; i < priv->tx_ring_size; i++) {
751
752 if (priv->tx_skbuff[i]) {
753 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
754 txbdp->length,
755 DMA_TO_DEVICE);
756 dev_kfree_skb_any(priv->tx_skbuff[i]);
757 priv->tx_skbuff[i] = NULL;
758 }
759
760 txbdp++;
761 }
762
763 kfree(priv->tx_skbuff);
764
765 rxbdp = priv->rx_bd_base;
766
767 /* rx_skbuff is not guaranteed to be allocated, so only
768 * free it and its contents if it is allocated */
769 if(priv->rx_skbuff != NULL) {
770 for (i = 0; i < priv->rx_ring_size; i++) {
771 if (priv->rx_skbuff[i]) {
772 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
773 priv->rx_buffer_size,
774 DMA_FROM_DEVICE);
775
776 dev_kfree_skb_any(priv->rx_skbuff[i]);
777 priv->rx_skbuff[i] = NULL;
778 }
779
780 rxbdp->status = 0;
781 rxbdp->length = 0;
782 rxbdp->bufPtr = 0;
783
784 rxbdp++;
785 }
786
787 kfree(priv->rx_skbuff);
788 }
789 }
790
791 void gfar_start(struct net_device *dev)
792 {
793 struct gfar_private *priv = netdev_priv(dev);
794 struct gfar __iomem *regs = priv->regs;
795 u32 tempval;
796
797 /* Enable Rx and Tx in MACCFG1 */
798 tempval = gfar_read(&regs->maccfg1);
799 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
800 gfar_write(&regs->maccfg1, tempval);
801
802 /* Initialize DMACTRL to have WWR and WOP */
803 tempval = gfar_read(&priv->regs->dmactrl);
804 tempval |= DMACTRL_INIT_SETTINGS;
805 gfar_write(&priv->regs->dmactrl, tempval);
806
807 /* Make sure we aren't stopped */
808 tempval = gfar_read(&priv->regs->dmactrl);
809 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
810 gfar_write(&priv->regs->dmactrl, tempval);
811
812 /* Clear THLT/RHLT, so that the DMA starts polling now */
813 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
814 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
815
816 /* Unmask the interrupts we look for */
817 gfar_write(&regs->imask, IMASK_DEFAULT);
818 }
819
820 /* Bring the controller up and running */
821 int startup_gfar(struct net_device *dev)
822 {
823 struct txbd8 *txbdp;
824 struct rxbd8 *rxbdp;
825 dma_addr_t addr = 0;
826 unsigned long vaddr;
827 int i;
828 struct gfar_private *priv = netdev_priv(dev);
829 struct gfar __iomem *regs = priv->regs;
830 int err = 0;
831 u32 rctrl = 0;
832 u32 attrs = 0;
833
834 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
835
836 /* Allocate memory for the buffer descriptors */
837 vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
838 sizeof (struct txbd8) * priv->tx_ring_size +
839 sizeof (struct rxbd8) * priv->rx_ring_size,
840 &addr, GFP_KERNEL);
841
842 if (vaddr == 0) {
843 if (netif_msg_ifup(priv))
844 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
845 dev->name);
846 return -ENOMEM;
847 }
848
849 priv->tx_bd_base = (struct txbd8 *) vaddr;
850
851 /* enet DMA only understands physical addresses */
852 gfar_write(&regs->tbase0, addr);
853
854 /* Start the rx descriptor ring where the tx ring leaves off */
855 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
856 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
857 priv->rx_bd_base = (struct rxbd8 *) vaddr;
858 gfar_write(&regs->rbase0, addr);
859
860 /* Setup the skbuff rings */
861 priv->tx_skbuff =
862 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
863 priv->tx_ring_size, GFP_KERNEL);
864
865 if (NULL == priv->tx_skbuff) {
866 if (netif_msg_ifup(priv))
867 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
868 dev->name);
869 err = -ENOMEM;
870 goto tx_skb_fail;
871 }
872
873 for (i = 0; i < priv->tx_ring_size; i++)
874 priv->tx_skbuff[i] = NULL;
875
876 priv->rx_skbuff =
877 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
878 priv->rx_ring_size, GFP_KERNEL);
879
880 if (NULL == priv->rx_skbuff) {
881 if (netif_msg_ifup(priv))
882 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
883 dev->name);
884 err = -ENOMEM;
885 goto rx_skb_fail;
886 }
887
888 for (i = 0; i < priv->rx_ring_size; i++)
889 priv->rx_skbuff[i] = NULL;
890
891 /* Initialize some variables in our dev structure */
892 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
893 priv->cur_rx = priv->rx_bd_base;
894 priv->skb_curtx = priv->skb_dirtytx = 0;
895 priv->skb_currx = 0;
896
897 /* Initialize Transmit Descriptor Ring */
898 txbdp = priv->tx_bd_base;
899 for (i = 0; i < priv->tx_ring_size; i++) {
900 txbdp->status = 0;
901 txbdp->length = 0;
902 txbdp->bufPtr = 0;
903 txbdp++;
904 }
905
906 /* Set the last descriptor in the ring to indicate wrap */
907 txbdp--;
908 txbdp->status |= TXBD_WRAP;
909
910 rxbdp = priv->rx_bd_base;
911 for (i = 0; i < priv->rx_ring_size; i++) {
912 struct sk_buff *skb;
913
914 skb = gfar_new_skb(dev);
915
916 if (!skb) {
917 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
918 dev->name);
919
920 goto err_rxalloc_fail;
921 }
922
923 priv->rx_skbuff[i] = skb;
924
925 gfar_new_rxbdp(dev, rxbdp, skb);
926
927 rxbdp++;
928 }
929
930 /* Set the last descriptor in the ring to wrap */
931 rxbdp--;
932 rxbdp->status |= RXBD_WRAP;
933
934 /* If the device has multiple interrupts, register for
935 * them. Otherwise, only register for the one */
936 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
937 /* Install our interrupt handlers for Error,
938 * Transmit, and Receive */
939 if (request_irq(priv->interruptError, gfar_error,
940 0, "enet_error", dev) < 0) {
941 if (netif_msg_intr(priv))
942 printk(KERN_ERR "%s: Can't get IRQ %d\n",
943 dev->name, priv->interruptError);
944
945 err = -1;
946 goto err_irq_fail;
947 }
948
949 if (request_irq(priv->interruptTransmit, gfar_transmit,
950 0, "enet_tx", dev) < 0) {
951 if (netif_msg_intr(priv))
952 printk(KERN_ERR "%s: Can't get IRQ %d\n",
953 dev->name, priv->interruptTransmit);
954
955 err = -1;
956
957 goto tx_irq_fail;
958 }
959
960 if (request_irq(priv->interruptReceive, gfar_receive,
961 0, "enet_rx", dev) < 0) {
962 if (netif_msg_intr(priv))
963 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
964 dev->name, priv->interruptReceive);
965
966 err = -1;
967 goto rx_irq_fail;
968 }
969 } else {
970 if (request_irq(priv->interruptTransmit, gfar_interrupt,
971 0, "gfar_interrupt", dev) < 0) {
972 if (netif_msg_intr(priv))
973 printk(KERN_ERR "%s: Can't get IRQ %d\n",
974 dev->name, priv->interruptError);
975
976 err = -1;
977 goto err_irq_fail;
978 }
979 }
980
981 phy_start(priv->phydev);
982
983 /* Configure the coalescing support */
984 if (priv->txcoalescing)
985 gfar_write(&regs->txic,
986 mk_ic_value(priv->txcount, priv->txtime));
987 else
988 gfar_write(&regs->txic, 0);
989
990 if (priv->rxcoalescing)
991 gfar_write(&regs->rxic,
992 mk_ic_value(priv->rxcount, priv->rxtime));
993 else
994 gfar_write(&regs->rxic, 0);
995
996 if (priv->rx_csum_enable)
997 rctrl |= RCTRL_CHECKSUMMING;
998
999 if (priv->extended_hash) {
1000 rctrl |= RCTRL_EXTHASH;
1001
1002 gfar_clear_exact_match(dev);
1003 rctrl |= RCTRL_EMEN;
1004 }
1005
1006 if (priv->vlan_enable)
1007 rctrl |= RCTRL_VLAN;
1008
1009 if (priv->padding) {
1010 rctrl &= ~RCTRL_PAL_MASK;
1011 rctrl |= RCTRL_PADDING(priv->padding);
1012 }
1013
1014 /* Init rctrl based on our settings */
1015 gfar_write(&priv->regs->rctrl, rctrl);
1016
1017 if (dev->features & NETIF_F_IP_CSUM)
1018 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1019
1020 /* Set the extraction length and index */
1021 attrs = ATTRELI_EL(priv->rx_stash_size) |
1022 ATTRELI_EI(priv->rx_stash_index);
1023
1024 gfar_write(&priv->regs->attreli, attrs);
1025
1026 /* Start with defaults, and add stashing or locking
1027 * depending on the approprate variables */
1028 attrs = ATTR_INIT_SETTINGS;
1029
1030 if (priv->bd_stash_en)
1031 attrs |= ATTR_BDSTASH;
1032
1033 if (priv->rx_stash_size != 0)
1034 attrs |= ATTR_BUFSTASH;
1035
1036 gfar_write(&priv->regs->attr, attrs);
1037
1038 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1039 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1040 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1041
1042 /* Start the controller */
1043 gfar_start(dev);
1044
1045 return 0;
1046
1047 rx_irq_fail:
1048 free_irq(priv->interruptTransmit, dev);
1049 tx_irq_fail:
1050 free_irq(priv->interruptError, dev);
1051 err_irq_fail:
1052 err_rxalloc_fail:
1053 rx_skb_fail:
1054 free_skb_resources(priv);
1055 tx_skb_fail:
1056 dma_free_coherent(&dev->dev,
1057 sizeof(struct txbd8)*priv->tx_ring_size
1058 + sizeof(struct rxbd8)*priv->rx_ring_size,
1059 priv->tx_bd_base,
1060 gfar_read(&regs->tbase0));
1061
1062 return err;
1063 }
1064
1065 /* Called when something needs to use the ethernet device */
1066 /* Returns 0 for success. */
1067 static int gfar_enet_open(struct net_device *dev)
1068 {
1069 struct gfar_private *priv = netdev_priv(dev);
1070 int err;
1071
1072 napi_enable(&priv->napi);
1073
1074 /* Initialize a bunch of registers */
1075 init_registers(dev);
1076
1077 gfar_set_mac_address(dev);
1078
1079 err = init_phy(dev);
1080
1081 if(err) {
1082 napi_disable(&priv->napi);
1083 return err;
1084 }
1085
1086 err = startup_gfar(dev);
1087 if (err) {
1088 napi_disable(&priv->napi);
1089 return err;
1090 }
1091
1092 netif_start_queue(dev);
1093
1094 return err;
1095 }
1096
1097 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1098 {
1099 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1100
1101 memset(fcb, 0, GMAC_FCB_LEN);
1102
1103 return fcb;
1104 }
1105
1106 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1107 {
1108 u8 flags = 0;
1109
1110 /* If we're here, it's a IP packet with a TCP or UDP
1111 * payload. We set it to checksum, using a pseudo-header
1112 * we provide
1113 */
1114 flags = TXFCB_DEFAULT;
1115
1116 /* Tell the controller what the protocol is */
1117 /* And provide the already calculated phcs */
1118 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1119 flags |= TXFCB_UDP;
1120 fcb->phcs = udp_hdr(skb)->check;
1121 } else
1122 fcb->phcs = tcp_hdr(skb)->check;
1123
1124 /* l3os is the distance between the start of the
1125 * frame (skb->data) and the start of the IP hdr.
1126 * l4os is the distance between the start of the
1127 * l3 hdr and the l4 hdr */
1128 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1129 fcb->l4os = skb_network_header_len(skb);
1130
1131 fcb->flags = flags;
1132 }
1133
1134 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1135 {
1136 fcb->flags |= TXFCB_VLN;
1137 fcb->vlctl = vlan_tx_tag_get(skb);
1138 }
1139
1140 /* This is called by the kernel when a frame is ready for transmission. */
1141 /* It is pointed to by the dev->hard_start_xmit function pointer */
1142 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1143 {
1144 struct gfar_private *priv = netdev_priv(dev);
1145 struct txfcb *fcb = NULL;
1146 struct txbd8 *txbdp;
1147 u16 status;
1148 unsigned long flags;
1149
1150 /* Update transmit stats */
1151 dev->stats.tx_bytes += skb->len;
1152
1153 /* Lock priv now */
1154 spin_lock_irqsave(&priv->txlock, flags);
1155
1156 /* Point at the first free tx descriptor */
1157 txbdp = priv->cur_tx;
1158
1159 /* Clear all but the WRAP status flags */
1160 status = txbdp->status & TXBD_WRAP;
1161
1162 /* Set up checksumming */
1163 if (likely((dev->features & NETIF_F_IP_CSUM)
1164 && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1165 fcb = gfar_add_fcb(skb, txbdp);
1166 status |= TXBD_TOE;
1167 gfar_tx_checksum(skb, fcb);
1168 }
1169
1170 if (priv->vlan_enable &&
1171 unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1172 if (unlikely(NULL == fcb)) {
1173 fcb = gfar_add_fcb(skb, txbdp);
1174 status |= TXBD_TOE;
1175 }
1176
1177 gfar_tx_vlan(skb, fcb);
1178 }
1179
1180 /* Set buffer length and pointer */
1181 txbdp->length = skb->len;
1182 txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1183 skb->len, DMA_TO_DEVICE);
1184
1185 /* Save the skb pointer so we can free it later */
1186 priv->tx_skbuff[priv->skb_curtx] = skb;
1187
1188 /* Update the current skb pointer (wrapping if this was the last) */
1189 priv->skb_curtx =
1190 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1191
1192 /* Flag the BD as interrupt-causing */
1193 status |= TXBD_INTERRUPT;
1194
1195 /* Flag the BD as ready to go, last in frame, and */
1196 /* in need of CRC */
1197 status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1198
1199 dev->trans_start = jiffies;
1200
1201 /* The powerpc-specific eieio() is used, as wmb() has too strong
1202 * semantics (it requires synchronization between cacheable and
1203 * uncacheable mappings, which eieio doesn't provide and which we
1204 * don't need), thus requiring a more expensive sync instruction. At
1205 * some point, the set of architecture-independent barrier functions
1206 * should be expanded to include weaker barriers.
1207 */
1208
1209 eieio();
1210 txbdp->status = status;
1211
1212 /* If this was the last BD in the ring, the next one */
1213 /* is at the beginning of the ring */
1214 if (txbdp->status & TXBD_WRAP)
1215 txbdp = priv->tx_bd_base;
1216 else
1217 txbdp++;
1218
1219 /* If the next BD still needs to be cleaned up, then the bds
1220 are full. We need to tell the kernel to stop sending us stuff. */
1221 if (txbdp == priv->dirty_tx) {
1222 netif_stop_queue(dev);
1223
1224 dev->stats.tx_fifo_errors++;
1225 }
1226
1227 /* Update the current txbd to the next one */
1228 priv->cur_tx = txbdp;
1229
1230 /* Tell the DMA to go go go */
1231 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1232
1233 /* Unlock priv */
1234 spin_unlock_irqrestore(&priv->txlock, flags);
1235
1236 return 0;
1237 }
1238
1239 /* Stops the kernel queue, and halts the controller */
1240 static int gfar_close(struct net_device *dev)
1241 {
1242 struct gfar_private *priv = netdev_priv(dev);
1243
1244 napi_disable(&priv->napi);
1245
1246 cancel_work_sync(&priv->reset_task);
1247 stop_gfar(dev);
1248
1249 /* Disconnect from the PHY */
1250 phy_disconnect(priv->phydev);
1251 priv->phydev = NULL;
1252
1253 netif_stop_queue(dev);
1254
1255 return 0;
1256 }
1257
1258 /* Changes the mac address if the controller is not running. */
1259 static int gfar_set_mac_address(struct net_device *dev)
1260 {
1261 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1262
1263 return 0;
1264 }
1265
1266
1267 /* Enables and disables VLAN insertion/extraction */
1268 static void gfar_vlan_rx_register(struct net_device *dev,
1269 struct vlan_group *grp)
1270 {
1271 struct gfar_private *priv = netdev_priv(dev);
1272 unsigned long flags;
1273 u32 tempval;
1274
1275 spin_lock_irqsave(&priv->rxlock, flags);
1276
1277 priv->vlgrp = grp;
1278
1279 if (grp) {
1280 /* Enable VLAN tag insertion */
1281 tempval = gfar_read(&priv->regs->tctrl);
1282 tempval |= TCTRL_VLINS;
1283
1284 gfar_write(&priv->regs->tctrl, tempval);
1285
1286 /* Enable VLAN tag extraction */
1287 tempval = gfar_read(&priv->regs->rctrl);
1288 tempval |= RCTRL_VLEX;
1289 gfar_write(&priv->regs->rctrl, tempval);
1290 } else {
1291 /* Disable VLAN tag insertion */
1292 tempval = gfar_read(&priv->regs->tctrl);
1293 tempval &= ~TCTRL_VLINS;
1294 gfar_write(&priv->regs->tctrl, tempval);
1295
1296 /* Disable VLAN tag extraction */
1297 tempval = gfar_read(&priv->regs->rctrl);
1298 tempval &= ~RCTRL_VLEX;
1299 gfar_write(&priv->regs->rctrl, tempval);
1300 }
1301
1302 spin_unlock_irqrestore(&priv->rxlock, flags);
1303 }
1304
1305 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1306 {
1307 int tempsize, tempval;
1308 struct gfar_private *priv = netdev_priv(dev);
1309 int oldsize = priv->rx_buffer_size;
1310 int frame_size = new_mtu + ETH_HLEN;
1311
1312 if (priv->vlan_enable)
1313 frame_size += VLAN_HLEN;
1314
1315 if (gfar_uses_fcb(priv))
1316 frame_size += GMAC_FCB_LEN;
1317
1318 frame_size += priv->padding;
1319
1320 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1321 if (netif_msg_drv(priv))
1322 printk(KERN_ERR "%s: Invalid MTU setting\n",
1323 dev->name);
1324 return -EINVAL;
1325 }
1326
1327 tempsize =
1328 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1329 INCREMENTAL_BUFFER_SIZE;
1330
1331 /* Only stop and start the controller if it isn't already
1332 * stopped, and we changed something */
1333 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1334 stop_gfar(dev);
1335
1336 priv->rx_buffer_size = tempsize;
1337
1338 dev->mtu = new_mtu;
1339
1340 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1341 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1342
1343 /* If the mtu is larger than the max size for standard
1344 * ethernet frames (ie, a jumbo frame), then set maccfg2
1345 * to allow huge frames, and to check the length */
1346 tempval = gfar_read(&priv->regs->maccfg2);
1347
1348 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1349 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1350 else
1351 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1352
1353 gfar_write(&priv->regs->maccfg2, tempval);
1354
1355 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1356 startup_gfar(dev);
1357
1358 return 0;
1359 }
1360
1361 /* gfar_reset_task gets scheduled when a packet has not been
1362 * transmitted after a set amount of time.
1363 * For now, assume that clearing out all the structures, and
1364 * starting over will fix the problem.
1365 */
1366 static void gfar_reset_task(struct work_struct *work)
1367 {
1368 struct gfar_private *priv = container_of(work, struct gfar_private,
1369 reset_task);
1370 struct net_device *dev = priv->dev;
1371
1372 if (dev->flags & IFF_UP) {
1373 stop_gfar(dev);
1374 startup_gfar(dev);
1375 }
1376
1377 netif_tx_schedule_all(dev);
1378 }
1379
1380 static void gfar_timeout(struct net_device *dev)
1381 {
1382 struct gfar_private *priv = netdev_priv(dev);
1383
1384 dev->stats.tx_errors++;
1385 schedule_work(&priv->reset_task);
1386 }
1387
1388 /* Interrupt Handler for Transmit complete */
1389 static int gfar_clean_tx_ring(struct net_device *dev)
1390 {
1391 struct txbd8 *bdp;
1392 struct gfar_private *priv = netdev_priv(dev);
1393 int howmany = 0;
1394
1395 bdp = priv->dirty_tx;
1396 while ((bdp->status & TXBD_READY) == 0) {
1397 /* If dirty_tx and cur_tx are the same, then either the */
1398 /* ring is empty or full now (it could only be full in the beginning, */
1399 /* obviously). If it is empty, we are done. */
1400 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1401 break;
1402
1403 howmany++;
1404
1405 /* Deferred means some collisions occurred during transmit, */
1406 /* but we eventually sent the packet. */
1407 if (bdp->status & TXBD_DEF)
1408 dev->stats.collisions++;
1409
1410 /* Unmap the DMA memory */
1411 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1412 bdp->length, DMA_TO_DEVICE);
1413
1414 /* Free the sk buffer associated with this TxBD */
1415 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1416
1417 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1418 priv->skb_dirtytx =
1419 (priv->skb_dirtytx +
1420 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1421
1422 /* Clean BD length for empty detection */
1423 bdp->length = 0;
1424
1425 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1426 if (bdp->status & TXBD_WRAP)
1427 bdp = priv->tx_bd_base;
1428 else
1429 bdp++;
1430
1431 /* Move dirty_tx to be the next bd */
1432 priv->dirty_tx = bdp;
1433
1434 /* We freed a buffer, so now we can restart transmission */
1435 if (netif_queue_stopped(dev))
1436 netif_wake_queue(dev);
1437 } /* while ((bdp->status & TXBD_READY) == 0) */
1438
1439 dev->stats.tx_packets += howmany;
1440
1441 return howmany;
1442 }
1443
1444 /* Interrupt Handler for Transmit complete */
1445 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1446 {
1447 struct net_device *dev = (struct net_device *) dev_id;
1448 struct gfar_private *priv = netdev_priv(dev);
1449
1450 /* Clear IEVENT */
1451 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1452
1453 /* Lock priv */
1454 spin_lock(&priv->txlock);
1455
1456 gfar_clean_tx_ring(dev);
1457
1458 /* If we are coalescing the interrupts, reset the timer */
1459 /* Otherwise, clear it */
1460 if (likely(priv->txcoalescing)) {
1461 gfar_write(&priv->regs->txic, 0);
1462 gfar_write(&priv->regs->txic,
1463 mk_ic_value(priv->txcount, priv->txtime));
1464 }
1465
1466 spin_unlock(&priv->txlock);
1467
1468 return IRQ_HANDLED;
1469 }
1470
1471 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1472 struct sk_buff *skb)
1473 {
1474 struct gfar_private *priv = netdev_priv(dev);
1475 u32 * status_len = (u32 *)bdp;
1476 u16 flags;
1477
1478 bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1479 priv->rx_buffer_size, DMA_FROM_DEVICE);
1480
1481 flags = RXBD_EMPTY | RXBD_INTERRUPT;
1482
1483 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1484 flags |= RXBD_WRAP;
1485
1486 eieio();
1487
1488 *status_len = (u32)flags << 16;
1489 }
1490
1491
1492 struct sk_buff * gfar_new_skb(struct net_device *dev)
1493 {
1494 unsigned int alignamount;
1495 struct gfar_private *priv = netdev_priv(dev);
1496 struct sk_buff *skb = NULL;
1497
1498 /* We have to allocate the skb, so keep trying till we succeed */
1499 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1500
1501 if (!skb)
1502 return NULL;
1503
1504 alignamount = RXBUF_ALIGNMENT -
1505 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1506
1507 /* We need the data buffer to be aligned properly. We will reserve
1508 * as many bytes as needed to align the data properly
1509 */
1510 skb_reserve(skb, alignamount);
1511
1512 return skb;
1513 }
1514
1515 static inline void count_errors(unsigned short status, struct net_device *dev)
1516 {
1517 struct gfar_private *priv = netdev_priv(dev);
1518 struct net_device_stats *stats = &dev->stats;
1519 struct gfar_extra_stats *estats = &priv->extra_stats;
1520
1521 /* If the packet was truncated, none of the other errors
1522 * matter */
1523 if (status & RXBD_TRUNCATED) {
1524 stats->rx_length_errors++;
1525
1526 estats->rx_trunc++;
1527
1528 return;
1529 }
1530 /* Count the errors, if there were any */
1531 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1532 stats->rx_length_errors++;
1533
1534 if (status & RXBD_LARGE)
1535 estats->rx_large++;
1536 else
1537 estats->rx_short++;
1538 }
1539 if (status & RXBD_NONOCTET) {
1540 stats->rx_frame_errors++;
1541 estats->rx_nonoctet++;
1542 }
1543 if (status & RXBD_CRCERR) {
1544 estats->rx_crcerr++;
1545 stats->rx_crc_errors++;
1546 }
1547 if (status & RXBD_OVERRUN) {
1548 estats->rx_overrun++;
1549 stats->rx_crc_errors++;
1550 }
1551 }
1552
1553 irqreturn_t gfar_receive(int irq, void *dev_id)
1554 {
1555 struct net_device *dev = (struct net_device *) dev_id;
1556 struct gfar_private *priv = netdev_priv(dev);
1557 u32 tempval;
1558
1559 /* support NAPI */
1560 /* Clear IEVENT, so interrupts aren't called again
1561 * because of the packets that have already arrived */
1562 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1563
1564 if (netif_rx_schedule_prep(dev, &priv->napi)) {
1565 tempval = gfar_read(&priv->regs->imask);
1566 tempval &= IMASK_RTX_DISABLED;
1567 gfar_write(&priv->regs->imask, tempval);
1568
1569 __netif_rx_schedule(dev, &priv->napi);
1570 } else {
1571 if (netif_msg_rx_err(priv))
1572 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1573 dev->name, gfar_read(&priv->regs->ievent),
1574 gfar_read(&priv->regs->imask));
1575 }
1576
1577 return IRQ_HANDLED;
1578 }
1579
1580 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1581 {
1582 /* If valid headers were found, and valid sums
1583 * were verified, then we tell the kernel that no
1584 * checksumming is necessary. Otherwise, it is */
1585 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1586 skb->ip_summed = CHECKSUM_UNNECESSARY;
1587 else
1588 skb->ip_summed = CHECKSUM_NONE;
1589 }
1590
1591
1592 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1593 {
1594 struct rxfcb *fcb = (struct rxfcb *)skb->data;
1595
1596 /* Remove the FCB from the skb */
1597 skb_pull(skb, GMAC_FCB_LEN);
1598
1599 return fcb;
1600 }
1601
1602 /* gfar_process_frame() -- handle one incoming packet if skb
1603 * isn't NULL. */
1604 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1605 int length)
1606 {
1607 struct gfar_private *priv = netdev_priv(dev);
1608 struct rxfcb *fcb = NULL;
1609
1610 if (NULL == skb) {
1611 if (netif_msg_rx_err(priv))
1612 printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1613 dev->stats.rx_dropped++;
1614 priv->extra_stats.rx_skbmissing++;
1615 } else {
1616 int ret;
1617
1618 /* Prep the skb for the packet */
1619 skb_put(skb, length);
1620
1621 /* Grab the FCB if there is one */
1622 if (gfar_uses_fcb(priv))
1623 fcb = gfar_get_fcb(skb);
1624
1625 /* Remove the padded bytes, if there are any */
1626 if (priv->padding)
1627 skb_pull(skb, priv->padding);
1628
1629 if (priv->rx_csum_enable)
1630 gfar_rx_checksum(skb, fcb);
1631
1632 /* Tell the skb what kind of packet this is */
1633 skb->protocol = eth_type_trans(skb, dev);
1634
1635 /* Send the packet up the stack */
1636 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1637 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1638 fcb->vlctl);
1639 } else
1640 ret = netif_receive_skb(skb);
1641
1642 if (NET_RX_DROP == ret)
1643 priv->extra_stats.kernel_dropped++;
1644 }
1645
1646 return 0;
1647 }
1648
1649 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1650 * until the budget/quota has been reached. Returns the number
1651 * of frames handled
1652 */
1653 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1654 {
1655 struct rxbd8 *bdp;
1656 struct sk_buff *skb;
1657 u16 pkt_len;
1658 int howmany = 0;
1659 struct gfar_private *priv = netdev_priv(dev);
1660
1661 /* Get the first full descriptor */
1662 bdp = priv->cur_rx;
1663
1664 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1665 struct sk_buff *newskb;
1666 rmb();
1667
1668 /* Add another skb for the future */
1669 newskb = gfar_new_skb(dev);
1670
1671 skb = priv->rx_skbuff[priv->skb_currx];
1672
1673 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1674 priv->rx_buffer_size, DMA_FROM_DEVICE);
1675
1676 /* We drop the frame if we failed to allocate a new buffer */
1677 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1678 bdp->status & RXBD_ERR)) {
1679 count_errors(bdp->status, dev);
1680
1681 if (unlikely(!newskb))
1682 newskb = skb;
1683
1684 if (skb)
1685 dev_kfree_skb_any(skb);
1686 } else {
1687 /* Increment the number of packets */
1688 dev->stats.rx_packets++;
1689 howmany++;
1690
1691 /* Remove the FCS from the packet length */
1692 pkt_len = bdp->length - 4;
1693
1694 gfar_process_frame(dev, skb, pkt_len);
1695
1696 dev->stats.rx_bytes += pkt_len;
1697 }
1698
1699 dev->last_rx = jiffies;
1700
1701 priv->rx_skbuff[priv->skb_currx] = newskb;
1702
1703 /* Setup the new bdp */
1704 gfar_new_rxbdp(dev, bdp, newskb);
1705
1706 /* Update to the next pointer */
1707 if (bdp->status & RXBD_WRAP)
1708 bdp = priv->rx_bd_base;
1709 else
1710 bdp++;
1711
1712 /* update to point at the next skb */
1713 priv->skb_currx =
1714 (priv->skb_currx + 1) &
1715 RX_RING_MOD_MASK(priv->rx_ring_size);
1716 }
1717
1718 /* Update the current rxbd pointer to be the next one */
1719 priv->cur_rx = bdp;
1720
1721 return howmany;
1722 }
1723
1724 static int gfar_poll(struct napi_struct *napi, int budget)
1725 {
1726 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1727 struct net_device *dev = priv->dev;
1728 int howmany;
1729 unsigned long flags;
1730
1731 /* If we fail to get the lock, don't bother with the TX BDs */
1732 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1733 gfar_clean_tx_ring(dev);
1734 spin_unlock_irqrestore(&priv->txlock, flags);
1735 }
1736
1737 howmany = gfar_clean_rx_ring(dev, budget);
1738
1739 if (howmany < budget) {
1740 netif_rx_complete(dev, napi);
1741
1742 /* Clear the halt bit in RSTAT */
1743 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1744
1745 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1746
1747 /* If we are coalescing interrupts, update the timer */
1748 /* Otherwise, clear it */
1749 if (likely(priv->rxcoalescing)) {
1750 gfar_write(&priv->regs->rxic, 0);
1751 gfar_write(&priv->regs->rxic,
1752 mk_ic_value(priv->rxcount, priv->rxtime));
1753 }
1754 }
1755
1756 return howmany;
1757 }
1758
1759 #ifdef CONFIG_NET_POLL_CONTROLLER
1760 /*
1761 * Polling 'interrupt' - used by things like netconsole to send skbs
1762 * without having to re-enable interrupts. It's not called while
1763 * the interrupt routine is executing.
1764 */
1765 static void gfar_netpoll(struct net_device *dev)
1766 {
1767 struct gfar_private *priv = netdev_priv(dev);
1768
1769 /* If the device has multiple interrupts, run tx/rx */
1770 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1771 disable_irq(priv->interruptTransmit);
1772 disable_irq(priv->interruptReceive);
1773 disable_irq(priv->interruptError);
1774 gfar_interrupt(priv->interruptTransmit, dev);
1775 enable_irq(priv->interruptError);
1776 enable_irq(priv->interruptReceive);
1777 enable_irq(priv->interruptTransmit);
1778 } else {
1779 disable_irq(priv->interruptTransmit);
1780 gfar_interrupt(priv->interruptTransmit, dev);
1781 enable_irq(priv->interruptTransmit);
1782 }
1783 }
1784 #endif
1785
1786 /* The interrupt handler for devices with one interrupt */
1787 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1788 {
1789 struct net_device *dev = dev_id;
1790 struct gfar_private *priv = netdev_priv(dev);
1791
1792 /* Save ievent for future reference */
1793 u32 events = gfar_read(&priv->regs->ievent);
1794
1795 /* Check for reception */
1796 if (events & IEVENT_RX_MASK)
1797 gfar_receive(irq, dev_id);
1798
1799 /* Check for transmit completion */
1800 if (events & IEVENT_TX_MASK)
1801 gfar_transmit(irq, dev_id);
1802
1803 /* Check for errors */
1804 if (events & IEVENT_ERR_MASK)
1805 gfar_error(irq, dev_id);
1806
1807 return IRQ_HANDLED;
1808 }
1809
1810 /* Called every time the controller might need to be made
1811 * aware of new link state. The PHY code conveys this
1812 * information through variables in the phydev structure, and this
1813 * function converts those variables into the appropriate
1814 * register values, and can bring down the device if needed.
1815 */
1816 static void adjust_link(struct net_device *dev)
1817 {
1818 struct gfar_private *priv = netdev_priv(dev);
1819 struct gfar __iomem *regs = priv->regs;
1820 unsigned long flags;
1821 struct phy_device *phydev = priv->phydev;
1822 int new_state = 0;
1823
1824 spin_lock_irqsave(&priv->txlock, flags);
1825 if (phydev->link) {
1826 u32 tempval = gfar_read(&regs->maccfg2);
1827 u32 ecntrl = gfar_read(&regs->ecntrl);
1828
1829 /* Now we make sure that we can be in full duplex mode.
1830 * If not, we operate in half-duplex mode. */
1831 if (phydev->duplex != priv->oldduplex) {
1832 new_state = 1;
1833 if (!(phydev->duplex))
1834 tempval &= ~(MACCFG2_FULL_DUPLEX);
1835 else
1836 tempval |= MACCFG2_FULL_DUPLEX;
1837
1838 priv->oldduplex = phydev->duplex;
1839 }
1840
1841 if (phydev->speed != priv->oldspeed) {
1842 new_state = 1;
1843 switch (phydev->speed) {
1844 case 1000:
1845 tempval =
1846 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1847 break;
1848 case 100:
1849 case 10:
1850 tempval =
1851 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1852
1853 /* Reduced mode distinguishes
1854 * between 10 and 100 */
1855 if (phydev->speed == SPEED_100)
1856 ecntrl |= ECNTRL_R100;
1857 else
1858 ecntrl &= ~(ECNTRL_R100);
1859 break;
1860 default:
1861 if (netif_msg_link(priv))
1862 printk(KERN_WARNING
1863 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1864 dev->name, phydev->speed);
1865 break;
1866 }
1867
1868 priv->oldspeed = phydev->speed;
1869 }
1870
1871 gfar_write(&regs->maccfg2, tempval);
1872 gfar_write(&regs->ecntrl, ecntrl);
1873
1874 if (!priv->oldlink) {
1875 new_state = 1;
1876 priv->oldlink = 1;
1877 }
1878 } else if (priv->oldlink) {
1879 new_state = 1;
1880 priv->oldlink = 0;
1881 priv->oldspeed = 0;
1882 priv->oldduplex = -1;
1883 }
1884
1885 if (new_state && netif_msg_link(priv))
1886 phy_print_status(phydev);
1887
1888 spin_unlock_irqrestore(&priv->txlock, flags);
1889 }
1890
1891 /* Update the hash table based on the current list of multicast
1892 * addresses we subscribe to. Also, change the promiscuity of
1893 * the device based on the flags (this function is called
1894 * whenever dev->flags is changed */
1895 static void gfar_set_multi(struct net_device *dev)
1896 {
1897 struct dev_mc_list *mc_ptr;
1898 struct gfar_private *priv = netdev_priv(dev);
1899 struct gfar __iomem *regs = priv->regs;
1900 u32 tempval;
1901
1902 if(dev->flags & IFF_PROMISC) {
1903 /* Set RCTRL to PROM */
1904 tempval = gfar_read(&regs->rctrl);
1905 tempval |= RCTRL_PROM;
1906 gfar_write(&regs->rctrl, tempval);
1907 } else {
1908 /* Set RCTRL to not PROM */
1909 tempval = gfar_read(&regs->rctrl);
1910 tempval &= ~(RCTRL_PROM);
1911 gfar_write(&regs->rctrl, tempval);
1912 }
1913
1914 if(dev->flags & IFF_ALLMULTI) {
1915 /* Set the hash to rx all multicast frames */
1916 gfar_write(&regs->igaddr0, 0xffffffff);
1917 gfar_write(&regs->igaddr1, 0xffffffff);
1918 gfar_write(&regs->igaddr2, 0xffffffff);
1919 gfar_write(&regs->igaddr3, 0xffffffff);
1920 gfar_write(&regs->igaddr4, 0xffffffff);
1921 gfar_write(&regs->igaddr5, 0xffffffff);
1922 gfar_write(&regs->igaddr6, 0xffffffff);
1923 gfar_write(&regs->igaddr7, 0xffffffff);
1924 gfar_write(&regs->gaddr0, 0xffffffff);
1925 gfar_write(&regs->gaddr1, 0xffffffff);
1926 gfar_write(&regs->gaddr2, 0xffffffff);
1927 gfar_write(&regs->gaddr3, 0xffffffff);
1928 gfar_write(&regs->gaddr4, 0xffffffff);
1929 gfar_write(&regs->gaddr5, 0xffffffff);
1930 gfar_write(&regs->gaddr6, 0xffffffff);
1931 gfar_write(&regs->gaddr7, 0xffffffff);
1932 } else {
1933 int em_num;
1934 int idx;
1935
1936 /* zero out the hash */
1937 gfar_write(&regs->igaddr0, 0x0);
1938 gfar_write(&regs->igaddr1, 0x0);
1939 gfar_write(&regs->igaddr2, 0x0);
1940 gfar_write(&regs->igaddr3, 0x0);
1941 gfar_write(&regs->igaddr4, 0x0);
1942 gfar_write(&regs->igaddr5, 0x0);
1943 gfar_write(&regs->igaddr6, 0x0);
1944 gfar_write(&regs->igaddr7, 0x0);
1945 gfar_write(&regs->gaddr0, 0x0);
1946 gfar_write(&regs->gaddr1, 0x0);
1947 gfar_write(&regs->gaddr2, 0x0);
1948 gfar_write(&regs->gaddr3, 0x0);
1949 gfar_write(&regs->gaddr4, 0x0);
1950 gfar_write(&regs->gaddr5, 0x0);
1951 gfar_write(&regs->gaddr6, 0x0);
1952 gfar_write(&regs->gaddr7, 0x0);
1953
1954 /* If we have extended hash tables, we need to
1955 * clear the exact match registers to prepare for
1956 * setting them */
1957 if (priv->extended_hash) {
1958 em_num = GFAR_EM_NUM + 1;
1959 gfar_clear_exact_match(dev);
1960 idx = 1;
1961 } else {
1962 idx = 0;
1963 em_num = 0;
1964 }
1965
1966 if(dev->mc_count == 0)
1967 return;
1968
1969 /* Parse the list, and set the appropriate bits */
1970 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1971 if (idx < em_num) {
1972 gfar_set_mac_for_addr(dev, idx,
1973 mc_ptr->dmi_addr);
1974 idx++;
1975 } else
1976 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1977 }
1978 }
1979
1980 return;
1981 }
1982
1983
1984 /* Clears each of the exact match registers to zero, so they
1985 * don't interfere with normal reception */
1986 static void gfar_clear_exact_match(struct net_device *dev)
1987 {
1988 int idx;
1989 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1990
1991 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1992 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1993 }
1994
1995 /* Set the appropriate hash bit for the given addr */
1996 /* The algorithm works like so:
1997 * 1) Take the Destination Address (ie the multicast address), and
1998 * do a CRC on it (little endian), and reverse the bits of the
1999 * result.
2000 * 2) Use the 8 most significant bits as a hash into a 256-entry
2001 * table. The table is controlled through 8 32-bit registers:
2002 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2003 * gaddr7. This means that the 3 most significant bits in the
2004 * hash index which gaddr register to use, and the 5 other bits
2005 * indicate which bit (assuming an IBM numbering scheme, which
2006 * for PowerPC (tm) is usually the case) in the register holds
2007 * the entry. */
2008 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2009 {
2010 u32 tempval;
2011 struct gfar_private *priv = netdev_priv(dev);
2012 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2013 int width = priv->hash_width;
2014 u8 whichbit = (result >> (32 - width)) & 0x1f;
2015 u8 whichreg = result >> (32 - width + 5);
2016 u32 value = (1 << (31-whichbit));
2017
2018 tempval = gfar_read(priv->hash_regs[whichreg]);
2019 tempval |= value;
2020 gfar_write(priv->hash_regs[whichreg], tempval);
2021
2022 return;
2023 }
2024
2025
2026 /* There are multiple MAC Address register pairs on some controllers
2027 * This function sets the numth pair to a given address
2028 */
2029 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2030 {
2031 struct gfar_private *priv = netdev_priv(dev);
2032 int idx;
2033 char tmpbuf[MAC_ADDR_LEN];
2034 u32 tempval;
2035 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2036
2037 macptr += num*2;
2038
2039 /* Now copy it into the mac registers backwards, cuz */
2040 /* little endian is silly */
2041 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2042 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2043
2044 gfar_write(macptr, *((u32 *) (tmpbuf)));
2045
2046 tempval = *((u32 *) (tmpbuf + 4));
2047
2048 gfar_write(macptr+1, tempval);
2049 }
2050
2051 /* GFAR error interrupt handler */
2052 static irqreturn_t gfar_error(int irq, void *dev_id)
2053 {
2054 struct net_device *dev = dev_id;
2055 struct gfar_private *priv = netdev_priv(dev);
2056
2057 /* Save ievent for future reference */
2058 u32 events = gfar_read(&priv->regs->ievent);
2059
2060 /* Clear IEVENT */
2061 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2062
2063 /* Magic Packet is not an error. */
2064 if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2065 (events & IEVENT_MAG))
2066 events &= ~IEVENT_MAG;
2067
2068 /* Hmm... */
2069 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2070 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2071 dev->name, events, gfar_read(&priv->regs->imask));
2072
2073 /* Update the error counters */
2074 if (events & IEVENT_TXE) {
2075 dev->stats.tx_errors++;
2076
2077 if (events & IEVENT_LC)
2078 dev->stats.tx_window_errors++;
2079 if (events & IEVENT_CRL)
2080 dev->stats.tx_aborted_errors++;
2081 if (events & IEVENT_XFUN) {
2082 if (netif_msg_tx_err(priv))
2083 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2084 "packet dropped.\n", dev->name);
2085 dev->stats.tx_dropped++;
2086 priv->extra_stats.tx_underrun++;
2087
2088 /* Reactivate the Tx Queues */
2089 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2090 }
2091 if (netif_msg_tx_err(priv))
2092 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2093 }
2094 if (events & IEVENT_BSY) {
2095 dev->stats.rx_errors++;
2096 priv->extra_stats.rx_bsy++;
2097
2098 gfar_receive(irq, dev_id);
2099
2100 if (netif_msg_rx_err(priv))
2101 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2102 dev->name, gfar_read(&priv->regs->rstat));
2103 }
2104 if (events & IEVENT_BABR) {
2105 dev->stats.rx_errors++;
2106 priv->extra_stats.rx_babr++;
2107
2108 if (netif_msg_rx_err(priv))
2109 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2110 }
2111 if (events & IEVENT_EBERR) {
2112 priv->extra_stats.eberr++;
2113 if (netif_msg_rx_err(priv))
2114 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2115 }
2116 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2117 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2118
2119 if (events & IEVENT_BABT) {
2120 priv->extra_stats.tx_babt++;
2121 if (netif_msg_tx_err(priv))
2122 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2123 }
2124 return IRQ_HANDLED;
2125 }
2126
2127 /* work with hotplug and coldplug */
2128 MODULE_ALIAS("platform:fsl-gianfar");
2129
2130 /* Structure for a device driver */
2131 static struct platform_driver gfar_driver = {
2132 .probe = gfar_probe,
2133 .remove = gfar_remove,
2134 .suspend = gfar_suspend,
2135 .resume = gfar_resume,
2136 .driver = {
2137 .name = "fsl-gianfar",
2138 .owner = THIS_MODULE,
2139 },
2140 };
2141
2142 static int __init gfar_init(void)
2143 {
2144 int err = gfar_mdio_init();
2145
2146 if (err)
2147 return err;
2148
2149 err = platform_driver_register(&gfar_driver);
2150
2151 if (err)
2152 gfar_mdio_exit();
2153
2154 return err;
2155 }
2156
2157 static void __exit gfar_exit(void)
2158 {
2159 platform_driver_unregister(&gfar_driver);
2160 gfar_mdio_exit();
2161 }
2162
2163 module_init(gfar_init);
2164 module_exit(gfar_exit);
2165
Support for the Chinese Samsung S3C2440 based development boards