2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_counter.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/nmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_counter.h>
39 #include <asm/pgalloc.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
53 unsigned int num_processors
;
55 unsigned disabled_cpus __cpuinitdata
;
57 /* Processor that is doing the boot up */
58 unsigned int boot_cpu_physical_apicid
= -1U;
61 * The highest APIC ID seen during enumeration.
63 * This determines the messaging protocol we can use: if all APIC IDs
64 * are in the 0 ... 7 range, then we can use logical addressing which
65 * has some performance advantages (better broadcasting).
67 * If there's an APIC ID above 8, we use physical addressing.
69 unsigned int max_physical_apicid
;
72 * Bitmask of physically existing CPUs:
74 physid_mask_t phys_cpu_present_map
;
77 * Map cpu index to physical APIC ID
79 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
80 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
82 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
86 * Knob to control our willingness to enable the local APIC.
90 static int force_enable_local_apic
;
92 * APIC command line parameters
94 static int __init
parse_lapic(char *arg
)
96 force_enable_local_apic
= 1;
99 early_param("lapic", parse_lapic
);
100 /* Local APIC was disabled by the BIOS and enabled by the kernel */
101 static int enabled_via_apicbase
;
106 static int apic_calibrate_pmtmr __initdata
;
107 static __init
int setup_apicpmtimer(char *s
)
109 apic_calibrate_pmtmr
= 1;
113 __setup("apicpmtimer", setup_apicpmtimer
);
116 #ifdef CONFIG_X86_X2APIC
118 /* x2apic enabled before OS handover */
119 static int x2apic_preenabled
;
120 static int disable_x2apic
;
121 static __init
int setup_nox2apic(char *str
)
124 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
127 early_param("nox2apic", setup_nox2apic
);
130 unsigned long mp_lapic_addr
;
132 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
133 static int disable_apic_timer __cpuinitdata
;
134 /* Local APIC timer works in C2 */
135 int local_apic_timer_c2_ok
;
136 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
138 int first_system_vector
= 0xfe;
141 * Debug level, exported for io_apic.c
143 unsigned int apic_verbosity
;
147 /* Have we found an MP table */
148 int smp_found_config
;
150 static struct resource lapic_resource
= {
151 .name
= "Local APIC",
152 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
155 static unsigned int calibration_result
;
157 static int lapic_next_event(unsigned long delta
,
158 struct clock_event_device
*evt
);
159 static void lapic_timer_setup(enum clock_event_mode mode
,
160 struct clock_event_device
*evt
);
161 static void lapic_timer_broadcast(const struct cpumask
*mask
);
162 static void apic_pm_activate(void);
165 * The local apic timer can be used for any function which is CPU local.
167 static struct clock_event_device lapic_clockevent
= {
169 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
170 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
172 .set_mode
= lapic_timer_setup
,
173 .set_next_event
= lapic_next_event
,
174 .broadcast
= lapic_timer_broadcast
,
178 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
180 static unsigned long apic_phys
;
183 * Get the LAPIC version
185 static inline int lapic_get_version(void)
187 return GET_APIC_VERSION(apic_read(APIC_LVR
));
191 * Check, if the APIC is integrated or a separate chip
193 static inline int lapic_is_integrated(void)
198 return APIC_INTEGRATED(lapic_get_version());
203 * Check, whether this is a modern or a first generation APIC
205 static int modern_apic(void)
207 /* AMD systems use old APIC versions, so check the CPU */
208 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
209 boot_cpu_data
.x86
>= 0xf)
211 return lapic_get_version() >= 0x14;
214 void native_apic_wait_icr_idle(void)
216 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
220 u32
native_safe_apic_wait_icr_idle(void)
227 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
231 } while (timeout
++ < 1000);
236 void native_apic_icr_write(u32 low
, u32 id
)
238 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
239 apic_write(APIC_ICR
, low
);
242 u64
native_apic_icr_read(void)
246 icr2
= apic_read(APIC_ICR2
);
247 icr1
= apic_read(APIC_ICR
);
249 return icr1
| ((u64
)icr2
<< 32);
253 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
255 void __cpuinit
enable_NMI_through_LVT0(void)
259 /* unmask and set to NMI */
262 /* Level triggered for 82489DX (32bit mode) */
263 if (!lapic_is_integrated())
264 v
|= APIC_LVT_LEVEL_TRIGGER
;
266 apic_write(APIC_LVT0
, v
);
271 * get_physical_broadcast - Get number of physical broadcast IDs
273 int get_physical_broadcast(void)
275 return modern_apic() ? 0xff : 0xf;
280 * lapic_get_maxlvt - get the maximum number of local vector table entries
282 int lapic_get_maxlvt(void)
286 v
= apic_read(APIC_LVR
);
288 * - we always have APIC integrated on 64bit mode
289 * - 82489DXs do not report # of LVT entries
291 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
299 #define APIC_DIVISOR 16
302 * This function sets up the local APIC timer, with a timeout of
303 * 'clocks' APIC bus clock. During calibration we actually call
304 * this function twice on the boot CPU, once with a bogus timeout
305 * value, second time for real. The other (noncalibrating) CPUs
306 * call this function only once, with the real, calibrated value.
308 * We do reads before writes even if unnecessary, to get around the
309 * P5 APIC double write bug.
311 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
313 unsigned int lvtt_value
, tmp_value
;
315 lvtt_value
= LOCAL_TIMER_VECTOR
;
317 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
318 if (!lapic_is_integrated())
319 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
322 lvtt_value
|= APIC_LVT_MASKED
;
324 apic_write(APIC_LVTT
, lvtt_value
);
329 tmp_value
= apic_read(APIC_TDCR
);
330 apic_write(APIC_TDCR
,
331 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
335 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
339 * Setup extended LVT, AMD specific (K8, family 10h)
341 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
342 * MCE interrupts are supported. Thus MCE offset must be set to 0.
344 * If mask=1, the LVT entry does not generate interrupts while mask=0
345 * enables the vector. See also the BKDGs.
348 #define APIC_EILVT_LVTOFF_MCE 0
349 #define APIC_EILVT_LVTOFF_IBS 1
351 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
353 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
354 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
359 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
361 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
362 return APIC_EILVT_LVTOFF_MCE
;
365 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
367 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
368 return APIC_EILVT_LVTOFF_IBS
;
370 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
373 * Program the next event, relative to now
375 static int lapic_next_event(unsigned long delta
,
376 struct clock_event_device
*evt
)
378 apic_write(APIC_TMICT
, delta
);
383 * Setup the lapic timer in periodic or oneshot mode
385 static void lapic_timer_setup(enum clock_event_mode mode
,
386 struct clock_event_device
*evt
)
391 /* Lapic used as dummy for broadcast ? */
392 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
395 local_irq_save(flags
);
398 case CLOCK_EVT_MODE_PERIODIC
:
399 case CLOCK_EVT_MODE_ONESHOT
:
400 __setup_APIC_LVTT(calibration_result
,
401 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
403 case CLOCK_EVT_MODE_UNUSED
:
404 case CLOCK_EVT_MODE_SHUTDOWN
:
405 v
= apic_read(APIC_LVTT
);
406 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
407 apic_write(APIC_LVTT
, v
);
408 apic_write(APIC_TMICT
, 0xffffffff);
410 case CLOCK_EVT_MODE_RESUME
:
411 /* Nothing to do here */
415 local_irq_restore(flags
);
419 * Local APIC timer broadcast function
421 static void lapic_timer_broadcast(const struct cpumask
*mask
)
424 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
429 * Setup the local APIC timer for this CPU. Copy the initilized values
430 * of the boot CPU and register the clock event in the framework.
432 static void __cpuinit
setup_APIC_timer(void)
434 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
436 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
437 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
438 /* Make LAPIC timer preferrable over percpu HPET */
439 lapic_clockevent
.rating
= 150;
442 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
443 levt
->cpumask
= cpumask_of(smp_processor_id());
445 clockevents_register_device(levt
);
449 * In this functions we calibrate APIC bus clocks to the external timer.
451 * We want to do the calibration only once since we want to have local timer
452 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
455 * This was previously done by reading the PIT/HPET and waiting for a wrap
456 * around to find out, that a tick has elapsed. I have a box, where the PIT
457 * readout is broken, so it never gets out of the wait loop again. This was
458 * also reported by others.
460 * Monitoring the jiffies value is inaccurate and the clockevents
461 * infrastructure allows us to do a simple substitution of the interrupt
464 * The calibration routine also uses the pm_timer when possible, as the PIT
465 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
466 * back to normal later in the boot process).
469 #define LAPIC_CAL_LOOPS (HZ/10)
471 static __initdata
int lapic_cal_loops
= -1;
472 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
473 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
474 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
475 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
478 * Temporary interrupt handler.
480 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
482 unsigned long long tsc
= 0;
483 long tapic
= apic_read(APIC_TMCCT
);
484 unsigned long pm
= acpi_pm_read_early();
489 switch (lapic_cal_loops
++) {
491 lapic_cal_t1
= tapic
;
492 lapic_cal_tsc1
= tsc
;
494 lapic_cal_j1
= jiffies
;
497 case LAPIC_CAL_LOOPS
:
498 lapic_cal_t2
= tapic
;
499 lapic_cal_tsc2
= tsc
;
500 if (pm
< lapic_cal_pm1
)
501 pm
+= ACPI_PM_OVRRUN
;
503 lapic_cal_j2
= jiffies
;
509 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
511 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
512 const long pm_thresh
= pm_100ms
/ 100;
516 #ifndef CONFIG_X86_PM_TIMER
520 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
522 /* Check, if the PM timer is available */
526 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
528 if (deltapm
> (pm_100ms
- pm_thresh
) &&
529 deltapm
< (pm_100ms
+ pm_thresh
)) {
530 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
534 res
= (((u64
)deltapm
) * mult
) >> 22;
535 do_div(res
, 1000000);
536 pr_warning("APIC calibration not consistent "
537 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
539 /* Correct the lapic counter value */
540 res
= (((u64
)(*delta
)) * pm_100ms
);
541 do_div(res
, deltapm
);
542 pr_info("APIC delta adjusted to PM-Timer: "
543 "%lu (%ld)\n", (unsigned long)res
, *delta
);
546 /* Correct the tsc counter value */
548 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
549 do_div(res
, deltapm
);
550 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
551 "PM-Timer: %lu (%ld) \n",
552 (unsigned long)res
, *deltatsc
);
553 *deltatsc
= (long)res
;
559 static int __init
calibrate_APIC_clock(void)
561 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
562 void (*real_handler
)(struct clock_event_device
*dev
);
563 unsigned long deltaj
;
564 long delta
, deltatsc
;
565 int pm_referenced
= 0;
569 /* Replace the global interrupt handler */
570 real_handler
= global_clock_event
->event_handler
;
571 global_clock_event
->event_handler
= lapic_cal_handler
;
574 * Setup the APIC counter to maximum. There is no way the lapic
575 * can underflow in the 100ms detection time frame
577 __setup_APIC_LVTT(0xffffffff, 0, 0);
579 /* Let the interrupts run */
582 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
587 /* Restore the real event handler */
588 global_clock_event
->event_handler
= real_handler
;
590 /* Build delta t1-t2 as apic timer counts down */
591 delta
= lapic_cal_t1
- lapic_cal_t2
;
592 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
594 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
596 /* we trust the PM based calibration if possible */
597 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
600 /* Calculate the scaled math multiplication factor */
601 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
602 lapic_clockevent
.shift
);
603 lapic_clockevent
.max_delta_ns
=
604 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
605 lapic_clockevent
.min_delta_ns
=
606 clockevent_delta2ns(0xF, &lapic_clockevent
);
608 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
610 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
611 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
612 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
616 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
618 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
619 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
622 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
624 calibration_result
/ (1000000 / HZ
),
625 calibration_result
% (1000000 / HZ
));
628 * Do a sanity check on the APIC calibration result
630 if (calibration_result
< (1000000 / HZ
)) {
632 pr_warning("APIC frequency too slow, disabling apic timer\n");
636 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
639 * PM timer calibration failed or not turned on
640 * so lets try APIC timer based calibration
642 if (!pm_referenced
) {
643 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
646 * Setup the apic timer manually
648 levt
->event_handler
= lapic_cal_handler
;
649 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
650 lapic_cal_loops
= -1;
652 /* Let the interrupts run */
655 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
658 /* Stop the lapic timer */
659 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
662 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
663 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
665 /* Check, if the jiffies result is consistent */
666 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
667 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
669 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
673 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
674 pr_warning("APIC timer disabled due to verification failure\n");
682 * Setup the boot APIC
684 * Calibrate and verify the result.
686 void __init
setup_boot_APIC_clock(void)
689 * The local apic timer can be disabled via the kernel
690 * commandline or from the CPU detection code. Register the lapic
691 * timer as a dummy clock event source on SMP systems, so the
692 * broadcast mechanism is used. On UP systems simply ignore it.
694 if (disable_apic_timer
) {
695 pr_info("Disabling APIC timer\n");
696 /* No broadcast on UP ! */
697 if (num_possible_cpus() > 1) {
698 lapic_clockevent
.mult
= 1;
704 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
705 "calibrating APIC timer ...\n");
707 if (calibrate_APIC_clock()) {
708 /* No broadcast on UP ! */
709 if (num_possible_cpus() > 1)
715 * If nmi_watchdog is set to IO_APIC, we need the
716 * PIT/HPET going. Otherwise register lapic as a dummy
719 if (nmi_watchdog
!= NMI_IO_APIC
)
720 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
722 pr_warning("APIC timer registered as dummy,"
723 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
725 /* Setup the lapic or request the broadcast */
729 void __cpuinit
setup_secondary_APIC_clock(void)
735 * The guts of the apic timer interrupt
737 static void local_apic_timer_interrupt(void)
739 int cpu
= smp_processor_id();
740 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
743 * Normally we should not be here till LAPIC has been initialized but
744 * in some cases like kdump, its possible that there is a pending LAPIC
745 * timer interrupt from previous kernel's context and is delivered in
746 * new kernel the moment interrupts are enabled.
748 * Interrupts are enabled early and LAPIC is setup much later, hence
749 * its possible that when we get here evt->event_handler is NULL.
750 * Check for event_handler being NULL and discard the interrupt as
753 if (!evt
->event_handler
) {
754 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
756 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
761 * the NMI deadlock-detector uses this.
763 inc_irq_stat(apic_timer_irqs
);
765 evt
->event_handler(evt
);
767 perf_counter_unthrottle();
771 * Local APIC timer interrupt. This is the most natural way for doing
772 * local interrupts, but local timer interrupts can be emulated by
773 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
775 * [ if a single-CPU system runs an SMP kernel then we call the local
776 * interrupt as well. Thus we cannot inline the local irq ... ]
778 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
780 struct pt_regs
*old_regs
= set_irq_regs(regs
);
783 * NOTE! We'd better ACK the irq immediately,
784 * because timer handling can be slow.
788 * update_process_times() expects us to have done irq_enter().
789 * Besides, if we don't timer interrupts ignore the global
790 * interrupt lock, which is the WrongThing (tm) to do.
794 local_apic_timer_interrupt();
797 set_irq_regs(old_regs
);
800 int setup_profiling_timer(unsigned int multiplier
)
806 * Local APIC start and shutdown
810 * clear_local_APIC - shutdown the local APIC
812 * This is called, when a CPU is disabled and before rebooting, so the state of
813 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
814 * leftovers during boot.
816 void clear_local_APIC(void)
821 /* APIC hasn't been mapped yet */
822 if (!x2apic
&& !apic_phys
)
825 maxlvt
= lapic_get_maxlvt();
827 * Masking an LVT entry can trigger a local APIC error
828 * if the vector is zero. Mask LVTERR first to prevent this.
831 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
832 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
835 * Careful: we have to set masks only first to deassert
836 * any level-triggered sources.
838 v
= apic_read(APIC_LVTT
);
839 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
840 v
= apic_read(APIC_LVT0
);
841 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
842 v
= apic_read(APIC_LVT1
);
843 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
845 v
= apic_read(APIC_LVTPC
);
846 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
849 /* lets not touch this if we didn't frob it */
850 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
852 v
= apic_read(APIC_LVTTHMR
);
853 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
856 #ifdef CONFIG_X86_MCE_INTEL
858 v
= apic_read(APIC_LVTCMCI
);
859 if (!(v
& APIC_LVT_MASKED
))
860 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
865 * Clean APIC state for other OSs:
867 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
868 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
869 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
871 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
873 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
875 /* Integrated APIC (!82489DX) ? */
876 if (lapic_is_integrated()) {
878 /* Clear ESR due to Pentium errata 3AP and 11AP */
879 apic_write(APIC_ESR
, 0);
885 * disable_local_APIC - clear and disable the local APIC
887 void disable_local_APIC(void)
891 /* APIC hasn't been mapped yet */
898 * Disable APIC (implies clearing of registers
901 value
= apic_read(APIC_SPIV
);
902 value
&= ~APIC_SPIV_APIC_ENABLED
;
903 apic_write(APIC_SPIV
, value
);
907 * When LAPIC was disabled by the BIOS and enabled by the kernel,
908 * restore the disabled state.
910 if (enabled_via_apicbase
) {
913 rdmsr(MSR_IA32_APICBASE
, l
, h
);
914 l
&= ~MSR_IA32_APICBASE_ENABLE
;
915 wrmsr(MSR_IA32_APICBASE
, l
, h
);
921 * If Linux enabled the LAPIC against the BIOS default disable it down before
922 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
923 * not power-off. Additionally clear all LVT entries before disable_local_APIC
924 * for the case where Linux didn't enable the LAPIC.
926 void lapic_shutdown(void)
933 local_irq_save(flags
);
936 if (!enabled_via_apicbase
)
940 disable_local_APIC();
943 local_irq_restore(flags
);
947 * This is to verify that we're looking at a real local APIC.
948 * Check these against your board if the CPUs aren't getting
949 * started for no apparent reason.
951 int __init
verify_local_APIC(void)
953 unsigned int reg0
, reg1
;
956 * The version register is read-only in a real APIC.
958 reg0
= apic_read(APIC_LVR
);
959 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
960 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
961 reg1
= apic_read(APIC_LVR
);
962 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
965 * The two version reads above should print the same
966 * numbers. If the second one is different, then we
967 * poke at a non-APIC.
973 * Check if the version looks reasonably.
975 reg1
= GET_APIC_VERSION(reg0
);
976 if (reg1
== 0x00 || reg1
== 0xff)
978 reg1
= lapic_get_maxlvt();
979 if (reg1
< 0x02 || reg1
== 0xff)
983 * The ID register is read/write in a real APIC.
985 reg0
= apic_read(APIC_ID
);
986 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
987 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
988 reg1
= apic_read(APIC_ID
);
989 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
990 apic_write(APIC_ID
, reg0
);
991 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
995 * The next two are just to see if we have sane values.
996 * They're only really relevant if we're in Virtual Wire
997 * compatibility mode, but most boxes are anymore.
999 reg0
= apic_read(APIC_LVT0
);
1000 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1001 reg1
= apic_read(APIC_LVT1
);
1002 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1008 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1010 void __init
sync_Arb_IDs(void)
1013 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1016 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1022 apic_wait_icr_idle();
1024 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1025 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1026 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1030 * An initial setup of the virtual wire mode.
1032 void __init
init_bsp_APIC(void)
1037 * Don't do the setup now if we have a SMP BIOS as the
1038 * through-I/O-APIC virtual wire mode might be active.
1040 if (smp_found_config
|| !cpu_has_apic
)
1044 * Do not trust the local APIC being empty at bootup.
1051 value
= apic_read(APIC_SPIV
);
1052 value
&= ~APIC_VECTOR_MASK
;
1053 value
|= APIC_SPIV_APIC_ENABLED
;
1055 #ifdef CONFIG_X86_32
1056 /* This bit is reserved on P4/Xeon and should be cleared */
1057 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1058 (boot_cpu_data
.x86
== 15))
1059 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1062 value
|= APIC_SPIV_FOCUS_DISABLED
;
1063 value
|= SPURIOUS_APIC_VECTOR
;
1064 apic_write(APIC_SPIV
, value
);
1067 * Set up the virtual wire mode.
1069 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1070 value
= APIC_DM_NMI
;
1071 if (!lapic_is_integrated()) /* 82489DX */
1072 value
|= APIC_LVT_LEVEL_TRIGGER
;
1073 apic_write(APIC_LVT1
, value
);
1076 static void __cpuinit
lapic_setup_esr(void)
1078 unsigned int oldvalue
, value
, maxlvt
;
1080 if (!lapic_is_integrated()) {
1081 pr_info("No ESR for 82489DX.\n");
1085 if (apic
->disable_esr
) {
1087 * Something untraceable is creating bad interrupts on
1088 * secondary quads ... for the moment, just leave the
1089 * ESR disabled - we can't do anything useful with the
1090 * errors anyway - mbligh
1092 pr_info("Leaving ESR disabled.\n");
1096 maxlvt
= lapic_get_maxlvt();
1097 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1098 apic_write(APIC_ESR
, 0);
1099 oldvalue
= apic_read(APIC_ESR
);
1101 /* enables sending errors */
1102 value
= ERROR_APIC_VECTOR
;
1103 apic_write(APIC_LVTERR
, value
);
1106 * spec says clear errors after enabling vector.
1109 apic_write(APIC_ESR
, 0);
1110 value
= apic_read(APIC_ESR
);
1111 if (value
!= oldvalue
)
1112 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1113 "vector: 0x%08x after: 0x%08x\n",
1119 * setup_local_APIC - setup the local APIC
1121 void __cpuinit
setup_local_APIC(void)
1127 arch_disable_smp_support();
1131 #ifdef CONFIG_X86_32
1132 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1133 if (lapic_is_integrated() && apic
->disable_esr
) {
1134 apic_write(APIC_ESR
, 0);
1135 apic_write(APIC_ESR
, 0);
1136 apic_write(APIC_ESR
, 0);
1137 apic_write(APIC_ESR
, 0);
1140 perf_counters_lapic_init(0);
1145 * Double-check whether this APIC is really registered.
1146 * This is meaningless in clustered apic mode, so we skip it.
1148 if (!apic
->apic_id_registered())
1152 * Intel recommends to set DFR, LDR and TPR before enabling
1153 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1154 * document number 292116). So here it goes...
1156 apic
->init_apic_ldr();
1159 * Set Task Priority to 'accept all'. We never change this
1162 value
= apic_read(APIC_TASKPRI
);
1163 value
&= ~APIC_TPRI_MASK
;
1164 apic_write(APIC_TASKPRI
, value
);
1167 * After a crash, we no longer service the interrupts and a pending
1168 * interrupt from previous kernel might still have ISR bit set.
1170 * Most probably by now CPU has serviced that pending interrupt and
1171 * it might not have done the ack_APIC_irq() because it thought,
1172 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1173 * does not clear the ISR bit and cpu thinks it has already serivced
1174 * the interrupt. Hence a vector might get locked. It was noticed
1175 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1177 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1178 value
= apic_read(APIC_ISR
+ i
*0x10);
1179 for (j
= 31; j
>= 0; j
--) {
1186 * Now that we are all set up, enable the APIC
1188 value
= apic_read(APIC_SPIV
);
1189 value
&= ~APIC_VECTOR_MASK
;
1193 value
|= APIC_SPIV_APIC_ENABLED
;
1195 #ifdef CONFIG_X86_32
1197 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1198 * certain networking cards. If high frequency interrupts are
1199 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1200 * entry is masked/unmasked at a high rate as well then sooner or
1201 * later IOAPIC line gets 'stuck', no more interrupts are received
1202 * from the device. If focus CPU is disabled then the hang goes
1205 * [ This bug can be reproduced easily with a level-triggered
1206 * PCI Ne2000 networking cards and PII/PIII processors, dual
1210 * Actually disabling the focus CPU check just makes the hang less
1211 * frequent as it makes the interrupt distributon model be more
1212 * like LRU than MRU (the short-term load is more even across CPUs).
1213 * See also the comment in end_level_ioapic_irq(). --macro
1217 * - enable focus processor (bit==0)
1218 * - 64bit mode always use processor focus
1219 * so no need to set it
1221 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1225 * Set spurious IRQ vector
1227 value
|= SPURIOUS_APIC_VECTOR
;
1228 apic_write(APIC_SPIV
, value
);
1231 * Set up LVT0, LVT1:
1233 * set up through-local-APIC on the BP's LINT0. This is not
1234 * strictly necessary in pure symmetric-IO mode, but sometimes
1235 * we delegate interrupts to the 8259A.
1238 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1240 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1241 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1242 value
= APIC_DM_EXTINT
;
1243 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1244 smp_processor_id());
1246 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1247 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1248 smp_processor_id());
1250 apic_write(APIC_LVT0
, value
);
1253 * only the BP should see the LINT1 NMI signal, obviously.
1255 if (!smp_processor_id())
1256 value
= APIC_DM_NMI
;
1258 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1259 if (!lapic_is_integrated()) /* 82489DX */
1260 value
|= APIC_LVT_LEVEL_TRIGGER
;
1261 apic_write(APIC_LVT1
, value
);
1265 #ifdef CONFIG_X86_MCE_INTEL
1266 /* Recheck CMCI information after local APIC is up on CPU #0 */
1267 if (smp_processor_id() == 0)
1272 void __cpuinit
end_local_APIC_setup(void)
1276 #ifdef CONFIG_X86_32
1279 /* Disable the local apic timer */
1280 value
= apic_read(APIC_LVTT
);
1281 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1282 apic_write(APIC_LVTT
, value
);
1286 setup_apic_nmi_watchdog(NULL
);
1290 #ifdef CONFIG_X86_X2APIC
1291 void check_x2apic(void)
1293 if (x2apic_enabled()) {
1294 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1295 x2apic_preenabled
= x2apic
= 1;
1299 void enable_x2apic(void)
1306 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1307 if (!(msr
& X2APIC_ENABLE
)) {
1308 pr_info("Enabling x2apic\n");
1309 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1313 void __init
enable_IR_x2apic(void)
1315 #ifdef CONFIG_INTR_REMAP
1317 unsigned long flags
;
1318 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1320 if (!cpu_has_x2apic
)
1323 if (!x2apic_preenabled
&& disable_x2apic
) {
1324 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1325 "because of nox2apic\n");
1329 if (x2apic_preenabled
&& disable_x2apic
)
1330 panic("Bios already enabled x2apic, can't enforce nox2apic");
1332 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1333 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1334 "because of skipping io-apic setup\n");
1338 ret
= dmar_table_init();
1340 pr_info("dmar_table_init() failed with %d:\n", ret
);
1342 if (x2apic_preenabled
)
1343 panic("x2apic enabled by bios. But IR enabling failed");
1345 pr_info("Not enabling x2apic,Intr-remapping\n");
1349 ioapic_entries
= alloc_ioapic_entries();
1350 if (!ioapic_entries
) {
1351 pr_info("Allocate ioapic_entries failed: %d\n", ret
);
1355 ret
= save_IO_APIC_setup(ioapic_entries
);
1357 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1361 local_irq_save(flags
);
1362 mask_IO_APIC_setup(ioapic_entries
);
1365 ret
= enable_intr_remapping(EIM_32BIT_APIC_ID
);
1367 if (ret
&& x2apic_preenabled
) {
1368 local_irq_restore(flags
);
1369 panic("x2apic enabled by bios. But IR enabling failed");
1383 * IR enabling failed
1385 restore_IO_APIC_setup(ioapic_entries
);
1387 reinit_intr_remapped_IO_APIC(x2apic_preenabled
, ioapic_entries
);
1390 local_irq_restore(flags
);
1394 if (!x2apic_preenabled
)
1395 pr_info("Enabled x2apic and interrupt-remapping\n");
1397 pr_info("Enabled Interrupt-remapping\n");
1399 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1401 free_ioapic_entries(ioapic_entries
);
1403 if (!cpu_has_x2apic
)
1406 if (x2apic_preenabled
)
1407 panic("x2apic enabled prior OS handover,"
1408 " enable CONFIG_INTR_REMAP");
1410 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1416 #endif /* CONFIG_X86_X2APIC */
1418 #ifdef CONFIG_X86_64
1420 * Detect and enable local APICs on non-SMP boards.
1421 * Original code written by Keir Fraser.
1422 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1423 * not correctly set up (usually the APIC timer won't work etc.)
1425 static int __init
detect_init_APIC(void)
1427 if (!cpu_has_apic
) {
1428 pr_info("No local APIC present\n");
1432 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1433 boot_cpu_physical_apicid
= 0;
1438 * Detect and initialize APIC
1440 static int __init
detect_init_APIC(void)
1444 /* Disabled by kernel option? */
1448 switch (boot_cpu_data
.x86_vendor
) {
1449 case X86_VENDOR_AMD
:
1450 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1451 (boot_cpu_data
.x86
>= 15))
1454 case X86_VENDOR_INTEL
:
1455 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1456 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1463 if (!cpu_has_apic
) {
1465 * Over-ride BIOS and try to enable the local APIC only if
1466 * "lapic" specified.
1468 if (!force_enable_local_apic
) {
1469 pr_info("Local APIC disabled by BIOS -- "
1470 "you can enable it with \"lapic\"\n");
1474 * Some BIOSes disable the local APIC in the APIC_BASE
1475 * MSR. This can only be done in software for Intel P6 or later
1476 * and AMD K7 (Model > 1) or later.
1478 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1479 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1480 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1481 l
&= ~MSR_IA32_APICBASE_BASE
;
1482 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1483 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1484 enabled_via_apicbase
= 1;
1488 * The APIC feature bit should now be enabled
1491 features
= cpuid_edx(1);
1492 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1493 pr_warning("Could not enable APIC!\n");
1496 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1497 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1499 /* The BIOS may have set up the APIC at some other address */
1500 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1501 if (l
& MSR_IA32_APICBASE_ENABLE
)
1502 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1504 pr_info("Found and enabled local APIC!\n");
1511 pr_info("No local APIC present or hardware disabled\n");
1516 #ifdef CONFIG_X86_64
1517 void __init
early_init_lapic_mapping(void)
1519 unsigned long phys_addr
;
1522 * If no local APIC can be found then go out
1523 * : it means there is no mpatable and MADT
1525 if (!smp_found_config
)
1528 phys_addr
= mp_lapic_addr
;
1530 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1531 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1532 APIC_BASE
, phys_addr
);
1535 * Fetch the APIC ID of the BSP in case we have a
1536 * default configuration (or the MP table is broken).
1538 boot_cpu_physical_apicid
= read_apic_id();
1543 * init_apic_mappings - initialize APIC mappings
1545 void __init
init_apic_mappings(void)
1548 boot_cpu_physical_apicid
= read_apic_id();
1553 * If no local APIC can be found then set up a fake all
1554 * zeroes page to simulate the local APIC and another
1555 * one for the IO-APIC.
1557 if (!smp_found_config
&& detect_init_APIC()) {
1558 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1559 apic_phys
= __pa(apic_phys
);
1561 apic_phys
= mp_lapic_addr
;
1563 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1564 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1565 APIC_BASE
, apic_phys
);
1568 * Fetch the APIC ID of the BSP in case we have a
1569 * default configuration (or the MP table is broken).
1571 if (boot_cpu_physical_apicid
== -1U)
1572 boot_cpu_physical_apicid
= read_apic_id();
1576 * This initializes the IO-APIC and APIC hardware if this is
1579 int apic_version
[MAX_APICS
];
1581 int __init
APIC_init_uniprocessor(void)
1584 pr_info("Apic disabled\n");
1587 #ifdef CONFIG_X86_64
1588 if (!cpu_has_apic
) {
1590 pr_info("Apic disabled by BIOS\n");
1594 if (!smp_found_config
&& !cpu_has_apic
)
1598 * Complain if the BIOS pretends there is one.
1600 if (!cpu_has_apic
&&
1601 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1602 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1603 boot_cpu_physical_apicid
);
1604 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1610 #ifdef CONFIG_X86_64
1611 default_setup_apic_routing();
1614 verify_local_APIC();
1617 #ifdef CONFIG_X86_64
1618 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1621 * Hack: In case of kdump, after a crash, kernel might be booting
1622 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1623 * might be zero if read from MP tables. Get it from LAPIC.
1625 # ifdef CONFIG_CRASH_DUMP
1626 boot_cpu_physical_apicid
= read_apic_id();
1629 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1632 #ifdef CONFIG_X86_IO_APIC
1634 * Now enable IO-APICs, actually call clear_IO_APIC
1635 * We need clear_IO_APIC before enabling error vector
1637 if (!skip_ioapic_setup
&& nr_ioapics
)
1641 end_local_APIC_setup();
1643 #ifdef CONFIG_X86_IO_APIC
1644 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1648 localise_nmi_watchdog();
1651 localise_nmi_watchdog();
1655 #ifdef CONFIG_X86_64
1656 check_nmi_watchdog();
1663 * Local APIC interrupts
1667 * This interrupt should _never_ happen with our APIC/SMP architecture
1669 void smp_spurious_interrupt(struct pt_regs
*regs
)
1676 * Check if this really is a spurious interrupt and ACK it
1677 * if it is a vectored one. Just in case...
1678 * Spurious interrupts should not be ACKed.
1680 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1681 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1684 inc_irq_stat(irq_spurious_count
);
1686 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1687 pr_info("spurious APIC interrupt on CPU#%d, "
1688 "should never happen.\n", smp_processor_id());
1693 * This interrupt should never happen with our APIC/SMP architecture
1695 void smp_error_interrupt(struct pt_regs
*regs
)
1701 /* First tickle the hardware, only then report what went on. -- REW */
1702 v
= apic_read(APIC_ESR
);
1703 apic_write(APIC_ESR
, 0);
1704 v1
= apic_read(APIC_ESR
);
1706 atomic_inc(&irq_err_count
);
1709 * Here is what the APIC error bits mean:
1711 * 1: Receive CS error
1712 * 2: Send accept error
1713 * 3: Receive accept error
1715 * 5: Send illegal vector
1716 * 6: Received illegal vector
1717 * 7: Illegal register address
1719 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1720 smp_processor_id(), v
, v1
);
1725 * connect_bsp_APIC - attach the APIC to the interrupt system
1727 void __init
connect_bsp_APIC(void)
1729 #ifdef CONFIG_X86_32
1732 * Do not trust the local APIC being empty at bootup.
1736 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1737 * local APIC to INT and NMI lines.
1739 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1740 "enabling APIC mode.\n");
1745 if (apic
->enable_apic_mode
)
1746 apic
->enable_apic_mode();
1750 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1751 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1753 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1756 void disconnect_bsp_APIC(int virt_wire_setup
)
1760 #ifdef CONFIG_X86_32
1763 * Put the board back into PIC mode (has an effect only on
1764 * certain older boards). Note that APIC interrupts, including
1765 * IPIs, won't work beyond this point! The only exception are
1768 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1769 "entering PIC mode.\n");
1776 /* Go back to Virtual Wire compatibility mode */
1778 /* For the spurious interrupt use vector F, and enable it */
1779 value
= apic_read(APIC_SPIV
);
1780 value
&= ~APIC_VECTOR_MASK
;
1781 value
|= APIC_SPIV_APIC_ENABLED
;
1783 apic_write(APIC_SPIV
, value
);
1785 if (!virt_wire_setup
) {
1787 * For LVT0 make it edge triggered, active high,
1788 * external and enabled
1790 value
= apic_read(APIC_LVT0
);
1791 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1792 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1793 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1794 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1795 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1796 apic_write(APIC_LVT0
, value
);
1799 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1803 * For LVT1 make it edge triggered, active high,
1806 value
= apic_read(APIC_LVT1
);
1807 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1808 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1809 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1810 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1811 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1812 apic_write(APIC_LVT1
, value
);
1815 void __cpuinit
generic_processor_info(int apicid
, int version
)
1822 if (version
== 0x0) {
1823 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1824 "fixing up to 0x10. (tell your hw vendor)\n",
1828 apic_version
[apicid
] = version
;
1830 if (num_processors
>= nr_cpu_ids
) {
1831 int max
= nr_cpu_ids
;
1832 int thiscpu
= max
+ disabled_cpus
;
1835 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1836 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1843 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1845 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1847 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1848 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1850 physid_set(apicid
, phys_cpu_present_map
);
1851 if (apicid
== boot_cpu_physical_apicid
) {
1853 * x86_bios_cpu_apicid is required to have processors listed
1854 * in same order as logical cpu numbers. Hence the first
1855 * entry is BSP, and so on.
1859 if (apicid
> max_physical_apicid
)
1860 max_physical_apicid
= apicid
;
1862 #ifdef CONFIG_X86_32
1864 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1865 * but we need to work other dependencies like SMP_SUSPEND etc
1866 * before this can be done without some confusion.
1867 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1868 * - Ashok Raj <ashok.raj@intel.com>
1870 if (max_physical_apicid
>= 8) {
1871 switch (boot_cpu_data
.x86_vendor
) {
1872 case X86_VENDOR_INTEL
:
1873 if (!APIC_XAPIC(version
)) {
1877 /* If P4 and above fall through */
1878 case X86_VENDOR_AMD
:
1884 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1885 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1886 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1889 set_cpu_possible(cpu
, true);
1890 set_cpu_present(cpu
, true);
1893 int hard_smp_processor_id(void)
1895 return read_apic_id();
1898 void default_init_apic_ldr(void)
1902 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1903 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1904 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1905 apic_write(APIC_LDR
, val
);
1908 #ifdef CONFIG_X86_32
1909 int default_apicid_to_node(int logical_apicid
)
1912 return apicid_2_node
[hard_smp_processor_id()];
1926 * 'active' is true if the local APIC was enabled by us and
1927 * not the BIOS; this signifies that we are also responsible
1928 * for disabling it before entering apm/acpi suspend
1931 /* r/w apic fields */
1932 unsigned int apic_id
;
1933 unsigned int apic_taskpri
;
1934 unsigned int apic_ldr
;
1935 unsigned int apic_dfr
;
1936 unsigned int apic_spiv
;
1937 unsigned int apic_lvtt
;
1938 unsigned int apic_lvtpc
;
1939 unsigned int apic_lvt0
;
1940 unsigned int apic_lvt1
;
1941 unsigned int apic_lvterr
;
1942 unsigned int apic_tmict
;
1943 unsigned int apic_tdcr
;
1944 unsigned int apic_thmr
;
1947 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1949 unsigned long flags
;
1952 if (!apic_pm_state
.active
)
1955 maxlvt
= lapic_get_maxlvt();
1957 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1958 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1959 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1960 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1961 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1962 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1964 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1965 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1966 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1967 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1968 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1969 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1970 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1972 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1975 local_irq_save(flags
);
1976 disable_local_APIC();
1977 #ifdef CONFIG_INTR_REMAP
1978 if (intr_remapping_enabled
)
1979 disable_intr_remapping();
1981 local_irq_restore(flags
);
1985 static int lapic_resume(struct sys_device
*dev
)
1988 unsigned long flags
;
1991 #ifdef CONFIG_INTR_REMAP
1993 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1995 if (!apic_pm_state
.active
)
1998 local_irq_save(flags
);
2000 ioapic_entries
= alloc_ioapic_entries();
2001 if (!ioapic_entries
) {
2002 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2006 ret
= save_IO_APIC_setup(ioapic_entries
);
2008 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2009 free_ioapic_entries(ioapic_entries
);
2013 mask_IO_APIC_setup(ioapic_entries
);
2018 if (!apic_pm_state
.active
)
2021 local_irq_save(flags
);
2028 * Make sure the APICBASE points to the right address
2030 * FIXME! This will be wrong if we ever support suspend on
2031 * SMP! We'll need to do this as part of the CPU restore!
2033 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2034 l
&= ~MSR_IA32_APICBASE_BASE
;
2035 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2036 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2039 maxlvt
= lapic_get_maxlvt();
2040 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2041 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2042 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2043 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2044 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2045 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2046 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2047 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2048 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2050 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2053 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2054 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2055 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2056 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2057 apic_write(APIC_ESR
, 0);
2058 apic_read(APIC_ESR
);
2059 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2060 apic_write(APIC_ESR
, 0);
2061 apic_read(APIC_ESR
);
2063 #ifdef CONFIG_INTR_REMAP
2064 if (intr_remapping_enabled
)
2065 reenable_intr_remapping(EIM_32BIT_APIC_ID
);
2069 restore_IO_APIC_setup(ioapic_entries
);
2070 free_ioapic_entries(ioapic_entries
);
2074 local_irq_restore(flags
);
2081 * This device has no shutdown method - fully functioning local APICs
2082 * are needed on every CPU up until machine_halt/restart/poweroff.
2085 static struct sysdev_class lapic_sysclass
= {
2087 .resume
= lapic_resume
,
2088 .suspend
= lapic_suspend
,
2091 static struct sys_device device_lapic
= {
2093 .cls
= &lapic_sysclass
,
2096 static void __cpuinit
apic_pm_activate(void)
2098 apic_pm_state
.active
= 1;
2101 static int __init
init_lapic_sysfs(void)
2107 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2109 error
= sysdev_class_register(&lapic_sysclass
);
2111 error
= sysdev_register(&device_lapic
);
2115 /* local apic needs to resume before other devices access its registers. */
2116 core_initcall(init_lapic_sysfs
);
2118 #else /* CONFIG_PM */
2120 static void apic_pm_activate(void) { }
2122 #endif /* CONFIG_PM */
2124 #ifdef CONFIG_X86_64
2126 * apic_is_clustered_box() -- Check if we can expect good TSC
2128 * Thus far, the major user of this is IBM's Summit2 series:
2130 * Clustered boxes may have unsynced TSC problems if they are
2131 * multi-chassis. Use available data to take a good guess.
2132 * If in doubt, go HPET.
2134 __cpuinit
int apic_is_clustered_box(void)
2136 int i
, clusters
, zeros
;
2138 u16
*bios_cpu_apicid
;
2139 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2142 * there is not this kind of box with AMD CPU yet.
2143 * Some AMD box with quadcore cpu and 8 sockets apicid
2144 * will be [4, 0x23] or [8, 0x27] could be thought to
2145 * vsmp box still need checking...
2147 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2150 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2151 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2153 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2154 /* are we being called early in kernel startup? */
2155 if (bios_cpu_apicid
) {
2156 id
= bios_cpu_apicid
[i
];
2157 } else if (i
< nr_cpu_ids
) {
2159 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2165 if (id
!= BAD_APICID
)
2166 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2169 /* Problem: Partially populated chassis may not have CPUs in some of
2170 * the APIC clusters they have been allocated. Only present CPUs have
2171 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2172 * Since clusters are allocated sequentially, count zeros only if
2173 * they are bounded by ones.
2177 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2178 if (test_bit(i
, clustermap
)) {
2179 clusters
+= 1 + zeros
;
2185 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2186 * not guaranteed to be synced between boards
2188 if (is_vsmp_box() && clusters
> 1)
2192 * If clusters > 2, then should be multi-chassis.
2193 * May have to revisit this when multi-core + hyperthreaded CPUs come
2194 * out, but AFAIK this will work even for them.
2196 return (clusters
> 2);
2201 * APIC command line parameters
2203 static int __init
setup_disableapic(char *arg
)
2206 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2209 early_param("disableapic", setup_disableapic
);
2211 /* same as disableapic, for compatibility */
2212 static int __init
setup_nolapic(char *arg
)
2214 return setup_disableapic(arg
);
2216 early_param("nolapic", setup_nolapic
);
2218 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2220 local_apic_timer_c2_ok
= 1;
2223 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2225 static int __init
parse_disable_apic_timer(char *arg
)
2227 disable_apic_timer
= 1;
2230 early_param("noapictimer", parse_disable_apic_timer
);
2232 static int __init
parse_nolapic_timer(char *arg
)
2234 disable_apic_timer
= 1;
2237 early_param("nolapic_timer", parse_nolapic_timer
);
2239 static int __init
apic_set_verbosity(char *arg
)
2242 #ifdef CONFIG_X86_64
2243 skip_ioapic_setup
= 0;
2249 if (strcmp("debug", arg
) == 0)
2250 apic_verbosity
= APIC_DEBUG
;
2251 else if (strcmp("verbose", arg
) == 0)
2252 apic_verbosity
= APIC_VERBOSE
;
2254 pr_warning("APIC Verbosity level %s not recognised"
2255 " use apic=verbose or apic=debug\n", arg
);
2261 early_param("apic", apic_set_verbosity
);
2263 static int __init
lapic_insert_resource(void)
2268 /* Put local APIC into the resource map. */
2269 lapic_resource
.start
= apic_phys
;
2270 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2271 insert_resource(&iomem_resource
, &lapic_resource
);
2277 * need call insert after e820_reserve_resources()
2278 * that is using request_resource
2280 late_initcall(lapic_insert_resource
);