2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
138 unsigned long long addr
;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
145 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
146 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
148 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring
->cycle_state
);
152 ring
->deq_seg
= ring
->deq_seg
->next
;
153 ring
->dequeue
= ring
->deq_seg
->trbs
;
154 next
= ring
->dequeue
;
156 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
157 if (ring
== xhci
->event_ring
)
158 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
159 else if (ring
== xhci
->cmd_ring
)
160 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
162 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
182 union xhci_trb
*next
;
183 unsigned long long addr
;
185 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
186 next
= ++(ring
->enqueue
);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
194 if (ring
!= xhci
->event_ring
) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci
)) {
200 next
->link
.control
&= ~TRB_CHAIN
;
201 next
->link
.control
|= chain
;
203 /* Give this link TRB to the hardware */
205 if (next
->link
.control
& TRB_CYCLE
)
206 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
208 next
->link
.control
|= (u32
) TRB_CYCLE
;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
212 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
214 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring
->cycle_state
);
219 ring
->enq_seg
= ring
->enq_seg
->next
;
220 ring
->enqueue
= ring
->enq_seg
->trbs
;
221 next
= ring
->enqueue
;
223 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
224 if (ring
== xhci
->event_ring
)
225 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
226 else if (ring
== xhci
->cmd_ring
)
227 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
229 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
239 unsigned int num_trbs
)
242 union xhci_trb
*enq
= ring
->enqueue
;
243 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
245 /* Check if ring is empty */
246 if (enq
== ring
->dequeue
)
248 /* Make sure there's an extra empty TRB available */
249 for (i
= 0; i
<= num_trbs
; ++i
) {
250 if (enq
== ring
->dequeue
)
253 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
254 enq_seg
= enq_seg
->next
;
261 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
266 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
267 xhci
->event_ring
->dequeue
);
268 if (deq
== 0 && !in_interrupt())
269 xhci_warn(xhci
, "WARN something wrong with SW event ring "
271 /* Update HC event ring dequeue pointer */
272 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
273 temp
&= ERST_PTR_MASK
;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
278 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
280 &xhci
->ir_set
->erst_dequeue
);
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
288 xhci_dbg(xhci
, "// Ding dong!\n");
289 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
290 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
295 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
296 unsigned int slot_id
,
297 unsigned int ep_index
)
299 struct xhci_virt_ep
*ep
;
300 unsigned int ep_state
;
302 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
304 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
305 ep_state
= ep
->ep_state
;
306 /* Don't ring the doorbell for this endpoint if there are pending
307 * cancellations because the we don't want to interrupt processing.
309 if (!ep
->cancels_pending
&& !(ep_state
& SET_DEQ_PENDING
)
310 && !(ep_state
& EP_HALTED
)) {
311 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
312 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
313 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
314 * isn't time-critical and we shouldn't make the CPU wait for
317 xhci_readl(xhci
, db_addr
);
322 * Find the segment that trb is in. Start searching in start_seg.
323 * If we must move past a segment that has a link TRB with a toggle cycle state
324 * bit set, then we will toggle the value pointed at by cycle_state.
326 static struct xhci_segment
*find_trb_seg(
327 struct xhci_segment
*start_seg
,
328 union xhci_trb
*trb
, int *cycle_state
)
330 struct xhci_segment
*cur_seg
= start_seg
;
331 struct xhci_generic_trb
*generic_trb
;
333 while (cur_seg
->trbs
> trb
||
334 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
335 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
336 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
337 (generic_trb
->field
[3] & LINK_TOGGLE
))
338 *cycle_state
= ~(*cycle_state
) & 0x1;
339 cur_seg
= cur_seg
->next
;
340 if (cur_seg
== start_seg
)
341 /* Looped over the entire list. Oops! */
348 * Move the xHC's endpoint ring dequeue pointer past cur_td.
349 * Record the new state of the xHC's endpoint ring dequeue segment,
350 * dequeue pointer, and new consumer cycle state in state.
351 * Update our internal representation of the ring's dequeue pointer.
353 * We do this in three jumps:
354 * - First we update our new ring state to be the same as when the xHC stopped.
355 * - Then we traverse the ring to find the segment that contains
356 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
357 * any link TRBs with the toggle cycle bit set.
358 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
359 * if we've moved it past a link TRB with the toggle cycle bit set.
361 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
362 unsigned int slot_id
, unsigned int ep_index
,
363 struct xhci_td
*cur_td
, struct xhci_dequeue_state
*state
)
365 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
366 struct xhci_ring
*ep_ring
= dev
->eps
[ep_index
].ring
;
367 struct xhci_generic_trb
*trb
;
368 struct xhci_ep_ctx
*ep_ctx
;
371 state
->new_cycle_state
= 0;
372 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
373 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
374 dev
->eps
[ep_index
].stopped_trb
,
375 &state
->new_cycle_state
);
376 if (!state
->new_deq_seg
)
378 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
379 xhci_dbg(xhci
, "Finding endpoint context\n");
380 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
381 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
383 state
->new_deq_ptr
= cur_td
->last_trb
;
384 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
385 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
387 &state
->new_cycle_state
);
388 if (!state
->new_deq_seg
)
391 trb
= &state
->new_deq_ptr
->generic
;
392 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
393 (trb
->field
[3] & LINK_TOGGLE
))
394 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
395 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
397 /* Don't update the ring cycle state for the producer (us). */
398 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
400 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
401 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
402 (unsigned long long) addr
);
403 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
404 ep_ring
->dequeue
= state
->new_deq_ptr
;
405 ep_ring
->deq_seg
= state
->new_deq_seg
;
408 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
409 struct xhci_td
*cur_td
)
411 struct xhci_segment
*cur_seg
;
412 union xhci_trb
*cur_trb
;
414 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
416 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
417 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
418 TRB_TYPE(TRB_LINK
)) {
419 /* Unchain any chained Link TRBs, but
420 * leave the pointers intact.
422 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
423 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
424 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
425 "in seg %p (0x%llx dma)\n",
427 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
429 (unsigned long long)cur_seg
->dma
);
431 cur_trb
->generic
.field
[0] = 0;
432 cur_trb
->generic
.field
[1] = 0;
433 cur_trb
->generic
.field
[2] = 0;
434 /* Preserve only the cycle bit of this TRB */
435 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
436 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
437 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
438 "in seg %p (0x%llx dma)\n",
440 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
442 (unsigned long long)cur_seg
->dma
);
444 if (cur_trb
== cur_td
->last_trb
)
449 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
450 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
451 union xhci_trb
*deq_ptr
, u32 cycle_state
);
453 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
454 unsigned int slot_id
, unsigned int ep_index
,
455 struct xhci_dequeue_state
*deq_state
)
457 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
459 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
460 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
461 deq_state
->new_deq_seg
,
462 (unsigned long long)deq_state
->new_deq_seg
->dma
,
463 deq_state
->new_deq_ptr
,
464 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
465 deq_state
->new_cycle_state
);
466 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
467 deq_state
->new_deq_seg
,
468 deq_state
->new_deq_ptr
,
469 (u32
) deq_state
->new_cycle_state
);
470 /* Stop the TD queueing code from ringing the doorbell until
471 * this command completes. The HC won't set the dequeue pointer
472 * if the ring is running, and ringing the doorbell starts the
475 ep
->ep_state
|= SET_DEQ_PENDING
;
479 * When we get a command completion for a Stop Endpoint Command, we need to
480 * unlink any cancelled TDs from the ring. There are two ways to do that:
482 * 1. If the HW was in the middle of processing the TD that needs to be
483 * cancelled, then we must move the ring's dequeue pointer past the last TRB
484 * in the TD with a Set Dequeue Pointer Command.
485 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
486 * bit cleared) so that the HW will skip over them.
488 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
491 unsigned int slot_id
;
492 unsigned int ep_index
;
493 struct xhci_ring
*ep_ring
;
494 struct xhci_virt_ep
*ep
;
495 struct list_head
*entry
;
496 struct xhci_td
*cur_td
= 0;
497 struct xhci_td
*last_unlinked_td
;
499 struct xhci_dequeue_state deq_state
;
500 #ifdef CONFIG_USB_HCD_STAT
501 ktime_t stop_time
= ktime_get();
504 memset(&deq_state
, 0, sizeof(deq_state
));
505 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
506 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
507 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
510 if (list_empty(&ep
->cancelled_td_list
))
513 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
514 * We have the xHCI lock, so nothing can modify this list until we drop
515 * it. We're also in the event handler, so we can't get re-interrupted
516 * if another Stop Endpoint command completes
518 list_for_each(entry
, &ep
->cancelled_td_list
) {
519 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
520 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
522 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
524 * If we stopped on the TD we need to cancel, then we have to
525 * move the xHC endpoint ring dequeue pointer past this TD.
527 if (cur_td
== ep
->stopped_td
)
528 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
531 td_to_noop(xhci
, ep_ring
, cur_td
);
533 * The event handler won't see a completion for this TD anymore,
534 * so remove it from the endpoint ring's TD list. Keep it in
535 * the cancelled TD list for URB completion later.
537 list_del(&cur_td
->td_list
);
538 ep
->cancels_pending
--;
540 last_unlinked_td
= cur_td
;
542 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
543 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
544 xhci_queue_new_dequeue_state(xhci
,
545 slot_id
, ep_index
, &deq_state
);
546 xhci_ring_cmd_db(xhci
);
548 /* Otherwise just ring the doorbell to restart the ring */
549 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
553 * Drop the lock and complete the URBs in the cancelled TD list.
554 * New TDs to be cancelled might be added to the end of the list before
555 * we can complete all the URBs for the TDs we already unlinked.
556 * So stop when we've completed the URB for the last TD we unlinked.
559 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
560 struct xhci_td
, cancelled_td_list
);
561 list_del(&cur_td
->cancelled_td_list
);
563 /* Clean up the cancelled URB */
564 #ifdef CONFIG_USB_HCD_STAT
565 hcd_stat_update(xhci
->tp_stat
, cur_td
->urb
->actual_length
,
566 ktime_sub(stop_time
, cur_td
->start_time
));
568 cur_td
->urb
->hcpriv
= NULL
;
569 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), cur_td
->urb
);
571 xhci_dbg(xhci
, "Giveback cancelled URB %p\n", cur_td
->urb
);
572 spin_unlock(&xhci
->lock
);
573 /* Doesn't matter what we pass for status, since the core will
574 * just overwrite it (because the URB has been unlinked).
576 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), cur_td
->urb
, 0);
579 spin_lock(&xhci
->lock
);
580 } while (cur_td
!= last_unlinked_td
);
582 /* Return to the event handler with xhci->lock re-acquired */
586 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
587 * we need to clear the set deq pending flag in the endpoint ring state, so that
588 * the TD queueing code can ring the doorbell again. We also need to ring the
589 * endpoint doorbell to restart the ring, but only if there aren't more
590 * cancellations pending.
592 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
593 struct xhci_event_cmd
*event
,
596 unsigned int slot_id
;
597 unsigned int ep_index
;
598 struct xhci_ring
*ep_ring
;
599 struct xhci_virt_device
*dev
;
600 struct xhci_ep_ctx
*ep_ctx
;
601 struct xhci_slot_ctx
*slot_ctx
;
603 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
604 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
605 dev
= xhci
->devs
[slot_id
];
606 ep_ring
= dev
->eps
[ep_index
].ring
;
607 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
608 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
610 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
611 unsigned int ep_state
;
612 unsigned int slot_state
;
614 switch (GET_COMP_CODE(event
->status
)) {
616 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
617 "of stream ID configuration\n");
620 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
621 "to incorrect slot or ep state.\n");
622 ep_state
= ep_ctx
->ep_info
;
623 ep_state
&= EP_STATE_MASK
;
624 slot_state
= slot_ctx
->dev_state
;
625 slot_state
= GET_SLOT_STATE(slot_state
);
626 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
627 slot_state
, ep_state
);
630 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
631 "slot %u was not enabled.\n", slot_id
);
634 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
635 "completion code of %u.\n",
636 GET_COMP_CODE(event
->status
));
639 /* OK what do we do now? The endpoint state is hosed, and we
640 * should never get to this point if the synchronization between
641 * queueing, and endpoint state are correct. This might happen
642 * if the device gets disconnected after we've finished
643 * cancelling URBs, which might not be an error...
646 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
650 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
651 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
654 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
655 struct xhci_event_cmd
*event
,
659 unsigned int ep_index
;
660 struct xhci_ring
*ep_ring
;
662 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
663 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
664 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
665 /* This command will only fail if the endpoint wasn't halted,
668 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
669 (unsigned int) GET_COMP_CODE(event
->status
));
671 /* HW with the reset endpoint quirk needs to have a configure endpoint
672 * command complete before the endpoint can be used. Queue that here
673 * because the HW can't handle two commands being queued in a row.
675 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
676 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
677 xhci_queue_configure_endpoint(xhci
,
678 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
680 xhci_ring_cmd_db(xhci
);
682 /* Clear our internal halted state and restart the ring */
683 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
684 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
688 /* Check to see if a command in the device's command queue matches this one.
689 * Signal the completion or free the command, and return 1. Return 0 if the
690 * completed command isn't at the head of the command list.
692 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
693 struct xhci_virt_device
*virt_dev
,
694 struct xhci_event_cmd
*event
)
696 struct xhci_command
*command
;
698 if (list_empty(&virt_dev
->cmd_list
))
701 command
= list_entry(virt_dev
->cmd_list
.next
,
702 struct xhci_command
, cmd_list
);
703 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
707 GET_COMP_CODE(event
->status
);
708 list_del(&command
->cmd_list
);
709 if (command
->completion
)
710 complete(command
->completion
);
712 xhci_free_command(xhci
, command
);
716 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
717 struct xhci_event_cmd
*event
)
719 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
721 dma_addr_t cmd_dequeue_dma
;
722 struct xhci_input_control_ctx
*ctrl_ctx
;
723 struct xhci_virt_device
*virt_dev
;
724 unsigned int ep_index
;
725 struct xhci_ring
*ep_ring
;
726 unsigned int ep_state
;
728 cmd_dma
= event
->cmd_trb
;
729 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
730 xhci
->cmd_ring
->dequeue
);
731 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
732 if (cmd_dequeue_dma
== 0) {
733 xhci
->error_bitmask
|= 1 << 4;
736 /* Does the DMA address match our internal dequeue pointer address? */
737 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
738 xhci
->error_bitmask
|= 1 << 5;
741 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
742 case TRB_TYPE(TRB_ENABLE_SLOT
):
743 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
744 xhci
->slot_id
= slot_id
;
747 complete(&xhci
->addr_dev
);
749 case TRB_TYPE(TRB_DISABLE_SLOT
):
750 if (xhci
->devs
[slot_id
])
751 xhci_free_virt_device(xhci
, slot_id
);
753 case TRB_TYPE(TRB_CONFIG_EP
):
754 virt_dev
= xhci
->devs
[slot_id
];
755 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
758 * Configure endpoint commands can come from the USB core
759 * configuration or alt setting changes, or because the HW
760 * needed an extra configure endpoint command after a reset
761 * endpoint command. In the latter case, the xHCI driver is
762 * not waiting on the configure endpoint command.
764 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
766 /* Input ctx add_flags are the endpoint index plus one */
767 ep_index
= xhci_last_valid_endpoint(ctrl_ctx
->add_flags
) - 1;
768 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
770 /* This must have been an initial configure endpoint */
771 xhci
->devs
[slot_id
]->cmd_status
=
772 GET_COMP_CODE(event
->status
);
773 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
776 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
777 xhci_dbg(xhci
, "Completed config ep cmd - last ep index = %d, "
778 "state = %d\n", ep_index
, ep_state
);
779 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
780 ep_state
& EP_HALTED
) {
781 /* Clear our internal halted state and restart ring */
782 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
784 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
786 xhci
->devs
[slot_id
]->cmd_status
=
787 GET_COMP_CODE(event
->status
);
788 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
791 case TRB_TYPE(TRB_EVAL_CONTEXT
):
792 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
793 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
795 case TRB_TYPE(TRB_ADDR_DEV
):
796 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
797 complete(&xhci
->addr_dev
);
799 case TRB_TYPE(TRB_STOP_RING
):
800 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
802 case TRB_TYPE(TRB_SET_DEQ
):
803 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
805 case TRB_TYPE(TRB_CMD_NOOP
):
806 ++xhci
->noops_handled
;
808 case TRB_TYPE(TRB_RESET_EP
):
809 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
812 /* Skip over unknown commands on the event ring */
813 xhci
->error_bitmask
|= 1 << 6;
816 inc_deq(xhci
, xhci
->cmd_ring
, false);
819 static void handle_port_status(struct xhci_hcd
*xhci
,
820 union xhci_trb
*event
)
824 /* Port status change events always have a successful completion code */
825 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
826 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
827 xhci
->error_bitmask
|= 1 << 8;
829 /* FIXME: core doesn't care about all port link state changes yet */
830 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
831 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
833 /* Update event ring dequeue pointer before dropping the lock */
834 inc_deq(xhci
, xhci
->event_ring
, true);
835 xhci_set_hc_event_deq(xhci
);
837 spin_unlock(&xhci
->lock
);
838 /* Pass this up to the core */
839 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
840 spin_lock(&xhci
->lock
);
844 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
845 * at end_trb, which may be in another segment. If the suspect DMA address is a
846 * TRB in this TD, this function returns that TRB's segment. Otherwise it
849 static struct xhci_segment
*trb_in_td(
850 struct xhci_segment
*start_seg
,
851 union xhci_trb
*start_trb
,
852 union xhci_trb
*end_trb
,
853 dma_addr_t suspect_dma
)
855 dma_addr_t start_dma
;
856 dma_addr_t end_seg_dma
;
857 dma_addr_t end_trb_dma
;
858 struct xhci_segment
*cur_seg
;
860 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
864 /* We may get an event for a Link TRB in the middle of a TD */
865 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
866 &start_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
867 /* If the end TRB isn't in this segment, this is set to 0 */
868 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
870 if (end_trb_dma
> 0) {
871 /* The end TRB is in this segment, so suspect should be here */
872 if (start_dma
<= end_trb_dma
) {
873 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
876 /* Case for one segment with
877 * a TD wrapped around to the top
879 if ((suspect_dma
>= start_dma
&&
880 suspect_dma
<= end_seg_dma
) ||
881 (suspect_dma
>= cur_seg
->dma
&&
882 suspect_dma
<= end_trb_dma
))
887 /* Might still be somewhere in this segment */
888 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
891 cur_seg
= cur_seg
->next
;
892 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
898 * If this function returns an error condition, it means it got a Transfer
899 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
900 * At this point, the host controller is probably hosed and should be reset.
902 static int handle_tx_event(struct xhci_hcd
*xhci
,
903 struct xhci_transfer_event
*event
)
905 struct xhci_virt_device
*xdev
;
906 struct xhci_virt_ep
*ep
;
907 struct xhci_ring
*ep_ring
;
908 unsigned int slot_id
;
910 struct xhci_td
*td
= 0;
911 dma_addr_t event_dma
;
912 struct xhci_segment
*event_seg
;
913 union xhci_trb
*event_trb
;
915 int status
= -EINPROGRESS
;
916 struct xhci_ep_ctx
*ep_ctx
;
919 xhci_dbg(xhci
, "In %s\n", __func__
);
920 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
921 xdev
= xhci
->devs
[slot_id
];
923 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
927 /* Endpoint ID is 1 based, our index is zero based */
928 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
929 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
930 ep
= &xdev
->eps
[ep_index
];
932 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
933 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
934 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
938 event_dma
= event
->buffer
;
939 /* This TRB should be in the TD at the head of this ring's TD list */
940 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
941 if (list_empty(&ep_ring
->td_list
)) {
942 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
943 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
944 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
945 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
946 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
950 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
951 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
953 /* Is this a TRB in the currently executing TD? */
954 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
955 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
956 td
->last_trb
, event_dma
);
957 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
959 /* HC is busted, give up! */
960 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
963 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
964 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
965 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
966 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
967 lower_32_bits(event
->buffer
));
968 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
969 upper_32_bits(event
->buffer
));
970 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
971 (unsigned int) event
->transfer_len
);
972 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
973 (unsigned int) event
->flags
);
975 /* Look for common error cases */
976 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
977 switch (trb_comp_code
) {
978 /* Skip codes that require special handling depending on
985 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
987 case COMP_STOP_INVAL
:
988 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
991 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
992 ep
->ep_state
|= EP_HALTED
;
996 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1000 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1004 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1005 status
= -EOVERFLOW
;
1008 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1012 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
1016 /* Now update the urb's actual_length and give back to the core */
1017 /* Was this a control transfer? */
1018 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
1019 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1020 switch (trb_comp_code
) {
1022 if (event_trb
== ep_ring
->dequeue
) {
1023 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
1024 status
= -ESHUTDOWN
;
1025 } else if (event_trb
!= td
->last_trb
) {
1026 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
1027 status
= -ESHUTDOWN
;
1029 xhci_dbg(xhci
, "Successful control transfer!\n");
1034 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1035 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1036 status
= -EREMOTEIO
;
1041 /* The 0.96 spec says a babbling control endpoint
1042 * is not halted. The 0.96 spec says it is. Some HW
1043 * claims to be 0.95 compliant, but it halts the control
1044 * endpoint anyway. Check if a babble halted the
1047 if (ep_ctx
->ep_info
!= EP_STATE_HALTED
)
1049 /* else fall through */
1051 /* Did we transfer part of the data (middle) phase? */
1052 if (event_trb
!= ep_ring
->dequeue
&&
1053 event_trb
!= td
->last_trb
)
1054 td
->urb
->actual_length
=
1055 td
->urb
->transfer_buffer_length
1056 - TRB_LEN(event
->transfer_len
);
1058 td
->urb
->actual_length
= 0;
1060 ep
->stopped_td
= td
;
1061 ep
->stopped_trb
= event_trb
;
1062 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1063 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1064 xhci_ring_cmd_db(xhci
);
1067 /* Others already handled above */
1071 * Did we transfer any data, despite the errors that might have
1072 * happened? I.e. did we get past the setup stage?
1074 if (event_trb
!= ep_ring
->dequeue
) {
1075 /* The event was for the status stage */
1076 if (event_trb
== td
->last_trb
) {
1077 if (td
->urb
->actual_length
!= 0) {
1078 /* Don't overwrite a previously set error code */
1079 if ((status
== -EINPROGRESS
||
1081 (td
->urb
->transfer_flags
1082 & URB_SHORT_NOT_OK
))
1083 /* Did we already see a short data stage? */
1084 status
= -EREMOTEIO
;
1086 td
->urb
->actual_length
=
1087 td
->urb
->transfer_buffer_length
;
1090 /* Maybe the event was for the data stage? */
1091 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1092 /* We didn't stop on a link TRB in the middle */
1093 td
->urb
->actual_length
=
1094 td
->urb
->transfer_buffer_length
-
1095 TRB_LEN(event
->transfer_len
);
1096 xhci_dbg(xhci
, "Waiting for status stage event\n");
1103 switch (trb_comp_code
) {
1105 /* Double check that the HW transferred everything. */
1106 if (event_trb
!= td
->last_trb
) {
1107 xhci_warn(xhci
, "WARN Successful completion "
1109 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1110 status
= -EREMOTEIO
;
1114 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1115 xhci_dbg(xhci
, "Successful bulk "
1118 xhci_dbg(xhci
, "Successful interrupt "
1124 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1125 status
= -EREMOTEIO
;
1130 /* Others already handled above */
1133 dev_dbg(&td
->urb
->dev
->dev
,
1134 "ep %#x - asked for %d bytes, "
1135 "%d bytes untransferred\n",
1136 td
->urb
->ep
->desc
.bEndpointAddress
,
1137 td
->urb
->transfer_buffer_length
,
1138 TRB_LEN(event
->transfer_len
));
1139 /* Fast path - was this the last TRB in the TD for this URB? */
1140 if (event_trb
== td
->last_trb
) {
1141 if (TRB_LEN(event
->transfer_len
) != 0) {
1142 td
->urb
->actual_length
=
1143 td
->urb
->transfer_buffer_length
-
1144 TRB_LEN(event
->transfer_len
);
1145 if (td
->urb
->transfer_buffer_length
<
1146 td
->urb
->actual_length
) {
1147 xhci_warn(xhci
, "HC gave bad length "
1148 "of %d bytes left\n",
1149 TRB_LEN(event
->transfer_len
));
1150 td
->urb
->actual_length
= 0;
1151 if (td
->urb
->transfer_flags
&
1153 status
= -EREMOTEIO
;
1157 /* Don't overwrite a previously set error code */
1158 if (status
== -EINPROGRESS
) {
1159 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1160 status
= -EREMOTEIO
;
1165 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1166 /* Ignore a short packet completion if the
1167 * untransferred length was zero.
1169 if (status
== -EREMOTEIO
)
1173 /* Slow path - walk the list, starting from the dequeue
1174 * pointer, to get the actual length transferred.
1176 union xhci_trb
*cur_trb
;
1177 struct xhci_segment
*cur_seg
;
1179 td
->urb
->actual_length
= 0;
1180 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1181 cur_trb
!= event_trb
;
1182 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1183 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
1184 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
1185 td
->urb
->actual_length
+=
1186 TRB_LEN(cur_trb
->generic
.field
[2]);
1188 /* If the ring didn't stop on a Link or No-op TRB, add
1189 * in the actual bytes transferred from the Normal TRB
1191 if (trb_comp_code
!= COMP_STOP_INVAL
)
1192 td
->urb
->actual_length
+=
1193 TRB_LEN(cur_trb
->generic
.field
[2]) -
1194 TRB_LEN(event
->transfer_len
);
1197 if (trb_comp_code
== COMP_STOP_INVAL
||
1198 trb_comp_code
== COMP_STOP
) {
1199 /* The Endpoint Stop Command completion will take care of any
1200 * stopped TDs. A stopped TD may be restarted, so don't update
1201 * the ring dequeue pointer or take this TD off any lists yet.
1203 ep
->stopped_td
= td
;
1204 ep
->stopped_trb
= event_trb
;
1206 if (trb_comp_code
== COMP_STALL
||
1207 trb_comp_code
== COMP_BABBLE
) {
1208 /* The transfer is completed from the driver's
1209 * perspective, but we need to issue a set dequeue
1210 * command for this stalled endpoint to move the dequeue
1211 * pointer past the TD. We can't do that here because
1212 * the halt condition must be cleared first.
1214 ep
->stopped_td
= td
;
1215 ep
->stopped_trb
= event_trb
;
1217 /* Update ring dequeue pointer */
1218 while (ep_ring
->dequeue
!= td
->last_trb
)
1219 inc_deq(xhci
, ep_ring
, false);
1220 inc_deq(xhci
, ep_ring
, false);
1224 /* Clean up the endpoint's TD list */
1226 /* Do one last check of the actual transfer length.
1227 * If the host controller said we transferred more data than
1228 * the buffer length, urb->actual_length will be a very big
1229 * number (since it's unsigned). Play it safe and say we didn't
1230 * transfer anything.
1232 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1233 xhci_warn(xhci
, "URB transfer length is wrong, "
1234 "xHC issue? req. len = %u, "
1236 urb
->transfer_buffer_length
,
1237 urb
->actual_length
);
1238 urb
->actual_length
= 0;
1239 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1240 status
= -EREMOTEIO
;
1244 list_del(&td
->td_list
);
1245 /* Was this TD slated to be cancelled but completed anyway? */
1246 if (!list_empty(&td
->cancelled_td_list
)) {
1247 list_del(&td
->cancelled_td_list
);
1248 ep
->cancels_pending
--;
1250 /* Leave the TD around for the reset endpoint function to use
1251 * (but only if it's not a control endpoint, since we already
1252 * queued the Set TR dequeue pointer command for stalled
1253 * control endpoints).
1255 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
1256 (trb_comp_code
!= COMP_STALL
&&
1257 trb_comp_code
!= COMP_BABBLE
)) {
1263 inc_deq(xhci
, xhci
->event_ring
, true);
1264 xhci_set_hc_event_deq(xhci
);
1266 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1268 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1269 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1270 urb
, urb
->actual_length
, status
);
1271 spin_unlock(&xhci
->lock
);
1272 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1273 spin_lock(&xhci
->lock
);
1279 * This function handles all OS-owned events on the event ring. It may drop
1280 * xhci->lock between event processing (e.g. to pass up port status changes).
1282 void xhci_handle_event(struct xhci_hcd
*xhci
)
1284 union xhci_trb
*event
;
1285 int update_ptrs
= 1;
1288 xhci_dbg(xhci
, "In %s\n", __func__
);
1289 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1290 xhci
->error_bitmask
|= 1 << 1;
1294 event
= xhci
->event_ring
->dequeue
;
1295 /* Does the HC or OS own the TRB? */
1296 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1297 xhci
->event_ring
->cycle_state
) {
1298 xhci
->error_bitmask
|= 1 << 2;
1301 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1303 /* FIXME: Handle more event types. */
1304 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1305 case TRB_TYPE(TRB_COMPLETION
):
1306 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1307 handle_cmd_completion(xhci
, &event
->event_cmd
);
1308 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1310 case TRB_TYPE(TRB_PORT_STATUS
):
1311 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1312 handle_port_status(xhci
, event
);
1313 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1316 case TRB_TYPE(TRB_TRANSFER
):
1317 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1318 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1319 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1321 xhci
->error_bitmask
|= 1 << 9;
1326 xhci
->error_bitmask
|= 1 << 3;
1330 /* Update SW and HC event ring dequeue pointer */
1331 inc_deq(xhci
, xhci
->event_ring
, true);
1332 xhci_set_hc_event_deq(xhci
);
1334 /* Are there more items on the event ring? */
1335 xhci_handle_event(xhci
);
1338 /**** Endpoint Ring Operations ****/
1341 * Generic function for queueing a TRB on a ring.
1342 * The caller must have checked to make sure there's room on the ring.
1344 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1346 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1348 struct xhci_generic_trb
*trb
;
1350 trb
= &ring
->enqueue
->generic
;
1351 trb
->field
[0] = field1
;
1352 trb
->field
[1] = field2
;
1353 trb
->field
[2] = field3
;
1354 trb
->field
[3] = field4
;
1355 inc_enq(xhci
, ring
, consumer
);
1359 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1360 * FIXME allocate segments if the ring is full.
1362 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1363 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1365 /* Make sure the endpoint has been added to xHC schedule */
1366 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1368 case EP_STATE_DISABLED
:
1370 * USB core changed config/interfaces without notifying us,
1371 * or hardware is reporting the wrong state.
1373 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1375 case EP_STATE_ERROR
:
1376 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
1377 /* FIXME event handling code for error needs to clear it */
1378 /* XXX not sure if this should be -ENOENT or not */
1380 case EP_STATE_HALTED
:
1381 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
1382 case EP_STATE_STOPPED
:
1383 case EP_STATE_RUNNING
:
1386 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1388 * FIXME issue Configure Endpoint command to try to get the HC
1389 * back into a known state.
1393 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1394 /* FIXME allocate more room */
1395 xhci_err(xhci
, "ERROR no room on ep ring\n");
1401 static int prepare_transfer(struct xhci_hcd
*xhci
,
1402 struct xhci_virt_device
*xdev
,
1403 unsigned int ep_index
,
1404 unsigned int num_trbs
,
1406 struct xhci_td
**td
,
1410 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1411 ret
= prepare_ring(xhci
, xdev
->eps
[ep_index
].ring
,
1412 ep_ctx
->ep_info
& EP_STATE_MASK
,
1413 num_trbs
, mem_flags
);
1416 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1419 INIT_LIST_HEAD(&(*td
)->td_list
);
1420 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1422 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1423 if (unlikely(ret
)) {
1429 urb
->hcpriv
= (void *) (*td
);
1430 /* Add this TD to the tail of the endpoint ring's TD list */
1431 list_add_tail(&(*td
)->td_list
, &xdev
->eps
[ep_index
].ring
->td_list
);
1432 (*td
)->start_seg
= xdev
->eps
[ep_index
].ring
->enq_seg
;
1433 (*td
)->first_trb
= xdev
->eps
[ep_index
].ring
->enqueue
;
1438 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1440 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1441 struct scatterlist
*sg
;
1444 num_sgs
= urb
->num_sgs
;
1445 temp
= urb
->transfer_buffer_length
;
1447 xhci_dbg(xhci
, "count sg list trbs: \n");
1449 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1450 unsigned int previous_total_trbs
= num_trbs
;
1451 unsigned int len
= sg_dma_len(sg
);
1453 /* Scatter gather list entries may cross 64KB boundaries */
1454 running_total
= TRB_MAX_BUFF_SIZE
-
1455 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1456 if (running_total
!= 0)
1459 /* How many more 64KB chunks to transfer, how many more TRBs? */
1460 while (running_total
< sg_dma_len(sg
)) {
1462 running_total
+= TRB_MAX_BUFF_SIZE
;
1464 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1465 i
, (unsigned long long)sg_dma_address(sg
),
1466 len
, len
, num_trbs
- previous_total_trbs
);
1468 len
= min_t(int, len
, temp
);
1473 xhci_dbg(xhci
, "\n");
1474 if (!in_interrupt())
1475 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1476 urb
->ep
->desc
.bEndpointAddress
,
1477 urb
->transfer_buffer_length
,
1482 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1485 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1486 "TRBs, %d left\n", __func__
,
1487 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1488 if (running_total
!= urb
->transfer_buffer_length
)
1489 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1490 "queued %#x (%d), asked for %#x (%d)\n",
1492 urb
->ep
->desc
.bEndpointAddress
,
1493 running_total
, running_total
,
1494 urb
->transfer_buffer_length
,
1495 urb
->transfer_buffer_length
);
1498 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1499 unsigned int ep_index
, int start_cycle
,
1500 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1503 * Pass all the TRBs to the hardware at once and make sure this write
1507 start_trb
->field
[3] |= start_cycle
;
1508 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1512 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1513 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1514 * (comprised of sg list entries) can take several service intervals to
1517 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1518 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1520 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
1521 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1525 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
1526 ep_interval
= urb
->interval
;
1527 /* Convert to microframes */
1528 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1529 urb
->dev
->speed
== USB_SPEED_FULL
)
1531 /* FIXME change this to a warning and a suggestion to use the new API
1532 * to set the polling interval (once the API is added).
1534 if (xhci_interval
!= ep_interval
) {
1535 if (!printk_ratelimit())
1536 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
1537 " (%d microframe%s) than xHCI "
1538 "(%d microframe%s)\n",
1540 ep_interval
== 1 ? "" : "s",
1542 xhci_interval
== 1 ? "" : "s");
1543 urb
->interval
= xhci_interval
;
1544 /* Convert back to frames for LS/FS devices */
1545 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1546 urb
->dev
->speed
== USB_SPEED_FULL
)
1549 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
1552 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1553 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1555 struct xhci_ring
*ep_ring
;
1556 unsigned int num_trbs
;
1558 struct scatterlist
*sg
;
1560 int trb_buff_len
, this_sg_len
, running_total
;
1564 struct xhci_generic_trb
*start_trb
;
1567 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1568 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1569 num_sgs
= urb
->num_sgs
;
1571 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1572 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1573 if (trb_buff_len
< 0)
1574 return trb_buff_len
;
1576 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1577 * until we've finished creating all the other TRBs. The ring's cycle
1578 * state may change as we enqueue the other TRBs, so save it too.
1580 start_trb
= &ep_ring
->enqueue
->generic
;
1581 start_cycle
= ep_ring
->cycle_state
;
1585 * How much data is in the first TRB?
1587 * There are three forces at work for TRB buffer pointers and lengths:
1588 * 1. We don't want to walk off the end of this sg-list entry buffer.
1589 * 2. The transfer length that the driver requested may be smaller than
1590 * the amount of memory allocated for this scatter-gather list.
1591 * 3. TRBs buffers can't cross 64KB boundaries.
1594 addr
= (u64
) sg_dma_address(sg
);
1595 this_sg_len
= sg_dma_len(sg
);
1596 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1597 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1598 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1599 if (trb_buff_len
> urb
->transfer_buffer_length
)
1600 trb_buff_len
= urb
->transfer_buffer_length
;
1601 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1605 /* Queue the first TRB, even if it's zero-length */
1608 u32 length_field
= 0;
1610 /* Don't change the cycle bit of the first TRB until later */
1614 field
|= ep_ring
->cycle_state
;
1616 /* Chain all the TRBs together; clear the chain bit in the last
1617 * TRB to indicate it's the last TRB in the chain.
1622 /* FIXME - add check for ZERO_PACKET flag before this */
1623 td
->last_trb
= ep_ring
->enqueue
;
1626 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1627 "64KB boundary at %#x, end dma = %#x\n",
1628 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1629 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1630 (unsigned int) addr
+ trb_buff_len
);
1631 if (TRB_MAX_BUFF_SIZE
-
1632 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1633 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1634 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1635 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1636 (unsigned int) addr
+ trb_buff_len
);
1638 length_field
= TRB_LEN(trb_buff_len
) |
1639 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1641 queue_trb(xhci
, ep_ring
, false,
1642 lower_32_bits(addr
),
1643 upper_32_bits(addr
),
1645 /* We always want to know if the TRB was short,
1646 * or we won't get an event when it completes.
1647 * (Unless we use event data TRBs, which are a
1648 * waste of space and HC resources.)
1650 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1652 running_total
+= trb_buff_len
;
1654 /* Calculate length for next transfer --
1655 * Are we done queueing all the TRBs for this sg entry?
1657 this_sg_len
-= trb_buff_len
;
1658 if (this_sg_len
== 0) {
1663 addr
= (u64
) sg_dma_address(sg
);
1664 this_sg_len
= sg_dma_len(sg
);
1666 addr
+= trb_buff_len
;
1669 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1670 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1671 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1672 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1674 urb
->transfer_buffer_length
- running_total
;
1675 } while (running_total
< urb
->transfer_buffer_length
);
1677 check_trb_math(urb
, num_trbs
, running_total
);
1678 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1682 /* This is very similar to what ehci-q.c qtd_fill() does */
1683 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1684 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1686 struct xhci_ring
*ep_ring
;
1689 struct xhci_generic_trb
*start_trb
;
1692 u32 field
, length_field
;
1694 int running_total
, trb_buff_len
, ret
;
1698 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1700 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1703 /* How much data is (potentially) left before the 64KB boundary? */
1704 running_total
= TRB_MAX_BUFF_SIZE
-
1705 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1707 /* If there's some data on this 64KB chunk, or we have to send a
1708 * zero-length transfer, we need at least one TRB
1710 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1712 /* How many more 64KB chunks to transfer, how many more TRBs? */
1713 while (running_total
< urb
->transfer_buffer_length
) {
1715 running_total
+= TRB_MAX_BUFF_SIZE
;
1717 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1719 if (!in_interrupt())
1720 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1721 urb
->ep
->desc
.bEndpointAddress
,
1722 urb
->transfer_buffer_length
,
1723 urb
->transfer_buffer_length
,
1724 (unsigned long long)urb
->transfer_dma
,
1727 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1728 num_trbs
, urb
, &td
, mem_flags
);
1733 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1734 * until we've finished creating all the other TRBs. The ring's cycle
1735 * state may change as we enqueue the other TRBs, so save it too.
1737 start_trb
= &ep_ring
->enqueue
->generic
;
1738 start_cycle
= ep_ring
->cycle_state
;
1741 /* How much data is in the first TRB? */
1742 addr
= (u64
) urb
->transfer_dma
;
1743 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1744 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1745 if (urb
->transfer_buffer_length
< trb_buff_len
)
1746 trb_buff_len
= urb
->transfer_buffer_length
;
1750 /* Queue the first TRB, even if it's zero-length */
1754 /* Don't change the cycle bit of the first TRB until later */
1758 field
|= ep_ring
->cycle_state
;
1760 /* Chain all the TRBs together; clear the chain bit in the last
1761 * TRB to indicate it's the last TRB in the chain.
1766 /* FIXME - add check for ZERO_PACKET flag before this */
1767 td
->last_trb
= ep_ring
->enqueue
;
1770 length_field
= TRB_LEN(trb_buff_len
) |
1771 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1773 queue_trb(xhci
, ep_ring
, false,
1774 lower_32_bits(addr
),
1775 upper_32_bits(addr
),
1777 /* We always want to know if the TRB was short,
1778 * or we won't get an event when it completes.
1779 * (Unless we use event data TRBs, which are a
1780 * waste of space and HC resources.)
1782 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1784 running_total
+= trb_buff_len
;
1786 /* Calculate length for next transfer */
1787 addr
+= trb_buff_len
;
1788 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
1789 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
1790 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
1791 } while (running_total
< urb
->transfer_buffer_length
);
1793 check_trb_math(urb
, num_trbs
, running_total
);
1794 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1798 /* Caller must have locked xhci->lock */
1799 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1800 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1802 struct xhci_ring
*ep_ring
;
1805 struct usb_ctrlrequest
*setup
;
1806 struct xhci_generic_trb
*start_trb
;
1808 u32 field
, length_field
;
1811 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1814 * Need to copy setup packet into setup TRB, so we can't use the setup
1817 if (!urb
->setup_packet
)
1820 if (!in_interrupt())
1821 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
1823 /* 1 TRB for setup, 1 for status */
1826 * Don't need to check if we need additional event data and normal TRBs,
1827 * since data in control transfers will never get bigger than 16MB
1828 * XXX: can we get a buffer that crosses 64KB boundaries?
1830 if (urb
->transfer_buffer_length
> 0)
1832 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
1833 urb
, &td
, mem_flags
);
1838 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1839 * until we've finished creating all the other TRBs. The ring's cycle
1840 * state may change as we enqueue the other TRBs, so save it too.
1842 start_trb
= &ep_ring
->enqueue
->generic
;
1843 start_cycle
= ep_ring
->cycle_state
;
1845 /* Queue setup TRB - see section 6.4.1.2.1 */
1846 /* FIXME better way to translate setup_packet into two u32 fields? */
1847 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
1848 queue_trb(xhci
, ep_ring
, false,
1849 /* FIXME endianness is probably going to bite my ass here. */
1850 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
1851 setup
->wIndex
| setup
->wLength
<< 16,
1852 TRB_LEN(8) | TRB_INTR_TARGET(0),
1853 /* Immediate data in pointer */
1854 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
1856 /* If there's data, queue data TRBs */
1858 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
1859 TD_REMAINDER(urb
->transfer_buffer_length
) |
1861 if (urb
->transfer_buffer_length
> 0) {
1862 if (setup
->bRequestType
& USB_DIR_IN
)
1863 field
|= TRB_DIR_IN
;
1864 queue_trb(xhci
, ep_ring
, false,
1865 lower_32_bits(urb
->transfer_dma
),
1866 upper_32_bits(urb
->transfer_dma
),
1868 /* Event on short tx */
1869 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
1872 /* Save the DMA address of the last TRB in the TD */
1873 td
->last_trb
= ep_ring
->enqueue
;
1875 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1876 /* If the device sent data, the status stage is an OUT transfer */
1877 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
1881 queue_trb(xhci
, ep_ring
, false,
1885 /* Event on completion */
1886 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
1888 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1892 /**** Command Ring Operations ****/
1894 /* Generic function for queueing a command TRB on the command ring.
1895 * Check to make sure there's room on the command ring for one command TRB.
1896 * Also check that there's room reserved for commands that must not fail.
1897 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
1898 * then only check for the number of reserved spots.
1899 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
1900 * because the command event handler may want to resubmit a failed command.
1902 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
1903 u32 field3
, u32 field4
, bool command_must_succeed
)
1905 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
1906 if (!command_must_succeed
)
1909 if (!room_on_ring(xhci
, xhci
->cmd_ring
, reserved_trbs
)) {
1910 if (!in_interrupt())
1911 xhci_err(xhci
, "ERR: No room for command on command ring\n");
1912 if (command_must_succeed
)
1913 xhci_err(xhci
, "ERR: Reserved TRB counting for "
1914 "unfailable commands failed.\n");
1917 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
1918 field4
| xhci
->cmd_ring
->cycle_state
);
1922 /* Queue a no-op command on the command ring */
1923 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
1925 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
), false);
1929 * Place a no-op command on the command ring to test the command and
1932 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
1934 if (queue_cmd_noop(xhci
) < 0)
1936 xhci
->noops_submitted
++;
1937 return xhci_ring_cmd_db
;
1940 /* Queue a slot enable or disable request on the command ring */
1941 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
1943 return queue_command(xhci
, 0, 0, 0,
1944 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
1947 /* Queue an address device command TRB */
1948 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1951 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1952 upper_32_bits(in_ctx_ptr
), 0,
1953 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
1957 /* Queue a configure endpoint command TRB */
1958 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1959 u32 slot_id
, bool command_must_succeed
)
1961 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1962 upper_32_bits(in_ctx_ptr
), 0,
1963 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
1964 command_must_succeed
);
1967 /* Queue an evaluate context command TRB */
1968 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1971 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1972 upper_32_bits(in_ctx_ptr
), 0,
1973 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
1977 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1978 unsigned int ep_index
)
1980 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1981 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1982 u32 type
= TRB_TYPE(TRB_STOP_RING
);
1984 return queue_command(xhci
, 0, 0, 0,
1985 trb_slot_id
| trb_ep_index
| type
, false);
1988 /* Set Transfer Ring Dequeue Pointer command.
1989 * This should not be used for endpoints that have streams enabled.
1991 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
1992 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
1993 union xhci_trb
*deq_ptr
, u32 cycle_state
)
1996 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1997 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1998 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
2000 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
2002 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
2003 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
2007 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
2008 upper_32_bits(addr
), 0,
2009 trb_slot_id
| trb_ep_index
| type
, false);
2012 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
2013 unsigned int ep_index
)
2015 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2016 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2017 u32 type
= TRB_TYPE(TRB_RESET_EP
);
2019 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,