arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/pm.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/sysdev.h>
  24
  25 #include <mach/hardware.h>
  26 #include <mach/pxa3xx-regs.h>
  27 #include <mach/reset.h>
  28 #include <mach/ohci.h>
  29 #include <mach/pm.h>
  30 #include <mach/dma.h>
  31 #include <mach/ssp.h>
  32
  33 #include "generic.h"
  34 #include "devices.h"
  35 #include "clock.h"
  36
  37 /* Crystal clock: 13MHz */
  38 #define BASE_CLK        13000000
  39
  40 /* Ring Oscillator Clock: 60MHz */
  41 #define RO_CLK          60000000
  42
  43 #define ACCR_D0CS       (1 << 26)
  44 #define ACCR_PCCE       (1 << 11)
  45
  46 /* crystal frequency to static memory controller multiplier (SMCFS) */
  47 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
  48
  49 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
  50 static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
  51
  52 /*
  53  * Get the clock frequency as reflected by CCSR and the turbo flag.
  54  * We assume these values have been applied via a fcs.
  55  * If info is not 0 we also display the current settings.
  56  */
  57 unsigned int pxa3xx_get_clk_frequency_khz(int info)
  58 {
  59         unsigned long acsr, xclkcfg;
  60         unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
  61
  62         /* Read XCLKCFG register turbo bit */
  63         __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
  64         t = xclkcfg & 0x1;
  65
  66         acsr = ACSR;
  67
  68         xl  = acsr & 0x1f;
  69         xn  = (acsr >> 8) & 0x7;
  70         hss = (acsr >> 14) & 0x3;
  71
  72         XL = xl * BASE_CLK;
  73         XN = xn * XL;
  74
  75         ro = acsr & ACCR_D0CS;
  76
  77         CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
  78         HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  79
  80         if (info) {
  81                 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
  82                         RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
  83                         (ro) ? "" : "in");
  84                 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
  85                         XL / 1000000, (XL % 1000000) / 10000, xl);
  86                 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
  87                         XN / 1000000, (XN % 1000000) / 10000, xn,
  88                         (t) ? "" : "in");
  89                 pr_info("HSIO bus clock: %d.%02dMHz\n",
  90                         HSS / 1000000, (HSS % 1000000) / 10000);
  91         }
  92
  93         return CLK / 1000;
  94 }
  95
  96 /*
  97  * Return the current static memory controller clock frequency
  98  * in units of 10kHz
  99  */
 100 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
 101 {
 102         unsigned long acsr;
 103         unsigned int smcfs, clk = 0;
 104
 105         acsr = ACSR;
 106
 107         smcfs = (acsr >> 23) & 0x7;
 108         clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
 109
 110         return (clk / 10000);
 111 }
 112
 113 void pxa3xx_clear_reset_status(unsigned int mask)
 114 {
 115         /* RESET_STATUS_* has a 1:1 mapping with ARSR */
 116         ARSR = mask;
 117 }
 118
 119 /*
 120  * Return the current AC97 clock frequency.
 121  */
 122 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
 123 {
 124         unsigned long rate = 312000000;
 125         unsigned long ac97_div;
 126
 127         ac97_div = AC97_DIV;
 128
 129         /* This may loose precision for some rates but won't for the
 130          * standard 24.576MHz.
 131          */
 132         rate /= (ac97_div >> 12) & 0x7fff;
 133         rate *= (ac97_div & 0xfff);
 134
 135         return rate;
 136 }
 137
 138 /*
 139  * Return the current HSIO bus clock frequency
 140  */
 141 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
 142 {
 143         unsigned long acsr;
 144         unsigned int hss, hsio_clk;
 145
 146         acsr = ACSR;
 147
 148         hss = (acsr >> 14) & 0x3;
 149         hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
 150
 151         return hsio_clk;
 152 }
 153
 154 void clk_pxa3xx_cken_enable(struct clk *clk)
 155 {
 156         unsigned long mask = 1ul << (clk->cken & 0x1f);
 157
 158         if (clk->cken < 32)
 159                 CKENA |= mask;
 160         else
 161                 CKENB |= mask;
 162 }
 163
 164 void clk_pxa3xx_cken_disable(struct clk *clk)
 165 {
 166         unsigned long mask = 1ul << (clk->cken & 0x1f);
 167
 168         if (clk->cken < 32)
 169                 CKENA &= ~mask;
 170         else
 171                 CKENB &= ~mask;
 172 }
 173
 174 const struct clkops clk_pxa3xx_cken_ops = {
 175         .enable         = clk_pxa3xx_cken_enable,
 176         .disable        = clk_pxa3xx_cken_disable,
 177 };
 178
 179 static const struct clkops clk_pxa3xx_hsio_ops = {
 180         .enable         = clk_pxa3xx_cken_enable,
 181         .disable        = clk_pxa3xx_cken_disable,
 182         .getrate        = clk_pxa3xx_hsio_getrate,
 183 };
 184
 185 static const struct clkops clk_pxa3xx_ac97_ops = {
 186         .enable         = clk_pxa3xx_cken_enable,
 187         .disable        = clk_pxa3xx_cken_disable,
 188         .getrate        = clk_pxa3xx_ac97_getrate,
 189 };
 190
 191 static void clk_pout_enable(struct clk *clk)
 192 {
 193         OSCC |= OSCC_PEN;
 194 }
 195
 196 static void clk_pout_disable(struct clk *clk)
 197 {
 198         OSCC &= ~OSCC_PEN;
 199 }
 200
 201 static const struct clkops clk_pout_ops = {
 202         .enable         = clk_pout_enable,
 203         .disable        = clk_pout_disable,
 204 };
 205
 206 static struct clk pxa3xx_clks[] = {
 207         {
 208                 .name           = "CLK_POUT",
 209                 .ops            = &clk_pout_ops,
 210                 .rate           = 13000000,
 211                 .delay          = 70,
 212         },
 213
 214         PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
 215         PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
 216         PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
 217
 218         PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
 219         PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
 220         PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
 221
 222         PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
 223         PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa27x_device_udc.dev),
 224         PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
 225         PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
 226
 227         PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
 228         PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
 229         PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
 230         PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
 231         PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
 232         PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
 233
 234         PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
 235         PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
 236 };
 237
 238 #ifdef CONFIG_PM
 239
 240 #define ISRAM_START     0x5c000000
 241 #define ISRAM_SIZE      SZ_256K
 242
 243 static void __iomem *sram;
 244 static unsigned long wakeup_src;
 245
 246 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 247 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 248
 249 enum {  SLEEP_SAVE_CKENA,
 250         SLEEP_SAVE_CKENB,
 251         SLEEP_SAVE_ACCR,
 252
 253         SLEEP_SAVE_COUNT,
 254 };
 255
 256 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
 257 {
 258         SAVE(CKENA);
 259         SAVE(CKENB);
 260         SAVE(ACCR);
 261 }
 262
 263 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
 264 {
 265         RESTORE(ACCR);
 266         RESTORE(CKENA);
 267         RESTORE(CKENB);
 268 }
 269
 270 /*
 271  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 272  * memory controller has to be reinitialised, so we place some code
 273  * in the SRAM to perform this function.
 274  *
 275  * We disable FIQs across the standby - otherwise, we might receive a
 276  * FIQ while the SDRAM is unavailable.
 277  */
 278 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 279 {
 280         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 281         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 282
 283         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 284                     pm_enter_standby_end - pm_enter_standby_start);
 285
 286         AD2D0SR = ~0;
 287         AD2D1SR = ~0;
 288         AD2D0ER = wakeup_src;
 289         AD2D1ER = 0;
 290         ASCR = ASCR;
 291         ARSR = ARSR;
 292
 293         local_fiq_disable();
 294         fn(pwrmode);
 295         local_fiq_enable();
 296
 297         AD2D0ER = 0;
 298         AD2D1ER = 0;
 299 }
 300
 301 /*
 302  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 303  * PXA3xx development kits assumes that the resuming process continues
 304  * with the address stored within the first 4 bytes of SDRAM. The PSPR
 305  * register is used privately by BootROM and OBM, and _must_ be set to
 306  * 0x5c014000 for the moment.
 307  */
 308 static void pxa3xx_cpu_pm_suspend(void)
 309 {
 310         volatile unsigned long *p = (volatile void *)0xc0000000;
 311         unsigned long saved_data = *p;
 312
 313         extern void pxa3xx_cpu_suspend(void);
 314         extern void pxa3xx_cpu_resume(void);
 315
 316         /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 317         CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
 318         CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
 319
 320         /* clear and setup wakeup source */
 321         AD3SR = ~0;
 322         AD3ER = wakeup_src;
 323         ASCR = ASCR;
 324         ARSR = ARSR;
 325
 326         PCFR |= (1u << 13);                     /* L1_DIS */
 327         PCFR &= ~((1u << 12) | (1u << 1));      /* L0_EN | SL_ROD */
 328
 329         PSPR = 0x5c014000;
 330
 331         /* overwrite with the resume address */
 332         *p = virt_to_phys(pxa3xx_cpu_resume);
 333
 334         pxa3xx_cpu_suspend();
 335
 336         *p = saved_data;
 337
 338         AD3ER = 0;
 339 }
 340
 341 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 342 {
 343         /*
 344          * Don't sleep if no wakeup sources are defined
 345          */
 346         if (wakeup_src == 0) {
 347                 printk(KERN_ERR "Not suspending: no wakeup sources\n");
 348                 return;
 349         }
 350
 351         switch (state) {
 352         case PM_SUSPEND_STANDBY:
 353                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 354                 break;
 355
 356         case PM_SUSPEND_MEM:
 357                 pxa3xx_cpu_pm_suspend();
 358                 break;
 359         }
 360 }
 361
 362 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 363 {
 364         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 365 }
 366
 367 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 368         .save_count     = SLEEP_SAVE_COUNT,
 369         .save           = pxa3xx_cpu_pm_save,
 370         .restore        = pxa3xx_cpu_pm_restore,
 371         .valid          = pxa3xx_cpu_pm_valid,
 372         .enter          = pxa3xx_cpu_pm_enter,
 373 };
 374
 375 static void __init pxa3xx_init_pm(void)
 376 {
 377         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 378         if (!sram) {
 379                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 380                 return;
 381         }
 382
 383         /*
 384          * Since we copy wakeup code into the SRAM, we need to ensure
 385          * that it is preserved over the low power modes.  Note: bit 8
 386          * is undocumented in the developer manual, but must be set.
 387          */
 388         AD1R |= ADXR_L2 | ADXR_R0;
 389         AD2R |= ADXR_L2 | ADXR_R0;
 390         AD3R |= ADXR_L2 | ADXR_R0;
 391
 392         /*
 393          * Clear the resume enable registers.
 394          */
 395         AD1D0ER = 0;
 396         AD2D0ER = 0;
 397         AD2D1ER = 0;
 398         AD3ER = 0;
 399
 400         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 401 }
 402
 403 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 404 {
 405         unsigned long flags, mask = 0;
 406
 407         switch (irq) {
 408         case IRQ_SSP3:
 409                 mask = ADXER_MFP_WSSP3;
 410                 break;
 411         case IRQ_MSL:
 412                 mask = ADXER_WMSL0;
 413                 break;
 414         case IRQ_USBH2:
 415         case IRQ_USBH1:
 416                 mask = ADXER_WUSBH;
 417                 break;
 418         case IRQ_KEYPAD:
 419                 mask = ADXER_WKP;
 420                 break;
 421         case IRQ_AC97:
 422                 mask = ADXER_MFP_WAC97;
 423                 break;
 424         case IRQ_USIM:
 425                 mask = ADXER_WUSIM0;
 426                 break;
 427         case IRQ_SSP2:
 428                 mask = ADXER_MFP_WSSP2;
 429                 break;
 430         case IRQ_I2C:
 431                 mask = ADXER_MFP_WI2C;
 432                 break;
 433         case IRQ_STUART:
 434                 mask = ADXER_MFP_WUART3;
 435                 break;
 436         case IRQ_BTUART:
 437                 mask = ADXER_MFP_WUART2;
 438                 break;
 439         case IRQ_FFUART:
 440                 mask = ADXER_MFP_WUART1;
 441                 break;
 442         case IRQ_MMC:
 443                 mask = ADXER_MFP_WMMC1;
 444                 break;
 445         case IRQ_SSP:
 446                 mask = ADXER_MFP_WSSP1;
 447                 break;
 448         case IRQ_RTCAlrm:
 449                 mask = ADXER_WRTC;
 450                 break;
 451         case IRQ_SSP4:
 452                 mask = ADXER_MFP_WSSP4;
 453                 break;
 454         case IRQ_TSI:
 455                 mask = ADXER_WTSI;
 456                 break;
 457         case IRQ_USIM2:
 458                 mask = ADXER_WUSIM1;
 459                 break;
 460         case IRQ_MMC2:
 461                 mask = ADXER_MFP_WMMC2;
 462                 break;
 463         case IRQ_NAND:
 464                 mask = ADXER_MFP_WFLASH;
 465                 break;
 466         case IRQ_USB2:
 467                 mask = ADXER_WUSB2;
 468                 break;
 469         case IRQ_WAKEUP0:
 470                 mask = ADXER_WEXTWAKE0;
 471                 break;
 472         case IRQ_WAKEUP1:
 473                 mask = ADXER_WEXTWAKE1;
 474                 break;
 475         case IRQ_MMC3:
 476                 mask = ADXER_MFP_GEN12;
 477                 break;
 478         default:
 479                 return -EINVAL;
 480         }
 481
 482         local_irq_save(flags);
 483         if (on)
 484                 wakeup_src |= mask;
 485         else
 486                 wakeup_src &= ~mask;
 487         local_irq_restore(flags);
 488
 489         return 0;
 490 }
 491 #else
 492 static inline void pxa3xx_init_pm(void) {}
 493 #define pxa3xx_set_wake NULL
 494 #endif
 495
 496 void __init pxa3xx_init_irq(void)
 497 {
 498         /* enable CP6 access */
 499         u32 value;
 500         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 501         value |= (1 << 6);
 502         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 503
 504         pxa_init_irq(56, pxa3xx_set_wake);
 505         pxa_init_gpio(128, NULL);
 506 }
 507
 508 /*
 509  * device registration specific to PXA3xx.
 510  */
 511
 512 static struct platform_device *devices[] __initdata = {
 513 /*      &pxa_device_udc,        The UDC driver is PXA25x only */
 514         &pxa_device_ffuart,
 515         &pxa_device_btuart,
 516         &pxa_device_stuart,
 517         &pxa_device_i2s,
 518         &pxa_device_rtc,
 519         &pxa27x_device_ssp1,
 520         &pxa27x_device_ssp2,
 521         &pxa27x_device_ssp3,
 522         &pxa3xx_device_ssp4,
 523         &pxa27x_device_pwm0,
 524         &pxa27x_device_pwm1,
 525 };
 526
 527 static struct sys_device pxa3xx_sysdev[] = {
 528         {
 529                 .cls    = &pxa_irq_sysclass,
 530         }, {
 531                 .cls    = &pxa3xx_mfp_sysclass,
 532         }, {
 533                 .cls    = &pxa_gpio_sysclass,
 534         },
 535 };
 536
 537 static int __init pxa3xx_init(void)
 538 {
 539         int i, ret = 0;
 540
 541         if (cpu_is_pxa3xx()) {
 542
 543                 reset_status = ARSR;
 544
 545                 /*
 546                  * clear RDH bit every time after reset
 547                  *
 548                  * Note: the last 3 bits DxS are write-1-to-clear so carefully
 549                  * preserve them here in case they will be referenced later
 550                  */
 551                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 552
 553                 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
 554
 555                 if ((ret = pxa_init_dma(32)))
 556                         return ret;
 557
 558                 pxa3xx_init_pm();
 559
 560                 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
 561                         ret = sysdev_register(&pxa3xx_sysdev[i]);
 562                         if (ret)
 563                                 pr_err("failed to register sysdev[%d]\n", i);
 564                 }
 565
 566                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 567         }
 568
 569         return ret;
 570 }
 571
 572 postcore_initcall(pxa3xx_init);