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[PATCH] reiserfs: handle trans_id overflow
[linux-2.6/mini2440.git] / drivers / scsi / sata_mv.c
blob275ed9bd898cae8a0d1d25d5d47b7a077715179f
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.6"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
57
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
64
65 MV_MAX_Q_DEPTH = 32,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 */
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_MAX_SG_CT = 176,
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
90 ATA_FLAG_NO_ATAPI),
91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
92
93 CRQB_FLAG_READ = (1 << 0),
94 CRQB_TAG_SHIFT = 1,
95 CRQB_CMD_ADDR_SHIFT = 8,
96 CRQB_CMD_CS = (0x2 << 11),
97 CRQB_CMD_LAST = (1 << 15),
98
99 CRPB_FLAG_STATUS_SHIFT = 8,
100
101 EPRD_FLAG_END_OF_TBL = (1 << 31),
102
103 /* PCI interface registers */
104
105 PCI_COMMAND_OFS = 0xc00,
106
107 PCI_MAIN_CMD_STS_OFS = 0xd30,
108 STOP_PCI_MASTER = (1 << 2),
109 PCI_MASTER_EMPTY = (1 << 3),
110 GLOB_SFT_RST = (1 << 4),
111
112 MV_PCI_MODE = 0xd00,
113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
122
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
126
127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
128 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
129 PORT0_ERR = (1 << 0), /* shift by port # */
130 PORT0_DONE = (1 << 1), /* shift by port # */
131 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
132 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
133 PCI_ERR = (1 << 18),
134 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
135 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
136 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
137 GPIO_INT = (1 << 22),
138 SELF_INT = (1 << 23),
139 TWSI_INT = (1 << 24),
140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
143 HC_MAIN_RSVD),
144
145 /* SATAHC registers */
146 HC_CFG_OFS = 0,
147
148 HC_IRQ_CAUSE_OFS = 0x14,
149 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
150 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
151 DEV_IRQ = (1 << 8), /* shift by port # */
152
153 /* Shadow block registers */
154 SHD_BLK_OFS = 0x100,
155 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
156
157 /* SATA registers */
158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
159 SATA_ACTIVE_OFS = 0x350,
160 PHY_MODE3 = 0x310,
161 PHY_MODE4 = 0x314,
162 PHY_MODE2 = 0x330,
163 MV5_PHY_MODE = 0x74,
164 MV5_LT_MODE = 0x30,
165 MV5_PHY_CTL = 0x0C,
166 SATA_INTERFACE_CTL = 0x050,
167
168 MV_M2_PREAMP_MASK = 0x7e0,
169
170 /* Port registers */
171 EDMA_CFG_OFS = 0,
172 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
173 EDMA_CFG_NCQ = (1 << 5),
174 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
175 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
176 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
177
178 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
179 EDMA_ERR_IRQ_MASK_OFS = 0xc,
180 EDMA_ERR_D_PAR = (1 << 0),
181 EDMA_ERR_PRD_PAR = (1 << 1),
182 EDMA_ERR_DEV = (1 << 2),
183 EDMA_ERR_DEV_DCON = (1 << 3),
184 EDMA_ERR_DEV_CON = (1 << 4),
185 EDMA_ERR_SERR = (1 << 5),
186 EDMA_ERR_SELF_DIS = (1 << 7),
187 EDMA_ERR_BIST_ASYNC = (1 << 8),
188 EDMA_ERR_CRBQ_PAR = (1 << 9),
189 EDMA_ERR_CRPB_PAR = (1 << 10),
190 EDMA_ERR_INTRL_PAR = (1 << 11),
191 EDMA_ERR_IORDY = (1 << 12),
192 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
193 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
194 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
197 EDMA_ERR_TRANS_PROTO = (1 << 31),
198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
202 EDMA_ERR_LNK_DATA_RX |
203 EDMA_ERR_LNK_DATA_TX |
204 EDMA_ERR_TRANS_PROTO),
205
206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
208
209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
210 EDMA_REQ_Q_PTR_SHIFT = 5,
211
212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
215 EDMA_RSP_Q_PTR_SHIFT = 3,
216
217 EDMA_CMD_OFS = 0x28,
218 EDMA_EN = (1 << 0),
219 EDMA_DS = (1 << 1),
220 ATA_RST = (1 << 2),
221
222 EDMA_IORDY_TMOUT = 0x34,
223 EDMA_ARB_CFG = 0x38,
224
225 /* Host private flags (hp_flags) */
226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_ERRATA_XX42A0 = (1 << 5),
232 MV_HP_50XX = (1 << 6),
233 MV_HP_GEN_IIE = (1 << 7),
234
235 /* Port private flags (pp_flags) */
236 MV_PP_FLAG_EDMA_EN = (1 << 0),
237 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
238 };
239
240 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
241 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
242 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
243 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
244 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
245
246 enum {
247 /* Our DMA boundary is determined by an ePRD being unable to handle
248 * anything larger than 64KB
249 */
250 MV_DMA_BOUNDARY = 0xffffU,
251
252 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
253
254 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
255 };
256
257 enum chip_type {
258 chip_504x,
259 chip_508x,
260 chip_5080,
261 chip_604x,
262 chip_608x,
263 chip_6042,
264 chip_7042,
265 };
266
267 /* Command ReQuest Block: 32B */
268 struct mv_crqb {
269 u32 sg_addr;
270 u32 sg_addr_hi;
271 u16 ctrl_flags;
272 u16 ata_cmd[11];
273 };
274
275 struct mv_crqb_iie {
276 u32 addr;
277 u32 addr_hi;
278 u32 flags;
279 u32 len;
280 u32 ata_cmd[4];
281 };
282
283 /* Command ResPonse Block: 8B */
284 struct mv_crpb {
285 u16 id;
286 u16 flags;
287 u32 tmstmp;
288 };
289
290 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
291 struct mv_sg {
292 u32 addr;
293 u32 flags_size;
294 u32 addr_hi;
295 u32 reserved;
296 };
297
298 struct mv_port_priv {
299 struct mv_crqb *crqb;
300 dma_addr_t crqb_dma;
301 struct mv_crpb *crpb;
302 dma_addr_t crpb_dma;
303 struct mv_sg *sg_tbl;
304 dma_addr_t sg_tbl_dma;
305
306 unsigned req_producer; /* cp of req_in_ptr */
307 unsigned rsp_consumer; /* cp of rsp_out_ptr */
308 u32 pp_flags;
309 };
310
311 struct mv_port_signal {
312 u32 amps;
313 u32 pre;
314 };
315
316 struct mv_host_priv;
317 struct mv_hw_ops {
318 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
319 unsigned int port);
320 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
321 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
322 void __iomem *mmio);
323 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
324 unsigned int n_hc);
325 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
326 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
327 };
328
329 struct mv_host_priv {
330 u32 hp_flags;
331 struct mv_port_signal signal[8];
332 const struct mv_hw_ops *ops;
333 };
334
335 static void mv_irq_clear(struct ata_port *ap);
336 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
337 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
338 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
339 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
340 static void mv_phy_reset(struct ata_port *ap);
341 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
342 static void mv_host_stop(struct ata_host_set *host_set);
343 static int mv_port_start(struct ata_port *ap);
344 static void mv_port_stop(struct ata_port *ap);
345 static void mv_qc_prep(struct ata_queued_cmd *qc);
346 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
347 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
348 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
349 struct pt_regs *regs);
350 static void mv_eng_timeout(struct ata_port *ap);
351 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
352
353 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
354 unsigned int port);
355 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
356 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
357 void __iomem *mmio);
358 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
359 unsigned int n_hc);
360 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
361 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
362
363 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
364 unsigned int port);
365 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
366 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
367 void __iomem *mmio);
368 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
369 unsigned int n_hc);
370 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
371 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
372 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
373 unsigned int port_no);
374 static void mv_stop_and_reset(struct ata_port *ap);
375
376 static struct scsi_host_template mv_sht = {
377 .module = THIS_MODULE,
378 .name = DRV_NAME,
379 .ioctl = ata_scsi_ioctl,
380 .queuecommand = ata_scsi_queuecmd,
381 .eh_strategy_handler = ata_scsi_error,
382 .can_queue = MV_USE_Q_DEPTH,
383 .this_id = ATA_SHT_THIS_ID,
384 .sg_tablesize = MV_MAX_SG_CT / 2,
385 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
386 .emulated = ATA_SHT_EMULATED,
387 .use_clustering = ATA_SHT_USE_CLUSTERING,
388 .proc_name = DRV_NAME,
389 .dma_boundary = MV_DMA_BOUNDARY,
390 .slave_configure = ata_scsi_slave_config,
391 .bios_param = ata_std_bios_param,
392 };
393
394 static const struct ata_port_operations mv5_ops = {
395 .port_disable = ata_port_disable,
396
397 .tf_load = ata_tf_load,
398 .tf_read = ata_tf_read,
399 .check_status = ata_check_status,
400 .exec_command = ata_exec_command,
401 .dev_select = ata_std_dev_select,
402
403 .phy_reset = mv_phy_reset,
404
405 .qc_prep = mv_qc_prep,
406 .qc_issue = mv_qc_issue,
407
408 .eng_timeout = mv_eng_timeout,
409
410 .irq_handler = mv_interrupt,
411 .irq_clear = mv_irq_clear,
412
413 .scr_read = mv5_scr_read,
414 .scr_write = mv5_scr_write,
415
416 .port_start = mv_port_start,
417 .port_stop = mv_port_stop,
418 .host_stop = mv_host_stop,
419 };
420
421 static const struct ata_port_operations mv6_ops = {
422 .port_disable = ata_port_disable,
423
424 .tf_load = ata_tf_load,
425 .tf_read = ata_tf_read,
426 .check_status = ata_check_status,
427 .exec_command = ata_exec_command,
428 .dev_select = ata_std_dev_select,
429
430 .phy_reset = mv_phy_reset,
431
432 .qc_prep = mv_qc_prep,
433 .qc_issue = mv_qc_issue,
434
435 .eng_timeout = mv_eng_timeout,
436
437 .irq_handler = mv_interrupt,
438 .irq_clear = mv_irq_clear,
439
440 .scr_read = mv_scr_read,
441 .scr_write = mv_scr_write,
442
443 .port_start = mv_port_start,
444 .port_stop = mv_port_stop,
445 .host_stop = mv_host_stop,
446 };
447
448 static const struct ata_port_operations mv_iie_ops = {
449 .port_disable = ata_port_disable,
450
451 .tf_load = ata_tf_load,
452 .tf_read = ata_tf_read,
453 .check_status = ata_check_status,
454 .exec_command = ata_exec_command,
455 .dev_select = ata_std_dev_select,
456
457 .phy_reset = mv_phy_reset,
458
459 .qc_prep = mv_qc_prep_iie,
460 .qc_issue = mv_qc_issue,
461
462 .eng_timeout = mv_eng_timeout,
463
464 .irq_handler = mv_interrupt,
465 .irq_clear = mv_irq_clear,
466
467 .scr_read = mv_scr_read,
468 .scr_write = mv_scr_write,
469
470 .port_start = mv_port_start,
471 .port_stop = mv_port_stop,
472 .host_stop = mv_host_stop,
473 };
474
475 static const struct ata_port_info mv_port_info[] = {
476 { /* chip_504x */
477 .sht = &mv_sht,
478 .host_flags = MV_COMMON_FLAGS,
479 .pio_mask = 0x1f, /* pio0-4 */
480 .udma_mask = 0x7f, /* udma0-6 */
481 .port_ops = &mv5_ops,
482 },
483 { /* chip_508x */
484 .sht = &mv_sht,
485 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
486 .pio_mask = 0x1f, /* pio0-4 */
487 .udma_mask = 0x7f, /* udma0-6 */
488 .port_ops = &mv5_ops,
489 },
490 { /* chip_5080 */
491 .sht = &mv_sht,
492 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
493 .pio_mask = 0x1f, /* pio0-4 */
494 .udma_mask = 0x7f, /* udma0-6 */
495 .port_ops = &mv5_ops,
496 },
497 { /* chip_604x */
498 .sht = &mv_sht,
499 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
500 .pio_mask = 0x1f, /* pio0-4 */
501 .udma_mask = 0x7f, /* udma0-6 */
502 .port_ops = &mv6_ops,
503 },
504 { /* chip_608x */
505 .sht = &mv_sht,
506 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
507 MV_FLAG_DUAL_HC),
508 .pio_mask = 0x1f, /* pio0-4 */
509 .udma_mask = 0x7f, /* udma0-6 */
510 .port_ops = &mv6_ops,
511 },
512 { /* chip_6042 */
513 .sht = &mv_sht,
514 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
515 .pio_mask = 0x1f, /* pio0-4 */
516 .udma_mask = 0x7f, /* udma0-6 */
517 .port_ops = &mv_iie_ops,
518 },
519 { /* chip_7042 */
520 .sht = &mv_sht,
521 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
522 MV_FLAG_DUAL_HC),
523 .pio_mask = 0x1f, /* pio0-4 */
524 .udma_mask = 0x7f, /* udma0-6 */
525 .port_ops = &mv_iie_ops,
526 },
527 };
528
529 static const struct pci_device_id mv_pci_tbl[] = {
530 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
531 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
532 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
533 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
534
535 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
536 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
537 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042},
538 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
539 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
540
541 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
542 {} /* terminate list */
543 };
544
545 static struct pci_driver mv_pci_driver = {
546 .name = DRV_NAME,
547 .id_table = mv_pci_tbl,
548 .probe = mv_init_one,
549 .remove = ata_pci_remove_one,
550 };
551
552 static const struct mv_hw_ops mv5xxx_ops = {
553 .phy_errata = mv5_phy_errata,
554 .enable_leds = mv5_enable_leds,
555 .read_preamp = mv5_read_preamp,
556 .reset_hc = mv5_reset_hc,
557 .reset_flash = mv5_reset_flash,
558 .reset_bus = mv5_reset_bus,
559 };
560
561 static const struct mv_hw_ops mv6xxx_ops = {
562 .phy_errata = mv6_phy_errata,
563 .enable_leds = mv6_enable_leds,
564 .read_preamp = mv6_read_preamp,
565 .reset_hc = mv6_reset_hc,
566 .reset_flash = mv6_reset_flash,
567 .reset_bus = mv_reset_pci_bus,
568 };
569
570 /*
571 * module options
572 */
573 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
574
575
576 /*
577 * Functions
578 */
579
580 static inline void writelfl(unsigned long data, void __iomem *addr)
581 {
582 writel(data, addr);
583 (void) readl(addr); /* flush to avoid PCI posted write */
584 }
585
586 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
587 {
588 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
589 }
590
591 static inline unsigned int mv_hc_from_port(unsigned int port)
592 {
593 return port >> MV_PORT_HC_SHIFT;
594 }
595
596 static inline unsigned int mv_hardport_from_port(unsigned int port)
597 {
598 return port & MV_PORT_MASK;
599 }
600
601 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
602 unsigned int port)
603 {
604 return mv_hc_base(base, mv_hc_from_port(port));
605 }
606
607 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
608 {
609 return mv_hc_base_from_port(base, port) +
610 MV_SATAHC_ARBTR_REG_SZ +
611 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
612 }
613
614 static inline void __iomem *mv_ap_base(struct ata_port *ap)
615 {
616 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
617 }
618
619 static inline int mv_get_hc_count(unsigned long host_flags)
620 {
621 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
622 }
623
624 static void mv_irq_clear(struct ata_port *ap)
625 {
626 }
627
628 /**
629 * mv_start_dma - Enable eDMA engine
630 * @base: port base address
631 * @pp: port private data
632 *
633 * Verify the local cache of the eDMA state is accurate with a
634 * WARN_ON.
635 *
636 * LOCKING:
637 * Inherited from caller.
638 */
639 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
640 {
641 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
642 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
643 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
644 }
645 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
646 }
647
648 /**
649 * mv_stop_dma - Disable eDMA engine
650 * @ap: ATA channel to manipulate
651 *
652 * Verify the local cache of the eDMA state is accurate with a
653 * WARN_ON.
654 *
655 * LOCKING:
656 * Inherited from caller.
657 */
658 static void mv_stop_dma(struct ata_port *ap)
659 {
660 void __iomem *port_mmio = mv_ap_base(ap);
661 struct mv_port_priv *pp = ap->private_data;
662 u32 reg;
663 int i;
664
665 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
666 /* Disable EDMA if active. The disable bit auto clears.
667 */
668 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
669 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
670 } else {
671 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
672 }
673
674 /* now properly wait for the eDMA to stop */
675 for (i = 1000; i > 0; i--) {
676 reg = readl(port_mmio + EDMA_CMD_OFS);
677 if (!(EDMA_EN & reg)) {
678 break;
679 }
680 udelay(100);
681 }
682
683 if (EDMA_EN & reg) {
684 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
685 /* FIXME: Consider doing a reset here to recover */
686 }
687 }
688
689 #ifdef ATA_DEBUG
690 static void mv_dump_mem(void __iomem *start, unsigned bytes)
691 {
692 int b, w;
693 for (b = 0; b < bytes; ) {
694 DPRINTK("%p: ", start + b);
695 for (w = 0; b < bytes && w < 4; w++) {
696 printk("%08x ",readl(start + b));
697 b += sizeof(u32);
698 }
699 printk("\n");
700 }
701 }
702 #endif
703
704 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
705 {
706 #ifdef ATA_DEBUG
707 int b, w;
708 u32 dw;
709 for (b = 0; b < bytes; ) {
710 DPRINTK("%02x: ", b);
711 for (w = 0; b < bytes && w < 4; w++) {
712 (void) pci_read_config_dword(pdev,b,&dw);
713 printk("%08x ",dw);
714 b += sizeof(u32);
715 }
716 printk("\n");
717 }
718 #endif
719 }
720 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
721 struct pci_dev *pdev)
722 {
723 #ifdef ATA_DEBUG
724 void __iomem *hc_base = mv_hc_base(mmio_base,
725 port >> MV_PORT_HC_SHIFT);
726 void __iomem *port_base;
727 int start_port, num_ports, p, start_hc, num_hcs, hc;
728
729 if (0 > port) {
730 start_hc = start_port = 0;
731 num_ports = 8; /* shld be benign for 4 port devs */
732 num_hcs = 2;
733 } else {
734 start_hc = port >> MV_PORT_HC_SHIFT;
735 start_port = port;
736 num_ports = num_hcs = 1;
737 }
738 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
739 num_ports > 1 ? num_ports - 1 : start_port);
740
741 if (NULL != pdev) {
742 DPRINTK("PCI config space regs:\n");
743 mv_dump_pci_cfg(pdev, 0x68);
744 }
745 DPRINTK("PCI regs:\n");
746 mv_dump_mem(mmio_base+0xc00, 0x3c);
747 mv_dump_mem(mmio_base+0xd00, 0x34);
748 mv_dump_mem(mmio_base+0xf00, 0x4);
749 mv_dump_mem(mmio_base+0x1d00, 0x6c);
750 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
751 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
752 DPRINTK("HC regs (HC %i):\n", hc);
753 mv_dump_mem(hc_base, 0x1c);
754 }
755 for (p = start_port; p < start_port + num_ports; p++) {
756 port_base = mv_port_base(mmio_base, p);
757 DPRINTK("EDMA regs (port %i):\n",p);
758 mv_dump_mem(port_base, 0x54);
759 DPRINTK("SATA regs (port %i):\n",p);
760 mv_dump_mem(port_base+0x300, 0x60);
761 }
762 #endif
763 }
764
765 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
766 {
767 unsigned int ofs;
768
769 switch (sc_reg_in) {
770 case SCR_STATUS:
771 case SCR_CONTROL:
772 case SCR_ERROR:
773 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
774 break;
775 case SCR_ACTIVE:
776 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
777 break;
778 default:
779 ofs = 0xffffffffU;
780 break;
781 }
782 return ofs;
783 }
784
785 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
786 {
787 unsigned int ofs = mv_scr_offset(sc_reg_in);
788
789 if (0xffffffffU != ofs) {
790 return readl(mv_ap_base(ap) + ofs);
791 } else {
792 return (u32) ofs;
793 }
794 }
795
796 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
797 {
798 unsigned int ofs = mv_scr_offset(sc_reg_in);
799
800 if (0xffffffffU != ofs) {
801 writelfl(val, mv_ap_base(ap) + ofs);
802 }
803 }
804
805 /**
806 * mv_host_stop - Host specific cleanup/stop routine.
807 * @host_set: host data structure
808 *
809 * Disable ints, cleanup host memory, call general purpose
810 * host_stop.
811 *
812 * LOCKING:
813 * Inherited from caller.
814 */
815 static void mv_host_stop(struct ata_host_set *host_set)
816 {
817 struct mv_host_priv *hpriv = host_set->private_data;
818 struct pci_dev *pdev = to_pci_dev(host_set->dev);
819
820 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
821 pci_disable_msi(pdev);
822 } else {
823 pci_intx(pdev, 0);
824 }
825 kfree(hpriv);
826 ata_host_stop(host_set);
827 }
828
829 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
830 {
831 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
832 }
833
834 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
835 {
836 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
837
838 /* set up non-NCQ EDMA configuration */
839 cfg &= ~0x1f; /* clear queue depth */
840 cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
841 cfg &= ~(1 << 9); /* disable equeue */
842
843 if (IS_GEN_I(hpriv))
844 cfg |= (1 << 8); /* enab config burst size mask */
845
846 else if (IS_GEN_II(hpriv))
847 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
848
849 else if (IS_GEN_IIE(hpriv)) {
850 cfg |= (1 << 23); /* dis RX PM port mask */
851 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
852 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
853 cfg |= (1 << 18); /* enab early completion */
854 cfg |= (1 << 17); /* enab host q cache */
855 cfg |= (1 << 22); /* enab cutthrough */
856 }
857
858 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
859 }
860
861 /**
862 * mv_port_start - Port specific init/start routine.
863 * @ap: ATA channel to manipulate
864 *
865 * Allocate and point to DMA memory, init port private memory,
866 * zero indices.
867 *
868 * LOCKING:
869 * Inherited from caller.
870 */
871 static int mv_port_start(struct ata_port *ap)
872 {
873 struct device *dev = ap->host_set->dev;
874 struct mv_host_priv *hpriv = ap->host_set->private_data;
875 struct mv_port_priv *pp;
876 void __iomem *port_mmio = mv_ap_base(ap);
877 void *mem;
878 dma_addr_t mem_dma;
879 int rc = -ENOMEM;
880
881 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
882 if (!pp)
883 goto err_out;
884 memset(pp, 0, sizeof(*pp));
885
886 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
887 GFP_KERNEL);
888 if (!mem)
889 goto err_out_pp;
890 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
891
892 rc = ata_pad_alloc(ap, dev);
893 if (rc)
894 goto err_out_priv;
895
896 /* First item in chunk of DMA memory:
897 * 32-slot command request table (CRQB), 32 bytes each in size
898 */
899 pp->crqb = mem;
900 pp->crqb_dma = mem_dma;
901 mem += MV_CRQB_Q_SZ;
902 mem_dma += MV_CRQB_Q_SZ;
903
904 /* Second item:
905 * 32-slot command response table (CRPB), 8 bytes each in size
906 */
907 pp->crpb = mem;
908 pp->crpb_dma = mem_dma;
909 mem += MV_CRPB_Q_SZ;
910 mem_dma += MV_CRPB_Q_SZ;
911
912 /* Third item:
913 * Table of scatter-gather descriptors (ePRD), 16 bytes each
914 */
915 pp->sg_tbl = mem;
916 pp->sg_tbl_dma = mem_dma;
917
918 mv_edma_cfg(hpriv, port_mmio);
919
920 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
921 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
922 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
923
924 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
925 writelfl(pp->crqb_dma & 0xffffffff,
926 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
927 else
928 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
929
930 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
931
932 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
933 writelfl(pp->crpb_dma & 0xffffffff,
934 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
935 else
936 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
937
938 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
939 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
940
941 pp->req_producer = pp->rsp_consumer = 0;
942
943 /* Don't turn on EDMA here...do it before DMA commands only. Else
944 * we'll be unable to send non-data, PIO, etc due to restricted access
945 * to shadow regs.
946 */
947 ap->private_data = pp;
948 return 0;
949
950 err_out_priv:
951 mv_priv_free(pp, dev);
952 err_out_pp:
953 kfree(pp);
954 err_out:
955 return rc;
956 }
957
958 /**
959 * mv_port_stop - Port specific cleanup/stop routine.
960 * @ap: ATA channel to manipulate
961 *
962 * Stop DMA, cleanup port memory.
963 *
964 * LOCKING:
965 * This routine uses the host_set lock to protect the DMA stop.
966 */
967 static void mv_port_stop(struct ata_port *ap)
968 {
969 struct device *dev = ap->host_set->dev;
970 struct mv_port_priv *pp = ap->private_data;
971 unsigned long flags;
972
973 spin_lock_irqsave(&ap->host_set->lock, flags);
974 mv_stop_dma(ap);
975 spin_unlock_irqrestore(&ap->host_set->lock, flags);
976
977 ap->private_data = NULL;
978 ata_pad_free(ap, dev);
979 mv_priv_free(pp, dev);
980 kfree(pp);
981 }
982
983 /**
984 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
985 * @qc: queued command whose SG list to source from
986 *
987 * Populate the SG list and mark the last entry.
988 *
989 * LOCKING:
990 * Inherited from caller.
991 */
992 static void mv_fill_sg(struct ata_queued_cmd *qc)
993 {
994 struct mv_port_priv *pp = qc->ap->private_data;
995 unsigned int i = 0;
996 struct scatterlist *sg;
997
998 ata_for_each_sg(sg, qc) {
999 dma_addr_t addr;
1000 u32 sg_len, len, offset;
1001
1002 addr = sg_dma_address(sg);
1003 sg_len = sg_dma_len(sg);
1004
1005 while (sg_len) {
1006 offset = addr & MV_DMA_BOUNDARY;
1007 len = sg_len;
1008 if ((offset + sg_len) > 0x10000)
1009 len = 0x10000 - offset;
1010
1011 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
1012 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1013 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
1014
1015 sg_len -= len;
1016 addr += len;
1017
1018 if (!sg_len && ata_sg_is_last(sg, qc))
1019 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1020
1021 i++;
1022 }
1023 }
1024 }
1025
1026 static inline unsigned mv_inc_q_index(unsigned *index)
1027 {
1028 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
1029 return *index;
1030 }
1031
1032 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
1033 {
1034 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1035 (last ? CRQB_CMD_LAST : 0);
1036 }
1037
1038 /**
1039 * mv_qc_prep - Host specific command preparation.
1040 * @qc: queued command to prepare
1041 *
1042 * This routine simply redirects to the general purpose routine
1043 * if command is not DMA. Else, it handles prep of the CRQB
1044 * (command request block), does some sanity checking, and calls
1045 * the SG load routine.
1046 *
1047 * LOCKING:
1048 * Inherited from caller.
1049 */
1050 static void mv_qc_prep(struct ata_queued_cmd *qc)
1051 {
1052 struct ata_port *ap = qc->ap;
1053 struct mv_port_priv *pp = ap->private_data;
1054 u16 *cw;
1055 struct ata_taskfile *tf;
1056 u16 flags = 0;
1057
1058 if (ATA_PROT_DMA != qc->tf.protocol)
1059 return;
1060
1061 /* the req producer index should be the same as we remember it */
1062 WARN_ON(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
1063 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1064 pp->req_producer);
1065
1066 /* Fill in command request block
1067 */
1068 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1069 flags |= CRQB_FLAG_READ;
1070 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1071 flags |= qc->tag << CRQB_TAG_SHIFT;
1072
1073 pp->crqb[pp->req_producer].sg_addr =
1074 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1075 pp->crqb[pp->req_producer].sg_addr_hi =
1076 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1077 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
1078
1079 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
1080 tf = &qc->tf;
1081
1082 /* Sadly, the CRQB cannot accomodate all registers--there are
1083 * only 11 bytes...so we must pick and choose required
1084 * registers based on the command. So, we drop feature and
1085 * hob_feature for [RW] DMA commands, but they are needed for
1086 * NCQ. NCQ will drop hob_nsect.
1087 */
1088 switch (tf->command) {
1089 case ATA_CMD_READ:
1090 case ATA_CMD_READ_EXT:
1091 case ATA_CMD_WRITE:
1092 case ATA_CMD_WRITE_EXT:
1093 case ATA_CMD_WRITE_FUA_EXT:
1094 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1095 break;
1096 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1097 case ATA_CMD_FPDMA_READ:
1098 case ATA_CMD_FPDMA_WRITE:
1099 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1100 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1101 break;
1102 #endif /* FIXME: remove this line when NCQ added */
1103 default:
1104 /* The only other commands EDMA supports in non-queued and
1105 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1106 * of which are defined/used by Linux. If we get here, this
1107 * driver needs work.
1108 *
1109 * FIXME: modify libata to give qc_prep a return value and
1110 * return error here.
1111 */
1112 BUG_ON(tf->command);
1113 break;
1114 }
1115 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1116 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1117 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1118 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1119 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1120 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1121 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1122 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1123 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1124
1125 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1126 return;
1127 mv_fill_sg(qc);
1128 }
1129
1130 /**
1131 * mv_qc_prep_iie - Host specific command preparation.
1132 * @qc: queued command to prepare
1133 *
1134 * This routine simply redirects to the general purpose routine
1135 * if command is not DMA. Else, it handles prep of the CRQB
1136 * (command request block), does some sanity checking, and calls
1137 * the SG load routine.
1138 *
1139 * LOCKING:
1140 * Inherited from caller.
1141 */
1142 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1143 {
1144 struct ata_port *ap = qc->ap;
1145 struct mv_port_priv *pp = ap->private_data;
1146 struct mv_crqb_iie *crqb;
1147 struct ata_taskfile *tf;
1148 u32 flags = 0;
1149
1150 if (ATA_PROT_DMA != qc->tf.protocol)
1151 return;
1152
1153 /* the req producer index should be the same as we remember it */
1154 WARN_ON(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
1155 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1156 pp->req_producer);
1157
1158 /* Fill in Gen IIE command request block
1159 */
1160 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1161 flags |= CRQB_FLAG_READ;
1162
1163 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1164 flags |= qc->tag << CRQB_TAG_SHIFT;
1165
1166 crqb = (struct mv_crqb_iie *) &pp->crqb[pp->req_producer];
1167 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1168 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1169 crqb->flags = cpu_to_le32(flags);
1170
1171 tf = &qc->tf;
1172 crqb->ata_cmd[0] = cpu_to_le32(
1173 (tf->command << 16) |
1174 (tf->feature << 24)
1175 );
1176 crqb->ata_cmd[1] = cpu_to_le32(
1177 (tf->lbal << 0) |
1178 (tf->lbam << 8) |
1179 (tf->lbah << 16) |
1180 (tf->device << 24)
1181 );
1182 crqb->ata_cmd[2] = cpu_to_le32(
1183 (tf->hob_lbal << 0) |
1184 (tf->hob_lbam << 8) |
1185 (tf->hob_lbah << 16) |
1186 (tf->hob_feature << 24)
1187 );
1188 crqb->ata_cmd[3] = cpu_to_le32(
1189 (tf->nsect << 0) |
1190 (tf->hob_nsect << 8)
1191 );
1192
1193 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1194 return;
1195 mv_fill_sg(qc);
1196 }
1197
1198 /**
1199 * mv_qc_issue - Initiate a command to the host
1200 * @qc: queued command to start
1201 *
1202 * This routine simply redirects to the general purpose routine
1203 * if command is not DMA. Else, it sanity checks our local
1204 * caches of the request producer/consumer indices then enables
1205 * DMA and bumps the request producer index.
1206 *
1207 * LOCKING:
1208 * Inherited from caller.
1209 */
1210 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1211 {
1212 void __iomem *port_mmio = mv_ap_base(qc->ap);
1213 struct mv_port_priv *pp = qc->ap->private_data;
1214 u32 in_ptr;
1215
1216 if (ATA_PROT_DMA != qc->tf.protocol) {
1217 /* We're about to send a non-EDMA capable command to the
1218 * port. Turn off EDMA so there won't be problems accessing
1219 * shadow block, etc registers.
1220 */
1221 mv_stop_dma(qc->ap);
1222 return ata_qc_issue_prot(qc);
1223 }
1224
1225 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1226
1227 /* the req producer index should be the same as we remember it */
1228 WARN_ON(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1229 pp->req_producer);
1230 /* until we do queuing, the queue should be empty at this point */
1231 WARN_ON(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1232 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1233 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1234
1235 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1236
1237 mv_start_dma(port_mmio, pp);
1238
1239 /* and write the request in pointer to kick the EDMA to life */
1240 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1241 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1242 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1243
1244 return 0;
1245 }
1246
1247 /**
1248 * mv_get_crpb_status - get status from most recently completed cmd
1249 * @ap: ATA channel to manipulate
1250 *
1251 * This routine is for use when the port is in DMA mode, when it
1252 * will be using the CRPB (command response block) method of
1253 * returning command completion information. We check indices
1254 * are good, grab status, and bump the response consumer index to
1255 * prove that we're up to date.
1256 *
1257 * LOCKING:
1258 * Inherited from caller.
1259 */
1260 static u8 mv_get_crpb_status(struct ata_port *ap)
1261 {
1262 void __iomem *port_mmio = mv_ap_base(ap);
1263 struct mv_port_priv *pp = ap->private_data;
1264 u32 out_ptr;
1265 u8 ata_status;
1266
1267 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1268
1269 /* the response consumer index should be the same as we remember it */
1270 WARN_ON(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1271 pp->rsp_consumer);
1272
1273 ata_status = pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT;
1274
1275 /* increment our consumer index... */
1276 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1277
1278 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1279 WARN_ON(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1280 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1281 pp->rsp_consumer);
1282
1283 /* write out our inc'd consumer index so EDMA knows we're caught up */
1284 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1285 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1286 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1287
1288 /* Return ATA status register for completed CRPB */
1289 return ata_status;
1290 }
1291
1292 /**
1293 * mv_err_intr - Handle error interrupts on the port
1294 * @ap: ATA channel to manipulate
1295 *
1296 * In most cases, just clear the interrupt and move on. However,
1297 * some cases require an eDMA reset, which is done right before
1298 * the COMRESET in mv_phy_reset(). The SERR case requires a
1299 * clear of pending errors in the SATA SERROR register. Finally,
1300 * if the port disabled DMA, update our cached copy to match.
1301 *
1302 * LOCKING:
1303 * Inherited from caller.
1304 */
1305 static void mv_err_intr(struct ata_port *ap)
1306 {
1307 void __iomem *port_mmio = mv_ap_base(ap);
1308 u32 edma_err_cause, serr = 0;
1309
1310 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1311
1312 if (EDMA_ERR_SERR & edma_err_cause) {
1313 serr = scr_read(ap, SCR_ERROR);
1314 scr_write_flush(ap, SCR_ERROR, serr);
1315 }
1316 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1317 struct mv_port_priv *pp = ap->private_data;
1318 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1319 }
1320 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1321 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1322
1323 /* Clear EDMA now that SERR cleanup done */
1324 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1325
1326 /* check for fatal here and recover if needed */
1327 if (EDMA_ERR_FATAL & edma_err_cause) {
1328 mv_stop_and_reset(ap);
1329 }
1330 }
1331
1332 /**
1333 * mv_host_intr - Handle all interrupts on the given host controller
1334 * @host_set: host specific structure
1335 * @relevant: port error bits relevant to this host controller
1336 * @hc: which host controller we're to look at
1337 *
1338 * Read then write clear the HC interrupt status then walk each
1339 * port connected to the HC and see if it needs servicing. Port
1340 * success ints are reported in the HC interrupt status reg, the
1341 * port error ints are reported in the higher level main
1342 * interrupt status register and thus are passed in via the
1343 * 'relevant' argument.
1344 *
1345 * LOCKING:
1346 * Inherited from caller.
1347 */
1348 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1349 unsigned int hc)
1350 {
1351 void __iomem *mmio = host_set->mmio_base;
1352 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1353 struct ata_port *ap;
1354 struct ata_queued_cmd *qc;
1355 u32 hc_irq_cause;
1356 int shift, port, port0, hard_port, handled;
1357 unsigned int err_mask;
1358
1359 if (hc == 0) {
1360 port0 = 0;
1361 } else {
1362 port0 = MV_PORTS_PER_HC;
1363 }
1364
1365 /* we'll need the HC success int register in most cases */
1366 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1367 if (hc_irq_cause) {
1368 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1369 }
1370
1371 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1372 hc,relevant,hc_irq_cause);
1373
1374 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1375 u8 ata_status = 0;
1376 ap = host_set->ports[port];
1377 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1378 handled = 0; /* ensure ata_status is set if handled++ */
1379
1380 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1381 /* new CRPB on the queue; just one at a time until NCQ
1382 */
1383 ata_status = mv_get_crpb_status(ap);
1384 handled++;
1385 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1386 /* received ATA IRQ; read the status reg to clear INTRQ
1387 */
1388 ata_status = readb((void __iomem *)
1389 ap->ioaddr.status_addr);
1390 handled++;
1391 }
1392
1393 if (ap &&
1394 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1395 continue;
1396
1397 err_mask = ac_err_mask(ata_status);
1398
1399 shift = port << 1; /* (port * 2) */
1400 if (port >= MV_PORTS_PER_HC) {
1401 shift++; /* skip bit 8 in the HC Main IRQ reg */
1402 }
1403 if ((PORT0_ERR << shift) & relevant) {
1404 mv_err_intr(ap);
1405 err_mask |= AC_ERR_OTHER;
1406 handled++;
1407 }
1408
1409 if (handled && ap) {
1410 qc = ata_qc_from_tag(ap, ap->active_tag);
1411 if (NULL != qc) {
1412 VPRINTK("port %u IRQ found for qc, "
1413 "ata_status 0x%x\n", port,ata_status);
1414 /* mark qc status appropriately */
1415 if (!(qc->tf.ctl & ATA_NIEN)) {
1416 qc->err_mask |= err_mask;
1417 ata_qc_complete(qc);
1418 }
1419 }
1420 }
1421 }
1422 VPRINTK("EXIT\n");
1423 }
1424
1425 /**
1426 * mv_interrupt -
1427 * @irq: unused
1428 * @dev_instance: private data; in this case the host structure
1429 * @regs: unused
1430 *
1431 * Read the read only register to determine if any host
1432 * controllers have pending interrupts. If so, call lower level
1433 * routine to handle. Also check for PCI errors which are only
1434 * reported here.
1435 *
1436 * LOCKING:
1437 * This routine holds the host_set lock while processing pending
1438 * interrupts.
1439 */
1440 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1441 struct pt_regs *regs)
1442 {
1443 struct ata_host_set *host_set = dev_instance;
1444 unsigned int hc, handled = 0, n_hcs;
1445 void __iomem *mmio = host_set->mmio_base;
1446 u32 irq_stat;
1447
1448 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1449
1450 /* check the cases where we either have nothing pending or have read
1451 * a bogus register value which can indicate HW removal or PCI fault
1452 */
1453 if (!irq_stat || (0xffffffffU == irq_stat)) {
1454 return IRQ_NONE;
1455 }
1456
1457 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1458 spin_lock(&host_set->lock);
1459
1460 for (hc = 0; hc < n_hcs; hc++) {
1461 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1462 if (relevant) {
1463 mv_host_intr(host_set, relevant, hc);
1464 handled++;
1465 }
1466 }
1467 if (PCI_ERR & irq_stat) {
1468 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1469 readl(mmio + PCI_IRQ_CAUSE_OFS));
1470
1471 DPRINTK("All regs @ PCI error\n");
1472 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1473
1474 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1475 handled++;
1476 }
1477 spin_unlock(&host_set->lock);
1478
1479 return IRQ_RETVAL(handled);
1480 }
1481
1482 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1483 {
1484 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1485 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1486
1487 return hc_mmio + ofs;
1488 }
1489
1490 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1491 {
1492 unsigned int ofs;
1493
1494 switch (sc_reg_in) {
1495 case SCR_STATUS:
1496 case SCR_ERROR:
1497 case SCR_CONTROL:
1498 ofs = sc_reg_in * sizeof(u32);
1499 break;
1500 default:
1501 ofs = 0xffffffffU;
1502 break;
1503 }
1504 return ofs;
1505 }
1506
1507 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1508 {
1509 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1510 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1511
1512 if (ofs != 0xffffffffU)
1513 return readl(mmio + ofs);
1514 else
1515 return (u32) ofs;
1516 }
1517
1518 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1519 {
1520 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1521 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1522
1523 if (ofs != 0xffffffffU)
1524 writelfl(val, mmio + ofs);
1525 }
1526
1527 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1528 {
1529 u8 rev_id;
1530 int early_5080;
1531
1532 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1533
1534 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1535
1536 if (!early_5080) {
1537 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1538 tmp |= (1 << 0);
1539 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1540 }
1541
1542 mv_reset_pci_bus(pdev, mmio);
1543 }
1544
1545 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1546 {
1547 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1548 }
1549
1550 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1551 void __iomem *mmio)
1552 {
1553 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1554 u32 tmp;
1555
1556 tmp = readl(phy_mmio + MV5_PHY_MODE);
1557
1558 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1559 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1560 }
1561
1562 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1563 {
1564 u32 tmp;
1565
1566 writel(0, mmio + MV_GPIO_PORT_CTL);
1567
1568 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1569
1570 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1571 tmp |= ~(1 << 0);
1572 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1573 }
1574
1575 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1576 unsigned int port)
1577 {
1578 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1579 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1580 u32 tmp;
1581 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1582
1583 if (fix_apm_sq) {
1584 tmp = readl(phy_mmio + MV5_LT_MODE);
1585 tmp |= (1 << 19);
1586 writel(tmp, phy_mmio + MV5_LT_MODE);
1587
1588 tmp = readl(phy_mmio + MV5_PHY_CTL);
1589 tmp &= ~0x3;
1590 tmp |= 0x1;
1591 writel(tmp, phy_mmio + MV5_PHY_CTL);
1592 }
1593
1594 tmp = readl(phy_mmio + MV5_PHY_MODE);
1595 tmp &= ~mask;
1596 tmp |= hpriv->signal[port].pre;
1597 tmp |= hpriv->signal[port].amps;
1598 writel(tmp, phy_mmio + MV5_PHY_MODE);
1599 }
1600
1601
1602 #undef ZERO
1603 #define ZERO(reg) writel(0, port_mmio + (reg))
1604 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1605 unsigned int port)
1606 {
1607 void __iomem *port_mmio = mv_port_base(mmio, port);
1608
1609 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1610
1611 mv_channel_reset(hpriv, mmio, port);
1612
1613 ZERO(0x028); /* command */
1614 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1615 ZERO(0x004); /* timer */
1616 ZERO(0x008); /* irq err cause */
1617 ZERO(0x00c); /* irq err mask */
1618 ZERO(0x010); /* rq bah */
1619 ZERO(0x014); /* rq inp */
1620 ZERO(0x018); /* rq outp */
1621 ZERO(0x01c); /* respq bah */
1622 ZERO(0x024); /* respq outp */
1623 ZERO(0x020); /* respq inp */
1624 ZERO(0x02c); /* test control */
1625 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1626 }
1627 #undef ZERO
1628
1629 #define ZERO(reg) writel(0, hc_mmio + (reg))
1630 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1631 unsigned int hc)
1632 {
1633 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1634 u32 tmp;
1635
1636 ZERO(0x00c);
1637 ZERO(0x010);
1638 ZERO(0x014);
1639 ZERO(0x018);
1640
1641 tmp = readl(hc_mmio + 0x20);
1642 tmp &= 0x1c1c1c1c;
1643 tmp |= 0x03030303;
1644 writel(tmp, hc_mmio + 0x20);
1645 }
1646 #undef ZERO
1647
1648 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1649 unsigned int n_hc)
1650 {
1651 unsigned int hc, port;
1652
1653 for (hc = 0; hc < n_hc; hc++) {
1654 for (port = 0; port < MV_PORTS_PER_HC; port++)
1655 mv5_reset_hc_port(hpriv, mmio,
1656 (hc * MV_PORTS_PER_HC) + port);
1657
1658 mv5_reset_one_hc(hpriv, mmio, hc);
1659 }
1660
1661 return 0;
1662 }
1663
1664 #undef ZERO
1665 #define ZERO(reg) writel(0, mmio + (reg))
1666 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1667 {
1668 u32 tmp;
1669
1670 tmp = readl(mmio + MV_PCI_MODE);
1671 tmp &= 0xff00ffff;
1672 writel(tmp, mmio + MV_PCI_MODE);
1673
1674 ZERO(MV_PCI_DISC_TIMER);
1675 ZERO(MV_PCI_MSI_TRIGGER);
1676 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1677 ZERO(HC_MAIN_IRQ_MASK_OFS);
1678 ZERO(MV_PCI_SERR_MASK);
1679 ZERO(PCI_IRQ_CAUSE_OFS);
1680 ZERO(PCI_IRQ_MASK_OFS);
1681 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1682 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1683 ZERO(MV_PCI_ERR_ATTRIBUTE);
1684 ZERO(MV_PCI_ERR_COMMAND);
1685 }
1686 #undef ZERO
1687
1688 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1689 {
1690 u32 tmp;
1691
1692 mv5_reset_flash(hpriv, mmio);
1693
1694 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1695 tmp &= 0x3;
1696 tmp |= (1 << 5) | (1 << 6);
1697 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1698 }
1699
1700 /**
1701 * mv6_reset_hc - Perform the 6xxx global soft reset
1702 * @mmio: base address of the HBA
1703 *
1704 * This routine only applies to 6xxx parts.
1705 *
1706 * LOCKING:
1707 * Inherited from caller.
1708 */
1709 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1710 unsigned int n_hc)
1711 {
1712 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1713 int i, rc = 0;
1714 u32 t;
1715
1716 /* Following procedure defined in PCI "main command and status
1717 * register" table.
1718 */
1719 t = readl(reg);
1720 writel(t | STOP_PCI_MASTER, reg);
1721
1722 for (i = 0; i < 1000; i++) {
1723 udelay(1);
1724 t = readl(reg);
1725 if (PCI_MASTER_EMPTY & t) {
1726 break;
1727 }
1728 }
1729 if (!(PCI_MASTER_EMPTY & t)) {
1730 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1731 rc = 1;
1732 goto done;
1733 }
1734
1735 /* set reset */
1736 i = 5;
1737 do {
1738 writel(t | GLOB_SFT_RST, reg);
1739 t = readl(reg);
1740 udelay(1);
1741 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1742
1743 if (!(GLOB_SFT_RST & t)) {
1744 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1745 rc = 1;
1746 goto done;
1747 }
1748
1749 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1750 i = 5;
1751 do {
1752 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1753 t = readl(reg);
1754 udelay(1);
1755 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1756
1757 if (GLOB_SFT_RST & t) {
1758 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1759 rc = 1;
1760 }
1761 done:
1762 return rc;
1763 }
1764
1765 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1766 void __iomem *mmio)
1767 {
1768 void __iomem *port_mmio;
1769 u32 tmp;
1770
1771 tmp = readl(mmio + MV_RESET_CFG);
1772 if ((tmp & (1 << 0)) == 0) {
1773 hpriv->signal[idx].amps = 0x7 << 8;
1774 hpriv->signal[idx].pre = 0x1 << 5;
1775 return;
1776 }
1777
1778 port_mmio = mv_port_base(mmio, idx);
1779 tmp = readl(port_mmio + PHY_MODE2);
1780
1781 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1782 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1783 }
1784
1785 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1786 {
1787 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1788 }
1789
1790 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1791 unsigned int port)
1792 {
1793 void __iomem *port_mmio = mv_port_base(mmio, port);
1794
1795 u32 hp_flags = hpriv->hp_flags;
1796 int fix_phy_mode2 =
1797 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1798 int fix_phy_mode4 =
1799 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1800 u32 m2, tmp;
1801
1802 if (fix_phy_mode2) {
1803 m2 = readl(port_mmio + PHY_MODE2);
1804 m2 &= ~(1 << 16);
1805 m2 |= (1 << 31);
1806 writel(m2, port_mmio + PHY_MODE2);
1807
1808 udelay(200);
1809
1810 m2 = readl(port_mmio + PHY_MODE2);
1811 m2 &= ~((1 << 16) | (1 << 31));
1812 writel(m2, port_mmio + PHY_MODE2);
1813
1814 udelay(200);
1815 }
1816
1817 /* who knows what this magic does */
1818 tmp = readl(port_mmio + PHY_MODE3);
1819 tmp &= ~0x7F800000;
1820 tmp |= 0x2A800000;
1821 writel(tmp, port_mmio + PHY_MODE3);
1822
1823 if (fix_phy_mode4) {
1824 u32 m4;
1825
1826 m4 = readl(port_mmio + PHY_MODE4);
1827
1828 if (hp_flags & MV_HP_ERRATA_60X1B2)
1829 tmp = readl(port_mmio + 0x310);
1830
1831 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1832
1833 writel(m4, port_mmio + PHY_MODE4);
1834
1835 if (hp_flags & MV_HP_ERRATA_60X1B2)
1836 writel(tmp, port_mmio + 0x310);
1837 }
1838
1839 /* Revert values of pre-emphasis and signal amps to the saved ones */
1840 m2 = readl(port_mmio + PHY_MODE2);
1841
1842 m2 &= ~MV_M2_PREAMP_MASK;
1843 m2 |= hpriv->signal[port].amps;
1844 m2 |= hpriv->signal[port].pre;
1845 m2 &= ~(1 << 16);
1846
1847 /* according to mvSata 3.6.1, some IIE values are fixed */
1848 if (IS_GEN_IIE(hpriv)) {
1849 m2 &= ~0xC30FF01F;
1850 m2 |= 0x0000900F;
1851 }
1852
1853 writel(m2, port_mmio + PHY_MODE2);
1854 }
1855
1856 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1857 unsigned int port_no)
1858 {
1859 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1860
1861 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1862
1863 if (IS_60XX(hpriv)) {
1864 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1865 ifctl |= (1 << 12) | (1 << 7);
1866 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1867 }
1868
1869 udelay(25); /* allow reset propagation */
1870
1871 /* Spec never mentions clearing the bit. Marvell's driver does
1872 * clear the bit, however.
1873 */
1874 writelfl(0, port_mmio + EDMA_CMD_OFS);
1875
1876 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1877
1878 if (IS_50XX(hpriv))
1879 mdelay(1);
1880 }
1881
1882 static void mv_stop_and_reset(struct ata_port *ap)
1883 {
1884 struct mv_host_priv *hpriv = ap->host_set->private_data;
1885 void __iomem *mmio = ap->host_set->mmio_base;
1886
1887 mv_stop_dma(ap);
1888
1889 mv_channel_reset(hpriv, mmio, ap->port_no);
1890
1891 __mv_phy_reset(ap, 0);
1892 }
1893
1894 static inline void __msleep(unsigned int msec, int can_sleep)
1895 {
1896 if (can_sleep)
1897 msleep(msec);
1898 else
1899 mdelay(msec);
1900 }
1901
1902 /**
1903 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1904 * @ap: ATA channel to manipulate
1905 *
1906 * Part of this is taken from __sata_phy_reset and modified to
1907 * not sleep since this routine gets called from interrupt level.
1908 *
1909 * LOCKING:
1910 * Inherited from caller. This is coded to safe to call at
1911 * interrupt level, i.e. it does not sleep.
1912 */
1913 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1914 {
1915 struct mv_port_priv *pp = ap->private_data;
1916 struct mv_host_priv *hpriv = ap->host_set->private_data;
1917 void __iomem *port_mmio = mv_ap_base(ap);
1918 struct ata_taskfile tf;
1919 struct ata_device *dev = &ap->device[0];
1920 unsigned long timeout;
1921 int retry = 5;
1922 u32 sstatus;
1923
1924 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1925
1926 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1927 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1928 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1929
1930 /* Issue COMRESET via SControl */
1931 comreset_retry:
1932 scr_write_flush(ap, SCR_CONTROL, 0x301);
1933 __msleep(1, can_sleep);
1934
1935 scr_write_flush(ap, SCR_CONTROL, 0x300);
1936 __msleep(20, can_sleep);
1937
1938 timeout = jiffies + msecs_to_jiffies(200);
1939 do {
1940 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1941 if ((sstatus == 3) || (sstatus == 0))
1942 break;
1943
1944 __msleep(1, can_sleep);
1945 } while (time_before(jiffies, timeout));
1946
1947 /* work around errata */
1948 if (IS_60XX(hpriv) &&
1949 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1950 (retry-- > 0))
1951 goto comreset_retry;
1952
1953 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1954 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1955 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1956
1957 if (sata_dev_present(ap)) {
1958 ata_port_probe(ap);
1959 } else {
1960 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1961 ap->id, scr_read(ap, SCR_STATUS));
1962 ata_port_disable(ap);
1963 return;
1964 }
1965 ap->cbl = ATA_CBL_SATA;
1966
1967 /* even after SStatus reflects that device is ready,
1968 * it seems to take a while for link to be fully
1969 * established (and thus Status no longer 0x80/0x7F),
1970 * so we poll a bit for that, here.
1971 */
1972 retry = 20;
1973 while (1) {
1974 u8 drv_stat = ata_check_status(ap);
1975 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1976 break;
1977 __msleep(500, can_sleep);
1978 if (retry-- <= 0)
1979 break;
1980 }
1981
1982 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1983 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1984 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1985 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1986
1987 dev->class = ata_dev_classify(&tf);
1988 if (!ata_dev_present(dev)) {
1989 VPRINTK("Port disabled post-sig: No device present.\n");
1990 ata_port_disable(ap);
1991 }
1992
1993 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1994
1995 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1996
1997 VPRINTK("EXIT\n");
1998 }
1999
2000 static void mv_phy_reset(struct ata_port *ap)
2001 {
2002 __mv_phy_reset(ap, 1);
2003 }
2004
2005 /**
2006 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2007 * @ap: ATA channel to manipulate
2008 *
2009 * Intent is to clear all pending error conditions, reset the
2010 * chip/bus, fail the command, and move on.
2011 *
2012 * LOCKING:
2013 * This routine holds the host_set lock while failing the command.
2014 */
2015 static void mv_eng_timeout(struct ata_port *ap)
2016 {
2017 struct ata_queued_cmd *qc;
2018
2019 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
2020 DPRINTK("All regs @ start of eng_timeout\n");
2021 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
2022 to_pci_dev(ap->host_set->dev));
2023
2024 qc = ata_qc_from_tag(ap, ap->active_tag);
2025 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2026 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
2027 &qc->scsicmd->cmnd);
2028
2029 mv_err_intr(ap);
2030 mv_stop_and_reset(ap);
2031
2032 qc->err_mask |= AC_ERR_TIMEOUT;
2033 ata_eh_qc_complete(qc);
2034 }
2035
2036 /**
2037 * mv_port_init - Perform some early initialization on a single port.
2038 * @port: libata data structure storing shadow register addresses
2039 * @port_mmio: base address of the port
2040 *
2041 * Initialize shadow register mmio addresses, clear outstanding
2042 * interrupts on the port, and unmask interrupts for the future
2043 * start of the port.
2044 *
2045 * LOCKING:
2046 * Inherited from caller.
2047 */
2048 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2049 {
2050 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
2051 unsigned serr_ofs;
2052
2053 /* PIO related setup
2054 */
2055 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2056 port->error_addr =
2057 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2058 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2059 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2060 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2061 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2062 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2063 port->status_addr =
2064 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2065 /* special case: control/altstatus doesn't have ATA_REG_ address */
2066 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2067
2068 /* unused: */
2069 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
2070
2071 /* Clear any currently outstanding port interrupt conditions */
2072 serr_ofs = mv_scr_offset(SCR_ERROR);
2073 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2074 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2075
2076 /* unmask all EDMA error interrupts */
2077 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2078
2079 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2080 readl(port_mmio + EDMA_CFG_OFS),
2081 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2082 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2083 }
2084
2085 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2086 unsigned int board_idx)
2087 {
2088 u8 rev_id;
2089 u32 hp_flags = hpriv->hp_flags;
2090
2091 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2092
2093 switch(board_idx) {
2094 case chip_5080:
2095 hpriv->ops = &mv5xxx_ops;
2096 hp_flags |= MV_HP_50XX;
2097
2098 switch (rev_id) {
2099 case 0x1:
2100 hp_flags |= MV_HP_ERRATA_50XXB0;
2101 break;
2102 case 0x3:
2103 hp_flags |= MV_HP_ERRATA_50XXB2;
2104 break;
2105 default:
2106 dev_printk(KERN_WARNING, &pdev->dev,
2107 "Applying 50XXB2 workarounds to unknown rev\n");
2108 hp_flags |= MV_HP_ERRATA_50XXB2;
2109 break;
2110 }
2111 break;
2112
2113 case chip_504x:
2114 case chip_508x:
2115 hpriv->ops = &mv5xxx_ops;
2116 hp_flags |= MV_HP_50XX;
2117
2118 switch (rev_id) {
2119 case 0x0:
2120 hp_flags |= MV_HP_ERRATA_50XXB0;
2121 break;
2122 case 0x3:
2123 hp_flags |= MV_HP_ERRATA_50XXB2;
2124 break;
2125 default:
2126 dev_printk(KERN_WARNING, &pdev->dev,
2127 "Applying B2 workarounds to unknown rev\n");
2128 hp_flags |= MV_HP_ERRATA_50XXB2;
2129 break;
2130 }
2131 break;
2132
2133 case chip_604x:
2134 case chip_608x:
2135 hpriv->ops = &mv6xxx_ops;
2136
2137 switch (rev_id) {
2138 case 0x7:
2139 hp_flags |= MV_HP_ERRATA_60X1B2;
2140 break;
2141 case 0x9:
2142 hp_flags |= MV_HP_ERRATA_60X1C0;
2143 break;
2144 default:
2145 dev_printk(KERN_WARNING, &pdev->dev,
2146 "Applying B2 workarounds to unknown rev\n");
2147 hp_flags |= MV_HP_ERRATA_60X1B2;
2148 break;
2149 }
2150 break;
2151
2152 case chip_7042:
2153 case chip_6042:
2154 hpriv->ops = &mv6xxx_ops;
2155
2156 hp_flags |= MV_HP_GEN_IIE;
2157
2158 switch (rev_id) {
2159 case 0x0:
2160 hp_flags |= MV_HP_ERRATA_XX42A0;
2161 break;
2162 case 0x1:
2163 hp_flags |= MV_HP_ERRATA_60X1C0;
2164 break;
2165 default:
2166 dev_printk(KERN_WARNING, &pdev->dev,
2167 "Applying 60X1C0 workarounds to unknown rev\n");
2168 hp_flags |= MV_HP_ERRATA_60X1C0;
2169 break;
2170 }
2171 break;
2172
2173 default:
2174 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2175 return 1;
2176 }
2177
2178 hpriv->hp_flags = hp_flags;
2179
2180 return 0;
2181 }
2182
2183 /**
2184 * mv_init_host - Perform some early initialization of the host.
2185 * @pdev: host PCI device
2186 * @probe_ent: early data struct representing the host
2187 *
2188 * If possible, do an early global reset of the host. Then do
2189 * our port init and clear/unmask all/relevant host interrupts.
2190 *
2191 * LOCKING:
2192 * Inherited from caller.
2193 */
2194 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2195 unsigned int board_idx)
2196 {
2197 int rc = 0, n_hc, port, hc;
2198 void __iomem *mmio = probe_ent->mmio_base;
2199 struct mv_host_priv *hpriv = probe_ent->private_data;
2200
2201 /* global interrupt mask */
2202 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2203
2204 rc = mv_chip_id(pdev, hpriv, board_idx);
2205 if (rc)
2206 goto done;
2207
2208 n_hc = mv_get_hc_count(probe_ent->host_flags);
2209 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2210
2211 for (port = 0; port < probe_ent->n_ports; port++)
2212 hpriv->ops->read_preamp(hpriv, port, mmio);
2213
2214 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2215 if (rc)
2216 goto done;
2217
2218 hpriv->ops->reset_flash(hpriv, mmio);
2219 hpriv->ops->reset_bus(pdev, mmio);
2220 hpriv->ops->enable_leds(hpriv, mmio);
2221
2222 for (port = 0; port < probe_ent->n_ports; port++) {
2223 if (IS_60XX(hpriv)) {
2224 void __iomem *port_mmio = mv_port_base(mmio, port);
2225
2226 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2227 ifctl |= (1 << 12);
2228 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2229 }
2230
2231 hpriv->ops->phy_errata(hpriv, mmio, port);
2232 }
2233
2234 for (port = 0; port < probe_ent->n_ports; port++) {
2235 void __iomem *port_mmio = mv_port_base(mmio, port);
2236 mv_port_init(&probe_ent->port[port], port_mmio);
2237 }
2238
2239 for (hc = 0; hc < n_hc; hc++) {
2240 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2241
2242 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2243 "(before clear)=0x%08x\n", hc,
2244 readl(hc_mmio + HC_CFG_OFS),
2245 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2246
2247 /* Clear any currently outstanding hc interrupt conditions */
2248 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2249 }
2250
2251 /* Clear any currently outstanding host interrupt conditions */
2252 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2253
2254 /* and unmask interrupt generation for host regs */
2255 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2256 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2257
2258 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2259 "PCI int cause/mask=0x%08x/0x%08x\n",
2260 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2261 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2262 readl(mmio + PCI_IRQ_CAUSE_OFS),
2263 readl(mmio + PCI_IRQ_MASK_OFS));
2264
2265 done:
2266 return rc;
2267 }
2268
2269 /**
2270 * mv_print_info - Dump key info to kernel log for perusal.
2271 * @probe_ent: early data struct representing the host
2272 *
2273 * FIXME: complete this.
2274 *
2275 * LOCKING:
2276 * Inherited from caller.
2277 */
2278 static void mv_print_info(struct ata_probe_ent *probe_ent)
2279 {
2280 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2281 struct mv_host_priv *hpriv = probe_ent->private_data;
2282 u8 rev_id, scc;
2283 const char *scc_s;
2284
2285 /* Use this to determine the HW stepping of the chip so we know
2286 * what errata to workaround
2287 */
2288 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2289
2290 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2291 if (scc == 0)
2292 scc_s = "SCSI";
2293 else if (scc == 0x01)
2294 scc_s = "RAID";
2295 else
2296 scc_s = "unknown";
2297
2298 dev_printk(KERN_INFO, &pdev->dev,
2299 "%u slots %u ports %s mode IRQ via %s\n",
2300 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2301 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2302 }
2303
2304 /**
2305 * mv_init_one - handle a positive probe of a Marvell host
2306 * @pdev: PCI device found
2307 * @ent: PCI device ID entry for the matched host
2308 *
2309 * LOCKING:
2310 * Inherited from caller.
2311 */
2312 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2313 {
2314 static int printed_version = 0;
2315 struct ata_probe_ent *probe_ent = NULL;
2316 struct mv_host_priv *hpriv;
2317 unsigned int board_idx = (unsigned int)ent->driver_data;
2318 void __iomem *mmio_base;
2319 int pci_dev_busy = 0, rc;
2320
2321 if (!printed_version++)
2322 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2323
2324 rc = pci_enable_device(pdev);
2325 if (rc) {
2326 return rc;
2327 }
2328
2329 rc = pci_request_regions(pdev, DRV_NAME);
2330 if (rc) {
2331 pci_dev_busy = 1;
2332 goto err_out;
2333 }
2334
2335 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2336 if (probe_ent == NULL) {
2337 rc = -ENOMEM;
2338 goto err_out_regions;
2339 }
2340
2341 memset(probe_ent, 0, sizeof(*probe_ent));
2342 probe_ent->dev = pci_dev_to_dev(pdev);
2343 INIT_LIST_HEAD(&probe_ent->node);
2344
2345 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2346 if (mmio_base == NULL) {
2347 rc = -ENOMEM;
2348 goto err_out_free_ent;
2349 }
2350
2351 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2352 if (!hpriv) {
2353 rc = -ENOMEM;
2354 goto err_out_iounmap;
2355 }
2356 memset(hpriv, 0, sizeof(*hpriv));
2357
2358 probe_ent->sht = mv_port_info[board_idx].sht;
2359 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2360 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2361 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2362 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2363
2364 probe_ent->irq = pdev->irq;
2365 probe_ent->irq_flags = SA_SHIRQ;
2366 probe_ent->mmio_base = mmio_base;
2367 probe_ent->private_data = hpriv;
2368
2369 /* initialize adapter */
2370 rc = mv_init_host(pdev, probe_ent, board_idx);
2371 if (rc) {
2372 goto err_out_hpriv;
2373 }
2374
2375 /* Enable interrupts */
2376 if (msi && pci_enable_msi(pdev) == 0) {
2377 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2378 } else {
2379 pci_intx(pdev, 1);
2380 }
2381
2382 mv_dump_pci_cfg(pdev, 0x68);
2383 mv_print_info(probe_ent);
2384
2385 if (ata_device_add(probe_ent) == 0) {
2386 rc = -ENODEV; /* No devices discovered */
2387 goto err_out_dev_add;
2388 }
2389
2390 kfree(probe_ent);
2391 return 0;
2392
2393 err_out_dev_add:
2394 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2395 pci_disable_msi(pdev);
2396 } else {
2397 pci_intx(pdev, 0);
2398 }
2399 err_out_hpriv:
2400 kfree(hpriv);
2401 err_out_iounmap:
2402 pci_iounmap(pdev, mmio_base);
2403 err_out_free_ent:
2404 kfree(probe_ent);
2405 err_out_regions:
2406 pci_release_regions(pdev);
2407 err_out:
2408 if (!pci_dev_busy) {
2409 pci_disable_device(pdev);
2410 }
2411
2412 return rc;
2413 }
2414
2415 static int __init mv_init(void)
2416 {
2417 return pci_module_init(&mv_pci_driver);
2418 }
2419
2420 static void __exit mv_exit(void)
2421 {
2422 pci_unregister_driver(&mv_pci_driver);
2423 }
2424
2425 MODULE_AUTHOR("Brett Russ");
2426 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2427 MODULE_LICENSE("GPL");
2428 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2429 MODULE_VERSION(DRV_VERSION);
2430
2431 module_param(msi, int, 0444);
2432 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2433
2434 module_init(mv_init);
2435 module_exit(mv_exit);
Support for the Chinese Samsung S3C2440 based development boards