2 * linux/arch/arm/mach-omap1/clock.c
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
23 #include <asm/arch/usb.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/sram.h>
29 __u32 arm_idlect1_mask
;
31 /*-------------------------------------------------------------------------
32 * Omap1 specific clock functions
33 *-------------------------------------------------------------------------*/
35 static void omap1_watchdog_recalc(struct clk
* clk
)
37 clk
->rate
= clk
->parent
->rate
/ 14;
40 static void omap1_uart_recalc(struct clk
* clk
)
42 unsigned int val
= omap_readl(clk
->enable_reg
);
43 if (val
& clk
->enable_bit
)
49 static int omap1_clk_enable_dsp_domain(struct clk
*clk
)
53 retval
= omap1_clk_enable(&api_ck
.clk
);
55 retval
= omap1_clk_enable_generic(clk
);
56 omap1_clk_disable(&api_ck
.clk
);
62 static void omap1_clk_disable_dsp_domain(struct clk
*clk
)
64 if (omap1_clk_enable(&api_ck
.clk
) == 0) {
65 omap1_clk_disable_generic(clk
);
66 omap1_clk_disable(&api_ck
.clk
);
70 static int omap1_clk_enable_uart_functional(struct clk
*clk
)
73 struct uart_clk
*uclk
;
75 ret
= omap1_clk_enable_generic(clk
);
77 /* Set smart idle acknowledgement mode */
78 uclk
= (struct uart_clk
*)clk
;
79 omap_writeb((omap_readb(uclk
->sysc_addr
) & ~0x10) | 8,
86 static void omap1_clk_disable_uart_functional(struct clk
*clk
)
88 struct uart_clk
*uclk
;
90 /* Set force idle acknowledgement mode */
91 uclk
= (struct uart_clk
*)clk
;
92 omap_writeb((omap_readb(uclk
->sysc_addr
) & ~0x18), uclk
->sysc_addr
);
94 omap1_clk_disable_generic(clk
);
97 static void omap1_clk_allow_idle(struct clk
*clk
)
99 struct arm_idlect1_clk
* iclk
= (struct arm_idlect1_clk
*)clk
;
101 if (!(clk
->flags
& CLOCK_IDLE_CONTROL
))
104 if (iclk
->no_idle_count
> 0 && !(--iclk
->no_idle_count
))
105 arm_idlect1_mask
|= 1 << iclk
->idlect_shift
;
108 static void omap1_clk_deny_idle(struct clk
*clk
)
110 struct arm_idlect1_clk
* iclk
= (struct arm_idlect1_clk
*)clk
;
112 if (!(clk
->flags
& CLOCK_IDLE_CONTROL
))
115 if (iclk
->no_idle_count
++ == 0)
116 arm_idlect1_mask
&= ~(1 << iclk
->idlect_shift
);
119 static __u16
verify_ckctl_value(__u16 newval
)
121 /* This function checks for following limitations set
122 * by the hardware (all conditions must be true):
123 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
128 * In addition following rules are enforced:
132 * However, maximum frequencies are not checked for!
141 per_exp
= (newval
>> CKCTL_PERDIV_OFFSET
) & 3;
142 lcd_exp
= (newval
>> CKCTL_LCDDIV_OFFSET
) & 3;
143 arm_exp
= (newval
>> CKCTL_ARMDIV_OFFSET
) & 3;
144 dsp_exp
= (newval
>> CKCTL_DSPDIV_OFFSET
) & 3;
145 tc_exp
= (newval
>> CKCTL_TCDIV_OFFSET
) & 3;
146 dspmmu_exp
= (newval
>> CKCTL_DSPMMUDIV_OFFSET
) & 3;
148 if (dspmmu_exp
< dsp_exp
)
149 dspmmu_exp
= dsp_exp
;
150 if (dspmmu_exp
> dsp_exp
+1)
151 dspmmu_exp
= dsp_exp
+1;
152 if (tc_exp
< arm_exp
)
154 if (tc_exp
< dspmmu_exp
)
156 if (tc_exp
> lcd_exp
)
158 if (tc_exp
> per_exp
)
162 newval
|= per_exp
<< CKCTL_PERDIV_OFFSET
;
163 newval
|= lcd_exp
<< CKCTL_LCDDIV_OFFSET
;
164 newval
|= arm_exp
<< CKCTL_ARMDIV_OFFSET
;
165 newval
|= dsp_exp
<< CKCTL_DSPDIV_OFFSET
;
166 newval
|= tc_exp
<< CKCTL_TCDIV_OFFSET
;
167 newval
|= dspmmu_exp
<< CKCTL_DSPMMUDIV_OFFSET
;
172 static int calc_dsor_exp(struct clk
*clk
, unsigned long rate
)
174 /* Note: If target frequency is too low, this function will return 4,
175 * which is invalid value. Caller must check for this value and act
178 * Note: This function does not check for following limitations set
179 * by the hardware (all conditions must be true):
180 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
185 unsigned long realrate
;
189 if (unlikely(!(clk
->flags
& RATE_CKCTL
)))
192 parent
= clk
->parent
;
193 if (unlikely(parent
== 0))
196 realrate
= parent
->rate
;
197 for (dsor_exp
=0; dsor_exp
<4; dsor_exp
++) {
198 if (realrate
<= rate
)
207 static void omap1_ckctl_recalc(struct clk
* clk
)
211 /* Calculate divisor encoded as 2-bit exponent */
212 dsor
= 1 << (3 & (omap_readw(ARM_CKCTL
) >> clk
->rate_offset
));
214 if (unlikely(clk
->rate
== clk
->parent
->rate
/ dsor
))
215 return; /* No change, quick exit */
216 clk
->rate
= clk
->parent
->rate
/ dsor
;
218 if (unlikely(clk
->flags
& RATE_PROPAGATES
))
222 static void omap1_ckctl_recalc_dsp_domain(struct clk
* clk
)
226 /* Calculate divisor encoded as 2-bit exponent
228 * The clock control bits are in DSP domain,
229 * so api_ck is needed for access.
230 * Note that DSP_CKCTL virt addr = phys addr, so
231 * we must use __raw_readw() instead of omap_readw().
233 omap1_clk_enable(&api_ck
.clk
);
234 dsor
= 1 << (3 & (__raw_readw(DSP_CKCTL
) >> clk
->rate_offset
));
235 omap1_clk_disable(&api_ck
.clk
);
237 if (unlikely(clk
->rate
== clk
->parent
->rate
/ dsor
))
238 return; /* No change, quick exit */
239 clk
->rate
= clk
->parent
->rate
/ dsor
;
241 if (unlikely(clk
->flags
& RATE_PROPAGATES
))
245 /* MPU virtual clock functions */
246 static int omap1_select_table_rate(struct clk
* clk
, unsigned long rate
)
248 /* Find the highest supported frequency <= rate and switch to it */
249 struct mpu_rate
* ptr
;
251 if (clk
!= &virtual_ck_mpu
)
254 for (ptr
= rate_table
; ptr
->rate
; ptr
++) {
255 if (ptr
->xtal
!= ck_ref
.rate
)
258 /* DPLL1 cannot be reprogrammed without risking system crash */
259 if (likely(ck_dpll1
.rate
!=0) && ptr
->pll_rate
!= ck_dpll1
.rate
)
262 /* Can check only after xtal frequency check */
263 if (ptr
->rate
<= rate
)
271 * In most cases we should not need to reprogram DPLL.
272 * Reprogramming the DPLL is tricky, it must be done from SRAM.
274 omap_sram_reprogram_clock(ptr
->dpllctl_val
, ptr
->ckctl_val
);
276 ck_dpll1
.rate
= ptr
->pll_rate
;
277 propagate_rate(&ck_dpll1
);
281 static int omap1_clk_set_rate_dsp_domain(struct clk
*clk
, unsigned long rate
)
287 if (clk
->flags
& RATE_CKCTL
) {
288 dsor_exp
= calc_dsor_exp(clk
, rate
);
294 regval
= __raw_readw(DSP_CKCTL
);
295 regval
&= ~(3 << clk
->rate_offset
);
296 regval
|= dsor_exp
<< clk
->rate_offset
;
297 __raw_writew(regval
, DSP_CKCTL
);
298 clk
->rate
= clk
->parent
->rate
/ (1 << dsor_exp
);
302 if (unlikely(ret
== 0 && (clk
->flags
& RATE_PROPAGATES
)))
308 static long omap1_round_to_table_rate(struct clk
* clk
, unsigned long rate
)
310 /* Find the highest supported frequency <= rate */
311 struct mpu_rate
* ptr
;
314 if (clk
!= &virtual_ck_mpu
)
317 highest_rate
= -EINVAL
;
319 for (ptr
= rate_table
; ptr
->rate
; ptr
++) {
320 if (ptr
->xtal
!= ck_ref
.rate
)
323 highest_rate
= ptr
->rate
;
325 /* Can check only after xtal frequency check */
326 if (ptr
->rate
<= rate
)
333 static unsigned calc_ext_dsor(unsigned long rate
)
337 /* MCLK and BCLK divisor selection is not linear:
338 * freq = 96MHz / dsor
340 * RATIO_SEL range: dsor <-> RATIO_SEL
341 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
342 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
343 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
346 for (dsor
= 2; dsor
< 96; ++dsor
) {
347 if ((dsor
& 1) && dsor
> 8)
349 if (rate
>= 96000000 / dsor
)
355 /* Only needed on 1510 */
356 static int omap1_set_uart_rate(struct clk
* clk
, unsigned long rate
)
360 val
= omap_readl(clk
->enable_reg
);
361 if (rate
== 12000000)
362 val
&= ~(1 << clk
->enable_bit
);
363 else if (rate
== 48000000)
364 val
|= (1 << clk
->enable_bit
);
367 omap_writel(val
, clk
->enable_reg
);
373 /* External clock (MCLK & BCLK) functions */
374 static int omap1_set_ext_clk_rate(struct clk
* clk
, unsigned long rate
)
379 dsor
= calc_ext_dsor(rate
);
380 clk
->rate
= 96000000 / dsor
;
382 ratio_bits
= ((dsor
- 8) / 2 + 6) << 2;
384 ratio_bits
= (dsor
- 2) << 2;
386 ratio_bits
|= omap_readw(clk
->enable_reg
) & ~0xfd;
387 omap_writew(ratio_bits
, clk
->enable_reg
);
392 static long omap1_round_ext_clk_rate(struct clk
* clk
, unsigned long rate
)
394 return 96000000 / calc_ext_dsor(rate
);
397 static void omap1_init_ext_clk(struct clk
* clk
)
402 /* Determine current rate and ensure clock is based on 96MHz APLL */
403 ratio_bits
= omap_readw(clk
->enable_reg
) & ~1;
404 omap_writew(ratio_bits
, clk
->enable_reg
);
406 ratio_bits
= (ratio_bits
& 0xfc) >> 2;
408 dsor
= (ratio_bits
- 6) * 2 + 8;
410 dsor
= ratio_bits
+ 2;
412 clk
-> rate
= 96000000 / dsor
;
415 static int omap1_clk_enable(struct clk
*clk
)
418 if (clk
->usecount
++ == 0) {
419 if (likely(clk
->parent
)) {
420 ret
= omap1_clk_enable(clk
->parent
);
422 if (unlikely(ret
!= 0)) {
427 if (clk
->flags
& CLOCK_NO_IDLE_PARENT
)
428 if (!cpu_is_omap24xx())
429 omap1_clk_deny_idle(clk
->parent
);
432 ret
= clk
->enable(clk
);
434 if (unlikely(ret
!= 0) && clk
->parent
) {
435 omap1_clk_disable(clk
->parent
);
443 static void omap1_clk_disable(struct clk
*clk
)
445 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
447 if (likely(clk
->parent
)) {
448 omap1_clk_disable(clk
->parent
);
449 if (clk
->flags
& CLOCK_NO_IDLE_PARENT
)
450 if (!cpu_is_omap24xx())
451 omap1_clk_allow_idle(clk
->parent
);
456 static int omap1_clk_enable_generic(struct clk
*clk
)
461 if (clk
->flags
& ALWAYS_ENABLED
)
464 if (unlikely(clk
->enable_reg
== 0)) {
465 printk(KERN_ERR
"clock.c: Enable for %s without enable code\n",
470 if (clk
->flags
& ENABLE_REG_32BIT
) {
471 if (clk
->flags
& VIRTUAL_IO_ADDRESS
) {
472 regval32
= __raw_readl(clk
->enable_reg
);
473 regval32
|= (1 << clk
->enable_bit
);
474 __raw_writel(regval32
, clk
->enable_reg
);
476 regval32
= omap_readl(clk
->enable_reg
);
477 regval32
|= (1 << clk
->enable_bit
);
478 omap_writel(regval32
, clk
->enable_reg
);
481 if (clk
->flags
& VIRTUAL_IO_ADDRESS
) {
482 regval16
= __raw_readw(clk
->enable_reg
);
483 regval16
|= (1 << clk
->enable_bit
);
484 __raw_writew(regval16
, clk
->enable_reg
);
486 regval16
= omap_readw(clk
->enable_reg
);
487 regval16
|= (1 << clk
->enable_bit
);
488 omap_writew(regval16
, clk
->enable_reg
);
495 static void omap1_clk_disable_generic(struct clk
*clk
)
500 if (clk
->enable_reg
== 0)
503 if (clk
->flags
& ENABLE_REG_32BIT
) {
504 if (clk
->flags
& VIRTUAL_IO_ADDRESS
) {
505 regval32
= __raw_readl(clk
->enable_reg
);
506 regval32
&= ~(1 << clk
->enable_bit
);
507 __raw_writel(regval32
, clk
->enable_reg
);
509 regval32
= omap_readl(clk
->enable_reg
);
510 regval32
&= ~(1 << clk
->enable_bit
);
511 omap_writel(regval32
, clk
->enable_reg
);
514 if (clk
->flags
& VIRTUAL_IO_ADDRESS
) {
515 regval16
= __raw_readw(clk
->enable_reg
);
516 regval16
&= ~(1 << clk
->enable_bit
);
517 __raw_writew(regval16
, clk
->enable_reg
);
519 regval16
= omap_readw(clk
->enable_reg
);
520 regval16
&= ~(1 << clk
->enable_bit
);
521 omap_writew(regval16
, clk
->enable_reg
);
526 static long omap1_clk_round_rate(struct clk
*clk
, unsigned long rate
)
530 if (clk
->flags
& RATE_FIXED
)
533 if (clk
->flags
& RATE_CKCTL
) {
534 dsor_exp
= calc_dsor_exp(clk
, rate
);
539 return clk
->parent
->rate
/ (1 << dsor_exp
);
542 if(clk
->round_rate
!= 0)
543 return clk
->round_rate(clk
, rate
);
548 static int omap1_clk_set_rate(struct clk
*clk
, unsigned long rate
)
555 ret
= clk
->set_rate(clk
, rate
);
556 else if (clk
->flags
& RATE_CKCTL
) {
557 dsor_exp
= calc_dsor_exp(clk
, rate
);
563 regval
= omap_readw(ARM_CKCTL
);
564 regval
&= ~(3 << clk
->rate_offset
);
565 regval
|= dsor_exp
<< clk
->rate_offset
;
566 regval
= verify_ckctl_value(regval
);
567 omap_writew(regval
, ARM_CKCTL
);
568 clk
->rate
= clk
->parent
->rate
/ (1 << dsor_exp
);
572 if (unlikely(ret
== 0 && (clk
->flags
& RATE_PROPAGATES
)))
578 /*-------------------------------------------------------------------------
579 * Omap1 clock reset and init functions
580 *-------------------------------------------------------------------------*/
582 #ifdef CONFIG_OMAP_RESET_CLOCKS
584 * Resets some clocks that may be left on from bootloader,
585 * but leaves serial clocks on. See also omap_late_clk_reset().
587 static inline void omap1_early_clk_reset(void)
589 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
592 static int __init
omap1_late_clk_reset(void)
594 /* Turn off all unused clocks */
598 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
599 regval32
= omap_readw(SOFT_REQ_REG
) & (1 << 4);
600 omap_writew(regval32
, SOFT_REQ_REG
);
601 omap_writew(0, SOFT_REQ_REG2
);
603 list_for_each_entry(p
, &clocks
, node
) {
604 if (p
->usecount
> 0 || (p
->flags
& ALWAYS_ENABLED
) ||
608 /* Clocks in the DSP domain need api_ck. Just assume bootloader
609 * has not enabled any DSP clocks */
610 if ((u32
)p
->enable_reg
== DSP_IDLECT2
) {
611 printk(KERN_INFO
"Skipping reset check for DSP domain "
612 "clock \"%s\"\n", p
->name
);
616 /* Is the clock already disabled? */
617 if (p
->flags
& ENABLE_REG_32BIT
) {
618 if (p
->flags
& VIRTUAL_IO_ADDRESS
)
619 regval32
= __raw_readl(p
->enable_reg
);
621 regval32
= omap_readl(p
->enable_reg
);
623 if (p
->flags
& VIRTUAL_IO_ADDRESS
)
624 regval32
= __raw_readw(p
->enable_reg
);
626 regval32
= omap_readw(p
->enable_reg
);
629 if ((regval32
& (1 << p
->enable_bit
)) == 0)
632 /* FIXME: This clock seems to be necessary but no-one
633 * has asked for its activation. */
634 if (p
== &tc2_ck
// FIX: pm.c (SRAM), CCP, Camera
635 || p
== &ck_dpll1out
.clk
// FIX: SoSSI, SSR
636 || p
== &arm_gpio_ck
// FIX: GPIO code for 1510
638 printk(KERN_INFO
"FIXME: Clock \"%s\" seems unused\n",
643 printk(KERN_INFO
"Disabling unused clock \"%s\"... ", p
->name
);
650 late_initcall(omap1_late_clk_reset
);
653 #define omap1_early_clk_reset() {}
656 static struct clk_functions omap1_clk_functions
= {
657 .clk_enable
= omap1_clk_enable
,
658 .clk_disable
= omap1_clk_disable
,
659 .clk_round_rate
= omap1_clk_round_rate
,
660 .clk_set_rate
= omap1_clk_set_rate
,
663 int __init
omap1_clk_init(void)
666 const struct omap_clock_config
*info
;
667 int crystal_type
= 0; /* Default 12 MHz */
669 omap1_early_clk_reset();
670 clk_init(&omap1_clk_functions
);
672 /* By default all idlect1 clocks are allowed to idle */
673 arm_idlect1_mask
= ~0;
675 for (clkp
= onchip_clks
; clkp
< onchip_clks
+ARRAY_SIZE(onchip_clks
); clkp
++) {
676 if (((*clkp
)->flags
&CLOCK_IN_OMAP1510
) && cpu_is_omap1510()) {
681 if (((*clkp
)->flags
&CLOCK_IN_OMAP16XX
) && cpu_is_omap16xx()) {
686 if (((*clkp
)->flags
&CLOCK_IN_OMAP730
) && cpu_is_omap730()) {
691 if (((*clkp
)->flags
&CLOCK_IN_OMAP310
) && cpu_is_omap310()) {
697 info
= omap_get_config(OMAP_TAG_CLOCK
, struct omap_clock_config
);
699 if (!cpu_is_omap1510())
700 crystal_type
= info
->system_clock_type
;
703 #if defined(CONFIG_ARCH_OMAP730)
704 ck_ref
.rate
= 13000000;
705 #elif defined(CONFIG_ARCH_OMAP16XX)
706 if (crystal_type
== 2)
707 ck_ref
.rate
= 19200000;
710 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
711 omap_readw(ARM_SYSST
), omap_readw(DPLL_CTL
),
712 omap_readw(ARM_CKCTL
));
714 /* We want to be in syncronous scalable mode */
715 omap_writew(0x1000, ARM_SYSST
);
717 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
718 /* Use values set by bootloader. Determine PLL rate and recalculate
719 * dependent clocks as if kernel had changed PLL or divisors.
722 unsigned pll_ctl_val
= omap_readw(DPLL_CTL
);
724 ck_dpll1
.rate
= ck_ref
.rate
; /* Base xtal rate */
725 if (pll_ctl_val
& 0x10) {
726 /* PLL enabled, apply multiplier and divisor */
727 if (pll_ctl_val
& 0xf80)
728 ck_dpll1
.rate
*= (pll_ctl_val
& 0xf80) >> 7;
729 ck_dpll1
.rate
/= ((pll_ctl_val
& 0x60) >> 5) + 1;
731 /* PLL disabled, apply bypass divisor */
732 switch (pll_ctl_val
& 0xc) {
744 propagate_rate(&ck_dpll1
);
746 /* Find the highest supported frequency and enable it */
747 if (omap1_select_table_rate(&virtual_ck_mpu
, ~0)) {
748 printk(KERN_ERR
"System frequencies not set. Check your config.\n");
749 /* Guess sane values (60MHz) */
750 omap_writew(0x2290, DPLL_CTL
);
751 omap_writew(0x1005, ARM_CKCTL
);
752 ck_dpll1
.rate
= 60000000;
753 propagate_rate(&ck_dpll1
);
756 /* Cache rates for clocks connected to ck_ref (not dpll1) */
757 propagate_rate(&ck_ref
);
758 printk(KERN_INFO
"Clocking rate (xtal/DPLL1/MPU): "
759 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
760 ck_ref
.rate
/ 1000000, (ck_ref
.rate
/ 100000) % 10,
761 ck_dpll1
.rate
/ 1000000, (ck_dpll1
.rate
/ 100000) % 10,
762 arm_ck
.rate
/ 1000000, (arm_ck
.rate
/ 100000) % 10);
764 #ifdef CONFIG_MACH_OMAP_PERSEUS2
765 /* Select slicer output as OMAP input clock */
766 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL
) & ~0x1, OMAP730_PCC_UPLD_CTRL
);
769 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
770 omap_writew(omap_readw(ARM_CKCTL
) & 0x0fff, ARM_CKCTL
);
772 /* Put DSP/MPUI into reset until needed */
773 omap_writew(0, ARM_RSTCT1
);
774 omap_writew(1, ARM_RSTCT2
);
775 omap_writew(0x400, ARM_IDLECT1
);
778 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
779 * of the ARM_IDLECT2 register must be set to zero. The power-on
780 * default value of this bit is one.
782 omap_writew(0x0000, ARM_IDLECT2
); /* Turn LCD clock off also */
785 * Only enable those clocks we will need, let the drivers
786 * enable other clocks as necessary
788 clk_enable(&armper_ck
.clk
);
789 clk_enable(&armxor_ck
.clk
);
790 clk_enable(&armtim_ck
.clk
); /* This should be done by timer code */
792 if (cpu_is_omap15xx())
793 clk_enable(&arm_gpio_ck
);