2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
140 /* Update the dequeue pointer further if that was a link TRB or we're at
141 * the end of an event ring segment (which doesn't have link TRBS)
143 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
144 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
145 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
147 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
149 (unsigned int) ring
->cycle_state
);
151 ring
->deq_seg
= ring
->deq_seg
->next
;
152 ring
->dequeue
= ring
->deq_seg
->trbs
;
153 next
= ring
->dequeue
;
158 * See Cycle bit rules. SW is the consumer for the event ring only.
159 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
161 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
162 * chain bit is set), then set the chain bit in all the following link TRBs.
163 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
164 * have their chain bit cleared (so that each Link TRB is a separate TD).
166 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
167 * set, but other sections talk about dealing with the chain bit set.
168 * Assume section 6.4.4.1 is wrong, and the chain bit can be set in a Link TRB.
170 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
173 union xhci_trb
*next
;
175 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
176 next
= ++(ring
->enqueue
);
179 /* Update the dequeue pointer further if that was a link TRB or we're at
180 * the end of an event ring segment (which doesn't have link TRBS)
182 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
184 if (ring
!= xhci
->event_ring
) {
185 next
->link
.control
&= ~TRB_CHAIN
;
186 next
->link
.control
|= chain
;
187 /* Give this link TRB to the hardware */
189 if (next
->link
.control
& TRB_CYCLE
)
190 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
192 next
->link
.control
|= (u32
) TRB_CYCLE
;
194 /* Toggle the cycle bit after the last ring segment. */
195 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
196 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
198 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
200 (unsigned int) ring
->cycle_state
);
203 ring
->enq_seg
= ring
->enq_seg
->next
;
204 ring
->enqueue
= ring
->enq_seg
->trbs
;
205 next
= ring
->enqueue
;
210 * Check to see if there's room to enqueue num_trbs on the ring. See rules
212 * FIXME: this would be simpler and faster if we just kept track of the number
213 * of free TRBs in a ring.
215 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
216 unsigned int num_trbs
)
219 union xhci_trb
*enq
= ring
->enqueue
;
220 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
222 /* Check if ring is empty */
223 if (enq
== ring
->dequeue
)
225 /* Make sure there's an extra empty TRB available */
226 for (i
= 0; i
<= num_trbs
; ++i
) {
227 if (enq
== ring
->dequeue
)
230 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
231 enq_seg
= enq_seg
->next
;
238 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
243 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
244 xhci
->event_ring
->dequeue
);
245 if (deq
== 0 && !in_interrupt())
246 xhci_warn(xhci
, "WARN something wrong with SW event ring "
248 /* Update HC event ring dequeue pointer */
249 temp
= xhci_readl(xhci
, &xhci
->ir_set
->erst_dequeue
[0]);
250 temp
&= ERST_PTR_MASK
;
252 xhci_dbg(xhci
, "// Write event ring dequeue pointer\n");
253 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_dequeue
[1]);
254 xhci_writel(xhci
, (deq
& ~ERST_PTR_MASK
) | temp
,
255 &xhci
->ir_set
->erst_dequeue
[0]);
258 /* Ring the host controller doorbell after placing a command on the ring */
259 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
263 xhci_dbg(xhci
, "// Ding dong!\n");
264 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
265 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
266 /* Flush PCI posted writes */
267 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
270 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
271 unsigned int slot_id
,
272 unsigned int ep_index
)
274 struct xhci_ring
*ep_ring
;
276 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
278 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
279 /* Don't ring the doorbell for this endpoint if there are pending
280 * cancellations because the we don't want to interrupt processing.
282 if (!ep_ring
->cancels_pending
&& !(ep_ring
->state
& SET_DEQ_PENDING
)
283 && !(ep_ring
->state
& EP_HALTED
)) {
284 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
285 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
286 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
287 * isn't time-critical and we shouldn't make the CPU wait for
290 xhci_readl(xhci
, db_addr
);
295 * Find the segment that trb is in. Start searching in start_seg.
296 * If we must move past a segment that has a link TRB with a toggle cycle state
297 * bit set, then we will toggle the value pointed at by cycle_state.
299 static struct xhci_segment
*find_trb_seg(
300 struct xhci_segment
*start_seg
,
301 union xhci_trb
*trb
, int *cycle_state
)
303 struct xhci_segment
*cur_seg
= start_seg
;
304 struct xhci_generic_trb
*generic_trb
;
306 while (cur_seg
->trbs
> trb
||
307 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
308 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
309 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
310 (generic_trb
->field
[3] & LINK_TOGGLE
))
311 *cycle_state
= ~(*cycle_state
) & 0x1;
312 cur_seg
= cur_seg
->next
;
313 if (cur_seg
== start_seg
)
314 /* Looped over the entire list. Oops! */
320 struct dequeue_state
{
321 struct xhci_segment
*new_deq_seg
;
322 union xhci_trb
*new_deq_ptr
;
327 * Move the xHC's endpoint ring dequeue pointer past cur_td.
328 * Record the new state of the xHC's endpoint ring dequeue segment,
329 * dequeue pointer, and new consumer cycle state in state.
330 * Update our internal representation of the ring's dequeue pointer.
332 * We do this in three jumps:
333 * - First we update our new ring state to be the same as when the xHC stopped.
334 * - Then we traverse the ring to find the segment that contains
335 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
336 * any link TRBs with the toggle cycle bit set.
337 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
338 * if we've moved it past a link TRB with the toggle cycle bit set.
340 static void find_new_dequeue_state(struct xhci_hcd
*xhci
,
341 unsigned int slot_id
, unsigned int ep_index
,
342 struct xhci_td
*cur_td
, struct dequeue_state
*state
)
344 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
345 struct xhci_ring
*ep_ring
= dev
->ep_rings
[ep_index
];
346 struct xhci_generic_trb
*trb
;
348 state
->new_cycle_state
= 0;
349 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
350 ep_ring
->stopped_trb
,
351 &state
->new_cycle_state
);
352 if (!state
->new_deq_seg
)
354 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
355 state
->new_cycle_state
= 0x1 & dev
->out_ctx
->ep
[ep_index
].deq
[0];
357 state
->new_deq_ptr
= cur_td
->last_trb
;
358 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
360 &state
->new_cycle_state
);
361 if (!state
->new_deq_seg
)
364 trb
= &state
->new_deq_ptr
->generic
;
365 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
366 (trb
->field
[3] & LINK_TOGGLE
))
367 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
368 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
370 /* Don't update the ring cycle state for the producer (us). */
371 ep_ring
->dequeue
= state
->new_deq_ptr
;
372 ep_ring
->deq_seg
= state
->new_deq_seg
;
375 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
376 struct xhci_td
*cur_td
)
378 struct xhci_segment
*cur_seg
;
379 union xhci_trb
*cur_trb
;
381 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
383 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
384 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
385 TRB_TYPE(TRB_LINK
)) {
386 /* Unchain any chained Link TRBs, but
387 * leave the pointers intact.
389 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
390 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
391 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
392 "in seg %p (0x%llx dma)\n",
394 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
396 (unsigned long long)cur_seg
->dma
);
398 cur_trb
->generic
.field
[0] = 0;
399 cur_trb
->generic
.field
[1] = 0;
400 cur_trb
->generic
.field
[2] = 0;
401 /* Preserve only the cycle bit of this TRB */
402 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
403 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
404 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
405 "in seg %p (0x%llx dma)\n",
407 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
409 (unsigned long long)cur_seg
->dma
);
411 if (cur_trb
== cur_td
->last_trb
)
416 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
417 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
418 union xhci_trb
*deq_ptr
, u32 cycle_state
);
421 * When we get a command completion for a Stop Endpoint Command, we need to
422 * unlink any cancelled TDs from the ring. There are two ways to do that:
424 * 1. If the HW was in the middle of processing the TD that needs to be
425 * cancelled, then we must move the ring's dequeue pointer past the last TRB
426 * in the TD with a Set Dequeue Pointer Command.
427 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
428 * bit cleared) so that the HW will skip over them.
430 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
433 unsigned int slot_id
;
434 unsigned int ep_index
;
435 struct xhci_ring
*ep_ring
;
436 struct list_head
*entry
;
437 struct xhci_td
*cur_td
= 0;
438 struct xhci_td
*last_unlinked_td
;
440 struct dequeue_state deq_state
;
441 #ifdef CONFIG_USB_HCD_STAT
442 ktime_t stop_time
= ktime_get();
445 memset(&deq_state
, 0, sizeof(deq_state
));
446 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
447 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
448 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
450 if (list_empty(&ep_ring
->cancelled_td_list
))
453 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
454 * We have the xHCI lock, so nothing can modify this list until we drop
455 * it. We're also in the event handler, so we can't get re-interrupted
456 * if another Stop Endpoint command completes
458 list_for_each(entry
, &ep_ring
->cancelled_td_list
) {
459 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
460 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
462 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
464 * If we stopped on the TD we need to cancel, then we have to
465 * move the xHC endpoint ring dequeue pointer past this TD.
467 if (cur_td
== ep_ring
->stopped_td
)
468 find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
471 td_to_noop(xhci
, ep_ring
, cur_td
);
473 * The event handler won't see a completion for this TD anymore,
474 * so remove it from the endpoint ring's TD list. Keep it in
475 * the cancelled TD list for URB completion later.
477 list_del(&cur_td
->td_list
);
478 ep_ring
->cancels_pending
--;
480 last_unlinked_td
= cur_td
;
482 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
483 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
484 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
485 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
486 deq_state
.new_deq_seg
,
487 (unsigned long long)deq_state
.new_deq_seg
->dma
,
488 deq_state
.new_deq_ptr
,
489 (unsigned long long)xhci_trb_virt_to_dma(deq_state
.new_deq_seg
, deq_state
.new_deq_ptr
),
490 deq_state
.new_cycle_state
);
491 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
492 deq_state
.new_deq_seg
,
493 deq_state
.new_deq_ptr
,
494 (u32
) deq_state
.new_cycle_state
);
495 /* Stop the TD queueing code from ringing the doorbell until
496 * this command completes. The HC won't set the dequeue pointer
497 * if the ring is running, and ringing the doorbell starts the
500 ep_ring
->state
|= SET_DEQ_PENDING
;
501 xhci_ring_cmd_db(xhci
);
503 /* Otherwise just ring the doorbell to restart the ring */
504 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
508 * Drop the lock and complete the URBs in the cancelled TD list.
509 * New TDs to be cancelled might be added to the end of the list before
510 * we can complete all the URBs for the TDs we already unlinked.
511 * So stop when we've completed the URB for the last TD we unlinked.
514 cur_td
= list_entry(ep_ring
->cancelled_td_list
.next
,
515 struct xhci_td
, cancelled_td_list
);
516 list_del(&cur_td
->cancelled_td_list
);
518 /* Clean up the cancelled URB */
519 #ifdef CONFIG_USB_HCD_STAT
520 hcd_stat_update(xhci
->tp_stat
, cur_td
->urb
->actual_length
,
521 ktime_sub(stop_time
, cur_td
->start_time
));
523 cur_td
->urb
->hcpriv
= NULL
;
524 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), cur_td
->urb
);
526 xhci_dbg(xhci
, "Giveback cancelled URB %p\n", cur_td
->urb
);
527 spin_unlock(&xhci
->lock
);
528 /* Doesn't matter what we pass for status, since the core will
529 * just overwrite it (because the URB has been unlinked).
531 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), cur_td
->urb
, 0);
534 spin_lock(&xhci
->lock
);
535 } while (cur_td
!= last_unlinked_td
);
537 /* Return to the event handler with xhci->lock re-acquired */
541 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
542 * we need to clear the set deq pending flag in the endpoint ring state, so that
543 * the TD queueing code can ring the doorbell again. We also need to ring the
544 * endpoint doorbell to restart the ring, but only if there aren't more
545 * cancellations pending.
547 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
548 struct xhci_event_cmd
*event
,
551 unsigned int slot_id
;
552 unsigned int ep_index
;
553 struct xhci_ring
*ep_ring
;
554 struct xhci_virt_device
*dev
;
556 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
557 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
558 dev
= xhci
->devs
[slot_id
];
559 ep_ring
= dev
->ep_rings
[ep_index
];
561 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
562 unsigned int ep_state
;
563 unsigned int slot_state
;
565 switch (GET_COMP_CODE(event
->status
)) {
567 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
568 "of stream ID configuration\n");
571 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
572 "to incorrect slot or ep state.\n");
573 ep_state
= dev
->out_ctx
->ep
[ep_index
].ep_info
;
574 ep_state
&= EP_STATE_MASK
;
575 slot_state
= dev
->out_ctx
->slot
.dev_state
;
576 slot_state
= GET_SLOT_STATE(slot_state
);
577 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
578 slot_state
, ep_state
);
581 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
582 "slot %u was not enabled.\n", slot_id
);
585 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
586 "completion code of %u.\n",
587 GET_COMP_CODE(event
->status
));
590 /* OK what do we do now? The endpoint state is hosed, and we
591 * should never get to this point if the synchronization between
592 * queueing, and endpoint state are correct. This might happen
593 * if the device gets disconnected after we've finished
594 * cancelling URBs, which might not be an error...
597 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq[0] = 0x%x, "
599 dev
->out_ctx
->ep
[ep_index
].deq
[0],
600 dev
->out_ctx
->ep
[ep_index
].deq
[1]);
603 ep_ring
->state
&= ~SET_DEQ_PENDING
;
604 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
607 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
608 struct xhci_event_cmd
*event
,
612 unsigned int ep_index
;
614 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
615 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
616 /* This command will only fail if the endpoint wasn't halted,
619 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
620 (unsigned int) GET_COMP_CODE(event
->status
));
622 /* Clear our internal halted state and restart the ring */
623 xhci
->devs
[slot_id
]->ep_rings
[ep_index
]->state
&= ~EP_HALTED
;
624 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
627 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
628 struct xhci_event_cmd
*event
)
630 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
632 dma_addr_t cmd_dequeue_dma
;
634 cmd_dma
= (((u64
) event
->cmd_trb
[1]) << 32) + event
->cmd_trb
[0];
635 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
636 xhci
->cmd_ring
->dequeue
);
637 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
638 if (cmd_dequeue_dma
== 0) {
639 xhci
->error_bitmask
|= 1 << 4;
642 /* Does the DMA address match our internal dequeue pointer address? */
643 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
644 xhci
->error_bitmask
|= 1 << 5;
647 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
648 case TRB_TYPE(TRB_ENABLE_SLOT
):
649 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
650 xhci
->slot_id
= slot_id
;
653 complete(&xhci
->addr_dev
);
655 case TRB_TYPE(TRB_DISABLE_SLOT
):
656 if (xhci
->devs
[slot_id
])
657 xhci_free_virt_device(xhci
, slot_id
);
659 case TRB_TYPE(TRB_CONFIG_EP
):
660 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
661 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
663 case TRB_TYPE(TRB_ADDR_DEV
):
664 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
665 complete(&xhci
->addr_dev
);
667 case TRB_TYPE(TRB_STOP_RING
):
668 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
670 case TRB_TYPE(TRB_SET_DEQ
):
671 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
673 case TRB_TYPE(TRB_CMD_NOOP
):
674 ++xhci
->noops_handled
;
676 case TRB_TYPE(TRB_RESET_EP
):
677 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
680 /* Skip over unknown commands on the event ring */
681 xhci
->error_bitmask
|= 1 << 6;
684 inc_deq(xhci
, xhci
->cmd_ring
, false);
687 static void handle_port_status(struct xhci_hcd
*xhci
,
688 union xhci_trb
*event
)
692 /* Port status change events always have a successful completion code */
693 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
694 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
695 xhci
->error_bitmask
|= 1 << 8;
697 /* FIXME: core doesn't care about all port link state changes yet */
698 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
699 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
701 /* Update event ring dequeue pointer before dropping the lock */
702 inc_deq(xhci
, xhci
->event_ring
, true);
703 xhci_set_hc_event_deq(xhci
);
705 spin_unlock(&xhci
->lock
);
706 /* Pass this up to the core */
707 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
708 spin_lock(&xhci
->lock
);
712 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
713 * at end_trb, which may be in another segment. If the suspect DMA address is a
714 * TRB in this TD, this function returns that TRB's segment. Otherwise it
717 static struct xhci_segment
*trb_in_td(
718 struct xhci_segment
*start_seg
,
719 union xhci_trb
*start_trb
,
720 union xhci_trb
*end_trb
,
721 dma_addr_t suspect_dma
)
723 dma_addr_t start_dma
;
724 dma_addr_t end_seg_dma
;
725 dma_addr_t end_trb_dma
;
726 struct xhci_segment
*cur_seg
;
728 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
732 /* We may get an event for a Link TRB in the middle of a TD */
733 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
734 &start_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
735 /* If the end TRB isn't in this segment, this is set to 0 */
736 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
738 if (end_trb_dma
> 0) {
739 /* The end TRB is in this segment, so suspect should be here */
740 if (start_dma
<= end_trb_dma
) {
741 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
744 /* Case for one segment with
745 * a TD wrapped around to the top
747 if ((suspect_dma
>= start_dma
&&
748 suspect_dma
<= end_seg_dma
) ||
749 (suspect_dma
>= cur_seg
->dma
&&
750 suspect_dma
<= end_trb_dma
))
755 /* Might still be somewhere in this segment */
756 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
759 cur_seg
= cur_seg
->next
;
760 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
766 * If this function returns an error condition, it means it got a Transfer
767 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
768 * At this point, the host controller is probably hosed and should be reset.
770 static int handle_tx_event(struct xhci_hcd
*xhci
,
771 struct xhci_transfer_event
*event
)
773 struct xhci_virt_device
*xdev
;
774 struct xhci_ring
*ep_ring
;
776 struct xhci_td
*td
= 0;
777 dma_addr_t event_dma
;
778 struct xhci_segment
*event_seg
;
779 union xhci_trb
*event_trb
;
781 int status
= -EINPROGRESS
;
783 xdev
= xhci
->devs
[TRB_TO_SLOT_ID(event
->flags
)];
785 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
789 /* Endpoint ID is 1 based, our index is zero based */
790 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
791 ep_ring
= xdev
->ep_rings
[ep_index
];
792 if (!ep_ring
|| (xdev
->out_ctx
->ep
[ep_index
].ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
793 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
797 event_dma
= event
->buffer
[0];
798 if (event
->buffer
[1] != 0)
799 xhci_warn(xhci
, "WARN ignoring upper 32-bits of 64-bit TRB dma address\n");
801 /* This TRB should be in the TD at the head of this ring's TD list */
802 if (list_empty(&ep_ring
->td_list
)) {
803 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
804 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
805 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
806 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
807 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
811 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
813 /* Is this a TRB in the currently executing TD? */
814 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
815 td
->last_trb
, event_dma
);
817 /* HC is busted, give up! */
818 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
821 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
822 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
823 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
824 xhci_dbg(xhci
, "Offset 0x00 (buffer[0]) = 0x%x\n",
825 (unsigned int) event
->buffer
[0]);
826 xhci_dbg(xhci
, "Offset 0x04 (buffer[0]) = 0x%x\n",
827 (unsigned int) event
->buffer
[1]);
828 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
829 (unsigned int) event
->transfer_len
);
830 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
831 (unsigned int) event
->flags
);
833 /* Look for common error cases */
834 switch (GET_COMP_CODE(event
->transfer_len
)) {
835 /* Skip codes that require special handling depending on
842 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
844 case COMP_STOP_INVAL
:
845 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
848 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
849 ep_ring
->state
|= EP_HALTED
;
853 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
857 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
861 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
865 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
869 /* Now update the urb's actual_length and give back to the core */
870 /* Was this a control transfer? */
871 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
872 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
873 switch (GET_COMP_CODE(event
->transfer_len
)) {
875 if (event_trb
== ep_ring
->dequeue
) {
876 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
878 } else if (event_trb
!= td
->last_trb
) {
879 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
882 xhci_dbg(xhci
, "Successful control transfer!\n");
887 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
891 /* Others already handled above */
895 * Did we transfer any data, despite the errors that might have
896 * happened? I.e. did we get past the setup stage?
898 if (event_trb
!= ep_ring
->dequeue
) {
899 /* The event was for the status stage */
900 if (event_trb
== td
->last_trb
) {
901 td
->urb
->actual_length
=
902 td
->urb
->transfer_buffer_length
;
904 /* Maybe the event was for the data stage? */
905 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
)
906 /* We didn't stop on a link TRB in the middle */
907 td
->urb
->actual_length
=
908 td
->urb
->transfer_buffer_length
-
909 TRB_LEN(event
->transfer_len
);
913 switch (GET_COMP_CODE(event
->transfer_len
)) {
915 /* Double check that the HW transferred everything. */
916 if (event_trb
!= td
->last_trb
) {
917 xhci_warn(xhci
, "WARN Successful completion "
919 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
924 xhci_dbg(xhci
, "Successful bulk transfer!\n");
929 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
935 /* Others already handled above */
938 dev_dbg(&td
->urb
->dev
->dev
,
939 "ep %#x - asked for %d bytes, "
940 "%d bytes untransferred\n",
941 td
->urb
->ep
->desc
.bEndpointAddress
,
942 td
->urb
->transfer_buffer_length
,
943 TRB_LEN(event
->transfer_len
));
944 /* Fast path - was this the last TRB in the TD for this URB? */
945 if (event_trb
== td
->last_trb
) {
946 if (TRB_LEN(event
->transfer_len
) != 0) {
947 td
->urb
->actual_length
=
948 td
->urb
->transfer_buffer_length
-
949 TRB_LEN(event
->transfer_len
);
950 if (td
->urb
->actual_length
< 0) {
951 xhci_warn(xhci
, "HC gave bad length "
952 "of %d bytes left\n",
953 TRB_LEN(event
->transfer_len
));
954 td
->urb
->actual_length
= 0;
956 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
961 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
962 /* Ignore a short packet completion if the
963 * untransferred length was zero.
968 /* Slow path - walk the list, starting from the dequeue
969 * pointer, to get the actual length transferred.
971 union xhci_trb
*cur_trb
;
972 struct xhci_segment
*cur_seg
;
974 td
->urb
->actual_length
= 0;
975 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
976 cur_trb
!= event_trb
;
977 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
978 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
979 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
980 td
->urb
->actual_length
+=
981 TRB_LEN(cur_trb
->generic
.field
[2]);
983 /* If the ring didn't stop on a Link or No-op TRB, add
984 * in the actual bytes transferred from the Normal TRB
986 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
)
987 td
->urb
->actual_length
+=
988 TRB_LEN(cur_trb
->generic
.field
[2]) -
989 TRB_LEN(event
->transfer_len
);
992 /* The Endpoint Stop Command completion will take care of
993 * any stopped TDs. A stopped TD may be restarted, so don't update the
994 * ring dequeue pointer or take this TD off any lists yet.
996 if (GET_COMP_CODE(event
->transfer_len
) == COMP_STOP_INVAL
||
997 GET_COMP_CODE(event
->transfer_len
) == COMP_STOP
) {
998 ep_ring
->stopped_td
= td
;
999 ep_ring
->stopped_trb
= event_trb
;
1001 /* Update ring dequeue pointer */
1002 while (ep_ring
->dequeue
!= td
->last_trb
)
1003 inc_deq(xhci
, ep_ring
, false);
1004 inc_deq(xhci
, ep_ring
, false);
1006 /* Clean up the endpoint's TD list */
1008 list_del(&td
->td_list
);
1009 /* Was this TD slated to be cancelled but completed anyway? */
1010 if (!list_empty(&td
->cancelled_td_list
)) {
1011 list_del(&td
->cancelled_td_list
);
1012 ep_ring
->cancels_pending
--;
1018 inc_deq(xhci
, xhci
->event_ring
, true);
1019 xhci_set_hc_event_deq(xhci
);
1021 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1023 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1024 spin_unlock(&xhci
->lock
);
1025 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1026 spin_lock(&xhci
->lock
);
1032 * This function handles all OS-owned events on the event ring. It may drop
1033 * xhci->lock between event processing (e.g. to pass up port status changes).
1035 void xhci_handle_event(struct xhci_hcd
*xhci
)
1037 union xhci_trb
*event
;
1038 int update_ptrs
= 1;
1041 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1042 xhci
->error_bitmask
|= 1 << 1;
1046 event
= xhci
->event_ring
->dequeue
;
1047 /* Does the HC or OS own the TRB? */
1048 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1049 xhci
->event_ring
->cycle_state
) {
1050 xhci
->error_bitmask
|= 1 << 2;
1054 /* FIXME: Handle more event types. */
1055 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1056 case TRB_TYPE(TRB_COMPLETION
):
1057 handle_cmd_completion(xhci
, &event
->event_cmd
);
1059 case TRB_TYPE(TRB_PORT_STATUS
):
1060 handle_port_status(xhci
, event
);
1063 case TRB_TYPE(TRB_TRANSFER
):
1064 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1066 xhci
->error_bitmask
|= 1 << 9;
1071 xhci
->error_bitmask
|= 1 << 3;
1075 /* Update SW and HC event ring dequeue pointer */
1076 inc_deq(xhci
, xhci
->event_ring
, true);
1077 xhci_set_hc_event_deq(xhci
);
1079 /* Are there more items on the event ring? */
1080 xhci_handle_event(xhci
);
1083 /**** Endpoint Ring Operations ****/
1086 * Generic function for queueing a TRB on a ring.
1087 * The caller must have checked to make sure there's room on the ring.
1089 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1091 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1093 struct xhci_generic_trb
*trb
;
1095 trb
= &ring
->enqueue
->generic
;
1096 trb
->field
[0] = field1
;
1097 trb
->field
[1] = field2
;
1098 trb
->field
[2] = field3
;
1099 trb
->field
[3] = field4
;
1100 inc_enq(xhci
, ring
, consumer
);
1104 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1105 * FIXME allocate segments if the ring is full.
1107 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1108 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1110 /* Make sure the endpoint has been added to xHC schedule */
1111 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1113 case EP_STATE_DISABLED
:
1115 * USB core changed config/interfaces without notifying us,
1116 * or hardware is reporting the wrong state.
1118 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1120 case EP_STATE_HALTED
:
1121 case EP_STATE_ERROR
:
1122 xhci_warn(xhci
, "WARN waiting for halt or error on ep "
1124 /* FIXME event handling code for error needs to clear it */
1125 /* XXX not sure if this should be -ENOENT or not */
1127 case EP_STATE_STOPPED
:
1128 case EP_STATE_RUNNING
:
1131 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1133 * FIXME issue Configure Endpoint command to try to get the HC
1134 * back into a known state.
1138 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1139 /* FIXME allocate more room */
1140 xhci_err(xhci
, "ERROR no room on ep ring\n");
1146 static int prepare_transfer(struct xhci_hcd
*xhci
,
1147 struct xhci_virt_device
*xdev
,
1148 unsigned int ep_index
,
1149 unsigned int num_trbs
,
1151 struct xhci_td
**td
,
1156 ret
= prepare_ring(xhci
, xdev
->ep_rings
[ep_index
],
1157 xdev
->out_ctx
->ep
[ep_index
].ep_info
& EP_STATE_MASK
,
1158 num_trbs
, mem_flags
);
1161 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1164 INIT_LIST_HEAD(&(*td
)->td_list
);
1165 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1167 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1168 if (unlikely(ret
)) {
1174 urb
->hcpriv
= (void *) (*td
);
1175 /* Add this TD to the tail of the endpoint ring's TD list */
1176 list_add_tail(&(*td
)->td_list
, &xdev
->ep_rings
[ep_index
]->td_list
);
1177 (*td
)->start_seg
= xdev
->ep_rings
[ep_index
]->enq_seg
;
1178 (*td
)->first_trb
= xdev
->ep_rings
[ep_index
]->enqueue
;
1183 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1185 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1186 struct scatterlist
*sg
;
1189 num_sgs
= urb
->num_sgs
;
1190 temp
= urb
->transfer_buffer_length
;
1192 xhci_dbg(xhci
, "count sg list trbs: \n");
1194 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1195 unsigned int previous_total_trbs
= num_trbs
;
1196 unsigned int len
= sg_dma_len(sg
);
1198 /* Scatter gather list entries may cross 64KB boundaries */
1199 running_total
= TRB_MAX_BUFF_SIZE
-
1200 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1201 if (running_total
!= 0)
1204 /* How many more 64KB chunks to transfer, how many more TRBs? */
1205 while (running_total
< sg_dma_len(sg
)) {
1207 running_total
+= TRB_MAX_BUFF_SIZE
;
1209 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1210 i
, (unsigned long long)sg_dma_address(sg
),
1211 len
, len
, num_trbs
- previous_total_trbs
);
1213 len
= min_t(int, len
, temp
);
1218 xhci_dbg(xhci
, "\n");
1219 if (!in_interrupt())
1220 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1221 urb
->ep
->desc
.bEndpointAddress
,
1222 urb
->transfer_buffer_length
,
1227 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1230 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1231 "TRBs, %d left\n", __func__
,
1232 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1233 if (running_total
!= urb
->transfer_buffer_length
)
1234 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1235 "queued %#x (%d), asked for %#x (%d)\n",
1237 urb
->ep
->desc
.bEndpointAddress
,
1238 running_total
, running_total
,
1239 urb
->transfer_buffer_length
,
1240 urb
->transfer_buffer_length
);
1243 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1244 unsigned int ep_index
, int start_cycle
,
1245 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1248 * Pass all the TRBs to the hardware at once and make sure this write
1252 start_trb
->field
[3] |= start_cycle
;
1253 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1256 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1257 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1259 struct xhci_ring
*ep_ring
;
1260 unsigned int num_trbs
;
1262 struct scatterlist
*sg
;
1264 int trb_buff_len
, this_sg_len
, running_total
;
1268 struct xhci_generic_trb
*start_trb
;
1271 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1272 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1273 num_sgs
= urb
->num_sgs
;
1275 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1276 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1277 if (trb_buff_len
< 0)
1278 return trb_buff_len
;
1280 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1281 * until we've finished creating all the other TRBs. The ring's cycle
1282 * state may change as we enqueue the other TRBs, so save it too.
1284 start_trb
= &ep_ring
->enqueue
->generic
;
1285 start_cycle
= ep_ring
->cycle_state
;
1289 * How much data is in the first TRB?
1291 * There are three forces at work for TRB buffer pointers and lengths:
1292 * 1. We don't want to walk off the end of this sg-list entry buffer.
1293 * 2. The transfer length that the driver requested may be smaller than
1294 * the amount of memory allocated for this scatter-gather list.
1295 * 3. TRBs buffers can't cross 64KB boundaries.
1298 addr
= (u64
) sg_dma_address(sg
);
1299 this_sg_len
= sg_dma_len(sg
);
1300 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1301 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1302 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1303 if (trb_buff_len
> urb
->transfer_buffer_length
)
1304 trb_buff_len
= urb
->transfer_buffer_length
;
1305 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1309 /* Queue the first TRB, even if it's zero-length */
1312 u32 length_field
= 0;
1314 /* Don't change the cycle bit of the first TRB until later */
1318 field
|= ep_ring
->cycle_state
;
1320 /* Chain all the TRBs together; clear the chain bit in the last
1321 * TRB to indicate it's the last TRB in the chain.
1326 /* FIXME - add check for ZERO_PACKET flag before this */
1327 td
->last_trb
= ep_ring
->enqueue
;
1330 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1331 "64KB boundary at %#x, end dma = %#x\n",
1332 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1333 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1334 (unsigned int) addr
+ trb_buff_len
);
1335 if (TRB_MAX_BUFF_SIZE
-
1336 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1337 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1338 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1339 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1340 (unsigned int) addr
+ trb_buff_len
);
1342 length_field
= TRB_LEN(trb_buff_len
) |
1343 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1345 queue_trb(xhci
, ep_ring
, false,
1347 (u32
) ((u64
) addr
>> 32),
1349 /* We always want to know if the TRB was short,
1350 * or we won't get an event when it completes.
1351 * (Unless we use event data TRBs, which are a
1352 * waste of space and HC resources.)
1354 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1356 running_total
+= trb_buff_len
;
1358 /* Calculate length for next transfer --
1359 * Are we done queueing all the TRBs for this sg entry?
1361 this_sg_len
-= trb_buff_len
;
1362 if (this_sg_len
== 0) {
1367 addr
= (u64
) sg_dma_address(sg
);
1368 this_sg_len
= sg_dma_len(sg
);
1370 addr
+= trb_buff_len
;
1373 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1374 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1375 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1376 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1378 urb
->transfer_buffer_length
- running_total
;
1379 } while (running_total
< urb
->transfer_buffer_length
);
1381 check_trb_math(urb
, num_trbs
, running_total
);
1382 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1386 /* This is very similar to what ehci-q.c qtd_fill() does */
1387 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1388 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1390 struct xhci_ring
*ep_ring
;
1393 struct xhci_generic_trb
*start_trb
;
1396 u32 field
, length_field
;
1398 int running_total
, trb_buff_len
, ret
;
1402 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1404 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1407 /* How much data is (potentially) left before the 64KB boundary? */
1408 running_total
= TRB_MAX_BUFF_SIZE
-
1409 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1411 /* If there's some data on this 64KB chunk, or we have to send a
1412 * zero-length transfer, we need at least one TRB
1414 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1416 /* How many more 64KB chunks to transfer, how many more TRBs? */
1417 while (running_total
< urb
->transfer_buffer_length
) {
1419 running_total
+= TRB_MAX_BUFF_SIZE
;
1421 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1423 if (!in_interrupt())
1424 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1425 urb
->ep
->desc
.bEndpointAddress
,
1426 urb
->transfer_buffer_length
,
1427 urb
->transfer_buffer_length
,
1428 (unsigned long long)urb
->transfer_dma
,
1431 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1432 num_trbs
, urb
, &td
, mem_flags
);
1437 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1438 * until we've finished creating all the other TRBs. The ring's cycle
1439 * state may change as we enqueue the other TRBs, so save it too.
1441 start_trb
= &ep_ring
->enqueue
->generic
;
1442 start_cycle
= ep_ring
->cycle_state
;
1445 /* How much data is in the first TRB? */
1446 addr
= (u64
) urb
->transfer_dma
;
1447 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1448 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1449 if (urb
->transfer_buffer_length
< trb_buff_len
)
1450 trb_buff_len
= urb
->transfer_buffer_length
;
1454 /* Queue the first TRB, even if it's zero-length */
1458 /* Don't change the cycle bit of the first TRB until later */
1462 field
|= ep_ring
->cycle_state
;
1464 /* Chain all the TRBs together; clear the chain bit in the last
1465 * TRB to indicate it's the last TRB in the chain.
1470 /* FIXME - add check for ZERO_PACKET flag before this */
1471 td
->last_trb
= ep_ring
->enqueue
;
1474 length_field
= TRB_LEN(trb_buff_len
) |
1475 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1477 queue_trb(xhci
, ep_ring
, false,
1479 (u32
) ((u64
) addr
>> 32),
1481 /* We always want to know if the TRB was short,
1482 * or we won't get an event when it completes.
1483 * (Unless we use event data TRBs, which are a
1484 * waste of space and HC resources.)
1486 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1488 running_total
+= trb_buff_len
;
1490 /* Calculate length for next transfer */
1491 addr
+= trb_buff_len
;
1492 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
1493 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
1494 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
1495 } while (running_total
< urb
->transfer_buffer_length
);
1497 check_trb_math(urb
, num_trbs
, running_total
);
1498 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1502 /* Caller must have locked xhci->lock */
1503 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1504 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1506 struct xhci_ring
*ep_ring
;
1509 struct usb_ctrlrequest
*setup
;
1510 struct xhci_generic_trb
*start_trb
;
1512 u32 field
, length_field
;
1515 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1518 * Need to copy setup packet into setup TRB, so we can't use the setup
1521 if (!urb
->setup_packet
)
1524 if (!in_interrupt())
1525 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
1527 /* 1 TRB for setup, 1 for status */
1530 * Don't need to check if we need additional event data and normal TRBs,
1531 * since data in control transfers will never get bigger than 16MB
1532 * XXX: can we get a buffer that crosses 64KB boundaries?
1534 if (urb
->transfer_buffer_length
> 0)
1536 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
1537 urb
, &td
, mem_flags
);
1542 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1543 * until we've finished creating all the other TRBs. The ring's cycle
1544 * state may change as we enqueue the other TRBs, so save it too.
1546 start_trb
= &ep_ring
->enqueue
->generic
;
1547 start_cycle
= ep_ring
->cycle_state
;
1549 /* Queue setup TRB - see section 6.4.1.2.1 */
1550 /* FIXME better way to translate setup_packet into two u32 fields? */
1551 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
1552 queue_trb(xhci
, ep_ring
, false,
1553 /* FIXME endianness is probably going to bite my ass here. */
1554 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
1555 setup
->wIndex
| setup
->wLength
<< 16,
1556 TRB_LEN(8) | TRB_INTR_TARGET(0),
1557 /* Immediate data in pointer */
1558 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
1560 /* If there's data, queue data TRBs */
1562 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
1563 TD_REMAINDER(urb
->transfer_buffer_length
) |
1565 if (urb
->transfer_buffer_length
> 0) {
1566 if (setup
->bRequestType
& USB_DIR_IN
)
1567 field
|= TRB_DIR_IN
;
1568 queue_trb(xhci
, ep_ring
, false,
1569 lower_32_bits(urb
->transfer_dma
),
1570 upper_32_bits(urb
->transfer_dma
),
1572 /* Event on short tx */
1573 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
1576 /* Save the DMA address of the last TRB in the TD */
1577 td
->last_trb
= ep_ring
->enqueue
;
1579 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1580 /* If the device sent data, the status stage is an OUT transfer */
1581 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
1585 queue_trb(xhci
, ep_ring
, false,
1589 /* Event on completion */
1590 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
1592 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1596 /**** Command Ring Operations ****/
1598 /* Generic function for queueing a command TRB on the command ring */
1599 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1601 if (!room_on_ring(xhci
, xhci
->cmd_ring
, 1)) {
1602 if (!in_interrupt())
1603 xhci_err(xhci
, "ERR: No room for command on command ring\n");
1606 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
1607 field4
| xhci
->cmd_ring
->cycle_state
);
1611 /* Queue a no-op command on the command ring */
1612 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
1614 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
));
1618 * Place a no-op command on the command ring to test the command and
1621 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
1623 if (queue_cmd_noop(xhci
) < 0)
1625 xhci
->noops_submitted
++;
1626 return xhci_ring_cmd_db
;
1629 /* Queue a slot enable or disable request on the command ring */
1630 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
1632 return queue_command(xhci
, 0, 0, 0,
1633 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
));
1636 /* Queue an address device command TRB */
1637 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1640 return queue_command(xhci
, in_ctx_ptr
, 0, 0,
1641 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
));
1644 /* Queue a configure endpoint command TRB */
1645 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1648 return queue_command(xhci
, in_ctx_ptr
, 0, 0,
1649 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
));
1652 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1653 unsigned int ep_index
)
1655 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1656 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1657 u32 type
= TRB_TYPE(TRB_STOP_RING
);
1659 return queue_command(xhci
, 0, 0, 0,
1660 trb_slot_id
| trb_ep_index
| type
);
1663 /* Set Transfer Ring Dequeue Pointer command.
1664 * This should not be used for endpoints that have streams enabled.
1666 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
1667 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
1668 union xhci_trb
*deq_ptr
, u32 cycle_state
)
1671 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1672 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1673 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
1675 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
1677 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
1678 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
1680 return queue_command(xhci
, (u32
) addr
| cycle_state
, 0, 0,
1681 trb_slot_id
| trb_ep_index
| type
);
1684 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1685 unsigned int ep_index
)
1687 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1688 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1689 u32 type
= TRB_TYPE(TRB_RESET_EP
);
1691 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
);