2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
54 #define __apicdebuginit(type) static type __init
56 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
57 atomic_t irq_mis_count
;
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
62 static DEFINE_SPINLOCK(ioapic_lock
);
63 DEFINE_SPINLOCK(vector_lock
);
65 int timer_through_8259 __initdata
;
68 * Is the SiS APIC rmw bug present ?
69 * -1 = don't know, 0 = no, 1 = yes
71 int sis_apic_bug
= -1;
75 * # of IRQ routing registers
77 int nr_ioapic_registers
[MAX_IO_APICS
];
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
86 /* # of MP IRQ source entries */
89 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
90 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
93 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
95 static int disable_timer_pin_1 __initdata
;
102 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
103 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
104 [0] = { .vector
= FIRST_DEVICE_VECTOR
, },
107 static void __init
init_work(void *data
)
109 struct dyn_array
*da
= data
;
116 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
118 BUG_ON(legacy_count
> nr_irqs
);
120 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
123 static struct irq_cfg
*irq_cfgx
;
124 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irqs
, PAGE_SIZE
, init_work
);
126 static struct irq_cfg
*irq_cfg(unsigned int irq
)
131 return &irq_cfgx
[irq
];
135 * Rough estimation of how many shared IRQs there are, can
136 * be changed anytime.
141 * This is performance-critical, we want to do it O(1)
143 * the indexing order of this array favors 1:1 mappings
144 * between pins and IRQs.
147 static struct irq_pin_list
{
151 DEFINE_DYN_ARRAY(irq_2_pin
, sizeof(struct irq_pin_list
), pin_map_size
, 16, NULL
);
155 unsigned int unused
[3];
159 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
161 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
162 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
165 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
167 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
168 writel(reg
, &io_apic
->index
);
169 return readl(&io_apic
->data
);
172 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
174 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
175 writel(reg
, &io_apic
->index
);
176 writel(value
, &io_apic
->data
);
180 * Re-write a value: to be used for read-modify-write
181 * cycles where the read already set up the index register.
183 * Older SiS APIC requires we rewrite the index register
185 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
187 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
189 writel(reg
, &io_apic
->index
);
190 writel(value
, &io_apic
->data
);
194 struct { u32 w1
, w2
; };
195 struct IO_APIC_route_entry entry
;
198 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
200 union entry_union eu
;
202 spin_lock_irqsave(&ioapic_lock
, flags
);
203 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
204 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
205 spin_unlock_irqrestore(&ioapic_lock
, flags
);
210 * When we write a new IO APIC routing entry, we need to write the high
211 * word first! If the mask bit in the low word is clear, we will enable
212 * the interrupt, and we need to make sure the entry is fully populated
213 * before that happens.
216 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
218 union entry_union eu
;
220 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
221 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
224 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
227 spin_lock_irqsave(&ioapic_lock
, flags
);
228 __ioapic_write_entry(apic
, pin
, e
);
229 spin_unlock_irqrestore(&ioapic_lock
, flags
);
233 * When we mask an IO APIC routing entry, we need to write the low
234 * word first, in order to set the mask bit before we change the
237 static void ioapic_mask_entry(int apic
, int pin
)
240 union entry_union eu
= { .entry
.mask
= 1 };
242 spin_lock_irqsave(&ioapic_lock
, flags
);
243 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
244 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
245 spin_unlock_irqrestore(&ioapic_lock
, flags
);
249 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
250 * shared ISA-space IRQs, so we have to support them. We are super
251 * fast in the common case, and fast for shared ISA-space IRQs.
253 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
255 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
258 entry
= irq_2_pin
+ entry
->next
;
260 if (entry
->pin
!= -1) {
261 entry
->next
= first_free_entry
;
262 entry
= irq_2_pin
+ entry
->next
;
263 if (++first_free_entry
>= pin_map_size
)
264 panic("io_apic.c: whoops");
271 * Reroute an IRQ to a different pin.
273 static void __init
replace_pin_at_irq(unsigned int irq
,
274 int oldapic
, int oldpin
,
275 int newapic
, int newpin
)
277 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
280 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
281 entry
->apic
= newapic
;
286 entry
= irq_2_pin
+ entry
->next
;
290 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
292 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
293 unsigned int pin
, reg
;
299 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
302 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
305 entry
= irq_2_pin
+ entry
->next
;
310 static void __mask_IO_APIC_irq(unsigned int irq
)
312 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
316 static void __unmask_IO_APIC_irq(unsigned int irq
)
318 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
321 /* mask = 1, trigger = 0 */
322 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
324 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
325 IO_APIC_REDIR_LEVEL_TRIGGER
);
328 /* mask = 0, trigger = 1 */
329 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
331 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
332 IO_APIC_REDIR_MASKED
);
335 static void mask_IO_APIC_irq(unsigned int irq
)
339 spin_lock_irqsave(&ioapic_lock
, flags
);
340 __mask_IO_APIC_irq(irq
);
341 spin_unlock_irqrestore(&ioapic_lock
, flags
);
344 static void unmask_IO_APIC_irq(unsigned int irq
)
348 spin_lock_irqsave(&ioapic_lock
, flags
);
349 __unmask_IO_APIC_irq(irq
);
350 spin_unlock_irqrestore(&ioapic_lock
, flags
);
353 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
355 struct IO_APIC_route_entry entry
;
357 /* Check delivery_mode to be sure we're not clearing an SMI pin */
358 entry
= ioapic_read_entry(apic
, pin
);
359 if (entry
.delivery_mode
== dest_SMI
)
363 * Disable it in the IO-APIC irq-routing table:
365 ioapic_mask_entry(apic
, pin
);
368 static void clear_IO_APIC(void)
372 for (apic
= 0; apic
< nr_ioapics
; apic
++)
373 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
374 clear_IO_APIC_pin(apic
, pin
);
378 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
382 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
383 unsigned int apicid_value
;
385 struct irq_desc
*desc
;
387 cpus_and(tmp
, cpumask
, cpu_online_map
);
391 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
393 apicid_value
= cpu_mask_to_apicid(cpumask
);
394 /* Prepare to do the io_apic_write */
395 apicid_value
= apicid_value
<< 24;
396 spin_lock_irqsave(&ioapic_lock
, flags
);
401 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
404 entry
= irq_2_pin
+ entry
->next
;
406 desc
= irq_to_desc(irq
);
407 desc
->affinity
= cpumask
;
408 spin_unlock_irqrestore(&ioapic_lock
, flags
);
411 #endif /* CONFIG_SMP */
414 void send_IPI_self(int vector
)
421 apic_wait_icr_idle();
422 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
424 * Send the IPI. The write to APIC_ICR fires this off.
426 apic_write(APIC_ICR
, cfg
);
428 #endif /* !CONFIG_SMP */
432 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
433 * specific CPU-side IRQs.
437 static int pirq_entries
[MAX_PIRQS
];
438 static int pirqs_enabled
;
439 int skip_ioapic_setup
;
441 static int __init
ioapic_pirq_setup(char *str
)
444 int ints
[MAX_PIRQS
+1];
446 get_options(str
, ARRAY_SIZE(ints
), ints
);
448 for (i
= 0; i
< MAX_PIRQS
; i
++)
449 pirq_entries
[i
] = -1;
452 apic_printk(APIC_VERBOSE
, KERN_INFO
453 "PIRQ redirection, working around broken MP-BIOS.\n");
455 if (ints
[0] < MAX_PIRQS
)
458 for (i
= 0; i
< max
; i
++) {
459 apic_printk(APIC_VERBOSE
, KERN_DEBUG
460 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
462 * PIRQs are mapped upside down, usually.
464 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
469 __setup("pirq=", ioapic_pirq_setup
);
472 * Find the IRQ entry number of a certain pin.
474 static int find_irq_entry(int apic
, int pin
, int type
)
478 for (i
= 0; i
< mp_irq_entries
; i
++)
479 if (mp_irqs
[i
].mp_irqtype
== type
&&
480 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
481 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
482 mp_irqs
[i
].mp_dstirq
== pin
)
489 * Find the pin to which IRQ[irq] (ISA) is connected
491 static int __init
find_isa_irq_pin(int irq
, int type
)
495 for (i
= 0; i
< mp_irq_entries
; i
++) {
496 int lbus
= mp_irqs
[i
].mp_srcbus
;
498 if (test_bit(lbus
, mp_bus_not_pci
) &&
499 (mp_irqs
[i
].mp_irqtype
== type
) &&
500 (mp_irqs
[i
].mp_srcbusirq
== irq
))
502 return mp_irqs
[i
].mp_dstirq
;
507 static int __init
find_isa_irq_apic(int irq
, int type
)
511 for (i
= 0; i
< mp_irq_entries
; i
++) {
512 int lbus
= mp_irqs
[i
].mp_srcbus
;
514 if (test_bit(lbus
, mp_bus_not_pci
) &&
515 (mp_irqs
[i
].mp_irqtype
== type
) &&
516 (mp_irqs
[i
].mp_srcbusirq
== irq
))
519 if (i
< mp_irq_entries
) {
521 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
522 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
531 * Find a specific PCI IRQ entry.
532 * Not an __init, possibly needed by modules
534 static int pin_2_irq(int idx
, int apic
, int pin
);
536 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
538 int apic
, i
, best_guess
= -1;
540 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
541 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
542 if (test_bit(bus
, mp_bus_not_pci
)) {
543 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
546 for (i
= 0; i
< mp_irq_entries
; i
++) {
547 int lbus
= mp_irqs
[i
].mp_srcbus
;
549 for (apic
= 0; apic
< nr_ioapics
; apic
++)
550 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
551 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
554 if (!test_bit(lbus
, mp_bus_not_pci
) &&
555 !mp_irqs
[i
].mp_irqtype
&&
557 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
558 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
560 if (!(apic
|| IO_APIC_IRQ(irq
)))
563 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
566 * Use the first all-but-pin matching entry as a
567 * best-guess fuzzy result for broken mptables.
575 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
578 * This function currently is only a helper for the i386 smp boot process where
579 * we need to reprogram the ioredtbls to cater for the cpus which have come online
580 * so mask in all cases should simply be TARGET_CPUS
583 void __init
setup_ioapic_dest(void)
585 int pin
, ioapic
, irq
, irq_entry
;
587 if (skip_ioapic_setup
== 1)
590 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
591 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
592 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
595 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
596 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
603 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
605 * EISA Edge/Level control register, ELCR
607 static int EISA_ELCR(unsigned int irq
)
610 unsigned int port
= 0x4d0 + (irq
>> 3);
611 return (inb(port
) >> (irq
& 7)) & 1;
613 apic_printk(APIC_VERBOSE
, KERN_INFO
614 "Broken MPtable reports ISA irq %d\n", irq
);
619 /* ISA interrupts are always polarity zero edge triggered,
620 * when listed as conforming in the MP table. */
622 #define default_ISA_trigger(idx) (0)
623 #define default_ISA_polarity(idx) (0)
625 /* EISA interrupts are always polarity zero and can be edge or level
626 * trigger depending on the ELCR value. If an interrupt is listed as
627 * EISA conforming in the MP table, that means its trigger type must
628 * be read in from the ELCR */
630 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
631 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
633 /* PCI interrupts are always polarity one level triggered,
634 * when listed as conforming in the MP table. */
636 #define default_PCI_trigger(idx) (1)
637 #define default_PCI_polarity(idx) (1)
639 /* MCA interrupts are always polarity zero level triggered,
640 * when listed as conforming in the MP table. */
642 #define default_MCA_trigger(idx) (1)
643 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
645 static int MPBIOS_polarity(int idx
)
647 int bus
= mp_irqs
[idx
].mp_srcbus
;
651 * Determine IRQ line polarity (high active or low active):
653 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
654 case 0: /* conforms, ie. bus-type dependent polarity */
656 polarity
= test_bit(bus
, mp_bus_not_pci
)?
657 default_ISA_polarity(idx
):
658 default_PCI_polarity(idx
);
661 case 1: /* high active */
666 case 2: /* reserved */
668 printk(KERN_WARNING
"broken BIOS!!\n");
672 case 3: /* low active */
677 default: /* invalid */
679 printk(KERN_WARNING
"broken BIOS!!\n");
687 static int MPBIOS_trigger(int idx
)
689 int bus
= mp_irqs
[idx
].mp_srcbus
;
693 * Determine IRQ trigger mode (edge or level sensitive):
695 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
696 case 0: /* conforms, ie. bus-type dependent */
698 trigger
= test_bit(bus
, mp_bus_not_pci
)?
699 default_ISA_trigger(idx
):
700 default_PCI_trigger(idx
);
701 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
702 switch (mp_bus_id_to_type
[bus
]) {
703 case MP_BUS_ISA
: /* ISA pin */
705 /* set before the switch */
708 case MP_BUS_EISA
: /* EISA pin */
710 trigger
= default_EISA_trigger(idx
);
713 case MP_BUS_PCI
: /* PCI pin */
715 /* set before the switch */
718 case MP_BUS_MCA
: /* MCA pin */
720 trigger
= default_MCA_trigger(idx
);
725 printk(KERN_WARNING
"broken BIOS!!\n");
738 case 2: /* reserved */
740 printk(KERN_WARNING
"broken BIOS!!\n");
749 default: /* invalid */
751 printk(KERN_WARNING
"broken BIOS!!\n");
759 static inline int irq_polarity(int idx
)
761 return MPBIOS_polarity(idx
);
764 static inline int irq_trigger(int idx
)
766 return MPBIOS_trigger(idx
);
769 static int pin_2_irq(int idx
, int apic
, int pin
)
772 int bus
= mp_irqs
[idx
].mp_srcbus
;
775 * Debugging check, we are in big trouble if this message pops up!
777 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
778 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
780 if (test_bit(bus
, mp_bus_not_pci
))
781 irq
= mp_irqs
[idx
].mp_srcbusirq
;
784 * PCI IRQs are mapped in order
788 irq
+= nr_ioapic_registers
[i
++];
792 * For MPS mode, so far only needed by ES7000 platform
794 if (ioapic_renumber_irq
)
795 irq
= ioapic_renumber_irq(apic
, irq
);
799 * PCI IRQ command line redirection. Yes, limits are hardcoded.
801 if ((pin
>= 16) && (pin
<= 23)) {
802 if (pirq_entries
[pin
-16] != -1) {
803 if (!pirq_entries
[pin
-16]) {
804 apic_printk(APIC_VERBOSE
, KERN_DEBUG
805 "disabling PIRQ%d\n", pin
-16);
807 irq
= pirq_entries
[pin
-16];
808 apic_printk(APIC_VERBOSE
, KERN_DEBUG
809 "using PIRQ%d -> IRQ %d\n",
817 static inline int IO_APIC_irq_trigger(int irq
)
821 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
822 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
823 idx
= find_irq_entry(apic
, pin
, mp_INT
);
824 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
825 return irq_trigger(idx
);
829 * nonexistent IRQs are edge default
835 static int __assign_irq_vector(int irq
)
837 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
;
840 BUG_ON((unsigned)irq
>= nr_irqs
);
842 if (irq_cfg(irq
)->vector
> 0)
843 return irq_cfg(irq
)->vector
;
845 vector
= current_vector
;
846 offset
= current_offset
;
849 if (vector
>= first_system_vector
) {
850 offset
= (offset
+ 1) % 8;
851 vector
= FIRST_DEVICE_VECTOR
+ offset
;
853 if (vector
== current_vector
)
855 if (test_and_set_bit(vector
, used_vectors
))
858 current_vector
= vector
;
859 current_offset
= offset
;
860 irq_cfg(irq
)->vector
= vector
;
865 static int assign_irq_vector(int irq
)
870 spin_lock_irqsave(&vector_lock
, flags
);
871 vector
= __assign_irq_vector(irq
);
872 spin_unlock_irqrestore(&vector_lock
, flags
);
877 static struct irq_chip ioapic_chip
;
879 #define IOAPIC_AUTO -1
880 #define IOAPIC_EDGE 0
881 #define IOAPIC_LEVEL 1
883 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
885 struct irq_desc
*desc
;
887 desc
= irq_to_desc(irq
);
888 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
889 trigger
== IOAPIC_LEVEL
) {
890 desc
->status
|= IRQ_LEVEL
;
891 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
892 handle_fasteoi_irq
, "fasteoi");
894 desc
->status
&= ~IRQ_LEVEL
;
895 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
896 handle_edge_irq
, "edge");
898 set_intr_gate(vector
, interrupt
[irq
]);
901 static void __init
setup_IO_APIC_irqs(void)
903 struct IO_APIC_route_entry entry
;
904 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
906 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
908 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
909 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
912 * add it to the IO-APIC irq-routing table:
914 memset(&entry
, 0, sizeof(entry
));
916 entry
.delivery_mode
= INT_DELIVERY_MODE
;
917 entry
.dest_mode
= INT_DEST_MODE
;
918 entry
.mask
= 0; /* enable IRQ */
919 entry
.dest
.logical
.logical_dest
=
920 cpu_mask_to_apicid(TARGET_CPUS
);
922 idx
= find_irq_entry(apic
, pin
, mp_INT
);
925 apic_printk(APIC_VERBOSE
, KERN_DEBUG
926 " IO-APIC (apicid-pin) %d-%d",
927 mp_ioapics
[apic
].mp_apicid
,
931 apic_printk(APIC_VERBOSE
, ", %d-%d",
932 mp_ioapics
[apic
].mp_apicid
, pin
);
937 apic_printk(APIC_VERBOSE
, " not connected.\n");
941 entry
.trigger
= irq_trigger(idx
);
942 entry
.polarity
= irq_polarity(idx
);
944 if (irq_trigger(idx
)) {
949 irq
= pin_2_irq(idx
, apic
, pin
);
951 * skip adding the timer int on secondary nodes, which causes
952 * a small but painful rift in the time-space continuum
954 if (multi_timer_check(apic
, irq
))
957 add_pin_to_irq(irq
, apic
, pin
);
959 if (!apic
&& !IO_APIC_IRQ(irq
))
962 if (IO_APIC_IRQ(irq
)) {
963 vector
= assign_irq_vector(irq
);
964 entry
.vector
= vector
;
965 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
967 if (!apic
&& (irq
< 16))
968 disable_8259A_irq(irq
);
970 ioapic_write_entry(apic
, pin
, entry
);
975 apic_printk(APIC_VERBOSE
, " not connected.\n");
979 * Set up the timer pin, possibly with the 8259A-master behind.
981 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
984 struct IO_APIC_route_entry entry
;
986 memset(&entry
, 0, sizeof(entry
));
989 * We use logical delivery to get the timer IRQ
992 entry
.dest_mode
= INT_DEST_MODE
;
993 entry
.mask
= 1; /* mask IRQ now */
994 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
995 entry
.delivery_mode
= INT_DELIVERY_MODE
;
998 entry
.vector
= vector
;
1001 * The timer IRQ doesn't have to know that behind the
1002 * scene we may have a 8259A-master in AEOI mode ...
1004 ioapic_register_intr(0, vector
, IOAPIC_EDGE
);
1007 * Add it to the IO-APIC irq-routing table:
1009 ioapic_write_entry(apic
, pin
, entry
);
1013 __apicdebuginit(void) print_IO_APIC(void)
1016 union IO_APIC_reg_00 reg_00
;
1017 union IO_APIC_reg_01 reg_01
;
1018 union IO_APIC_reg_02 reg_02
;
1019 union IO_APIC_reg_03 reg_03
;
1020 unsigned long flags
;
1022 if (apic_verbosity
== APIC_QUIET
)
1025 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1026 for (i
= 0; i
< nr_ioapics
; i
++)
1027 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1028 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1031 * We are a bit conservative about what we expect. We have to
1032 * know about every hardware change ASAP.
1034 printk(KERN_INFO
"testing the IO APIC.......................\n");
1036 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1038 spin_lock_irqsave(&ioapic_lock
, flags
);
1039 reg_00
.raw
= io_apic_read(apic
, 0);
1040 reg_01
.raw
= io_apic_read(apic
, 1);
1041 if (reg_01
.bits
.version
>= 0x10)
1042 reg_02
.raw
= io_apic_read(apic
, 2);
1043 if (reg_01
.bits
.version
>= 0x20)
1044 reg_03
.raw
= io_apic_read(apic
, 3);
1045 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1047 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1048 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1049 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1050 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1051 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1053 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1054 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1056 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1057 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1060 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1061 * but the value of reg_02 is read as the previous read register
1062 * value, so ignore it if reg_02 == reg_01.
1064 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1065 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1066 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1070 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1071 * or reg_03, but the value of reg_0[23] is read as the previous read
1072 * register value, so ignore it if reg_03 == reg_0[12].
1074 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1075 reg_03
.raw
!= reg_01
.raw
) {
1076 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1077 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1080 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1082 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1083 " Stat Dest Deli Vect: \n");
1085 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1086 struct IO_APIC_route_entry entry
;
1088 entry
= ioapic_read_entry(apic
, i
);
1090 printk(KERN_DEBUG
" %02x %03X %02X ",
1092 entry
.dest
.logical
.logical_dest
,
1093 entry
.dest
.physical
.physical_dest
1096 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1101 entry
.delivery_status
,
1103 entry
.delivery_mode
,
1108 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1109 for (i
= 0; i
< nr_irqs
; i
++) {
1110 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1113 printk(KERN_DEBUG
"IRQ%d ", i
);
1115 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1118 entry
= irq_2_pin
+ entry
->next
;
1123 printk(KERN_INFO
".................................... done.\n");
1128 __apicdebuginit(void) print_APIC_bitfield(int base
)
1133 if (apic_verbosity
== APIC_QUIET
)
1136 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1137 for (i
= 0; i
< 8; i
++) {
1138 v
= apic_read(base
+ i
*0x10);
1139 for (j
= 0; j
< 32; j
++) {
1149 __apicdebuginit(void) print_local_APIC(void *dummy
)
1151 unsigned int v
, ver
, maxlvt
;
1154 if (apic_verbosity
== APIC_QUIET
)
1157 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1158 smp_processor_id(), hard_smp_processor_id());
1159 v
= apic_read(APIC_ID
);
1160 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1162 v
= apic_read(APIC_LVR
);
1163 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1164 ver
= GET_APIC_VERSION(v
);
1165 maxlvt
= lapic_get_maxlvt();
1167 v
= apic_read(APIC_TASKPRI
);
1168 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1170 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1171 v
= apic_read(APIC_ARBPRI
);
1172 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1173 v
& APIC_ARBPRI_MASK
);
1174 v
= apic_read(APIC_PROCPRI
);
1175 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1178 v
= apic_read(APIC_EOI
);
1179 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1180 v
= apic_read(APIC_RRR
);
1181 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1182 v
= apic_read(APIC_LDR
);
1183 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1184 v
= apic_read(APIC_DFR
);
1185 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1186 v
= apic_read(APIC_SPIV
);
1187 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1189 printk(KERN_DEBUG
"... APIC ISR field:\n");
1190 print_APIC_bitfield(APIC_ISR
);
1191 printk(KERN_DEBUG
"... APIC TMR field:\n");
1192 print_APIC_bitfield(APIC_TMR
);
1193 printk(KERN_DEBUG
"... APIC IRR field:\n");
1194 print_APIC_bitfield(APIC_IRR
);
1196 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1197 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1198 apic_write(APIC_ESR
, 0);
1199 v
= apic_read(APIC_ESR
);
1200 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1203 icr
= apic_icr_read();
1204 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1205 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1207 v
= apic_read(APIC_LVTT
);
1208 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1210 if (maxlvt
> 3) { /* PC is LVT#4. */
1211 v
= apic_read(APIC_LVTPC
);
1212 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1214 v
= apic_read(APIC_LVT0
);
1215 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1216 v
= apic_read(APIC_LVT1
);
1217 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1219 if (maxlvt
> 2) { /* ERR is LVT#3. */
1220 v
= apic_read(APIC_LVTERR
);
1221 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1224 v
= apic_read(APIC_TMICT
);
1225 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1226 v
= apic_read(APIC_TMCCT
);
1227 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1228 v
= apic_read(APIC_TDCR
);
1229 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1233 __apicdebuginit(void) print_all_local_APICs(void)
1235 on_each_cpu(print_local_APIC
, NULL
, 1);
1238 __apicdebuginit(void) print_PIC(void)
1241 unsigned long flags
;
1243 if (apic_verbosity
== APIC_QUIET
)
1246 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1248 spin_lock_irqsave(&i8259A_lock
, flags
);
1250 v
= inb(0xa1) << 8 | inb(0x21);
1251 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1253 v
= inb(0xa0) << 8 | inb(0x20);
1254 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1258 v
= inb(0xa0) << 8 | inb(0x20);
1262 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1264 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1266 v
= inb(0x4d1) << 8 | inb(0x4d0);
1267 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1270 __apicdebuginit(int) print_all_ICs(void)
1273 print_all_local_APICs();
1279 fs_initcall(print_all_ICs
);
1282 static void __init
enable_IO_APIC(void)
1284 union IO_APIC_reg_01 reg_01
;
1285 int i8259_apic
, i8259_pin
;
1287 unsigned long flags
;
1289 for (i
= 0; i
< pin_map_size
; i
++) {
1290 irq_2_pin
[i
].pin
= -1;
1291 irq_2_pin
[i
].next
= 0;
1294 for (i
= 0; i
< MAX_PIRQS
; i
++)
1295 pirq_entries
[i
] = -1;
1298 * The number of IO-APIC IRQ registers (== #pins):
1300 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1301 spin_lock_irqsave(&ioapic_lock
, flags
);
1302 reg_01
.raw
= io_apic_read(apic
, 1);
1303 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1304 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1306 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1308 /* See if any of the pins is in ExtINT mode */
1309 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1310 struct IO_APIC_route_entry entry
;
1311 entry
= ioapic_read_entry(apic
, pin
);
1314 /* If the interrupt line is enabled and in ExtInt mode
1315 * I have found the pin where the i8259 is connected.
1317 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1318 ioapic_i8259
.apic
= apic
;
1319 ioapic_i8259
.pin
= pin
;
1325 /* Look to see what if the MP table has reported the ExtINT */
1326 /* If we could not find the appropriate pin by looking at the ioapic
1327 * the i8259 probably is not connected the ioapic but give the
1328 * mptable a chance anyway.
1330 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1331 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1332 /* Trust the MP table if nothing is setup in the hardware */
1333 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1334 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1335 ioapic_i8259
.pin
= i8259_pin
;
1336 ioapic_i8259
.apic
= i8259_apic
;
1338 /* Complain if the MP table and the hardware disagree */
1339 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1340 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1342 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1346 * Do not trust the IO-APIC being empty at bootup
1352 * Not an __init, needed by the reboot code
1354 void disable_IO_APIC(void)
1357 * Clear the IO-APIC before rebooting:
1362 * If the i8259 is routed through an IOAPIC
1363 * Put that IOAPIC in virtual wire mode
1364 * so legacy interrupts can be delivered.
1366 if (ioapic_i8259
.pin
!= -1) {
1367 struct IO_APIC_route_entry entry
;
1369 memset(&entry
, 0, sizeof(entry
));
1370 entry
.mask
= 0; /* Enabled */
1371 entry
.trigger
= 0; /* Edge */
1373 entry
.polarity
= 0; /* High */
1374 entry
.delivery_status
= 0;
1375 entry
.dest_mode
= 0; /* Physical */
1376 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1378 entry
.dest
.physical
.physical_dest
= read_apic_id();
1381 * Add it to the IO-APIC irq-routing table:
1383 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1385 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1389 * function to set the IO-APIC physical IDs based on the
1390 * values stored in the MPC table.
1392 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1395 static void __init
setup_ioapic_ids_from_mpc(void)
1397 union IO_APIC_reg_00 reg_00
;
1398 physid_mask_t phys_id_present_map
;
1401 unsigned char old_id
;
1402 unsigned long flags
;
1404 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1408 * Don't check I/O APIC IDs for xAPIC systems. They have
1409 * no meaning without the serial APIC bus.
1411 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1412 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1415 * This is broken; anything with a real cpu count has to
1416 * circumvent this idiocy regardless.
1418 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1421 * Set the IOAPIC ID to the value stored in the MPC table.
1423 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1425 /* Read the register 0 value */
1426 spin_lock_irqsave(&ioapic_lock
, flags
);
1427 reg_00
.raw
= io_apic_read(apic
, 0);
1428 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1430 old_id
= mp_ioapics
[apic
].mp_apicid
;
1432 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1433 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1434 apic
, mp_ioapics
[apic
].mp_apicid
);
1435 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1437 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1441 * Sanity check, is the ID really free? Every APIC in a
1442 * system must have a unique ID or we get lots of nice
1443 * 'stuck on smp_invalidate_needed IPI wait' messages.
1445 if (check_apicid_used(phys_id_present_map
,
1446 mp_ioapics
[apic
].mp_apicid
)) {
1447 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1448 apic
, mp_ioapics
[apic
].mp_apicid
);
1449 for (i
= 0; i
< get_physical_broadcast(); i
++)
1450 if (!physid_isset(i
, phys_id_present_map
))
1452 if (i
>= get_physical_broadcast())
1453 panic("Max APIC ID exceeded!\n");
1454 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1456 physid_set(i
, phys_id_present_map
);
1457 mp_ioapics
[apic
].mp_apicid
= i
;
1460 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1461 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1462 "phys_id_present_map\n",
1463 mp_ioapics
[apic
].mp_apicid
);
1464 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1469 * We need to adjust the IRQ routing table
1470 * if the ID changed.
1472 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1473 for (i
= 0; i
< mp_irq_entries
; i
++)
1474 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1475 mp_irqs
[i
].mp_dstapic
1476 = mp_ioapics
[apic
].mp_apicid
;
1479 * Read the right value from the MPC table and
1480 * write it into the ID register.
1482 apic_printk(APIC_VERBOSE
, KERN_INFO
1483 "...changing IO-APIC physical APIC ID to %d ...",
1484 mp_ioapics
[apic
].mp_apicid
);
1486 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1487 spin_lock_irqsave(&ioapic_lock
, flags
);
1488 io_apic_write(apic
, 0, reg_00
.raw
);
1489 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1494 spin_lock_irqsave(&ioapic_lock
, flags
);
1495 reg_00
.raw
= io_apic_read(apic
, 0);
1496 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1497 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1498 printk("could not set ID!\n");
1500 apic_printk(APIC_VERBOSE
, " ok.\n");
1504 int no_timer_check __initdata
;
1506 static int __init
notimercheck(char *s
)
1511 __setup("no_timer_check", notimercheck
);
1514 * There is a nasty bug in some older SMP boards, their mptable lies
1515 * about the timer IRQ. We do the following to work around the situation:
1517 * - timer IRQ defaults to IO-APIC IRQ
1518 * - if this function detects that timer IRQs are defunct, then we fall
1519 * back to ISA timer IRQs
1521 static int __init
timer_irq_works(void)
1523 unsigned long t1
= jiffies
;
1524 unsigned long flags
;
1529 local_save_flags(flags
);
1531 /* Let ten ticks pass... */
1532 mdelay((10 * 1000) / HZ
);
1533 local_irq_restore(flags
);
1536 * Expect a few ticks at least, to be sure some possible
1537 * glue logic does not lock up after one or two first
1538 * ticks in a non-ExtINT mode. Also the local APIC
1539 * might have cached one ExtINT interrupt. Finally, at
1540 * least one tick may be lost due to delays.
1542 if (time_after(jiffies
, t1
+ 4))
1549 * In the SMP+IOAPIC case it might happen that there are an unspecified
1550 * number of pending IRQ events unhandled. These cases are very rare,
1551 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1552 * better to do it this way as thus we do not have to be aware of
1553 * 'pending' interrupts in the IRQ path, except at this point.
1556 * Edge triggered needs to resend any interrupt
1557 * that was delayed but this is now handled in the device
1564 * Starting up a edge-triggered IO-APIC interrupt is
1565 * nasty - we need to make sure that we get the edge.
1566 * If it is already asserted for some reason, we need
1567 * return 1 to indicate that is was pending.
1569 * This is not complete - we should be able to fake
1570 * an edge even if it isn't on the 8259A...
1572 * (We do this for level-triggered IRQs too - it cannot hurt.)
1574 static unsigned int startup_ioapic_irq(unsigned int irq
)
1576 int was_pending
= 0;
1577 unsigned long flags
;
1579 spin_lock_irqsave(&ioapic_lock
, flags
);
1581 disable_8259A_irq(irq
);
1582 if (i8259A_irq_pending(irq
))
1585 __unmask_IO_APIC_irq(irq
);
1586 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1591 static void ack_ioapic_irq(unsigned int irq
)
1593 move_native_irq(irq
);
1597 static void ack_ioapic_quirk_irq(unsigned int irq
)
1602 move_native_irq(irq
);
1604 * It appears there is an erratum which affects at least version 0x11
1605 * of I/O APIC (that's the 82093AA and cores integrated into various
1606 * chipsets). Under certain conditions a level-triggered interrupt is
1607 * erroneously delivered as edge-triggered one but the respective IRR
1608 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1609 * message but it will never arrive and further interrupts are blocked
1610 * from the source. The exact reason is so far unknown, but the
1611 * phenomenon was observed when two consecutive interrupt requests
1612 * from a given source get delivered to the same CPU and the source is
1613 * temporarily disabled in between.
1615 * A workaround is to simulate an EOI message manually. We achieve it
1616 * by setting the trigger mode to edge and then to level when the edge
1617 * trigger mode gets detected in the TMR of a local APIC for a
1618 * level-triggered interrupt. We mask the source for the time of the
1619 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1620 * The idea is from Manfred Spraul. --macro
1622 i
= irq_cfg(irq
)->vector
;
1624 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1628 if (!(v
& (1 << (i
& 0x1f)))) {
1629 atomic_inc(&irq_mis_count
);
1630 spin_lock(&ioapic_lock
);
1631 __mask_and_edge_IO_APIC_irq(irq
);
1632 __unmask_and_level_IO_APIC_irq(irq
);
1633 spin_unlock(&ioapic_lock
);
1637 static int ioapic_retrigger_irq(unsigned int irq
)
1639 send_IPI_self(irq_cfg(irq
)->vector
);
1644 static struct irq_chip ioapic_chip __read_mostly
= {
1646 .startup
= startup_ioapic_irq
,
1647 .mask
= mask_IO_APIC_irq
,
1648 .unmask
= unmask_IO_APIC_irq
,
1649 .ack
= ack_ioapic_irq
,
1650 .eoi
= ack_ioapic_quirk_irq
,
1652 .set_affinity
= set_ioapic_affinity_irq
,
1654 .retrigger
= ioapic_retrigger_irq
,
1658 static inline void init_IO_APIC_traps(void)
1661 struct irq_desc
*desc
;
1664 * NOTE! The local APIC isn't very good at handling
1665 * multiple interrupts at the same interrupt level.
1666 * As the interrupt level is determined by taking the
1667 * vector number and shifting that right by 4, we
1668 * want to spread these out a bit so that they don't
1669 * all fall in the same interrupt level.
1671 * Also, we've got to be careful not to trash gate
1672 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1674 for (irq
= 0; irq
< nr_irqs
; irq
++) {
1675 if (IO_APIC_IRQ(irq
) && !irq_cfg(irq
)->vector
) {
1677 * Hmm.. We don't have an entry for this,
1678 * so default to an old-fashioned 8259
1679 * interrupt if we can..
1682 make_8259A_irq(irq
);
1684 desc
= irq_to_desc(irq
);
1685 /* Strange. Oh, well.. */
1686 desc
->chip
= &no_irq_chip
;
1693 * The local APIC irq-chip implementation:
1696 static void ack_lapic_irq(unsigned int irq
)
1701 static void mask_lapic_irq(unsigned int irq
)
1705 v
= apic_read(APIC_LVT0
);
1706 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1709 static void unmask_lapic_irq(unsigned int irq
)
1713 v
= apic_read(APIC_LVT0
);
1714 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1717 static struct irq_chip lapic_chip __read_mostly
= {
1718 .name
= "local-APIC",
1719 .mask
= mask_lapic_irq
,
1720 .unmask
= unmask_lapic_irq
,
1721 .ack
= ack_lapic_irq
,
1724 static void lapic_register_intr(int irq
, int vector
)
1726 struct irq_desc
*desc
;
1728 desc
= irq_to_desc(irq
);
1729 desc
->status
&= ~IRQ_LEVEL
;
1730 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
1732 set_intr_gate(vector
, interrupt
[irq
]);
1735 static void __init
setup_nmi(void)
1738 * Dirty trick to enable the NMI watchdog ...
1739 * We put the 8259A master into AEOI mode and
1740 * unmask on all local APICs LVT0 as NMI.
1742 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1743 * is from Maciej W. Rozycki - so we do not have to EOI from
1744 * the NMI handler or the timer interrupt.
1746 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
1748 enable_NMI_through_LVT0();
1750 apic_printk(APIC_VERBOSE
, " done.\n");
1754 * This looks a bit hackish but it's about the only one way of sending
1755 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1756 * not support the ExtINT mode, unfortunately. We need to send these
1757 * cycles as some i82489DX-based boards have glue logic that keeps the
1758 * 8259A interrupt line asserted until INTA. --macro
1760 static inline void __init
unlock_ExtINT_logic(void)
1763 struct IO_APIC_route_entry entry0
, entry1
;
1764 unsigned char save_control
, save_freq_select
;
1766 pin
= find_isa_irq_pin(8, mp_INT
);
1771 apic
= find_isa_irq_apic(8, mp_INT
);
1777 entry0
= ioapic_read_entry(apic
, pin
);
1778 clear_IO_APIC_pin(apic
, pin
);
1780 memset(&entry1
, 0, sizeof(entry1
));
1782 entry1
.dest_mode
= 0; /* physical delivery */
1783 entry1
.mask
= 0; /* unmask IRQ now */
1784 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
1785 entry1
.delivery_mode
= dest_ExtINT
;
1786 entry1
.polarity
= entry0
.polarity
;
1790 ioapic_write_entry(apic
, pin
, entry1
);
1792 save_control
= CMOS_READ(RTC_CONTROL
);
1793 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1794 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1796 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1801 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1805 CMOS_WRITE(save_control
, RTC_CONTROL
);
1806 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1807 clear_IO_APIC_pin(apic
, pin
);
1809 ioapic_write_entry(apic
, pin
, entry0
);
1813 * This code may look a bit paranoid, but it's supposed to cooperate with
1814 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1815 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1816 * fanatically on his truly buggy board.
1818 static inline void __init
check_timer(void)
1820 int apic1
, pin1
, apic2
, pin2
;
1824 unsigned long flags
;
1826 local_irq_save(flags
);
1828 ver
= apic_read(APIC_LVR
);
1829 ver
= GET_APIC_VERSION(ver
);
1832 * get/set the timer IRQ vector:
1834 disable_8259A_irq(0);
1835 vector
= assign_irq_vector(0);
1836 set_intr_gate(vector
, interrupt
[0]);
1839 * As IRQ0 is to be enabled in the 8259A, the virtual
1840 * wire has to be disabled in the local APIC. Also
1841 * timer interrupts need to be acknowledged manually in
1842 * the 8259A for the i82489DX when using the NMI
1843 * watchdog as that APIC treats NMIs as level-triggered.
1844 * The AEOI mode will finish them in the 8259A
1847 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1849 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
1851 pin1
= find_isa_irq_pin(0, mp_INT
);
1852 apic1
= find_isa_irq_apic(0, mp_INT
);
1853 pin2
= ioapic_i8259
.pin
;
1854 apic2
= ioapic_i8259
.apic
;
1856 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
1857 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
1858 vector
, apic1
, pin1
, apic2
, pin2
);
1861 * Some BIOS writers are clueless and report the ExtINTA
1862 * I/O APIC input from the cascaded 8259A as the timer
1863 * interrupt input. So just in case, if only one pin
1864 * was found above, try it both directly and through the
1871 } else if (pin2
== -1) {
1878 * Ok, does IRQ0 through the IOAPIC work?
1881 add_pin_to_irq(0, apic1
, pin1
);
1882 setup_timer_IRQ0_pin(apic1
, pin1
, vector
);
1884 unmask_IO_APIC_irq(0);
1885 if (timer_irq_works()) {
1886 if (nmi_watchdog
== NMI_IO_APIC
) {
1888 enable_8259A_irq(0);
1890 if (disable_timer_pin_1
> 0)
1891 clear_IO_APIC_pin(0, pin1
);
1894 clear_IO_APIC_pin(apic1
, pin1
);
1896 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
1897 "8254 timer not connected to IO-APIC\n");
1899 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
1900 "(IRQ0) through the 8259A ...\n");
1901 apic_printk(APIC_QUIET
, KERN_INFO
1902 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
1904 * legacy devices should be connected to IO APIC #0
1906 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
1907 setup_timer_IRQ0_pin(apic2
, pin2
, vector
);
1908 unmask_IO_APIC_irq(0);
1909 enable_8259A_irq(0);
1910 if (timer_irq_works()) {
1911 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
1912 timer_through_8259
= 1;
1913 if (nmi_watchdog
== NMI_IO_APIC
) {
1914 disable_8259A_irq(0);
1916 enable_8259A_irq(0);
1921 * Cleanup, just in case ...
1923 disable_8259A_irq(0);
1924 clear_IO_APIC_pin(apic2
, pin2
);
1925 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
1928 if (nmi_watchdog
== NMI_IO_APIC
) {
1929 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
1930 "through the IO-APIC - disabling NMI Watchdog!\n");
1931 nmi_watchdog
= NMI_NONE
;
1935 apic_printk(APIC_QUIET
, KERN_INFO
1936 "...trying to set up timer as Virtual Wire IRQ...\n");
1938 lapic_register_intr(0, vector
);
1939 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
1940 enable_8259A_irq(0);
1942 if (timer_irq_works()) {
1943 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
1946 disable_8259A_irq(0);
1947 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
1948 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
1950 apic_printk(APIC_QUIET
, KERN_INFO
1951 "...trying to set up timer as ExtINT IRQ...\n");
1955 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1957 unlock_ExtINT_logic();
1959 if (timer_irq_works()) {
1960 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
1963 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
1964 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1965 "report. Then try booting with the 'noapic' option.\n");
1967 local_irq_restore(flags
);
1971 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
1972 * to devices. However there may be an I/O APIC pin available for
1973 * this interrupt regardless. The pin may be left unconnected, but
1974 * typically it will be reused as an ExtINT cascade interrupt for
1975 * the master 8259A. In the MPS case such a pin will normally be
1976 * reported as an ExtINT interrupt in the MP table. With ACPI
1977 * there is no provision for ExtINT interrupts, and in the absence
1978 * of an override it would be treated as an ordinary ISA I/O APIC
1979 * interrupt, that is edge-triggered and unmasked by default. We
1980 * used to do this, but it caused problems on some systems because
1981 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
1982 * the same ExtINT cascade interrupt to drive the local APIC of the
1983 * bootstrap processor. Therefore we refrain from routing IRQ2 to
1984 * the I/O APIC in all cases now. No actual device should request
1985 * it anyway. --macro
1987 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1989 void __init
setup_IO_APIC(void)
1993 /* Reserve all the system vectors. */
1994 for (i
= first_system_vector
; i
< NR_VECTORS
; i
++)
1995 set_bit(i
, used_vectors
);
1999 io_apic_irqs
= ~PIC_IRQS
;
2001 printk("ENABLING IO-APIC IRQs\n");
2004 * Set up IO-APIC IRQ routing.
2007 setup_ioapic_ids_from_mpc();
2009 setup_IO_APIC_irqs();
2010 init_IO_APIC_traps();
2015 * Called after all the initialization is done. If we didnt find any
2016 * APIC bugs then we can allow the modify fast path
2019 static int __init
io_apic_bug_finalize(void)
2021 if (sis_apic_bug
== -1)
2026 late_initcall(io_apic_bug_finalize
);
2028 struct sysfs_ioapic_data
{
2029 struct sys_device dev
;
2030 struct IO_APIC_route_entry entry
[0];
2032 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2034 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2036 struct IO_APIC_route_entry
*entry
;
2037 struct sysfs_ioapic_data
*data
;
2040 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2041 entry
= data
->entry
;
2042 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2043 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2048 static int ioapic_resume(struct sys_device
*dev
)
2050 struct IO_APIC_route_entry
*entry
;
2051 struct sysfs_ioapic_data
*data
;
2052 unsigned long flags
;
2053 union IO_APIC_reg_00 reg_00
;
2056 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2057 entry
= data
->entry
;
2059 spin_lock_irqsave(&ioapic_lock
, flags
);
2060 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2061 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2062 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2063 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2065 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2066 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2067 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2072 static struct sysdev_class ioapic_sysdev_class
= {
2074 .suspend
= ioapic_suspend
,
2075 .resume
= ioapic_resume
,
2078 static int __init
ioapic_init_sysfs(void)
2080 struct sys_device
*dev
;
2081 int i
, size
, error
= 0;
2083 error
= sysdev_class_register(&ioapic_sysdev_class
);
2087 for (i
= 0; i
< nr_ioapics
; i
++) {
2088 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2089 * sizeof(struct IO_APIC_route_entry
);
2090 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2091 if (!mp_ioapic_data
[i
]) {
2092 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2095 dev
= &mp_ioapic_data
[i
]->dev
;
2097 dev
->cls
= &ioapic_sysdev_class
;
2098 error
= sysdev_register(dev
);
2100 kfree(mp_ioapic_data
[i
]);
2101 mp_ioapic_data
[i
] = NULL
;
2102 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2110 device_initcall(ioapic_init_sysfs
);
2113 * Dynamic irq allocate and deallocation
2115 int create_irq(void)
2117 /* Allocate an unused irq */
2118 int irq
, new, vector
= 0;
2119 unsigned long flags
;
2122 spin_lock_irqsave(&vector_lock
, flags
);
2123 for (new = (nr_irqs
- 1); new >= 0; new--) {
2124 if (platform_legacy_irq(new))
2126 if (irq_cfg(new)->vector
!= 0)
2128 vector
= __assign_irq_vector(new);
2129 if (likely(vector
> 0))
2133 spin_unlock_irqrestore(&vector_lock
, flags
);
2136 set_intr_gate(vector
, interrupt
[irq
]);
2137 dynamic_irq_init(irq
);
2142 void destroy_irq(unsigned int irq
)
2144 unsigned long flags
;
2146 dynamic_irq_cleanup(irq
);
2148 spin_lock_irqsave(&vector_lock
, flags
);
2149 clear_bit(irq_cfg(irq
)->vector
, used_vectors
);
2150 irq_cfg(irq
)->vector
= 0;
2151 spin_unlock_irqrestore(&vector_lock
, flags
);
2155 * MSI message composition
2157 #ifdef CONFIG_PCI_MSI
2158 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2163 vector
= assign_irq_vector(irq
);
2165 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2167 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2170 ((INT_DEST_MODE
== 0) ?
2171 MSI_ADDR_DEST_MODE_PHYSICAL
:
2172 MSI_ADDR_DEST_MODE_LOGICAL
) |
2173 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2174 MSI_ADDR_REDIRECTION_CPU
:
2175 MSI_ADDR_REDIRECTION_LOWPRI
) |
2176 MSI_ADDR_DEST_ID(dest
);
2179 MSI_DATA_TRIGGER_EDGE
|
2180 MSI_DATA_LEVEL_ASSERT
|
2181 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2182 MSI_DATA_DELIVERY_FIXED
:
2183 MSI_DATA_DELIVERY_LOWPRI
) |
2184 MSI_DATA_VECTOR(vector
);
2190 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2196 struct irq_desc
*desc
;
2198 cpus_and(tmp
, mask
, cpu_online_map
);
2199 if (cpus_empty(tmp
))
2202 vector
= assign_irq_vector(irq
);
2206 dest
= cpu_mask_to_apicid(mask
);
2208 read_msi_msg(irq
, &msg
);
2210 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2211 msg
.data
|= MSI_DATA_VECTOR(vector
);
2212 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2213 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2215 write_msi_msg(irq
, &msg
);
2216 desc
= irq_to_desc(irq
);
2217 desc
->affinity
= mask
;
2219 #endif /* CONFIG_SMP */
2222 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2223 * which implement the MSI or MSI-X Capability Structure.
2225 static struct irq_chip msi_chip
= {
2227 .unmask
= unmask_msi_irq
,
2228 .mask
= mask_msi_irq
,
2229 .ack
= ack_ioapic_irq
,
2231 .set_affinity
= set_msi_irq_affinity
,
2233 .retrigger
= ioapic_retrigger_irq
,
2236 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2244 ret
= msi_compose_msg(dev
, irq
, &msg
);
2250 set_irq_msi(irq
, desc
);
2251 write_msi_msg(irq
, &msg
);
2253 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2259 void arch_teardown_msi_irq(unsigned int irq
)
2264 #endif /* CONFIG_PCI_MSI */
2267 * Hypertransport interrupt support
2269 #ifdef CONFIG_HT_IRQ
2273 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2275 struct ht_irq_msg msg
;
2276 fetch_ht_irq_msg(irq
, &msg
);
2278 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2279 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2281 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2282 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2284 write_ht_irq_msg(irq
, &msg
);
2287 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2291 struct irq_desc
*desc
;
2293 cpus_and(tmp
, mask
, cpu_online_map
);
2294 if (cpus_empty(tmp
))
2297 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2299 dest
= cpu_mask_to_apicid(mask
);
2301 target_ht_irq(irq
, dest
);
2302 desc
= irq_to_desc(irq
);
2303 desc
->affinity
= mask
;
2307 static struct irq_chip ht_irq_chip
= {
2309 .mask
= mask_ht_irq
,
2310 .unmask
= unmask_ht_irq
,
2311 .ack
= ack_ioapic_irq
,
2313 .set_affinity
= set_ht_irq_affinity
,
2315 .retrigger
= ioapic_retrigger_irq
,
2318 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2322 vector
= assign_irq_vector(irq
);
2324 struct ht_irq_msg msg
;
2329 cpu_set(vector
>> 8, tmp
);
2330 dest
= cpu_mask_to_apicid(tmp
);
2332 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2336 HT_IRQ_LOW_DEST_ID(dest
) |
2337 HT_IRQ_LOW_VECTOR(vector
) |
2338 ((INT_DEST_MODE
== 0) ?
2339 HT_IRQ_LOW_DM_PHYSICAL
:
2340 HT_IRQ_LOW_DM_LOGICAL
) |
2341 HT_IRQ_LOW_RQEOI_EDGE
|
2342 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2343 HT_IRQ_LOW_MT_FIXED
:
2344 HT_IRQ_LOW_MT_ARBITRATED
) |
2345 HT_IRQ_LOW_IRQ_MASKED
;
2347 write_ht_irq_msg(irq
, &msg
);
2349 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2350 handle_edge_irq
, "edge");
2354 #endif /* CONFIG_HT_IRQ */
2356 /* --------------------------------------------------------------------------
2357 ACPI-based IOAPIC Configuration
2358 -------------------------------------------------------------------------- */
2362 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2364 union IO_APIC_reg_00 reg_00
;
2365 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2367 unsigned long flags
;
2371 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2372 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2373 * supports up to 16 on one shared APIC bus.
2375 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2376 * advantage of new APIC bus architecture.
2379 if (physids_empty(apic_id_map
))
2380 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2382 spin_lock_irqsave(&ioapic_lock
, flags
);
2383 reg_00
.raw
= io_apic_read(ioapic
, 0);
2384 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2386 if (apic_id
>= get_physical_broadcast()) {
2387 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2388 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2389 apic_id
= reg_00
.bits
.ID
;
2393 * Every APIC in a system must have a unique ID or we get lots of nice
2394 * 'stuck on smp_invalidate_needed IPI wait' messages.
2396 if (check_apicid_used(apic_id_map
, apic_id
)) {
2398 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2399 if (!check_apicid_used(apic_id_map
, i
))
2403 if (i
== get_physical_broadcast())
2404 panic("Max apic_id exceeded!\n");
2406 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2407 "trying %d\n", ioapic
, apic_id
, i
);
2412 tmp
= apicid_to_cpu_present(apic_id
);
2413 physids_or(apic_id_map
, apic_id_map
, tmp
);
2415 if (reg_00
.bits
.ID
!= apic_id
) {
2416 reg_00
.bits
.ID
= apic_id
;
2418 spin_lock_irqsave(&ioapic_lock
, flags
);
2419 io_apic_write(ioapic
, 0, reg_00
.raw
);
2420 reg_00
.raw
= io_apic_read(ioapic
, 0);
2421 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2424 if (reg_00
.bits
.ID
!= apic_id
) {
2425 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2430 apic_printk(APIC_VERBOSE
, KERN_INFO
2431 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2437 int __init
io_apic_get_version(int ioapic
)
2439 union IO_APIC_reg_01 reg_01
;
2440 unsigned long flags
;
2442 spin_lock_irqsave(&ioapic_lock
, flags
);
2443 reg_01
.raw
= io_apic_read(ioapic
, 1);
2444 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2446 return reg_01
.bits
.version
;
2450 int __init
io_apic_get_redir_entries(int ioapic
)
2452 union IO_APIC_reg_01 reg_01
;
2453 unsigned long flags
;
2455 spin_lock_irqsave(&ioapic_lock
, flags
);
2456 reg_01
.raw
= io_apic_read(ioapic
, 1);
2457 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2459 return reg_01
.bits
.entries
;
2463 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2465 struct IO_APIC_route_entry entry
;
2467 if (!IO_APIC_IRQ(irq
)) {
2468 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2474 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2475 * Note that we mask (disable) IRQs now -- these get enabled when the
2476 * corresponding device driver registers for this IRQ.
2479 memset(&entry
, 0, sizeof(entry
));
2481 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2482 entry
.dest_mode
= INT_DEST_MODE
;
2483 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2484 entry
.trigger
= edge_level
;
2485 entry
.polarity
= active_high_low
;
2489 * IRQs < 16 are already in the irq_2_pin[] map
2492 add_pin_to_irq(irq
, ioapic
, pin
);
2494 entry
.vector
= assign_irq_vector(irq
);
2496 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2497 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2498 mp_ioapics
[ioapic
].mp_apicid
, pin
, entry
.vector
, irq
,
2499 edge_level
, active_high_low
);
2501 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2503 if (!ioapic
&& (irq
< 16))
2504 disable_8259A_irq(irq
);
2506 ioapic_write_entry(ioapic
, pin
, entry
);
2511 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2515 if (skip_ioapic_setup
)
2518 for (i
= 0; i
< mp_irq_entries
; i
++)
2519 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2520 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2522 if (i
>= mp_irq_entries
)
2525 *trigger
= irq_trigger(i
);
2526 *polarity
= irq_polarity(i
);
2530 #endif /* CONFIG_ACPI */
2532 static int __init
parse_disable_timer_pin_1(char *arg
)
2534 disable_timer_pin_1
= 1;
2537 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2539 static int __init
parse_enable_timer_pin_1(char *arg
)
2541 disable_timer_pin_1
= -1;
2544 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2546 static int __init
parse_noapic(char *arg
)
2548 /* disable IO-APIC */
2549 disable_ioapic_setup();
2552 early_param("noapic", parse_noapic
);
2554 void __init
ioapic_init_mappings(void)
2556 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2559 for (i
= 0; i
< nr_ioapics
; i
++) {
2560 if (smp_found_config
) {
2561 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2564 "WARNING: bogus zero IO-APIC "
2565 "address found in MPTABLE, "
2566 "disabling IO/APIC support!\n");
2567 smp_found_config
= 0;
2568 skip_ioapic_setup
= 1;
2569 goto fake_ioapic_page
;
2573 ioapic_phys
= (unsigned long)
2574 alloc_bootmem_pages(PAGE_SIZE
);
2575 ioapic_phys
= __pa(ioapic_phys
);
2577 set_fixmap_nocache(idx
, ioapic_phys
);
2578 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
2579 __fix_to_virt(idx
), ioapic_phys
);