5 * \author Gareth Hughes <gareth@valinux.com>
9 * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
12 * All Rights Reserved.
14 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation
17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18 * and/or sell copies of the Software, and to permit persons to whom the
19 * Software is furnished to do so, subject to the following conditions:
21 * The above copyright notice and this permission notice (including the next
22 * paragraph) shall be included in all copies or substantial portions of the
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
31 * DEALINGS IN THE SOFTWARE.
36 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
38 static int drm_ati_alloc_pcigart_table(struct drm_device
*dev
,
39 struct drm_ati_pcigart_info
*gart_info
)
41 gart_info
->table_handle
= drm_pci_alloc(dev
, gart_info
->table_size
,
43 gart_info
->table_mask
);
44 if (gart_info
->table_handle
== NULL
)
50 static void drm_ati_free_pcigart_table(struct drm_device
*dev
,
51 struct drm_ati_pcigart_info
*gart_info
)
53 drm_pci_free(dev
, gart_info
->table_handle
);
54 gart_info
->table_handle
= NULL
;
57 int drm_ati_pcigart_cleanup(struct drm_device
*dev
, struct drm_ati_pcigart_info
*gart_info
)
59 struct drm_sg_mem
*entry
= dev
->sg
;
64 /* we need to support large memory configurations */
66 DRM_ERROR("no scatter/gather memory!\n");
70 if (gart_info
->bus_addr
) {
72 max_pages
= (gart_info
->table_size
/ sizeof(u32
));
73 pages
= (entry
->pages
<= max_pages
)
74 ? entry
->pages
: max_pages
;
76 for (i
= 0; i
< pages
; i
++) {
77 if (!entry
->busaddr
[i
])
79 pci_unmap_page(dev
->pdev
, entry
->busaddr
[i
],
80 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
83 if (gart_info
->gart_table_location
== DRM_ATI_GART_MAIN
)
84 gart_info
->bus_addr
= 0;
87 if (gart_info
->gart_table_location
== DRM_ATI_GART_MAIN
&&
88 gart_info
->table_handle
) {
89 drm_ati_free_pcigart_table(dev
, gart_info
);
94 EXPORT_SYMBOL(drm_ati_pcigart_cleanup
);
96 int drm_ati_pcigart_init(struct drm_device
*dev
, struct drm_ati_pcigart_info
*gart_info
)
98 struct drm_local_map
*map
= &gart_info
->mapping
;
99 struct drm_sg_mem
*entry
= dev
->sg
;
100 void *address
= NULL
;
102 u32
*pci_gart
= NULL
, page_base
, gart_idx
;
103 dma_addr_t bus_address
= 0;
105 int max_ati_pages
, max_real_pages
;
108 DRM_ERROR("no scatter/gather memory!\n");
112 if (gart_info
->gart_table_location
== DRM_ATI_GART_MAIN
) {
113 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
115 ret
= drm_ati_alloc_pcigart_table(dev
, gart_info
);
117 DRM_ERROR("cannot allocate PCI GART page!\n");
121 pci_gart
= gart_info
->table_handle
->vaddr
;
122 address
= gart_info
->table_handle
->vaddr
;
123 bus_address
= gart_info
->table_handle
->busaddr
;
125 address
= gart_info
->addr
;
126 bus_address
= gart_info
->bus_addr
;
127 DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
128 (unsigned long long)bus_address
,
129 (unsigned long)address
);
133 max_ati_pages
= (gart_info
->table_size
/ sizeof(u32
));
134 max_real_pages
= max_ati_pages
/ (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
);
135 pages
= (entry
->pages
<= max_real_pages
)
136 ? entry
->pages
: max_real_pages
;
138 if (gart_info
->gart_table_location
== DRM_ATI_GART_MAIN
) {
139 memset(pci_gart
, 0, max_ati_pages
* sizeof(u32
));
141 memset_io((void __iomem
*)map
->handle
, 0, max_ati_pages
* sizeof(u32
));
145 for (i
= 0; i
< pages
; i
++) {
146 /* we need to support large memory configurations */
147 entry
->busaddr
[i
] = pci_map_page(dev
->pdev
, entry
->pagelist
[i
],
148 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
149 if (entry
->busaddr
[i
] == 0) {
150 DRM_ERROR("unable to map PCIGART pages!\n");
151 drm_ati_pcigart_cleanup(dev
, gart_info
);
156 page_base
= (u32
) entry
->busaddr
[i
];
158 for (j
= 0; j
< (PAGE_SIZE
/ ATI_PCIGART_PAGE_SIZE
); j
++) {
161 switch(gart_info
->gart_reg_if
) {
162 case DRM_ATI_GART_IGP
:
163 val
= page_base
| 0xc;
165 case DRM_ATI_GART_PCIE
:
166 val
= (page_base
>> 8) | 0xc;
169 case DRM_ATI_GART_PCI
:
173 if (gart_info
->gart_table_location
==
175 pci_gart
[gart_idx
] = cpu_to_le32(val
);
177 DRM_WRITE32(map
, gart_idx
* sizeof(u32
), val
);
179 page_base
+= ATI_PCIGART_PAGE_SIZE
;
184 #if defined(__i386__) || defined(__x86_64__)
191 gart_info
->addr
= address
;
192 gart_info
->bus_addr
= bus_address
;
195 EXPORT_SYMBOL(drm_ati_pcigart_init
);