arch/powerpc/include/asm/pci.h

   1 #ifndef __ASM_POWERPC_PCI_H
   2 #define __ASM_POWERPC_PCI_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <asm/machdep.h>
  18 #include <asm/scatterlist.h>
  19 #include <asm/io.h>
  20 #include <asm/prom.h>
  21 #include <asm/pci-bridge.h>
  22
  23 #include <asm-generic/pci-dma-compat.h>
  24
  25 /* Return values for ppc_md.pci_probe_mode function */
  26 #define PCI_PROBE_NONE          -1      /* Don't look at this bus at all */
  27 #define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
  28 #define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
  29
  30 #define PCIBIOS_MIN_IO          0x1000
  31 #define PCIBIOS_MIN_MEM         0x10000000
  32
  33 struct pci_dev;
  34
  35 /* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
  36 #define IOBASE_BRIDGE_NUMBER    0
  37 #define IOBASE_MEMORY           1
  38 #define IOBASE_IO               2
  39 #define IOBASE_ISA_IO           3
  40 #define IOBASE_ISA_MEM          4
  41
  42 /*
  43  * Set this to 1 if you want the kernel to re-assign all PCI
  44  * bus numbers (don't do that on ppc64 yet !)
  45  */
  46 #define pcibios_assign_all_busses() \
  47         (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS))
  48
  49 static inline void pcibios_set_master(struct pci_dev *dev)
  50 {
  51         /* No special bus mastering setup handling */
  52 }
  53
  54 static inline void pcibios_penalize_isa_irq(int irq, int active)
  55 {
  56         /* We don't do dynamic PCI IRQ allocation */
  57 }
  58
  59 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
  60 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
  61 {
  62         if (ppc_md.pci_get_legacy_ide_irq)
  63                 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
  64         return channel ? 15 : 14;
  65 }
  66
  67 #ifdef CONFIG_PCI
  68 extern void set_pci_dma_ops(struct dma_map_ops *dma_ops);
  69 extern struct dma_map_ops *get_pci_dma_ops(void);
  70 #else   /* CONFIG_PCI */
  71 #define set_pci_dma_ops(d)
  72 #define get_pci_dma_ops()       NULL
  73 #endif
  74
  75 #ifdef CONFIG_PPC64
  76
  77 /*
  78  * We want to avoid touching the cacheline size or MWI bit.
  79  * pSeries firmware sets the cacheline size (which is not the cpu cacheline
  80  * size in all cases) and hardware treats MWI the same as memory write.
  81  */
  82 #define PCI_DISABLE_MWI
  83
  84 #ifdef CONFIG_PCI
  85 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  86                                         enum pci_dma_burst_strategy *strat,
  87                                         unsigned long *strategy_parameter)
  88 {
  89         unsigned long cacheline_size;
  90         u8 byte;
  91
  92         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
  93         if (byte == 0)
  94                 cacheline_size = 1024;
  95         else
  96                 cacheline_size = (int) byte * 4;
  97
  98         *strat = PCI_DMA_BURST_MULTIPLE;
  99         *strategy_parameter = cacheline_size;
 100 }
 101 #endif
 102
 103 #else /* 32-bit */
 104
 105 #ifdef CONFIG_PCI
 106 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 107                                         enum pci_dma_burst_strategy *strat,
 108                                         unsigned long *strategy_parameter)
 109 {
 110         *strat = PCI_DMA_BURST_INFINITY;
 111         *strategy_parameter = ~0UL;
 112 }
 113 #endif
 114 #endif /* CONFIG_PPC64 */
 115
 116 extern int pci_domain_nr(struct pci_bus *bus);
 117
 118 /* Decide whether to display the domain number in /proc */
 119 extern int pci_proc_domain(struct pci_bus *bus);
 120
 121 /* MSI arch hooks */
 122 #define arch_setup_msi_irqs arch_setup_msi_irqs
 123 #define arch_teardown_msi_irqs arch_teardown_msi_irqs
 124 #define arch_msi_check_device arch_msi_check_device
 125
 126 struct vm_area_struct;
 127 /* Map a range of PCI memory or I/O space for a device into user space */
 128 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
 129                         enum pci_mmap_state mmap_state, int write_combine);
 130
 131 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
 132 #define HAVE_PCI_MMAP   1
 133
 134 extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
 135                            size_t count);
 136 extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
 137                            size_t count);
 138 extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 139                                       struct vm_area_struct *vma,
 140                                       enum pci_mmap_state mmap_state);
 141
 142 #define HAVE_PCI_LEGACY 1
 143
 144 #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
 145 /*
 146  * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
 147  * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
 148  * so on are not nops.
 149  * and thus...
 150  */
 151 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
 152         dma_addr_t ADDR_NAME;
 153 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
 154         __u32 LEN_NAME;
 155 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
 156         ((PTR)->ADDR_NAME)
 157 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
 158         (((PTR)->ADDR_NAME) = (VAL))
 159 #define pci_unmap_len(PTR, LEN_NAME)                    \
 160         ((PTR)->LEN_NAME)
 161 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
 162         (((PTR)->LEN_NAME) = (VAL))
 163
 164 #else /* 32-bit && coherent */
 165
 166 /* pci_unmap_{page,single} is a nop so... */
 167 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
 168 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
 169 #define pci_unmap_addr(PTR, ADDR_NAME)          (0)
 170 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
 171 #define pci_unmap_len(PTR, LEN_NAME)            (0)
 172 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
 173
 174 #endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */
 175
 176 #ifdef CONFIG_PPC64
 177
 178 /* The PCI address space does not equal the physical memory address
 179  * space (we have an IOMMU).  The IDE and SCSI device layers use
 180  * this boolean for bounce buffer decisions.
 181  */
 182 #define PCI_DMA_BUS_IS_PHYS     (0)
 183
 184 #else /* 32-bit */
 185
 186 /* The PCI address space does equal the physical memory
 187  * address space (no IOMMU).  The IDE and SCSI device layers use
 188  * this boolean for bounce buffer decisions.
 189  */
 190 #define PCI_DMA_BUS_IS_PHYS     (1)
 191
 192 #endif /* CONFIG_PPC64 */
 193
 194 extern void pcibios_resource_to_bus(struct pci_dev *dev,
 195                         struct pci_bus_region *region,
 196                         struct resource *res);
 197
 198 extern void pcibios_bus_to_resource(struct pci_dev *dev,
 199                         struct resource *res,
 200                         struct pci_bus_region *region);
 201
 202 extern void pcibios_claim_one_bus(struct pci_bus *b);
 203
 204 extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
 205
 206 extern void pcibios_resource_survey(void);
 207
 208 extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
 209 extern int remove_phb_dynamic(struct pci_controller *phb);
 210
 211 extern struct pci_dev *of_create_pci_dev(struct device_node *node,
 212                                         struct pci_bus *bus, int devfn);
 213
 214 extern void of_scan_pci_bridge(struct device_node *node,
 215                                 struct pci_dev *dev);
 216
 217 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
 218 extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
 219
 220 extern int pci_read_irq_line(struct pci_dev *dev);
 221
 222 struct file;
 223 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
 224                                          unsigned long pfn,
 225                                          unsigned long size,
 226                                          pgprot_t prot);
 227
 228 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
 229 extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
 230                                  const struct resource *rsrc,
 231                                  resource_size_t *start, resource_size_t *end);
 232
 233 extern void pcibios_setup_bus_devices(struct pci_bus *bus);
 234 extern void pcibios_setup_bus_self(struct pci_bus *bus);
 235 extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
 236 extern void pcibios_scan_phb(struct pci_controller *hose, void *sysdata);
 237
 238 #endif  /* __KERNEL__ */
 239 #endif /* __ASM_POWERPC_PCI_H */