arch/ia64/include/asm/pci.h

   1 #ifndef _ASM_IA64_PCI_H
   2 #define _ASM_IA64_PCI_H
   3
   4 #include <linux/mm.h>
   5 #include <linux/slab.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/string.h>
   8 #include <linux/types.h>
   9
  10 #include <asm/io.h>
  11 #include <asm/scatterlist.h>
  12 #include <asm/hw_irq.h>
  13
  14 /*
  15  * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
  16  * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
  17  * loader.
  18  */
  19 #define pcibios_assign_all_busses()     0
  20
  21 #define PCIBIOS_MIN_IO          0x1000
  22 #define PCIBIOS_MIN_MEM         0x10000000
  23
  24 void pcibios_config_init(void);
  25
  26 struct pci_dev;
  27
  28 /*
  29  * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
  30  * correspondence between device bus addresses and CPU physical addresses.
  31  * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
  32  * bounce buffer handling code in the block and network device layers.
  33  * Platforms with separate bus address spaces _must_ turn this off and provide
  34  * a device DMA mapping implementation that takes care of the necessary
  35  * address translation.
  36  *
  37  * For now, the ia64 platforms which may have separate/multiple bus address
  38  * spaces all have I/O MMUs which support the merging of physically
  39  * discontiguous buffers, so we can use that as the sole factor to determine
  40  * the setting of PCI_DMA_BUS_IS_PHYS.
  41  */
  42 extern unsigned long ia64_max_iommu_merge_mask;
  43 #define PCI_DMA_BUS_IS_PHYS     (ia64_max_iommu_merge_mask == ~0UL)
  44
  45 static inline void
  46 pcibios_set_master (struct pci_dev *dev)
  47 {
  48         /* No special bus mastering setup handling */
  49 }
  50
  51 static inline void
  52 pcibios_penalize_isa_irq (int irq, int active)
  53 {
  54         /* We don't do dynamic PCI IRQ allocation */
  55 }
  56
  57 #include <asm-generic/pci-dma-compat.h>
  58
  59 /* pci_unmap_{single,page} is not a nop, thus... */
  60 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
  61         dma_addr_t ADDR_NAME;
  62 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
  63         __u32 LEN_NAME;
  64 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
  65         ((PTR)->ADDR_NAME)
  66 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
  67         (((PTR)->ADDR_NAME) = (VAL))
  68 #define pci_unmap_len(PTR, LEN_NAME)                    \
  69         ((PTR)->LEN_NAME)
  70 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
  71         (((PTR)->LEN_NAME) = (VAL))
  72
  73 #ifdef CONFIG_PCI
  74 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  75                                         enum pci_dma_burst_strategy *strat,
  76                                         unsigned long *strategy_parameter)
  77 {
  78         unsigned long cacheline_size;
  79         u8 byte;
  80
  81         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
  82         if (byte == 0)
  83                 cacheline_size = 1024;
  84         else
  85                 cacheline_size = (int) byte * 4;
  86
  87         *strat = PCI_DMA_BURST_MULTIPLE;
  88         *strategy_parameter = cacheline_size;
  89 }
  90 #endif
  91
  92 #define HAVE_PCI_MMAP
  93 extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
  94                                 enum pci_mmap_state mmap_state, int write_combine);
  95 #define HAVE_PCI_LEGACY
  96 extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
  97                                       struct vm_area_struct *vma,
  98                                       enum pci_mmap_state mmap_state);
  99
 100 #define pci_get_legacy_mem platform_pci_get_legacy_mem
 101 #define pci_legacy_read platform_pci_legacy_read
 102 #define pci_legacy_write platform_pci_legacy_write
 103
 104 struct pci_window {
 105         struct resource resource;
 106         u64 offset;
 107 };
 108
 109 struct pci_controller {
 110         void *acpi_handle;
 111         void *iommu;
 112         int segment;
 113         int node;               /* nearest node with memory or -1 for global allocation */
 114
 115         unsigned int windows;
 116         struct pci_window *window;
 117
 118         void *platform_data;
 119 };
 120
 121 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
 122 #define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
 123
 124 extern struct pci_ops pci_root_ops;
 125
 126 static inline int pci_proc_domain(struct pci_bus *bus)
 127 {
 128         return (pci_domain_nr(bus) != 0);
 129 }
 130
 131 extern void pcibios_resource_to_bus(struct pci_dev *dev,
 132                 struct pci_bus_region *region, struct resource *res);
 133
 134 extern void pcibios_bus_to_resource(struct pci_dev *dev,
 135                 struct resource *res, struct pci_bus_region *region);
 136
 137 static inline struct resource *
 138 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 139 {
 140         struct resource *root = NULL;
 141
 142         if (res->flags & IORESOURCE_IO)
 143                 root = &ioport_resource;
 144         if (res->flags & IORESOURCE_MEM)
 145                 root = &iomem_resource;
 146
 147         return root;
 148 }
 149
 150 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
 151 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 152 {
 153         return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
 154 }
 155
 156 #ifdef CONFIG_DMAR
 157 extern void pci_iommu_alloc(void);
 158 #endif
 159 #endif /* _ASM_IA64_PCI_H */