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e1000: Add 82573 controller support to TSO fix
[linux-2.6/mini2440.git] / drivers / ieee1394 / ohci1394.c
blobb6b96fa04d6234ccfdcd5fa65697b614e04b2e58
1 /*
2 * ohci1394.c - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 * 2001 Ben Collins <bcollins@debian.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software Foundation,
19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 /*
23 * Things known to be working:
24 * . Async Request Transmit
25 * . Async Response Receive
26 * . Async Request Receive
27 * . Async Response Transmit
28 * . Iso Receive
29 * . DMA mmap for iso receive
30 * . Config ROM generation
31 *
32 * Things implemented, but still in test phase:
33 * . Iso Transmit
34 * . Async Stream Packets Transmit (Receive done via Iso interface)
35 *
36 * Things not implemented:
37 * . DMA error recovery
38 *
39 * Known bugs:
40 * . devctl BUS_RESET arg confusion (reset type or root holdoff?)
41 * added LONG_RESET_ROOT and SHORT_RESET_ROOT for root holdoff --kk
42 */
43
44 /*
45 * Acknowledgments:
46 *
47 * Adam J Richter <adam@yggdrasil.com>
48 * . Use of pci_class to find device
49 *
50 * Emilie Chung <emilie.chung@axis.com>
51 * . Tip on Async Request Filter
52 *
53 * Pascal Drolet <pascal.drolet@informission.ca>
54 * . Various tips for optimization and functionnalities
55 *
56 * Robert Ficklin <rficklin@westengineering.com>
57 * . Loop in irq_handler
58 *
59 * James Goodwin <jamesg@Filanet.com>
60 * . Various tips on initialization, self-id reception, etc.
61 *
62 * Albrecht Dress <ad@mpifr-bonn.mpg.de>
63 * . Apple PowerBook detection
64 *
65 * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
66 * . Reset the board properly before leaving + misc cleanups
67 *
68 * Leon van Stuivenberg <leonvs@iae.nl>
69 * . Bug fixes
70 *
71 * Ben Collins <bcollins@debian.org>
72 * . Working big-endian support
73 * . Updated to 2.4.x module scheme (PCI aswell)
74 * . Config ROM generation
75 *
76 * Manfred Weihs <weihs@ict.tuwien.ac.at>
77 * . Reworked code for initiating bus resets
78 * (long, short, with or without hold-off)
79 *
80 * Nandu Santhi <contactnandu@users.sourceforge.net>
81 * . Added support for nVidia nForce2 onboard Firewire chipset
82 *
83 */
84
85 #include <linux/config.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/slab.h>
89 #include <linux/interrupt.h>
90 #include <linux/wait.h>
91 #include <linux/errno.h>
92 #include <linux/module.h>
93 #include <linux/moduleparam.h>
94 #include <linux/pci.h>
95 #include <linux/fs.h>
96 #include <linux/poll.h>
97 #include <asm/byteorder.h>
98 #include <asm/atomic.h>
99 #include <asm/uaccess.h>
100 #include <linux/delay.h>
101 #include <linux/spinlock.h>
102
103 #include <asm/pgtable.h>
104 #include <asm/page.h>
105 #include <asm/irq.h>
106 #include <linux/sched.h>
107 #include <linux/types.h>
108 #include <linux/vmalloc.h>
109 #include <linux/init.h>
110
111 #ifdef CONFIG_PPC_PMAC
112 #include <asm/machdep.h>
113 #include <asm/pmac_feature.h>
114 #include <asm/prom.h>
115 #include <asm/pci-bridge.h>
116 #endif
117
118 #include "csr1212.h"
119 #include "ieee1394.h"
120 #include "ieee1394_types.h"
121 #include "hosts.h"
122 #include "dma.h"
123 #include "iso.h"
124 #include "ieee1394_core.h"
125 #include "highlevel.h"
126 #include "ohci1394.h"
127
128 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
129 #define OHCI1394_DEBUG
130 #endif
131
132 #ifdef DBGMSG
133 #undef DBGMSG
134 #endif
135
136 #ifdef OHCI1394_DEBUG
137 #define DBGMSG(fmt, args...) \
138 printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
139 #else
140 #define DBGMSG(fmt, args...)
141 #endif
142
143 #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG
144 #define OHCI_DMA_ALLOC(fmt, args...) \
145 HPSB_ERR("%s(%s)alloc(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
146 ++global_outstanding_dmas, ## args)
147 #define OHCI_DMA_FREE(fmt, args...) \
148 HPSB_ERR("%s(%s)free(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \
149 --global_outstanding_dmas, ## args)
150 static int global_outstanding_dmas = 0;
151 #else
152 #define OHCI_DMA_ALLOC(fmt, args...)
153 #define OHCI_DMA_FREE(fmt, args...)
154 #endif
155
156 /* print general (card independent) information */
157 #define PRINT_G(level, fmt, args...) \
158 printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args)
159
160 /* print card specific information */
161 #define PRINT(level, fmt, args...) \
162 printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
163
164 /* Module Parameters */
165 static int phys_dma = 1;
166 module_param(phys_dma, int, 0644);
167 MODULE_PARM_DESC(phys_dma, "Enable physical dma (default = 1).");
168
169 static void dma_trm_tasklet(unsigned long data);
170 static void dma_trm_reset(struct dma_trm_ctx *d);
171
172 static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
173 enum context_type type, int ctx, int num_desc,
174 int buf_size, int split_buf_size, int context_base);
175 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d);
176 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d);
177
178 static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
179 enum context_type type, int ctx, int num_desc,
180 int context_base);
181
182 static void ohci1394_pci_remove(struct pci_dev *pdev);
183
184 #ifndef __LITTLE_ENDIAN
185 static unsigned hdr_sizes[] =
186 {
187 3, /* TCODE_WRITEQ */
188 4, /* TCODE_WRITEB */
189 3, /* TCODE_WRITE_RESPONSE */
190 0, /* ??? */
191 3, /* TCODE_READQ */
192 4, /* TCODE_READB */
193 3, /* TCODE_READQ_RESPONSE */
194 4, /* TCODE_READB_RESPONSE */
195 1, /* TCODE_CYCLE_START (???) */
196 4, /* TCODE_LOCK_REQUEST */
197 2, /* TCODE_ISO_DATA */
198 4, /* TCODE_LOCK_RESPONSE */
199 };
200
201 /* Swap headers */
202 static inline void packet_swab(quadlet_t *data, int tcode)
203 {
204 size_t size = hdr_sizes[tcode];
205
206 if (tcode > TCODE_LOCK_RESPONSE || hdr_sizes[tcode] == 0)
207 return;
208
209 while (size--)
210 data[size] = swab32(data[size]);
211 }
212 #else
213 /* Don't waste cycles on same sex byte swaps */
214 #define packet_swab(w,x)
215 #endif /* !LITTLE_ENDIAN */
216
217 /***********************************
218 * IEEE-1394 functionality section *
219 ***********************************/
220
221 static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
222 {
223 int i;
224 unsigned long flags;
225 quadlet_t r;
226
227 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
228
229 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
230
231 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
232 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
233 break;
234
235 mdelay(1);
236 }
237
238 r = reg_read(ohci, OHCI1394_PhyControl);
239
240 if (i >= OHCI_LOOP_COUNT)
241 PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
242 r, r & 0x80000000, i);
243
244 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
245
246 return (r & 0x00ff0000) >> 16;
247 }
248
249 static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
250 {
251 int i;
252 unsigned long flags;
253 u32 r = 0;
254
255 spin_lock_irqsave (&ohci->phy_reg_lock, flags);
256
257 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
258
259 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
260 r = reg_read(ohci, OHCI1394_PhyControl);
261 if (!(r & 0x00004000))
262 break;
263
264 mdelay(1);
265 }
266
267 if (i == OHCI_LOOP_COUNT)
268 PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
269 r, r & 0x00004000, i);
270
271 spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
272
273 return;
274 }
275
276 /* Or's our value into the current value */
277 static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
278 {
279 u8 old;
280
281 old = get_phy_reg (ohci, addr);
282 old |= data;
283 set_phy_reg (ohci, addr, old);
284
285 return;
286 }
287
288 static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
289 int phyid, int isroot)
290 {
291 quadlet_t *q = ohci->selfid_buf_cpu;
292 quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
293 size_t size;
294 quadlet_t q0, q1;
295
296 /* Check status of self-id reception */
297
298 if (ohci->selfid_swap)
299 q0 = le32_to_cpu(q[0]);
300 else
301 q0 = q[0];
302
303 if ((self_id_count & 0x80000000) ||
304 ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
305 PRINT(KERN_ERR,
306 "Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)",
307 self_id_count, q0, ohci->self_id_errors);
308
309 /* Tip by James Goodwin <jamesg@Filanet.com>:
310 * We had an error, generate another bus reset in response. */
311 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
312 set_phy_reg_mask (ohci, 1, 0x40);
313 ohci->self_id_errors++;
314 } else {
315 PRINT(KERN_ERR,
316 "Too many errors on SelfID error reception, giving up!");
317 }
318 return;
319 }
320
321 /* SelfID Ok, reset error counter. */
322 ohci->self_id_errors = 0;
323
324 size = ((self_id_count & 0x00001FFC) >> 2) - 1;
325 q++;
326
327 while (size > 0) {
328 if (ohci->selfid_swap) {
329 q0 = le32_to_cpu(q[0]);
330 q1 = le32_to_cpu(q[1]);
331 } else {
332 q0 = q[0];
333 q1 = q[1];
334 }
335
336 if (q0 == ~q1) {
337 DBGMSG ("SelfID packet 0x%x received", q0);
338 hpsb_selfid_received(host, cpu_to_be32(q0));
339 if (((q0 & 0x3f000000) >> 24) == phyid)
340 DBGMSG ("SelfID for this node is 0x%08x", q0);
341 } else {
342 PRINT(KERN_ERR,
343 "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
344 }
345 q += 2;
346 size -= 2;
347 }
348
349 DBGMSG("SelfID complete");
350
351 return;
352 }
353
354 static void ohci_soft_reset(struct ti_ohci *ohci) {
355 int i;
356
357 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
358
359 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
360 if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset))
361 break;
362 mdelay(1);
363 }
364 DBGMSG ("Soft reset finished");
365 }
366
367
368 /* Generate the dma receive prgs and start the context */
369 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq)
370 {
371 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
372 int i;
373
374 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
375
376 for (i=0; i<d->num_desc; i++) {
377 u32 c;
378
379 c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH;
380 if (generate_irq)
381 c |= DMA_CTL_IRQ;
382
383 d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size);
384
385 /* End of descriptor list? */
386 if (i + 1 < d->num_desc) {
387 d->prg_cpu[i]->branchAddress =
388 cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
389 } else {
390 d->prg_cpu[i]->branchAddress =
391 cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
392 }
393
394 d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
395 d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
396 }
397
398 d->buf_ind = 0;
399 d->buf_offset = 0;
400
401 if (d->type == DMA_CTX_ISO) {
402 /* Clear contextControl */
403 reg_write(ohci, d->ctrlClear, 0xffffffff);
404
405 /* Set bufferFill, isochHeader, multichannel for IR context */
406 reg_write(ohci, d->ctrlSet, 0xd0000000);
407
408 /* Set the context match register to match on all tags */
409 reg_write(ohci, d->ctxtMatch, 0xf0000000);
410
411 /* Clear the multi channel mask high and low registers */
412 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
413 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
414
415 /* Set up isoRecvIntMask to generate interrupts */
416 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
417 }
418
419 /* Tell the controller where the first AR program is */
420 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
421
422 /* Run context */
423 reg_write(ohci, d->ctrlSet, 0x00008000);
424
425 DBGMSG("Receive DMA ctx=%d initialized", d->ctx);
426 }
427
428 /* Initialize the dma transmit context */
429 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
430 {
431 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
432
433 /* Stop the context */
434 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
435
436 d->prg_ind = 0;
437 d->sent_ind = 0;
438 d->free_prgs = d->num_desc;
439 d->branchAddrPtr = NULL;
440 INIT_LIST_HEAD(&d->fifo_list);
441 INIT_LIST_HEAD(&d->pending_list);
442
443 if (d->type == DMA_CTX_ISO) {
444 /* enable interrupts */
445 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
446 }
447
448 DBGMSG("Transmit DMA ctx=%d initialized", d->ctx);
449 }
450
451 /* Count the number of available iso contexts */
452 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
453 {
454 int i,ctx=0;
455 u32 tmp;
456
457 reg_write(ohci, reg, 0xffffffff);
458 tmp = reg_read(ohci, reg);
459
460 DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp);
461
462 /* Count the number of contexts */
463 for (i=0; i<32; i++) {
464 if (tmp & 1) ctx++;
465 tmp >>= 1;
466 }
467 return ctx;
468 }
469
470 /* Global initialization */
471 static void ohci_initialize(struct ti_ohci *ohci)
472 {
473 char irq_buf[16];
474 quadlet_t buf;
475 int num_ports, i;
476
477 spin_lock_init(&ohci->phy_reg_lock);
478
479 /* Put some defaults to these undefined bus options */
480 buf = reg_read(ohci, OHCI1394_BusOptions);
481 buf |= 0x60000000; /* Enable CMC and ISC */
482 if (hpsb_disable_irm)
483 buf &= ~0x80000000;
484 else
485 buf |= 0x80000000; /* Enable IRMC */
486 buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
487 buf &= ~0x18000000; /* Disable PMC and BMC */
488 reg_write(ohci, OHCI1394_BusOptions, buf);
489
490 /* Set the bus number */
491 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
492
493 /* Enable posted writes */
494 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
495
496 /* Clear link control register */
497 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
498
499 /* Enable cycle timer and cycle master and set the IRM
500 * contender bit in our self ID packets if appropriate. */
501 reg_write(ohci, OHCI1394_LinkControlSet,
502 OHCI1394_LinkControl_CycleTimerEnable |
503 OHCI1394_LinkControl_CycleMaster);
504 i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;
505 if (hpsb_disable_irm)
506 i &= ~PHY_04_CONTENDER;
507 else
508 i |= PHY_04_CONTENDER;
509 set_phy_reg(ohci, 4, i);
510
511 /* Set up self-id dma buffer */
512 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
513
514 /* enable self-id and phys */
515 reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID |
516 OHCI1394_LinkControl_RcvPhyPkt);
517
518 /* Set the Config ROM mapping register */
519 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
520
521 /* Now get our max packet size */
522 ohci->max_packet_size =
523 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
524
525 /* Don't accept phy packets into AR request context */
526 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
527
528 /* Clear the interrupt mask */
529 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
530 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
531
532 /* Clear the interrupt mask */
533 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
534 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
535
536 /* Initialize AR dma */
537 initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);
538 initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);
539
540 /* Initialize AT dma */
541 initialize_dma_trm_ctx(&ohci->at_req_context);
542 initialize_dma_trm_ctx(&ohci->at_resp_context);
543
544 /* Initialize IR Legacy DMA channel mask */
545 ohci->ir_legacy_channels = 0;
546
547 /*
548 * Accept AT requests from all nodes. This probably
549 * will have to be controlled from the subsystem
550 * on a per node basis.
551 */
552 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
553
554 /* Specify AT retries */
555 reg_write(ohci, OHCI1394_ATRetries,
556 OHCI1394_MAX_AT_REQ_RETRIES |
557 (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
558 (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
559
560 /* We don't want hardware swapping */
561 reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
562
563 /* Enable interrupts */
564 reg_write(ohci, OHCI1394_IntMaskSet,
565 OHCI1394_unrecoverableError |
566 OHCI1394_masterIntEnable |
567 OHCI1394_busReset |
568 OHCI1394_selfIDComplete |
569 OHCI1394_RSPkt |
570 OHCI1394_RQPkt |
571 OHCI1394_respTxComplete |
572 OHCI1394_reqTxComplete |
573 OHCI1394_isochRx |
574 OHCI1394_isochTx |
575 OHCI1394_cycleInconsistent);
576
577 /* Enable link */
578 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
579
580 buf = reg_read(ohci, OHCI1394_Version);
581 #ifndef __sparc__
582 sprintf (irq_buf, "%d", ohci->dev->irq);
583 #else
584 sprintf (irq_buf, "%s", __irq_itoa(ohci->dev->irq));
585 #endif
586 PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s] "
587 "MMIO=[%lx-%lx] Max Packet=[%d] IR/IT contexts=[%d/%d]",
588 ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
589 ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), irq_buf,
590 pci_resource_start(ohci->dev, 0),
591 pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
592 ohci->max_packet_size,
593 ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx);
594
595 /* Check all of our ports to make sure that if anything is
596 * connected, we enable that port. */
597 num_ports = get_phy_reg(ohci, 2) & 0xf;
598 for (i = 0; i < num_ports; i++) {
599 unsigned int status;
600
601 set_phy_reg(ohci, 7, i);
602 status = get_phy_reg(ohci, 8);
603
604 if (status & 0x20)
605 set_phy_reg(ohci, 8, status & ~1);
606 }
607
608 /* Serial EEPROM Sanity check. */
609 if ((ohci->max_packet_size < 512) ||
610 (ohci->max_packet_size > 4096)) {
611 /* Serial EEPROM contents are suspect, set a sane max packet
612 * size and print the raw contents for bug reports if verbose
613 * debug is enabled. */
614 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
615 int i;
616 #endif
617
618 PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, "
619 "attempting to setting max_packet_size to 512 bytes");
620 reg_write(ohci, OHCI1394_BusOptions,
621 (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);
622 ohci->max_packet_size = 512;
623 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
624 PRINT(KERN_DEBUG, " EEPROM Present: %d",
625 (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);
626 reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
627
628 for (i = 0;
629 ((i < 1000) &&
630 (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)
631 udelay(10);
632
633 for (i = 0; i < 0x20; i++) {
634 reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
635 PRINT(KERN_DEBUG, " EEPROM %02x: %02x", i,
636 (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);
637 }
638 #endif
639 }
640 }
641
642 /*
643 * Insert a packet in the DMA fifo and generate the DMA prg
644 * FIXME: rewrite the program in order to accept packets crossing
645 * page boundaries.
646 * check also that a single dma descriptor doesn't cross a
647 * page boundary.
648 */
649 static void insert_packet(struct ti_ohci *ohci,
650 struct dma_trm_ctx *d, struct hpsb_packet *packet)
651 {
652 u32 cycleTimer;
653 int idx = d->prg_ind;
654
655 DBGMSG("Inserting packet for node " NODE_BUS_FMT
656 ", tlabel=%d, tcode=0x%x, speed=%d",
657 NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel,
658 packet->tcode, packet->speed_code);
659
660 d->prg_cpu[idx]->begin.address = 0;
661 d->prg_cpu[idx]->begin.branchAddress = 0;
662
663 if (d->type == DMA_CTX_ASYNC_RESP) {
664 /*
665 * For response packets, we need to put a timeout value in
666 * the 16 lower bits of the status... let's try 1 sec timeout
667 */
668 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
669 d->prg_cpu[idx]->begin.status = cpu_to_le32(
670 (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
671 ((cycleTimer&0x01fff000)>>12));
672
673 DBGMSG("cycleTimer: %08x timeStamp: %08x",
674 cycleTimer, d->prg_cpu[idx]->begin.status);
675 } else
676 d->prg_cpu[idx]->begin.status = 0;
677
678 if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) {
679
680 if (packet->type == hpsb_raw) {
681 d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
682 d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]);
683 d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]);
684 } else {
685 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
686 (packet->header[0] & 0xFFFF);
687
688 if (packet->tcode == TCODE_ISO_DATA) {
689 /* Sending an async stream packet */
690 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
691 } else {
692 /* Sending a normal async request or response */
693 d->prg_cpu[idx]->data[1] =
694 (packet->header[1] & 0xFFFF) |
695 (packet->header[0] & 0xFFFF0000);
696 d->prg_cpu[idx]->data[2] = packet->header[2];
697 d->prg_cpu[idx]->data[3] = packet->header[3];
698 }
699 packet_swab(d->prg_cpu[idx]->data, packet->tcode);
700 }
701
702 if (packet->data_size) { /* block transmit */
703 if (packet->tcode == TCODE_STREAM_DATA){
704 d->prg_cpu[idx]->begin.control =
705 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
706 DMA_CTL_IMMEDIATE | 0x8);
707 } else {
708 d->prg_cpu[idx]->begin.control =
709 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
710 DMA_CTL_IMMEDIATE | 0x10);
711 }
712 d->prg_cpu[idx]->end.control =
713 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
714 DMA_CTL_IRQ |
715 DMA_CTL_BRANCH |
716 packet->data_size);
717 /*
718 * Check that the packet data buffer
719 * does not cross a page boundary.
720 *
721 * XXX Fix this some day. eth1394 seems to trigger
722 * it, but ignoring it doesn't seem to cause a
723 * problem.
724 */
725 #if 0
726 if (cross_bound((unsigned long)packet->data,
727 packet->data_size)>0) {
728 /* FIXME: do something about it */
729 PRINT(KERN_ERR,
730 "%s: packet data addr: %p size %Zd bytes "
731 "cross page boundary", __FUNCTION__,
732 packet->data, packet->data_size);
733 }
734 #endif
735 d->prg_cpu[idx]->end.address = cpu_to_le32(
736 pci_map_single(ohci->dev, packet->data,
737 packet->data_size,
738 PCI_DMA_TODEVICE));
739 OHCI_DMA_ALLOC("single, block transmit packet");
740
741 d->prg_cpu[idx]->end.branchAddress = 0;
742 d->prg_cpu[idx]->end.status = 0;
743 if (d->branchAddrPtr)
744 *(d->branchAddrPtr) =
745 cpu_to_le32(d->prg_bus[idx] | 0x3);
746 d->branchAddrPtr =
747 &(d->prg_cpu[idx]->end.branchAddress);
748 } else { /* quadlet transmit */
749 if (packet->type == hpsb_raw)
750 d->prg_cpu[idx]->begin.control =
751 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
752 DMA_CTL_IMMEDIATE |
753 DMA_CTL_IRQ |
754 DMA_CTL_BRANCH |
755 (packet->header_size + 4));
756 else
757 d->prg_cpu[idx]->begin.control =
758 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
759 DMA_CTL_IMMEDIATE |
760 DMA_CTL_IRQ |
761 DMA_CTL_BRANCH |
762 packet->header_size);
763
764 if (d->branchAddrPtr)
765 *(d->branchAddrPtr) =
766 cpu_to_le32(d->prg_bus[idx] | 0x2);
767 d->branchAddrPtr =
768 &(d->prg_cpu[idx]->begin.branchAddress);
769 }
770
771 } else { /* iso packet */
772 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
773 (packet->header[0] & 0xFFFF);
774 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
775 packet_swab(d->prg_cpu[idx]->data, packet->tcode);
776
777 d->prg_cpu[idx]->begin.control =
778 cpu_to_le32(DMA_CTL_OUTPUT_MORE |
779 DMA_CTL_IMMEDIATE | 0x8);
780 d->prg_cpu[idx]->end.control =
781 cpu_to_le32(DMA_CTL_OUTPUT_LAST |
782 DMA_CTL_UPDATE |
783 DMA_CTL_IRQ |
784 DMA_CTL_BRANCH |
785 packet->data_size);
786 d->prg_cpu[idx]->end.address = cpu_to_le32(
787 pci_map_single(ohci->dev, packet->data,
788 packet->data_size, PCI_DMA_TODEVICE));
789 OHCI_DMA_ALLOC("single, iso transmit packet");
790
791 d->prg_cpu[idx]->end.branchAddress = 0;
792 d->prg_cpu[idx]->end.status = 0;
793 DBGMSG("Iso xmit context info: header[%08x %08x]\n"
794 " begin=%08x %08x %08x %08x\n"
795 " %08x %08x %08x %08x\n"
796 " end =%08x %08x %08x %08x",
797 d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
798 d->prg_cpu[idx]->begin.control,
799 d->prg_cpu[idx]->begin.address,
800 d->prg_cpu[idx]->begin.branchAddress,
801 d->prg_cpu[idx]->begin.status,
802 d->prg_cpu[idx]->data[0],
803 d->prg_cpu[idx]->data[1],
804 d->prg_cpu[idx]->data[2],
805 d->prg_cpu[idx]->data[3],
806 d->prg_cpu[idx]->end.control,
807 d->prg_cpu[idx]->end.address,
808 d->prg_cpu[idx]->end.branchAddress,
809 d->prg_cpu[idx]->end.status);
810 if (d->branchAddrPtr)
811 *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
812 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
813 }
814 d->free_prgs--;
815
816 /* queue the packet in the appropriate context queue */
817 list_add_tail(&packet->driver_list, &d->fifo_list);
818 d->prg_ind = (d->prg_ind + 1) % d->num_desc;
819 }
820
821 /*
822 * This function fills the FIFO with the (eventual) pending packets
823 * and runs or wakes up the DMA prg if necessary.
824 *
825 * The function MUST be called with the d->lock held.
826 */
827 static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
828 {
829 struct hpsb_packet *packet, *ptmp;
830 int idx = d->prg_ind;
831 int z = 0;
832
833 /* insert the packets into the dma fifo */
834 list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) {
835 if (!d->free_prgs)
836 break;
837
838 /* For the first packet only */
839 if (!z)
840 z = (packet->data_size) ? 3 : 2;
841
842 /* Insert the packet */
843 list_del_init(&packet->driver_list);
844 insert_packet(ohci, d, packet);
845 }
846
847 /* Nothing must have been done, either no free_prgs or no packets */
848 if (z == 0)
849 return;
850
851 /* Is the context running ? (should be unless it is
852 the first packet to be sent in this context) */
853 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
854 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
855
856 DBGMSG("Starting transmit DMA ctx=%d",d->ctx);
857 reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
858
859 /* Check that the node id is valid, and not 63 */
860 if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63)
861 PRINT(KERN_ERR, "Running dma failed because Node ID is not valid");
862 else
863 reg_write(ohci, d->ctrlSet, 0x8000);
864 } else {
865 /* Wake up the dma context if necessary */
866 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
867 DBGMSG("Waking transmit DMA ctx=%d",d->ctx);
868
869 /* do this always, to avoid race condition */
870 reg_write(ohci, d->ctrlSet, 0x1000);
871 }
872
873 return;
874 }
875
876 /* Transmission of an async or iso packet */
877 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
878 {
879 struct ti_ohci *ohci = host->hostdata;
880 struct dma_trm_ctx *d;
881 unsigned long flags;
882
883 if (packet->data_size > ohci->max_packet_size) {
884 PRINT(KERN_ERR,
885 "Transmit packet size %Zd is too big",
886 packet->data_size);
887 return -EOVERFLOW;
888 }
889
890 /* Decide whether we have an iso, a request, or a response packet */
891 if (packet->type == hpsb_raw)
892 d = &ohci->at_req_context;
893 else if ((packet->tcode == TCODE_ISO_DATA) && (packet->type == hpsb_iso)) {
894 /* The legacy IT DMA context is initialized on first
895 * use. However, the alloc cannot be run from
896 * interrupt context, so we bail out if that is the
897 * case. I don't see anyone sending ISO packets from
898 * interrupt context anyway... */
899
900 if (ohci->it_legacy_context.ohci == NULL) {
901 if (in_interrupt()) {
902 PRINT(KERN_ERR,
903 "legacy IT context cannot be initialized during interrupt");
904 return -EINVAL;
905 }
906
907 if (alloc_dma_trm_ctx(ohci, &ohci->it_legacy_context,
908 DMA_CTX_ISO, 0, IT_NUM_DESC,
909 OHCI1394_IsoXmitContextBase) < 0) {
910 PRINT(KERN_ERR,
911 "error initializing legacy IT context");
912 return -ENOMEM;
913 }
914
915 initialize_dma_trm_ctx(&ohci->it_legacy_context);
916 }
917
918 d = &ohci->it_legacy_context;
919 } else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA))
920 d = &ohci->at_resp_context;
921 else
922 d = &ohci->at_req_context;
923
924 spin_lock_irqsave(&d->lock,flags);
925
926 list_add_tail(&packet->driver_list, &d->pending_list);
927
928 dma_trm_flush(ohci, d);
929
930 spin_unlock_irqrestore(&d->lock,flags);
931
932 return 0;
933 }
934
935 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
936 {
937 struct ti_ohci *ohci = host->hostdata;
938 int retval = 0;
939 unsigned long flags;
940 int phy_reg;
941
942 switch (cmd) {
943 case RESET_BUS:
944 switch (arg) {
945 case SHORT_RESET:
946 phy_reg = get_phy_reg(ohci, 5);
947 phy_reg |= 0x40;
948 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
949 break;
950 case LONG_RESET:
951 phy_reg = get_phy_reg(ohci, 1);
952 phy_reg |= 0x40;
953 set_phy_reg(ohci, 1, phy_reg); /* set IBR */
954 break;
955 case SHORT_RESET_NO_FORCE_ROOT:
956 phy_reg = get_phy_reg(ohci, 1);
957 if (phy_reg & 0x80) {
958 phy_reg &= ~0x80;
959 set_phy_reg(ohci, 1, phy_reg); /* clear RHB */
960 }
961
962 phy_reg = get_phy_reg(ohci, 5);
963 phy_reg |= 0x40;
964 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
965 break;
966 case LONG_RESET_NO_FORCE_ROOT:
967 phy_reg = get_phy_reg(ohci, 1);
968 phy_reg &= ~0x80;
969 phy_reg |= 0x40;
970 set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */
971 break;
972 case SHORT_RESET_FORCE_ROOT:
973 phy_reg = get_phy_reg(ohci, 1);
974 if (!(phy_reg & 0x80)) {
975 phy_reg |= 0x80;
976 set_phy_reg(ohci, 1, phy_reg); /* set RHB */
977 }
978
979 phy_reg = get_phy_reg(ohci, 5);
980 phy_reg |= 0x40;
981 set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
982 break;
983 case LONG_RESET_FORCE_ROOT:
984 phy_reg = get_phy_reg(ohci, 1);
985 phy_reg |= 0xc0;
986 set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */
987 break;
988 default:
989 retval = -1;
990 }
991 break;
992
993 case GET_CYCLE_COUNTER:
994 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
995 break;
996
997 case SET_CYCLE_COUNTER:
998 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
999 break;
1000
1001 case SET_BUS_ID:
1002 PRINT(KERN_ERR, "devctl command SET_BUS_ID err");
1003 break;
1004
1005 case ACT_CYCLE_MASTER:
1006 if (arg) {
1007 /* check if we are root and other nodes are present */
1008 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
1009 if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
1010 /*
1011 * enable cycleTimer, cycleMaster
1012 */
1013 DBGMSG("Cycle master enabled");
1014 reg_write(ohci, OHCI1394_LinkControlSet,
1015 OHCI1394_LinkControl_CycleTimerEnable |
1016 OHCI1394_LinkControl_CycleMaster);
1017 }
1018 } else {
1019 /* disable cycleTimer, cycleMaster, cycleSource */
1020 reg_write(ohci, OHCI1394_LinkControlClear,
1021 OHCI1394_LinkControl_CycleTimerEnable |
1022 OHCI1394_LinkControl_CycleMaster |
1023 OHCI1394_LinkControl_CycleSource);
1024 }
1025 break;
1026
1027 case CANCEL_REQUESTS:
1028 DBGMSG("Cancel request received");
1029 dma_trm_reset(&ohci->at_req_context);
1030 dma_trm_reset(&ohci->at_resp_context);
1031 break;
1032
1033 case ISO_LISTEN_CHANNEL:
1034 {
1035 u64 mask;
1036 struct dma_rcv_ctx *d = &ohci->ir_legacy_context;
1037 int ir_legacy_active;
1038
1039 if (arg<0 || arg>63) {
1040 PRINT(KERN_ERR,
1041 "%s: IS0 listen channel %d is out of range",
1042 __FUNCTION__, arg);
1043 return -EFAULT;
1044 }
1045
1046 mask = (u64)0x1<<arg;
1047
1048 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1049
1050 if (ohci->ISO_channel_usage & mask) {
1051 PRINT(KERN_ERR,
1052 "%s: IS0 listen channel %d is already used",
1053 __FUNCTION__, arg);
1054 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1055 return -EFAULT;
1056 }
1057
1058 ir_legacy_active = ohci->ir_legacy_channels;
1059
1060 ohci->ISO_channel_usage |= mask;
1061 ohci->ir_legacy_channels |= mask;
1062
1063 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1064
1065 if (!ir_legacy_active) {
1066 if (ohci1394_register_iso_tasklet(ohci,
1067 &ohci->ir_legacy_tasklet) < 0) {
1068 PRINT(KERN_ERR, "No IR DMA context available");
1069 return -EBUSY;
1070 }
1071
1072 /* the IR context can be assigned to any DMA context
1073 * by ohci1394_register_iso_tasklet */
1074 d->ctx = ohci->ir_legacy_tasklet.context;
1075 d->ctrlSet = OHCI1394_IsoRcvContextControlSet +
1076 32*d->ctx;
1077 d->ctrlClear = OHCI1394_IsoRcvContextControlClear +
1078 32*d->ctx;
1079 d->cmdPtr = OHCI1394_IsoRcvCommandPtr + 32*d->ctx;
1080 d->ctxtMatch = OHCI1394_IsoRcvContextMatch + 32*d->ctx;
1081
1082 initialize_dma_rcv_ctx(&ohci->ir_legacy_context, 1);
1083
1084 if (printk_ratelimit())
1085 DBGMSG("IR legacy activated");
1086 }
1087
1088 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1089
1090 if (arg>31)
1091 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet,
1092 1<<(arg-32));
1093 else
1094 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet,
1095 1<<arg);
1096
1097 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1098 DBGMSG("Listening enabled on channel %d", arg);
1099 break;
1100 }
1101 case ISO_UNLISTEN_CHANNEL:
1102 {
1103 u64 mask;
1104
1105 if (arg<0 || arg>63) {
1106 PRINT(KERN_ERR,
1107 "%s: IS0 unlisten channel %d is out of range",
1108 __FUNCTION__, arg);
1109 return -EFAULT;
1110 }
1111
1112 mask = (u64)0x1<<arg;
1113
1114 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
1115
1116 if (!(ohci->ISO_channel_usage & mask)) {
1117 PRINT(KERN_ERR,
1118 "%s: IS0 unlisten channel %d is not used",
1119 __FUNCTION__, arg);
1120 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1121 return -EFAULT;
1122 }
1123
1124 ohci->ISO_channel_usage &= ~mask;
1125 ohci->ir_legacy_channels &= ~mask;
1126
1127 if (arg>31)
1128 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear,
1129 1<<(arg-32));
1130 else
1131 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear,
1132 1<<arg);
1133
1134 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1135 DBGMSG("Listening disabled on channel %d", arg);
1136
1137 if (ohci->ir_legacy_channels == 0) {
1138 stop_dma_rcv_ctx(&ohci->ir_legacy_context);
1139 DBGMSG("ISO legacy receive context stopped");
1140 }
1141
1142 break;
1143 }
1144 default:
1145 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
1146 cmd);
1147 break;
1148 }
1149 return retval;
1150 }
1151
1152 /***********************************
1153 * rawiso ISO reception *
1154 ***********************************/
1155
1156 /*
1157 We use either buffer-fill or packet-per-buffer DMA mode. The DMA
1158 buffer is split into "blocks" (regions described by one DMA
1159 descriptor). Each block must be one page or less in size, and
1160 must not cross a page boundary.
1161
1162 There is one little wrinkle with buffer-fill mode: a packet that
1163 starts in the final block may wrap around into the first block. But
1164 the user API expects all packets to be contiguous. Our solution is
1165 to keep the very last page of the DMA buffer in reserve - if a
1166 packet spans the gap, we copy its tail into this page.
1167 */
1168
1169 struct ohci_iso_recv {
1170 struct ti_ohci *ohci;
1171
1172 struct ohci1394_iso_tasklet task;
1173 int task_active;
1174
1175 enum { BUFFER_FILL_MODE = 0,
1176 PACKET_PER_BUFFER_MODE = 1 } dma_mode;
1177
1178 /* memory and PCI mapping for the DMA descriptors */
1179 struct dma_prog_region prog;
1180 struct dma_cmd *block; /* = (struct dma_cmd*) prog.virt */
1181
1182 /* how many DMA blocks fit in the buffer */
1183 unsigned int nblocks;
1184
1185 /* stride of DMA blocks */
1186 unsigned int buf_stride;
1187
1188 /* number of blocks to batch between interrupts */
1189 int block_irq_interval;
1190
1191 /* block that DMA will finish next */
1192 int block_dma;
1193
1194 /* (buffer-fill only) block that the reader will release next */
1195 int block_reader;
1196
1197 /* (buffer-fill only) bytes of buffer the reader has released,
1198 less than one block */
1199 int released_bytes;
1200
1201 /* (buffer-fill only) buffer offset at which the next packet will appear */
1202 int dma_offset;
1203
1204 /* OHCI DMA context control registers */
1205 u32 ContextControlSet;
1206 u32 ContextControlClear;
1207 u32 CommandPtr;
1208 u32 ContextMatch;
1209 };
1210
1211 static void ohci_iso_recv_task(unsigned long data);
1212 static void ohci_iso_recv_stop(struct hpsb_iso *iso);
1213 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso);
1214 static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync);
1215 static void ohci_iso_recv_program(struct hpsb_iso *iso);
1216
1217 static int ohci_iso_recv_init(struct hpsb_iso *iso)
1218 {
1219 struct ti_ohci *ohci = iso->host->hostdata;
1220 struct ohci_iso_recv *recv;
1221 int ctx;
1222 int ret = -ENOMEM;
1223
1224 recv = kmalloc(sizeof(*recv), SLAB_KERNEL);
1225 if (!recv)
1226 return -ENOMEM;
1227
1228 iso->hostdata = recv;
1229 recv->ohci = ohci;
1230 recv->task_active = 0;
1231 dma_prog_region_init(&recv->prog);
1232 recv->block = NULL;
1233
1234 /* use buffer-fill mode, unless irq_interval is 1
1235 (note: multichannel requires buffer-fill) */
1236
1237 if (((iso->irq_interval == 1 && iso->dma_mode == HPSB_ISO_DMA_OLD_ABI) ||
1238 iso->dma_mode == HPSB_ISO_DMA_PACKET_PER_BUFFER) && iso->channel != -1) {
1239 recv->dma_mode = PACKET_PER_BUFFER_MODE;
1240 } else {
1241 recv->dma_mode = BUFFER_FILL_MODE;
1242 }
1243
1244 /* set nblocks, buf_stride, block_irq_interval */
1245
1246 if (recv->dma_mode == BUFFER_FILL_MODE) {
1247 recv->buf_stride = PAGE_SIZE;
1248
1249 /* one block per page of data in the DMA buffer, minus the final guard page */
1250 recv->nblocks = iso->buf_size/PAGE_SIZE - 1;
1251 if (recv->nblocks < 3) {
1252 DBGMSG("ohci_iso_recv_init: DMA buffer too small");
1253 goto err;
1254 }
1255
1256 /* iso->irq_interval is in packets - translate that to blocks */
1257 if (iso->irq_interval == 1)
1258 recv->block_irq_interval = 1;
1259 else
1260 recv->block_irq_interval = iso->irq_interval *
1261 ((recv->nblocks+1)/iso->buf_packets);
1262 if (recv->block_irq_interval*4 > recv->nblocks)
1263 recv->block_irq_interval = recv->nblocks/4;
1264 if (recv->block_irq_interval < 1)
1265 recv->block_irq_interval = 1;
1266
1267 } else {
1268 int max_packet_size;
1269
1270 recv->nblocks = iso->buf_packets;
1271 recv->block_irq_interval = iso->irq_interval;
1272 if (recv->block_irq_interval * 4 > iso->buf_packets)
1273 recv->block_irq_interval = iso->buf_packets / 4;
1274 if (recv->block_irq_interval < 1)
1275 recv->block_irq_interval = 1;
1276
1277 /* choose a buffer stride */
1278 /* must be a power of 2, and <= PAGE_SIZE */
1279
1280 max_packet_size = iso->buf_size / iso->buf_packets;
1281
1282 for (recv->buf_stride = 8; recv->buf_stride < max_packet_size;
1283 recv->buf_stride *= 2);
1284
1285 if (recv->buf_stride*iso->buf_packets > iso->buf_size ||
1286 recv->buf_stride > PAGE_SIZE) {
1287 /* this shouldn't happen, but anyway... */
1288 DBGMSG("ohci_iso_recv_init: problem choosing a buffer stride");
1289 goto err;
1290 }
1291 }
1292
1293 recv->block_reader = 0;
1294 recv->released_bytes = 0;
1295 recv->block_dma = 0;
1296 recv->dma_offset = 0;
1297
1298 /* size of DMA program = one descriptor per block */
1299 if (dma_prog_region_alloc(&recv->prog,
1300 sizeof(struct dma_cmd) * recv->nblocks,
1301 recv->ohci->dev))
1302 goto err;
1303
1304 recv->block = (struct dma_cmd*) recv->prog.kvirt;
1305
1306 ohci1394_init_iso_tasklet(&recv->task,
1307 iso->channel == -1 ? OHCI_ISO_MULTICHANNEL_RECEIVE :
1308 OHCI_ISO_RECEIVE,
1309 ohci_iso_recv_task, (unsigned long) iso);
1310
1311 if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) {
1312 ret = -EBUSY;
1313 goto err;
1314 }
1315
1316 recv->task_active = 1;
1317
1318 /* recv context registers are spaced 32 bytes apart */
1319 ctx = recv->task.context;
1320 recv->ContextControlSet = OHCI1394_IsoRcvContextControlSet + 32 * ctx;
1321 recv->ContextControlClear = OHCI1394_IsoRcvContextControlClear + 32 * ctx;
1322 recv->CommandPtr = OHCI1394_IsoRcvCommandPtr + 32 * ctx;
1323 recv->ContextMatch = OHCI1394_IsoRcvContextMatch + 32 * ctx;
1324
1325 if (iso->channel == -1) {
1326 /* clear multi-channel selection mask */
1327 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF);
1328 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF);
1329 }
1330
1331 /* write the DMA program */
1332 ohci_iso_recv_program(iso);
1333
1334 DBGMSG("ohci_iso_recv_init: %s mode, DMA buffer is %lu pages"
1335 " (%u bytes), using %u blocks, buf_stride %u, block_irq_interval %d",
1336 recv->dma_mode == BUFFER_FILL_MODE ?
1337 "buffer-fill" : "packet-per-buffer",
1338 iso->buf_size/PAGE_SIZE, iso->buf_size,
1339 recv->nblocks, recv->buf_stride, recv->block_irq_interval);
1340
1341 return 0;
1342
1343 err:
1344 ohci_iso_recv_shutdown(iso);
1345 return ret;
1346 }
1347
1348 static void ohci_iso_recv_stop(struct hpsb_iso *iso)
1349 {
1350 struct ohci_iso_recv *recv = iso->hostdata;
1351
1352 /* disable interrupts */
1353 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context);
1354
1355 /* halt DMA */
1356 ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL);
1357 }
1358
1359 static void ohci_iso_recv_shutdown(struct hpsb_iso *iso)
1360 {
1361 struct ohci_iso_recv *recv = iso->hostdata;
1362
1363 if (recv->task_active) {
1364 ohci_iso_recv_stop(iso);
1365 ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task);
1366 recv->task_active = 0;
1367 }
1368
1369 dma_prog_region_free(&recv->prog);
1370 kfree(recv);
1371 iso->hostdata = NULL;
1372 }
1373
1374 /* set up a "gapped" ring buffer DMA program */
1375 static void ohci_iso_recv_program(struct hpsb_iso *iso)
1376 {
1377 struct ohci_iso_recv *recv = iso->hostdata;
1378 int blk;
1379
1380 /* address of 'branch' field in previous DMA descriptor */
1381 u32 *prev_branch = NULL;
1382
1383 for (blk = 0; blk < recv->nblocks; blk++) {
1384 u32 control;
1385
1386 /* the DMA descriptor */
1387 struct dma_cmd *cmd = &recv->block[blk];
1388
1389 /* offset of the DMA descriptor relative to the DMA prog buffer */
1390 unsigned long prog_offset = blk * sizeof(struct dma_cmd);
1391
1392 /* offset of this packet's data within the DMA buffer */
1393 unsigned long buf_offset = blk * recv->buf_stride;
1394
1395 if (recv->dma_mode == BUFFER_FILL_MODE) {
1396 control = 2 << 28; /* INPUT_MORE */
1397 } else {
1398 control = 3 << 28; /* INPUT_LAST */
1399 }
1400
1401 control |= 8 << 24; /* s = 1, update xferStatus and resCount */
1402
1403 /* interrupt on last block, and at intervals */
1404 if (blk == recv->nblocks-1 || (blk % recv->block_irq_interval) == 0) {
1405 control |= 3 << 20; /* want interrupt */
1406 }
1407
1408 control |= 3 << 18; /* enable branch to address */
1409 control |= recv->buf_stride;
1410
1411 cmd->control = cpu_to_le32(control);
1412 cmd->address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, buf_offset));
1413 cmd->branchAddress = 0; /* filled in on next loop */
1414 cmd->status = cpu_to_le32(recv->buf_stride);
1415
1416 /* link the previous descriptor to this one */
1417 if (prev_branch) {
1418 *prev_branch = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, prog_offset) | 1);
1419 }
1420
1421 prev_branch = &cmd->branchAddress;
1422 }
1423
1424 /* the final descriptor's branch address and Z should be left at 0 */
1425 }
1426
1427 /* listen or unlisten to a specific channel (multi-channel mode only) */
1428 static void ohci_iso_recv_change_channel(struct hpsb_iso *iso, unsigned char channel, int listen)
1429 {
1430 struct ohci_iso_recv *recv = iso->hostdata;
1431 int reg, i;
1432
1433 if (channel < 32) {
1434 reg = listen ? OHCI1394_IRMultiChanMaskLoSet : OHCI1394_IRMultiChanMaskLoClear;
1435 i = channel;
1436 } else {
1437 reg = listen ? OHCI1394_IRMultiChanMaskHiSet : OHCI1394_IRMultiChanMaskHiClear;
1438 i = channel - 32;
1439 }
1440
1441 reg_write(recv->ohci, reg, (1 << i));
1442
1443 /* issue a dummy read to force all PCI writes to be posted immediately */
1444 mb();
1445 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1446 }
1447
1448 static void ohci_iso_recv_set_channel_mask(struct hpsb_iso *iso, u64 mask)
1449 {
1450 struct ohci_iso_recv *recv = iso->hostdata;
1451 int i;
1452
1453 for (i = 0; i < 64; i++) {
1454 if (mask & (1ULL << i)) {
1455 if (i < 32)
1456 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i));
1457 else
1458 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32)));
1459 } else {
1460 if (i < 32)
1461 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i));
1462 else
1463 reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32)));
1464 }
1465 }
1466
1467 /* issue a dummy read to force all PCI writes to be posted immediately */
1468 mb();
1469 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1470 }
1471
1472 static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync)
1473 {
1474 struct ohci_iso_recv *recv = iso->hostdata;
1475 struct ti_ohci *ohci = recv->ohci;
1476 u32 command, contextMatch;
1477
1478 reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF);
1479 wmb();
1480
1481 /* always keep ISO headers */
1482 command = (1 << 30);
1483
1484 if (recv->dma_mode == BUFFER_FILL_MODE)
1485 command |= (1 << 31);
1486
1487 reg_write(recv->ohci, recv->ContextControlSet, command);
1488
1489 /* match on specified tags */
1490 contextMatch = tag_mask << 28;
1491
1492 if (iso->channel == -1) {
1493 /* enable multichannel reception */
1494 reg_write(recv->ohci, recv->ContextControlSet, (1 << 28));
1495 } else {
1496 /* listen on channel */
1497 contextMatch |= iso->channel;
1498 }
1499
1500 if (cycle != -1) {
1501 u32 seconds;
1502
1503 /* enable cycleMatch */
1504 reg_write(recv->ohci, recv->ContextControlSet, (1 << 29));
1505
1506 /* set starting cycle */
1507 cycle &= 0x1FFF;
1508
1509 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
1510 just snarf them from the current time */
1511 seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
1512
1513 /* advance one second to give some extra time for DMA to start */
1514 seconds += 1;
1515
1516 cycle |= (seconds & 3) << 13;
1517
1518 contextMatch |= cycle << 12;
1519 }
1520
1521 if (sync != -1) {
1522 /* set sync flag on first DMA descriptor */
1523 struct dma_cmd *cmd = &recv->block[recv->block_dma];
1524 cmd->control |= cpu_to_le32(DMA_CTL_WAIT);
1525
1526 /* match sync field */
1527 contextMatch |= (sync&0xf)<<8;
1528 }
1529
1530 reg_write(recv->ohci, recv->ContextMatch, contextMatch);
1531
1532 /* address of first descriptor block */
1533 command = dma_prog_region_offset_to_bus(&recv->prog,
1534 recv->block_dma * sizeof(struct dma_cmd));
1535 command |= 1; /* Z=1 */
1536
1537 reg_write(recv->ohci, recv->CommandPtr, command);
1538
1539 /* enable interrupts */
1540 reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context);
1541
1542 wmb();
1543
1544 /* run */
1545 reg_write(recv->ohci, recv->ContextControlSet, 0x8000);
1546
1547 /* issue a dummy read of the cycle timer register to force
1548 all PCI writes to be posted immediately */
1549 mb();
1550 reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer);
1551
1552 /* check RUN */
1553 if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) {
1554 PRINT(KERN_ERR,
1555 "Error starting IR DMA (ContextControl 0x%08x)\n",
1556 reg_read(recv->ohci, recv->ContextControlSet));
1557 return -1;
1558 }
1559
1560 return 0;
1561 }
1562
1563 static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block)
1564 {
1565 /* re-use the DMA descriptor for the block */
1566 /* by linking the previous descriptor to it */
1567
1568 int next_i = block;
1569 int prev_i = (next_i == 0) ? (recv->nblocks - 1) : (next_i - 1);
1570
1571 struct dma_cmd *next = &recv->block[next_i];
1572 struct dma_cmd *prev = &recv->block[prev_i];
1573
1574 /* ignore out-of-range requests */
1575 if ((block < 0) || (block > recv->nblocks))
1576 return;
1577
1578 /* 'next' becomes the new end of the DMA chain,
1579 so disable branch and enable interrupt */
1580 next->branchAddress = 0;
1581 next->control |= cpu_to_le32(3 << 20);
1582 next->status = cpu_to_le32(recv->buf_stride);
1583
1584 /* link prev to next */
1585 prev->branchAddress = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog,
1586 sizeof(struct dma_cmd) * next_i)
1587 | 1); /* Z=1 */
1588
1589 /* disable interrupt on previous DMA descriptor, except at intervals */
1590 if ((prev_i % recv->block_irq_interval) == 0) {
1591 prev->control |= cpu_to_le32(3 << 20); /* enable interrupt */
1592 } else {
1593 prev->control &= cpu_to_le32(~(3<<20)); /* disable interrupt */
1594 }
1595 wmb();
1596
1597 /* wake up DMA in case it fell asleep */
1598 reg_write(recv->ohci, recv->ContextControlSet, (1 << 12));
1599 }
1600
1601 static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv,
1602 struct hpsb_iso_packet_info *info)
1603 {
1604 /* release the memory where the packet was */
1605 recv->released_bytes += info->total_len;
1606
1607 /* have we released enough memory for one block? */
1608 while (recv->released_bytes > recv->buf_stride) {
1609 ohci_iso_recv_release_block(recv, recv->block_reader);
1610 recv->block_reader = (recv->block_reader + 1) % recv->nblocks;
1611 recv->released_bytes -= recv->buf_stride;
1612 }
1613 }
1614
1615 static inline void ohci_iso_recv_release(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
1616 {
1617 struct ohci_iso_recv *recv = iso->hostdata;
1618 if (recv->dma_mode == BUFFER_FILL_MODE) {
1619 ohci_iso_recv_bufferfill_release(recv, info);
1620 } else {
1621 ohci_iso_recv_release_block(recv, info - iso->infos);
1622 }
1623 }
1624
1625 /* parse all packets from blocks that have been fully received */
1626 static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1627 {
1628 int wake = 0;
1629 int runaway = 0;
1630 struct ti_ohci *ohci = recv->ohci;
1631
1632 while (1) {
1633 /* we expect the next parsable packet to begin at recv->dma_offset */
1634 /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */
1635
1636 unsigned int offset;
1637 unsigned short len, cycle, total_len;
1638 unsigned char channel, tag, sy;
1639
1640 unsigned char *p = iso->data_buf.kvirt;
1641
1642 unsigned int this_block = recv->dma_offset/recv->buf_stride;
1643
1644 /* don't loop indefinitely */
1645 if (runaway++ > 100000) {
1646 atomic_inc(&iso->overflows);
1647 PRINT(KERN_ERR,
1648 "IR DMA error - Runaway during buffer parsing!\n");
1649 break;
1650 }
1651
1652 /* stop parsing once we arrive at block_dma (i.e. don't get ahead of DMA) */
1653 if (this_block == recv->block_dma)
1654 break;
1655
1656 wake = 1;
1657
1658 /* parse data length, tag, channel, and sy */
1659
1660 /* note: we keep our own local copies of 'len' and 'offset'
1661 so the user can't mess with them by poking in the mmap area */
1662
1663 len = p[recv->dma_offset+2] | (p[recv->dma_offset+3] << 8);
1664
1665 if (len > 4096) {
1666 PRINT(KERN_ERR,
1667 "IR DMA error - bogus 'len' value %u\n", len);
1668 }
1669
1670 channel = p[recv->dma_offset+1] & 0x3F;
1671 tag = p[recv->dma_offset+1] >> 6;
1672 sy = p[recv->dma_offset+0] & 0xF;
1673
1674 /* advance to data payload */
1675 recv->dma_offset += 4;
1676
1677 /* check for wrap-around */
1678 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1679 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1680 }
1681
1682 /* dma_offset now points to the first byte of the data payload */
1683 offset = recv->dma_offset;
1684
1685 /* advance to xferStatus/timeStamp */
1686 recv->dma_offset += len;
1687
1688 total_len = len + 8; /* 8 bytes header+trailer in OHCI packet */
1689 /* payload is padded to 4 bytes */
1690 if (len % 4) {
1691 recv->dma_offset += 4 - (len%4);
1692 total_len += 4 - (len%4);
1693 }
1694
1695 /* check for wrap-around */
1696 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1697 /* uh oh, the packet data wraps from the last
1698 to the first DMA block - make the packet
1699 contiguous by copying its "tail" into the
1700 guard page */
1701
1702 int guard_off = recv->buf_stride*recv->nblocks;
1703 int tail_len = len - (guard_off - offset);
1704
1705 if (tail_len > 0 && tail_len < recv->buf_stride) {
1706 memcpy(iso->data_buf.kvirt + guard_off,
1707 iso->data_buf.kvirt,
1708 tail_len);
1709 }
1710
1711 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1712 }
1713
1714 /* parse timestamp */
1715 cycle = p[recv->dma_offset+0] | (p[recv->dma_offset+1]<<8);
1716 cycle &= 0x1FFF;
1717
1718 /* advance to next packet */
1719 recv->dma_offset += 4;
1720
1721 /* check for wrap-around */
1722 if (recv->dma_offset >= recv->buf_stride*recv->nblocks) {
1723 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1724 }
1725
1726 hpsb_iso_packet_received(iso, offset, len, total_len, cycle, channel, tag, sy);
1727 }
1728
1729 if (wake)
1730 hpsb_iso_wake(iso);
1731 }
1732
1733 static void ohci_iso_recv_bufferfill_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1734 {
1735 int loop;
1736 struct ti_ohci *ohci = recv->ohci;
1737
1738 /* loop over all blocks */
1739 for (loop = 0; loop < recv->nblocks; loop++) {
1740
1741 /* check block_dma to see if it's done */
1742 struct dma_cmd *im = &recv->block[recv->block_dma];
1743
1744 /* check the DMA descriptor for new writes to xferStatus */
1745 u16 xferstatus = le32_to_cpu(im->status) >> 16;
1746
1747 /* rescount is the number of bytes *remaining to be written* in the block */
1748 u16 rescount = le32_to_cpu(im->status) & 0xFFFF;
1749
1750 unsigned char event = xferstatus & 0x1F;
1751
1752 if (!event) {
1753 /* nothing has happened to this block yet */
1754 break;
1755 }
1756
1757 if (event != 0x11) {
1758 atomic_inc(&iso->overflows);
1759 PRINT(KERN_ERR,
1760 "IR DMA error - OHCI error code 0x%02x\n", event);
1761 }
1762
1763 if (rescount != 0) {
1764 /* the card is still writing to this block;
1765 we can't touch it until it's done */
1766 break;
1767 }
1768
1769 /* OK, the block is finished... */
1770
1771 /* sync our view of the block */
1772 dma_region_sync_for_cpu(&iso->data_buf, recv->block_dma*recv->buf_stride, recv->buf_stride);
1773
1774 /* reset the DMA descriptor */
1775 im->status = recv->buf_stride;
1776
1777 /* advance block_dma */
1778 recv->block_dma = (recv->block_dma + 1) % recv->nblocks;
1779
1780 if ((recv->block_dma+1) % recv->nblocks == recv->block_reader) {
1781 atomic_inc(&iso->overflows);
1782 DBGMSG("ISO reception overflow - "
1783 "ran out of DMA blocks");
1784 }
1785 }
1786
1787 /* parse any packets that have arrived */
1788 ohci_iso_recv_bufferfill_parse(iso, recv);
1789 }
1790
1791 static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv)
1792 {
1793 int count;
1794 int wake = 0;
1795 struct ti_ohci *ohci = recv->ohci;
1796
1797 /* loop over the entire buffer */
1798 for (count = 0; count < recv->nblocks; count++) {
1799 u32 packet_len = 0;
1800
1801 /* pointer to the DMA descriptor */
1802 struct dma_cmd *il = ((struct dma_cmd*) recv->prog.kvirt) + iso->pkt_dma;
1803
1804 /* check the DMA descriptor for new writes to xferStatus */
1805 u16 xferstatus = le32_to_cpu(il->status) >> 16;
1806 u16 rescount = le32_to_cpu(il->status) & 0xFFFF;
1807
1808 unsigned char event = xferstatus & 0x1F;
1809
1810 if (!event) {
1811 /* this packet hasn't come in yet; we are done for now */
1812 goto out;
1813 }
1814
1815 if (event == 0x11) {
1816 /* packet received successfully! */
1817
1818 /* rescount is the number of bytes *remaining* in the packet buffer,
1819 after the packet was written */
1820 packet_len = recv->buf_stride - rescount;
1821
1822 } else if (event == 0x02) {
1823 PRINT(KERN_ERR, "IR DMA error - packet too long for buffer\n");
1824 } else if (event) {
1825 PRINT(KERN_ERR, "IR DMA error - OHCI error code 0x%02x\n", event);
1826 }
1827
1828 /* sync our view of the buffer */
1829 dma_region_sync_for_cpu(&iso->data_buf, iso->pkt_dma * recv->buf_stride, recv->buf_stride);
1830
1831 /* record the per-packet info */
1832 {
1833 /* iso header is 8 bytes ahead of the data payload */
1834 unsigned char *hdr;
1835
1836 unsigned int offset;
1837 unsigned short cycle;
1838 unsigned char channel, tag, sy;
1839
1840 offset = iso->pkt_dma * recv->buf_stride;
1841 hdr = iso->data_buf.kvirt + offset;
1842
1843 /* skip iso header */
1844 offset += 8;
1845 packet_len -= 8;
1846
1847 cycle = (hdr[0] | (hdr[1] << 8)) & 0x1FFF;
1848 channel = hdr[5] & 0x3F;
1849 tag = hdr[5] >> 6;
1850 sy = hdr[4] & 0xF;
1851
1852 hpsb_iso_packet_received(iso, offset, packet_len,
1853 recv->buf_stride, cycle, channel, tag, sy);
1854 }
1855
1856 /* reset the DMA descriptor */
1857 il->status = recv->buf_stride;
1858
1859 wake = 1;
1860 recv->block_dma = iso->pkt_dma;
1861 }
1862
1863 out:
1864 if (wake)
1865 hpsb_iso_wake(iso);
1866 }
1867
1868 static void ohci_iso_recv_task(unsigned long data)
1869 {
1870 struct hpsb_iso *iso = (struct hpsb_iso*) data;
1871 struct ohci_iso_recv *recv = iso->hostdata;
1872
1873 if (recv->dma_mode == BUFFER_FILL_MODE)
1874 ohci_iso_recv_bufferfill_task(iso, recv);
1875 else
1876 ohci_iso_recv_packetperbuf_task(iso, recv);
1877 }
1878
1879 /***********************************
1880 * rawiso ISO transmission *
1881 ***********************************/
1882
1883 struct ohci_iso_xmit {
1884 struct ti_ohci *ohci;
1885 struct dma_prog_region prog;
1886 struct ohci1394_iso_tasklet task;
1887 int task_active;
1888
1889 u32 ContextControlSet;
1890 u32 ContextControlClear;
1891 u32 CommandPtr;
1892 };
1893
1894 /* transmission DMA program:
1895 one OUTPUT_MORE_IMMEDIATE for the IT header
1896 one OUTPUT_LAST for the buffer data */
1897
1898 struct iso_xmit_cmd {
1899 struct dma_cmd output_more_immediate;
1900 u8 iso_hdr[8];
1901 u32 unused[2];
1902 struct dma_cmd output_last;
1903 };
1904
1905 static int ohci_iso_xmit_init(struct hpsb_iso *iso);
1906 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle);
1907 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso);
1908 static void ohci_iso_xmit_task(unsigned long data);
1909
1910 static int ohci_iso_xmit_init(struct hpsb_iso *iso)
1911 {
1912 struct ohci_iso_xmit *xmit;
1913 unsigned int prog_size;
1914 int ctx;
1915 int ret = -ENOMEM;
1916
1917 xmit = kmalloc(sizeof(*xmit), SLAB_KERNEL);
1918 if (!xmit)
1919 return -ENOMEM;
1920
1921 iso->hostdata = xmit;
1922 xmit->ohci = iso->host->hostdata;
1923 xmit->task_active = 0;
1924
1925 dma_prog_region_init(&xmit->prog);
1926
1927 prog_size = sizeof(struct iso_xmit_cmd) * iso->buf_packets;
1928
1929 if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev))
1930 goto err;
1931
1932 ohci1394_init_iso_tasklet(&xmit->task, OHCI_ISO_TRANSMIT,
1933 ohci_iso_xmit_task, (unsigned long) iso);
1934
1935 if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) {
1936 ret = -EBUSY;
1937 goto err;
1938 }
1939
1940 xmit->task_active = 1;
1941
1942 /* xmit context registers are spaced 16 bytes apart */
1943 ctx = xmit->task.context;
1944 xmit->ContextControlSet = OHCI1394_IsoXmitContextControlSet + 16 * ctx;
1945 xmit->ContextControlClear = OHCI1394_IsoXmitContextControlClear + 16 * ctx;
1946 xmit->CommandPtr = OHCI1394_IsoXmitCommandPtr + 16 * ctx;
1947
1948 return 0;
1949
1950 err:
1951 ohci_iso_xmit_shutdown(iso);
1952 return ret;
1953 }
1954
1955 static void ohci_iso_xmit_stop(struct hpsb_iso *iso)
1956 {
1957 struct ohci_iso_xmit *xmit = iso->hostdata;
1958 struct ti_ohci *ohci = xmit->ohci;
1959
1960 /* disable interrupts */
1961 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context);
1962
1963 /* halt DMA */
1964 if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) {
1965 /* XXX the DMA context will lock up if you try to send too much data! */
1966 PRINT(KERN_ERR,
1967 "you probably exceeded the OHCI card's bandwidth limit - "
1968 "reload the module and reduce xmit bandwidth");
1969 }
1970 }
1971
1972 static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso)
1973 {
1974 struct ohci_iso_xmit *xmit = iso->hostdata;
1975
1976 if (xmit->task_active) {
1977 ohci_iso_xmit_stop(iso);
1978 ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task);
1979 xmit->task_active = 0;
1980 }
1981
1982 dma_prog_region_free(&xmit->prog);
1983 kfree(xmit);
1984 iso->hostdata = NULL;
1985 }
1986
1987 static void ohci_iso_xmit_task(unsigned long data)
1988 {
1989 struct hpsb_iso *iso = (struct hpsb_iso*) data;
1990 struct ohci_iso_xmit *xmit = iso->hostdata;
1991 struct ti_ohci *ohci = xmit->ohci;
1992 int wake = 0;
1993 int count;
1994
1995 /* check the whole buffer if necessary, starting at pkt_dma */
1996 for (count = 0; count < iso->buf_packets; count++) {
1997 int cycle;
1998
1999 /* DMA descriptor */
2000 struct iso_xmit_cmd *cmd = dma_region_i(&xmit->prog, struct iso_xmit_cmd, iso->pkt_dma);
2001
2002 /* check for new writes to xferStatus */
2003 u16 xferstatus = le32_to_cpu(cmd->output_last.status) >> 16;
2004 u8 event = xferstatus & 0x1F;
2005
2006 if (!event) {
2007 /* packet hasn't been sent yet; we are done for now */
2008 break;
2009 }
2010
2011 if (event != 0x11)
2012 PRINT(KERN_ERR,
2013 "IT DMA error - OHCI error code 0x%02x\n", event);
2014
2015 /* at least one packet went out, so wake up the writer */
2016 wake = 1;
2017
2018 /* parse cycle */
2019 cycle = le32_to_cpu(cmd->output_last.status) & 0x1FFF;
2020
2021 /* tell the subsystem the packet has gone out */
2022 hpsb_iso_packet_sent(iso, cycle, event != 0x11);
2023
2024 /* reset the DMA descriptor for next time */
2025 cmd->output_last.status = 0;
2026 }
2027
2028 if (wake)
2029 hpsb_iso_wake(iso);
2030 }
2031
2032 static int ohci_iso_xmit_queue(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info)
2033 {
2034 struct ohci_iso_xmit *xmit = iso->hostdata;
2035 struct ti_ohci *ohci = xmit->ohci;
2036
2037 int next_i, prev_i;
2038 struct iso_xmit_cmd *next, *prev;
2039
2040 unsigned int offset;
2041 unsigned short len;
2042 unsigned char tag, sy;
2043
2044 /* check that the packet doesn't cross a page boundary
2045 (we could allow this if we added OUTPUT_MORE descriptor support) */
2046 if (cross_bound(info->offset, info->len)) {
2047 PRINT(KERN_ERR,
2048 "rawiso xmit: packet %u crosses a page boundary",
2049 iso->first_packet);
2050 return -EINVAL;
2051 }
2052
2053 offset = info->offset;
2054 len = info->len;
2055 tag = info->tag;
2056 sy = info->sy;
2057
2058 /* sync up the card's view of the buffer */
2059 dma_region_sync_for_device(&iso->data_buf, offset, len);
2060
2061 /* append first_packet to the DMA chain */
2062 /* by linking the previous descriptor to it */
2063 /* (next will become the new end of the DMA chain) */
2064
2065 next_i = iso->first_packet;
2066 prev_i = (next_i == 0) ? (iso->buf_packets - 1) : (next_i - 1);
2067
2068 next = dma_region_i(&xmit->prog, struct iso_xmit_cmd, next_i);
2069 prev = dma_region_i(&xmit->prog, struct iso_xmit_cmd, prev_i);
2070
2071 /* set up the OUTPUT_MORE_IMMEDIATE descriptor */
2072 memset(next, 0, sizeof(struct iso_xmit_cmd));
2073 next->output_more_immediate.control = cpu_to_le32(0x02000008);
2074
2075 /* ISO packet header is embedded in the OUTPUT_MORE_IMMEDIATE */
2076
2077 /* tcode = 0xA, and sy */
2078 next->iso_hdr[0] = 0xA0 | (sy & 0xF);
2079
2080 /* tag and channel number */
2081 next->iso_hdr[1] = (tag << 6) | (iso->channel & 0x3F);
2082
2083 /* transmission speed */
2084 next->iso_hdr[2] = iso->speed & 0x7;
2085
2086 /* payload size */
2087 next->iso_hdr[6] = len & 0xFF;
2088 next->iso_hdr[7] = len >> 8;
2089
2090 /* set up the OUTPUT_LAST */
2091 next->output_last.control = cpu_to_le32(1 << 28);
2092 next->output_last.control |= cpu_to_le32(1 << 27); /* update timeStamp */
2093 next->output_last.control |= cpu_to_le32(3 << 20); /* want interrupt */
2094 next->output_last.control |= cpu_to_le32(3 << 18); /* enable branch */
2095 next->output_last.control |= cpu_to_le32(len);
2096
2097 /* payload bus address */
2098 next->output_last.address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, offset));
2099
2100 /* leave branchAddress at zero for now */
2101
2102 /* re-write the previous DMA descriptor to chain to this one */
2103
2104 /* set prev branch address to point to next (Z=3) */
2105 prev->output_last.branchAddress = cpu_to_le32(
2106 dma_prog_region_offset_to_bus(&xmit->prog, sizeof(struct iso_xmit_cmd) * next_i) | 3);
2107
2108 /* disable interrupt, unless required by the IRQ interval */
2109 if (prev_i % iso->irq_interval) {
2110 prev->output_last.control &= cpu_to_le32(~(3 << 20)); /* no interrupt */
2111 } else {
2112 prev->output_last.control |= cpu_to_le32(3 << 20); /* enable interrupt */
2113 }
2114
2115 wmb();
2116
2117 /* wake DMA in case it is sleeping */
2118 reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12);
2119
2120 /* issue a dummy read of the cycle timer to force all PCI
2121 writes to be posted immediately */
2122 mb();
2123 reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer);
2124
2125 return 0;
2126 }
2127
2128 static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle)
2129 {
2130 struct ohci_iso_xmit *xmit = iso->hostdata;
2131 struct ti_ohci *ohci = xmit->ohci;
2132
2133 /* clear out the control register */
2134 reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF);
2135 wmb();
2136
2137 /* address and length of first descriptor block (Z=3) */
2138 reg_write(xmit->ohci, xmit->CommandPtr,
2139 dma_prog_region_offset_to_bus(&xmit->prog, iso->pkt_dma * sizeof(struct iso_xmit_cmd)) | 3);
2140
2141 /* cycle match */
2142 if (cycle != -1) {
2143 u32 start = cycle & 0x1FFF;
2144
2145 /* 'cycle' is only mod 8000, but we also need two 'seconds' bits -
2146 just snarf them from the current time */
2147 u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25;
2148
2149 /* advance one second to give some extra time for DMA to start */
2150 seconds += 1;
2151
2152 start |= (seconds & 3) << 13;
2153
2154 reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16));
2155 }
2156
2157 /* enable interrupts */
2158 reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context);
2159
2160 /* run */
2161 reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000);
2162 mb();
2163
2164 /* wait 100 usec to give the card time to go active */
2165 udelay(100);
2166
2167 /* check the RUN bit */
2168 if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) {
2169 PRINT(KERN_ERR, "Error starting IT DMA (ContextControl 0x%08x)\n",
2170 reg_read(xmit->ohci, xmit->ContextControlSet));
2171 return -1;
2172 }
2173
2174 return 0;
2175 }
2176
2177 static int ohci_isoctl(struct hpsb_iso *iso, enum isoctl_cmd cmd, unsigned long arg)
2178 {
2179
2180 switch(cmd) {
2181 case XMIT_INIT:
2182 return ohci_iso_xmit_init(iso);
2183 case XMIT_START:
2184 return ohci_iso_xmit_start(iso, arg);
2185 case XMIT_STOP:
2186 ohci_iso_xmit_stop(iso);
2187 return 0;
2188 case XMIT_QUEUE:
2189 return ohci_iso_xmit_queue(iso, (struct hpsb_iso_packet_info*) arg);
2190 case XMIT_SHUTDOWN:
2191 ohci_iso_xmit_shutdown(iso);
2192 return 0;
2193
2194 case RECV_INIT:
2195 return ohci_iso_recv_init(iso);
2196 case RECV_START: {
2197 int *args = (int*) arg;
2198 return ohci_iso_recv_start(iso, args[0], args[1], args[2]);
2199 }
2200 case RECV_STOP:
2201 ohci_iso_recv_stop(iso);
2202 return 0;
2203 case RECV_RELEASE:
2204 ohci_iso_recv_release(iso, (struct hpsb_iso_packet_info*) arg);
2205 return 0;
2206 case RECV_FLUSH:
2207 ohci_iso_recv_task((unsigned long) iso);
2208 return 0;
2209 case RECV_SHUTDOWN:
2210 ohci_iso_recv_shutdown(iso);
2211 return 0;
2212 case RECV_LISTEN_CHANNEL:
2213 ohci_iso_recv_change_channel(iso, arg, 1);
2214 return 0;
2215 case RECV_UNLISTEN_CHANNEL:
2216 ohci_iso_recv_change_channel(iso, arg, 0);
2217 return 0;
2218 case RECV_SET_CHANNEL_MASK:
2219 ohci_iso_recv_set_channel_mask(iso, *((u64*) arg));
2220 return 0;
2221
2222 default:
2223 PRINT_G(KERN_ERR, "ohci_isoctl cmd %d not implemented yet",
2224 cmd);
2225 break;
2226 }
2227 return -EINVAL;
2228 }
2229
2230 /***************************************
2231 * IEEE-1394 functionality section END *
2232 ***************************************/
2233
2234
2235 /********************************************************
2236 * Global stuff (interrupt handler, init/shutdown code) *
2237 ********************************************************/
2238
2239 static void dma_trm_reset(struct dma_trm_ctx *d)
2240 {
2241 unsigned long flags;
2242 LIST_HEAD(packet_list);
2243 struct ti_ohci *ohci = d->ohci;
2244 struct hpsb_packet *packet, *ptmp;
2245
2246 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
2247
2248 /* Lock the context, reset it and release it. Move the packets
2249 * that were pending in the context to packet_list and free
2250 * them after releasing the lock. */
2251
2252 spin_lock_irqsave(&d->lock, flags);
2253
2254 list_splice(&d->fifo_list, &packet_list);
2255 list_splice(&d->pending_list, &packet_list);
2256 INIT_LIST_HEAD(&d->fifo_list);
2257 INIT_LIST_HEAD(&d->pending_list);
2258
2259 d->branchAddrPtr = NULL;
2260 d->sent_ind = d->prg_ind;
2261 d->free_prgs = d->num_desc;
2262
2263 spin_unlock_irqrestore(&d->lock, flags);
2264
2265 if (list_empty(&packet_list))
2266 return;
2267
2268 PRINT(KERN_INFO, "AT dma reset ctx=%d, aborting transmission", d->ctx);
2269
2270 /* Now process subsystem callbacks for the packets from this
2271 * context. */
2272 list_for_each_entry_safe(packet, ptmp, &packet_list, driver_list) {
2273 list_del_init(&packet->driver_list);
2274 hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED);
2275 }
2276 }
2277
2278 static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci,
2279 quadlet_t rx_event,
2280 quadlet_t tx_event)
2281 {
2282 struct ohci1394_iso_tasklet *t;
2283 unsigned long mask;
2284 unsigned long flags;
2285
2286 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
2287
2288 list_for_each_entry(t, &ohci->iso_tasklet_list, link) {
2289 mask = 1 << t->context;
2290
2291 if (t->type == OHCI_ISO_TRANSMIT && tx_event & mask)
2292 tasklet_schedule(&t->tasklet);
2293 else if (rx_event & mask)
2294 tasklet_schedule(&t->tasklet);
2295 }
2296
2297 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
2298 }
2299
2300 static irqreturn_t ohci_irq_handler(int irq, void *dev_id,
2301 struct pt_regs *regs_are_unused)
2302 {
2303 quadlet_t event, node_id;
2304 struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
2305 struct hpsb_host *host = ohci->host;
2306 int phyid = -1, isroot = 0;
2307 unsigned long flags;
2308
2309 /* Read and clear the interrupt event register. Don't clear
2310 * the busReset event, though. This is done when we get the
2311 * selfIDComplete interrupt. */
2312 spin_lock_irqsave(&ohci->event_lock, flags);
2313 event = reg_read(ohci, OHCI1394_IntEventClear);
2314 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
2315 spin_unlock_irqrestore(&ohci->event_lock, flags);
2316
2317 if (!event)
2318 return IRQ_NONE;
2319
2320 /* If event is ~(u32)0 cardbus card was ejected. In this case
2321 * we just return, and clean up in the ohci1394_pci_remove
2322 * function. */
2323 if (event == ~(u32) 0) {
2324 DBGMSG("Device removed.");
2325 return IRQ_NONE;
2326 }
2327
2328 DBGMSG("IntEvent: %08x", event);
2329
2330 if (event & OHCI1394_unrecoverableError) {
2331 int ctx;
2332 PRINT(KERN_ERR, "Unrecoverable error!");
2333
2334 if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800)
2335 PRINT(KERN_ERR, "Async Req Tx Context died: "
2336 "ctrl[%08x] cmdptr[%08x]",
2337 reg_read(ohci, OHCI1394_AsReqTrContextControlSet),
2338 reg_read(ohci, OHCI1394_AsReqTrCommandPtr));
2339
2340 if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800)
2341 PRINT(KERN_ERR, "Async Rsp Tx Context died: "
2342 "ctrl[%08x] cmdptr[%08x]",
2343 reg_read(ohci, OHCI1394_AsRspTrContextControlSet),
2344 reg_read(ohci, OHCI1394_AsRspTrCommandPtr));
2345
2346 if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800)
2347 PRINT(KERN_ERR, "Async Req Rcv Context died: "
2348 "ctrl[%08x] cmdptr[%08x]",
2349 reg_read(ohci, OHCI1394_AsReqRcvContextControlSet),
2350 reg_read(ohci, OHCI1394_AsReqRcvCommandPtr));
2351
2352 if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800)
2353 PRINT(KERN_ERR, "Async Rsp Rcv Context died: "
2354 "ctrl[%08x] cmdptr[%08x]",
2355 reg_read(ohci, OHCI1394_AsRspRcvContextControlSet),
2356 reg_read(ohci, OHCI1394_AsRspRcvCommandPtr));
2357
2358 for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) {
2359 if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800)
2360 PRINT(KERN_ERR, "Iso Xmit %d Context died: "
2361 "ctrl[%08x] cmdptr[%08x]", ctx,
2362 reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)),
2363 reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx)));
2364 }
2365
2366 for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) {
2367 if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800)
2368 PRINT(KERN_ERR, "Iso Recv %d Context died: "
2369 "ctrl[%08x] cmdptr[%08x] match[%08x]", ctx,
2370 reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)),
2371 reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)),
2372 reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx)));
2373 }
2374
2375 event &= ~OHCI1394_unrecoverableError;
2376 }
2377
2378 if (event & OHCI1394_cycleInconsistent) {
2379 /* We subscribe to the cycleInconsistent event only to
2380 * clear the corresponding event bit... otherwise,
2381 * isochronous cycleMatch DMA won't work. */
2382 DBGMSG("OHCI1394_cycleInconsistent");
2383 event &= ~OHCI1394_cycleInconsistent;
2384 }
2385
2386 if (event & OHCI1394_busReset) {
2387 /* The busReset event bit can't be cleared during the
2388 * selfID phase, so we disable busReset interrupts, to
2389 * avoid burying the cpu in interrupt requests. */
2390 spin_lock_irqsave(&ohci->event_lock, flags);
2391 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2392
2393 if (ohci->check_busreset) {
2394 int loop_count = 0;
2395
2396 udelay(10);
2397
2398 while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
2399 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2400
2401 spin_unlock_irqrestore(&ohci->event_lock, flags);
2402 udelay(10);
2403 spin_lock_irqsave(&ohci->event_lock, flags);
2404
2405 /* The loop counter check is to prevent the driver
2406 * from remaining in this state forever. For the
2407 * initial bus reset, the loop continues for ever
2408 * and the system hangs, until some device is plugged-in
2409 * or out manually into a port! The forced reset seems
2410 * to solve this problem. This mainly effects nForce2. */
2411 if (loop_count > 10000) {
2412 ohci_devctl(host, RESET_BUS, LONG_RESET);
2413 DBGMSG("Detected bus-reset loop. Forced a bus reset!");
2414 loop_count = 0;
2415 }
2416
2417 loop_count++;
2418 }
2419 }
2420 spin_unlock_irqrestore(&ohci->event_lock, flags);
2421 if (!host->in_bus_reset) {
2422 DBGMSG("irq_handler: Bus reset requested");
2423
2424 /* Subsystem call */
2425 hpsb_bus_reset(ohci->host);
2426 }
2427 event &= ~OHCI1394_busReset;
2428 }
2429
2430 if (event & OHCI1394_reqTxComplete) {
2431 struct dma_trm_ctx *d = &ohci->at_req_context;
2432 DBGMSG("Got reqTxComplete interrupt "
2433 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2434 if (reg_read(ohci, d->ctrlSet) & 0x800)
2435 ohci1394_stop_context(ohci, d->ctrlClear,
2436 "reqTxComplete");
2437 else
2438 dma_trm_tasklet((unsigned long)d);
2439 //tasklet_schedule(&d->task);
2440 event &= ~OHCI1394_reqTxComplete;
2441 }
2442 if (event & OHCI1394_respTxComplete) {
2443 struct dma_trm_ctx *d = &ohci->at_resp_context;
2444 DBGMSG("Got respTxComplete interrupt "
2445 "status=0x%08X", reg_read(ohci, d->ctrlSet));
2446 if (reg_read(ohci, d->ctrlSet) & 0x800)
2447 ohci1394_stop_context(ohci, d->ctrlClear,
2448 "respTxComplete");
2449 else
2450 tasklet_schedule(&d->task);
2451 event &= ~OHCI1394_respTxComplete;
2452 }
2453 if (event & OHCI1394_RQPkt) {
2454 struct dma_rcv_ctx *d = &ohci->ar_req_context;
2455 DBGMSG("Got RQPkt interrupt status=0x%08X",
2456 reg_read(ohci, d->ctrlSet));
2457 if (reg_read(ohci, d->ctrlSet) & 0x800)
2458 ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
2459 else
2460 tasklet_schedule(&d->task);
2461 event &= ~OHCI1394_RQPkt;
2462 }
2463 if (event & OHCI1394_RSPkt) {
2464 struct dma_rcv_ctx *d = &ohci->ar_resp_context;
2465 DBGMSG("Got RSPkt interrupt status=0x%08X",
2466 reg_read(ohci, d->ctrlSet));
2467 if (reg_read(ohci, d->ctrlSet) & 0x800)
2468 ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
2469 else
2470 tasklet_schedule(&d->task);
2471 event &= ~OHCI1394_RSPkt;
2472 }
2473 if (event & OHCI1394_isochRx) {
2474 quadlet_t rx_event;
2475
2476 rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
2477 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event);
2478 ohci_schedule_iso_tasklets(ohci, rx_event, 0);
2479 event &= ~OHCI1394_isochRx;
2480 }
2481 if (event & OHCI1394_isochTx) {
2482 quadlet_t tx_event;
2483
2484 tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
2485 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event);
2486 ohci_schedule_iso_tasklets(ohci, 0, tx_event);
2487 event &= ~OHCI1394_isochTx;
2488 }
2489 if (event & OHCI1394_selfIDComplete) {
2490 if (host->in_bus_reset) {
2491 node_id = reg_read(ohci, OHCI1394_NodeID);
2492
2493 if (!(node_id & 0x80000000)) {
2494 PRINT(KERN_ERR,
2495 "SelfID received, but NodeID invalid "
2496 "(probably new bus reset occurred): %08X",
2497 node_id);
2498 goto selfid_not_valid;
2499 }
2500
2501 phyid = node_id & 0x0000003f;
2502 isroot = (node_id & 0x40000000) != 0;
2503
2504 DBGMSG("SelfID interrupt received "
2505 "(phyid %d, %s)", phyid,
2506 (isroot ? "root" : "not root"));
2507
2508 handle_selfid(ohci, host, phyid, isroot);
2509
2510 /* Clear the bus reset event and re-enable the
2511 * busReset interrupt. */
2512 spin_lock_irqsave(&ohci->event_lock, flags);
2513 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2514 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2515 spin_unlock_irqrestore(&ohci->event_lock, flags);
2516
2517 /* Accept Physical requests from all nodes. */
2518 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0xffffffff);
2519 reg_write(ohci,OHCI1394_AsReqFilterLoSet, 0xffffffff);
2520
2521 /* Turn on phys dma reception.
2522 *
2523 * TODO: Enable some sort of filtering management.
2524 */
2525 if (phys_dma) {
2526 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0xffffffff);
2527 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0xffffffff);
2528 reg_write(ohci,OHCI1394_PhyUpperBound, 0xffff0000);
2529 } else {
2530 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0x00000000);
2531 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0x00000000);
2532 }
2533
2534 DBGMSG("PhyReqFilter=%08x%08x",
2535 reg_read(ohci,OHCI1394_PhyReqFilterHiSet),
2536 reg_read(ohci,OHCI1394_PhyReqFilterLoSet));
2537
2538 hpsb_selfid_complete(host, phyid, isroot);
2539 } else
2540 PRINT(KERN_ERR,
2541 "SelfID received outside of bus reset sequence");
2542
2543 selfid_not_valid:
2544 event &= ~OHCI1394_selfIDComplete;
2545 }
2546
2547 /* Make sure we handle everything, just in case we accidentally
2548 * enabled an interrupt that we didn't write a handler for. */
2549 if (event)
2550 PRINT(KERN_ERR, "Unhandled interrupt(s) 0x%08x",
2551 event);
2552
2553 return IRQ_HANDLED;
2554 }
2555
2556 /* Put the buffer back into the dma context */
2557 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
2558 {
2559 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2560 DBGMSG("Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
2561
2562 d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size);
2563 d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0);
2564 idx = (idx + d->num_desc - 1 ) % d->num_desc;
2565 d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001);
2566
2567 /* To avoid a race, ensure 1394 interface hardware sees the inserted
2568 * context program descriptors before it sees the wakeup bit set. */
2569 wmb();
2570
2571 /* wake up the dma context if necessary */
2572 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
2573 PRINT(KERN_INFO,
2574 "Waking dma ctx=%d ... processing is probably too slow",
2575 d->ctx);
2576 }
2577
2578 /* do this always, to avoid race condition */
2579 reg_write(ohci, d->ctrlSet, 0x1000);
2580 }
2581
2582 #define cond_le32_to_cpu(data, noswap) \
2583 (noswap ? data : le32_to_cpu(data))
2584
2585 static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
2586 -1, 0, -1, 0, -1, -1, 16, -1};
2587
2588 /*
2589 * Determine the length of a packet in the buffer
2590 * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
2591 */
2592 static __inline__ int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr,
2593 int offset, unsigned char tcode, int noswap)
2594 {
2595 int length = -1;
2596
2597 if (d->type == DMA_CTX_ASYNC_REQ || d->type == DMA_CTX_ASYNC_RESP) {
2598 length = TCODE_SIZE[tcode];
2599 if (length == 0) {
2600 if (offset + 12 >= d->buf_size) {
2601 length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc]
2602 [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16);
2603 } else {
2604 length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16);
2605 }
2606 length += 20;
2607 }
2608 } else if (d->type == DMA_CTX_ISO) {
2609 /* Assumption: buffer fill mode with header/trailer */
2610 length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8;
2611 }
2612
2613 if (length > 0 && length % 4)
2614 length += 4 - (length % 4);
2615
2616 return length;
2617 }
2618
2619 /* Tasklet that processes dma receive buffers */
2620 static void dma_rcv_tasklet (unsigned long data)
2621 {
2622 struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
2623 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2624 unsigned int split_left, idx, offset, rescount;
2625 unsigned char tcode;
2626 int length, bytes_left, ack;
2627 unsigned long flags;
2628 quadlet_t *buf_ptr;
2629 char *split_ptr;
2630 char msg[256];
2631
2632 spin_lock_irqsave(&d->lock, flags);
2633
2634 idx = d->buf_ind;
2635 offset = d->buf_offset;
2636 buf_ptr = d->buf_cpu[idx] + offset/4;
2637
2638 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2639 bytes_left = d->buf_size - rescount - offset;
2640
2641 while (bytes_left > 0) {
2642 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf;
2643
2644 /* packet_length() will return < 4 for an error */
2645 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming);
2646
2647 if (length < 4) { /* something is wrong */
2648 sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d",
2649 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming),
2650 d->ctx, length);
2651 ohci1394_stop_context(ohci, d->ctrlClear, msg);
2652 spin_unlock_irqrestore(&d->lock, flags);
2653 return;
2654 }
2655
2656 /* The first case is where we have a packet that crosses
2657 * over more than one descriptor. The next case is where
2658 * it's all in the first descriptor. */
2659 if ((offset + length) > d->buf_size) {
2660 DBGMSG("Split packet rcv'd");
2661 if (length > d->split_buf_size) {
2662 ohci1394_stop_context(ohci, d->ctrlClear,
2663 "Split packet size exceeded");
2664 d->buf_ind = idx;
2665 d->buf_offset = offset;
2666 spin_unlock_irqrestore(&d->lock, flags);
2667 return;
2668 }
2669
2670 if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status)
2671 == d->buf_size) {
2672 /* Other part of packet not written yet.
2673 * this should never happen I think
2674 * anyway we'll get it on the next call. */
2675 PRINT(KERN_INFO,
2676 "Got only half a packet!");
2677 d->buf_ind = idx;
2678 d->buf_offset = offset;
2679 spin_unlock_irqrestore(&d->lock, flags);
2680 return;
2681 }
2682
2683 split_left = length;
2684 split_ptr = (char *)d->spb;
2685 memcpy(split_ptr,buf_ptr,d->buf_size-offset);
2686 split_left -= d->buf_size-offset;
2687 split_ptr += d->buf_size-offset;
2688 insert_dma_buffer(d, idx);
2689 idx = (idx+1) % d->num_desc;
2690 buf_ptr = d->buf_cpu[idx];
2691 offset=0;
2692
2693 while (split_left >= d->buf_size) {
2694 memcpy(split_ptr,buf_ptr,d->buf_size);
2695 split_ptr += d->buf_size;
2696 split_left -= d->buf_size;
2697 insert_dma_buffer(d, idx);
2698 idx = (idx+1) % d->num_desc;
2699 buf_ptr = d->buf_cpu[idx];
2700 }
2701
2702 if (split_left > 0) {
2703 memcpy(split_ptr, buf_ptr, split_left);
2704 offset = split_left;
2705 buf_ptr += offset/4;
2706 }
2707 } else {
2708 DBGMSG("Single packet rcv'd");
2709 memcpy(d->spb, buf_ptr, length);
2710 offset += length;
2711 buf_ptr += length/4;
2712 if (offset==d->buf_size) {
2713 insert_dma_buffer(d, idx);
2714 idx = (idx+1) % d->num_desc;
2715 buf_ptr = d->buf_cpu[idx];
2716 offset=0;
2717 }
2718 }
2719
2720 /* We get one phy packet to the async descriptor for each
2721 * bus reset. We always ignore it. */
2722 if (tcode != OHCI1394_TCODE_PHY) {
2723 if (!ohci->no_swap_incoming)
2724 packet_swab(d->spb, tcode);
2725 DBGMSG("Packet received from node"
2726 " %d ack=0x%02X spd=%d tcode=0x%X"
2727 " length=%d ctx=%d tlabel=%d",
2728 (d->spb[1]>>16)&0x3f,
2729 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f,
2730 (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3,
2731 tcode, length, d->ctx,
2732 (cond_le32_to_cpu(d->spb[0], ohci->no_swap_incoming)>>10)&0x3f);
2733
2734 ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f)
2735 == 0x11) ? 1 : 0;
2736
2737 hpsb_packet_received(ohci->host, d->spb,
2738 length-4, ack);
2739 }
2740 #ifdef OHCI1394_DEBUG
2741 else
2742 PRINT (KERN_DEBUG, "Got phy packet ctx=%d ... discarded",
2743 d->ctx);
2744 #endif
2745
2746 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
2747
2748 bytes_left = d->buf_size - rescount - offset;
2749
2750 }
2751
2752 d->buf_ind = idx;
2753 d->buf_offset = offset;
2754
2755 spin_unlock_irqrestore(&d->lock, flags);
2756 }
2757
2758 /* Bottom half that processes sent packets */
2759 static void dma_trm_tasklet (unsigned long data)
2760 {
2761 struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
2762 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
2763 struct hpsb_packet *packet, *ptmp;
2764 unsigned long flags;
2765 u32 status, ack;
2766 size_t datasize;
2767
2768 spin_lock_irqsave(&d->lock, flags);
2769
2770 list_for_each_entry_safe(packet, ptmp, &d->fifo_list, driver_list) {
2771 datasize = packet->data_size;
2772 if (datasize && packet->type != hpsb_raw)
2773 status = le32_to_cpu(
2774 d->prg_cpu[d->sent_ind]->end.status) >> 16;
2775 else
2776 status = le32_to_cpu(
2777 d->prg_cpu[d->sent_ind]->begin.status) >> 16;
2778
2779 if (status == 0)
2780 /* this packet hasn't been sent yet*/
2781 break;
2782
2783 #ifdef OHCI1394_DEBUG
2784 if (datasize)
2785 if (((le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf) == 0xa)
2786 DBGMSG("Stream packet sent to channel %d tcode=0x%X "
2787 "ack=0x%X spd=%d dataLength=%d ctx=%d",
2788 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>8)&0x3f,
2789 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2790 status&0x1f, (status>>5)&0x3,
2791 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16,
2792 d->ctx);
2793 else
2794 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2795 "%d ack=0x%X spd=%d dataLength=%d ctx=%d",
2796 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16)&0x3f,
2797 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf,
2798 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>10)&0x3f,
2799 status&0x1f, (status>>5)&0x3,
2800 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])>>16,
2801 d->ctx);
2802 else
2803 DBGMSG("Packet sent to node %d tcode=0x%X tLabel="
2804 "%d ack=0x%X spd=%d data=0x%08X ctx=%d",
2805 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
2806 >>16)&0x3f,
2807 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2808 >>4)&0xf,
2809 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
2810 >>10)&0x3f,
2811 status&0x1f, (status>>5)&0x3,
2812 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]),
2813 d->ctx);
2814 #endif
2815
2816 if (status & 0x10) {
2817 ack = status & 0xf;
2818 } else {
2819 switch (status & 0x1f) {
2820 case EVT_NO_STATUS: /* that should never happen */
2821 case EVT_RESERVED_A: /* that should never happen */
2822 case EVT_LONG_PACKET: /* that should never happen */
2823 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2824 ack = ACKX_SEND_ERROR;
2825 break;
2826 case EVT_MISSING_ACK:
2827 ack = ACKX_TIMEOUT;
2828 break;
2829 case EVT_UNDERRUN:
2830 ack = ACKX_SEND_ERROR;
2831 break;
2832 case EVT_OVERRUN: /* that should never happen */
2833 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2834 ack = ACKX_SEND_ERROR;
2835 break;
2836 case EVT_DESCRIPTOR_READ:
2837 case EVT_DATA_READ:
2838 case EVT_DATA_WRITE:
2839 ack = ACKX_SEND_ERROR;
2840 break;
2841 case EVT_BUS_RESET: /* that should never happen */
2842 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2843 ack = ACKX_SEND_ERROR;
2844 break;
2845 case EVT_TIMEOUT:
2846 ack = ACKX_TIMEOUT;
2847 break;
2848 case EVT_TCODE_ERR:
2849 ack = ACKX_SEND_ERROR;
2850 break;
2851 case EVT_RESERVED_B: /* that should never happen */
2852 case EVT_RESERVED_C: /* that should never happen */
2853 PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f);
2854 ack = ACKX_SEND_ERROR;
2855 break;
2856 case EVT_UNKNOWN:
2857 case EVT_FLUSHED:
2858 ack = ACKX_SEND_ERROR;
2859 break;
2860 default:
2861 PRINT(KERN_ERR, "Unhandled OHCI evt_* error 0x%x", status & 0x1f);
2862 ack = ACKX_SEND_ERROR;
2863 BUG();
2864 }
2865 }
2866
2867 list_del_init(&packet->driver_list);
2868 hpsb_packet_sent(ohci->host, packet, ack);
2869
2870 if (datasize) {
2871 pci_unmap_single(ohci->dev,
2872 cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address),
2873 datasize, PCI_DMA_TODEVICE);
2874 OHCI_DMA_FREE("single Xmit data packet");
2875 }
2876
2877 d->sent_ind = (d->sent_ind+1)%d->num_desc;
2878 d->free_prgs++;
2879 }
2880
2881 dma_trm_flush(ohci, d);
2882
2883 spin_unlock_irqrestore(&d->lock, flags);
2884 }
2885
2886 static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d)
2887 {
2888 if (d->ctrlClear) {
2889 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
2890
2891 if (d->type == DMA_CTX_ISO) {
2892 /* disable interrupts */
2893 reg_write(d->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << d->ctx);
2894 ohci1394_unregister_iso_tasklet(d->ohci, &d->ohci->ir_legacy_tasklet);
2895 } else {
2896 tasklet_kill(&d->task);
2897 }
2898 }
2899 }
2900
2901
2902 static void free_dma_rcv_ctx(struct dma_rcv_ctx *d)
2903 {
2904 int i;
2905 struct ti_ohci *ohci = d->ohci;
2906
2907 if (ohci == NULL)
2908 return;
2909
2910 DBGMSG("Freeing dma_rcv_ctx %d", d->ctx);
2911
2912 if (d->buf_cpu) {
2913 for (i=0; i<d->num_desc; i++)
2914 if (d->buf_cpu[i] && d->buf_bus[i]) {
2915 pci_free_consistent(
2916 ohci->dev, d->buf_size,
2917 d->buf_cpu[i], d->buf_bus[i]);
2918 OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i);
2919 }
2920 kfree(d->buf_cpu);
2921 kfree(d->buf_bus);
2922 }
2923 if (d->prg_cpu) {
2924 for (i=0; i<d->num_desc; i++)
2925 if (d->prg_cpu[i] && d->prg_bus[i]) {
2926 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
2927 OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i);
2928 }
2929 pci_pool_destroy(d->prg_pool);
2930 OHCI_DMA_FREE("dma_rcv prg pool");
2931 kfree(d->prg_cpu);
2932 kfree(d->prg_bus);
2933 }
2934 kfree(d->spb);
2935
2936 /* Mark this context as freed. */
2937 d->ohci = NULL;
2938 }
2939
2940 static int
2941 alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
2942 enum context_type type, int ctx, int num_desc,
2943 int buf_size, int split_buf_size, int context_base)
2944 {
2945 int i, len;
2946 static int num_allocs;
2947 static char pool_name[20];
2948
2949 d->ohci = ohci;
2950 d->type = type;
2951 d->ctx = ctx;
2952
2953 d->num_desc = num_desc;
2954 d->buf_size = buf_size;
2955 d->split_buf_size = split_buf_size;
2956
2957 d->ctrlSet = 0;
2958 d->ctrlClear = 0;
2959 d->cmdPtr = 0;
2960
2961 d->buf_cpu = kzalloc(d->num_desc * sizeof(*d->buf_cpu), GFP_ATOMIC);
2962 d->buf_bus = kzalloc(d->num_desc * sizeof(*d->buf_bus), GFP_ATOMIC);
2963
2964 if (d->buf_cpu == NULL || d->buf_bus == NULL) {
2965 PRINT(KERN_ERR, "Failed to allocate dma buffer");
2966 free_dma_rcv_ctx(d);
2967 return -ENOMEM;
2968 }
2969
2970 d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_ATOMIC);
2971 d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_ATOMIC);
2972
2973 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
2974 PRINT(KERN_ERR, "Failed to allocate dma prg");
2975 free_dma_rcv_ctx(d);
2976 return -ENOMEM;
2977 }
2978
2979 d->spb = kmalloc(d->split_buf_size, GFP_ATOMIC);
2980
2981 if (d->spb == NULL) {
2982 PRINT(KERN_ERR, "Failed to allocate split buffer");
2983 free_dma_rcv_ctx(d);
2984 return -ENOMEM;
2985 }
2986
2987 len = sprintf(pool_name, "ohci1394_rcv_prg");
2988 sprintf(pool_name+len, "%d", num_allocs);
2989 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
2990 sizeof(struct dma_cmd), 4, 0);
2991 if(d->prg_pool == NULL)
2992 {
2993 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
2994 free_dma_rcv_ctx(d);
2995 return -ENOMEM;
2996 }
2997 num_allocs++;
2998
2999 OHCI_DMA_ALLOC("dma_rcv prg pool");
3000
3001 for (i=0; i<d->num_desc; i++) {
3002 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
3003 d->buf_size,
3004 d->buf_bus+i);
3005 OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i);
3006
3007 if (d->buf_cpu[i] != NULL) {
3008 memset(d->buf_cpu[i], 0, d->buf_size);
3009 } else {
3010 PRINT(KERN_ERR,
3011 "Failed to allocate dma buffer");
3012 free_dma_rcv_ctx(d);
3013 return -ENOMEM;
3014 }
3015
3016 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i);
3017 OHCI_DMA_ALLOC("pool dma_rcv prg[%d]", i);
3018
3019 if (d->prg_cpu[i] != NULL) {
3020 memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
3021 } else {
3022 PRINT(KERN_ERR,
3023 "Failed to allocate dma prg");
3024 free_dma_rcv_ctx(d);
3025 return -ENOMEM;
3026 }
3027 }
3028
3029 spin_lock_init(&d->lock);
3030
3031 if (type == DMA_CTX_ISO) {
3032 ohci1394_init_iso_tasklet(&ohci->ir_legacy_tasklet,
3033 OHCI_ISO_MULTICHANNEL_RECEIVE,
3034 dma_rcv_tasklet, (unsigned long) d);
3035 } else {
3036 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3037 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3038 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3039
3040 tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long) d);
3041 }
3042
3043 return 0;
3044 }
3045
3046 static void free_dma_trm_ctx(struct dma_trm_ctx *d)
3047 {
3048 int i;
3049 struct ti_ohci *ohci = d->ohci;
3050
3051 if (ohci == NULL)
3052 return;
3053
3054 DBGMSG("Freeing dma_trm_ctx %d", d->ctx);
3055
3056 if (d->prg_cpu) {
3057 for (i=0; i<d->num_desc; i++)
3058 if (d->prg_cpu[i] && d->prg_bus[i]) {
3059 pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]);
3060 OHCI_DMA_FREE("pool dma_trm prg[%d]", i);
3061 }
3062 pci_pool_destroy(d->prg_pool);
3063 OHCI_DMA_FREE("dma_trm prg pool");
3064 kfree(d->prg_cpu);
3065 kfree(d->prg_bus);
3066 }
3067
3068 /* Mark this context as freed. */
3069 d->ohci = NULL;
3070 }
3071
3072 static int
3073 alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
3074 enum context_type type, int ctx, int num_desc,
3075 int context_base)
3076 {
3077 int i, len;
3078 static char pool_name[20];
3079 static int num_allocs=0;
3080
3081 d->ohci = ohci;
3082 d->type = type;
3083 d->ctx = ctx;
3084 d->num_desc = num_desc;
3085 d->ctrlSet = 0;
3086 d->ctrlClear = 0;
3087 d->cmdPtr = 0;
3088
3089 d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_KERNEL);
3090 d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_KERNEL);
3091
3092 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
3093 PRINT(KERN_ERR, "Failed to allocate at dma prg");
3094 free_dma_trm_ctx(d);
3095 return -ENOMEM;
3096 }
3097
3098 len = sprintf(pool_name, "ohci1394_trm_prg");
3099 sprintf(pool_name+len, "%d", num_allocs);
3100 d->prg_pool = pci_pool_create(pool_name, ohci->dev,
3101 sizeof(struct at_dma_prg), 4, 0);
3102 if (d->prg_pool == NULL) {
3103 PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name);
3104 free_dma_trm_ctx(d);
3105 return -ENOMEM;
3106 }
3107 num_allocs++;
3108
3109 OHCI_DMA_ALLOC("dma_rcv prg pool");
3110
3111 for (i = 0; i < d->num_desc; i++) {
3112 d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i);
3113 OHCI_DMA_ALLOC("pool dma_trm prg[%d]", i);
3114
3115 if (d->prg_cpu[i] != NULL) {
3116 memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
3117 } else {
3118 PRINT(KERN_ERR,
3119 "Failed to allocate at dma prg");
3120 free_dma_trm_ctx(d);
3121 return -ENOMEM;
3122 }
3123 }
3124
3125 spin_lock_init(&d->lock);
3126
3127 /* initialize tasklet */
3128 if (type == DMA_CTX_ISO) {
3129 ohci1394_init_iso_tasklet(&ohci->it_legacy_tasklet, OHCI_ISO_TRANSMIT,
3130 dma_trm_tasklet, (unsigned long) d);
3131 if (ohci1394_register_iso_tasklet(ohci,
3132 &ohci->it_legacy_tasklet) < 0) {
3133 PRINT(KERN_ERR, "No IT DMA context available");
3134 free_dma_trm_ctx(d);
3135 return -EBUSY;
3136 }
3137
3138 /* IT can be assigned to any context by register_iso_tasklet */
3139 d->ctx = ohci->it_legacy_tasklet.context;
3140 d->ctrlSet = OHCI1394_IsoXmitContextControlSet + 16 * d->ctx;
3141 d->ctrlClear = OHCI1394_IsoXmitContextControlClear + 16 * d->ctx;
3142 d->cmdPtr = OHCI1394_IsoXmitCommandPtr + 16 * d->ctx;
3143 } else {
3144 d->ctrlSet = context_base + OHCI1394_ContextControlSet;
3145 d->ctrlClear = context_base + OHCI1394_ContextControlClear;
3146 d->cmdPtr = context_base + OHCI1394_ContextCommandPtr;
3147 tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d);
3148 }
3149
3150 return 0;
3151 }
3152
3153 static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom)
3154 {
3155 struct ti_ohci *ohci = host->hostdata;
3156
3157 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0]));
3158 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2]));
3159
3160 memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN);
3161 }
3162
3163
3164 static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg,
3165 quadlet_t data, quadlet_t compare)
3166 {
3167 struct ti_ohci *ohci = host->hostdata;
3168 int i;
3169
3170 reg_write(ohci, OHCI1394_CSRData, data);
3171 reg_write(ohci, OHCI1394_CSRCompareData, compare);
3172 reg_write(ohci, OHCI1394_CSRControl, reg & 0x3);
3173
3174 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
3175 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
3176 break;
3177
3178 mdelay(1);
3179 }
3180
3181 return reg_read(ohci, OHCI1394_CSRData);
3182 }
3183
3184 static struct hpsb_host_driver ohci1394_driver = {
3185 .owner = THIS_MODULE,
3186 .name = OHCI1394_DRIVER_NAME,
3187 .set_hw_config_rom = ohci_set_hw_config_rom,
3188 .transmit_packet = ohci_transmit,
3189 .devctl = ohci_devctl,
3190 .isoctl = ohci_isoctl,
3191 .hw_csr_reg = ohci_hw_csr_reg,
3192 };
3193
3194 /***********************************
3195 * PCI Driver Interface functions *
3196 ***********************************/
3197
3198 #define FAIL(err, fmt, args...) \
3199 do { \
3200 PRINT_G(KERN_ERR, fmt , ## args); \
3201 ohci1394_pci_remove(dev); \
3202 return err; \
3203 } while (0)
3204
3205 static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
3206 const struct pci_device_id *ent)
3207 {
3208 struct hpsb_host *host;
3209 struct ti_ohci *ohci; /* shortcut to currently handled device */
3210 unsigned long ohci_base;
3211
3212 if (pci_enable_device(dev))
3213 FAIL(-ENXIO, "Failed to enable OHCI hardware");
3214 pci_set_master(dev);
3215
3216 host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev);
3217 if (!host) FAIL(-ENOMEM, "Failed to allocate host structure");
3218
3219 ohci = host->hostdata;
3220 ohci->dev = dev;
3221 ohci->host = host;
3222 ohci->init_state = OHCI_INIT_ALLOC_HOST;
3223 host->pdev = dev;
3224 pci_set_drvdata(dev, ohci);
3225
3226 /* We don't want hardware swapping */
3227 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3228
3229 /* Some oddball Apple controllers do not order the selfid
3230 * properly, so we make up for it here. */
3231 #ifndef __LITTLE_ENDIAN
3232 /* XXX: Need a better way to check this. I'm wondering if we can
3233 * read the values of the OHCI1394_PCI_HCI_Control and the
3234 * noByteSwapData registers to see if they were not cleared to
3235 * zero. Should this work? Obviously it's not defined what these
3236 * registers will read when they aren't supported. Bleh! */
3237 if (dev->vendor == PCI_VENDOR_ID_APPLE &&
3238 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) {
3239 ohci->no_swap_incoming = 1;
3240 ohci->selfid_swap = 0;
3241 } else
3242 ohci->selfid_swap = 1;
3243 #endif
3244
3245
3246 #ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW
3247 #define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e
3248 #endif
3249
3250 /* These chipsets require a bit of extra care when checking after
3251 * a busreset. */
3252 if ((dev->vendor == PCI_VENDOR_ID_APPLE &&
3253 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) ||
3254 (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
3255 dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW))
3256 ohci->check_busreset = 1;
3257
3258 /* We hardwire the MMIO length, since some CardBus adaptors
3259 * fail to report the right length. Anyway, the ohci spec
3260 * clearly says it's 2kb, so this shouldn't be a problem. */
3261 ohci_base = pci_resource_start(dev, 0);
3262 if (pci_resource_len(dev, 0) != OHCI1394_REGISTER_SIZE)
3263 PRINT(KERN_WARNING, "Unexpected PCI resource length of %lx!",
3264 pci_resource_len(dev, 0));
3265
3266 /* Seems PCMCIA handles this internally. Not sure why. Seems
3267 * pretty bogus to force a driver to special case this. */
3268 #ifndef PCMCIA
3269 if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME))
3270 FAIL(-ENOMEM, "MMIO resource (0x%lx - 0x%lx) unavailable",
3271 ohci_base, ohci_base + OHCI1394_REGISTER_SIZE);
3272 #endif
3273 ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;
3274
3275 ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE);
3276 if (ohci->registers == NULL)
3277 FAIL(-ENXIO, "Failed to remap registers - card not accessible");
3278 ohci->init_state = OHCI_INIT_HAVE_IOMAPPING;
3279 DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers);
3280
3281 /* csr_config rom allocation */
3282 ohci->csr_config_rom_cpu =
3283 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3284 &ohci->csr_config_rom_bus);
3285 OHCI_DMA_ALLOC("consistent csr_config_rom");
3286 if (ohci->csr_config_rom_cpu == NULL)
3287 FAIL(-ENOMEM, "Failed to allocate buffer config rom");
3288 ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER;
3289
3290 /* self-id dma buffer allocation */
3291 ohci->selfid_buf_cpu =
3292 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3293 &ohci->selfid_buf_bus);
3294 OHCI_DMA_ALLOC("consistent selfid_buf");
3295
3296 if (ohci->selfid_buf_cpu == NULL)
3297 FAIL(-ENOMEM, "Failed to allocate DMA buffer for self-id packets");
3298 ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER;
3299
3300 if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
3301 PRINT(KERN_INFO, "SelfID buffer %p is not aligned on "
3302 "8Kb boundary... may cause problems on some CXD3222 chip",
3303 ohci->selfid_buf_cpu);
3304
3305 /* No self-id errors at startup */
3306 ohci->self_id_errors = 0;
3307
3308 ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE;
3309 /* AR DMA request context allocation */
3310 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context,
3311 DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC,
3312 AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
3313 OHCI1394_AsReqRcvContextBase) < 0)
3314 FAIL(-ENOMEM, "Failed to allocate AR Req context");
3315
3316 /* AR DMA response context allocation */
3317 if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context,
3318 DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC,
3319 AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
3320 OHCI1394_AsRspRcvContextBase) < 0)
3321 FAIL(-ENOMEM, "Failed to allocate AR Resp context");
3322
3323 /* AT DMA request context */
3324 if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context,
3325 DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC,
3326 OHCI1394_AsReqTrContextBase) < 0)
3327 FAIL(-ENOMEM, "Failed to allocate AT Req context");
3328
3329 /* AT DMA response context */
3330 if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context,
3331 DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC,
3332 OHCI1394_AsRspTrContextBase) < 0)
3333 FAIL(-ENOMEM, "Failed to allocate AT Resp context");
3334
3335 /* Start off with a soft reset, to clear everything to a sane
3336 * state. */
3337 ohci_soft_reset(ohci);
3338
3339 /* Now enable LPS, which we need in order to start accessing
3340 * most of the registers. In fact, on some cards (ALI M5251),
3341 * accessing registers in the SClk domain without LPS enabled
3342 * will lock up the machine. Wait 50msec to make sure we have
3343 * full link enabled. */
3344 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3345
3346 /* Disable and clear interrupts */
3347 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3348 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3349
3350 mdelay(50);
3351
3352 /* Determine the number of available IR and IT contexts. */
3353 ohci->nb_iso_rcv_ctx =
3354 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
3355 ohci->nb_iso_xmit_ctx =
3356 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
3357
3358 /* Set the usage bits for non-existent contexts so they can't
3359 * be allocated */
3360 ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx;
3361 ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx;
3362
3363 INIT_LIST_HEAD(&ohci->iso_tasklet_list);
3364 spin_lock_init(&ohci->iso_tasklet_list_lock);
3365 ohci->ISO_channel_usage = 0;
3366 spin_lock_init(&ohci->IR_channel_lock);
3367
3368 /* Allocate the IR DMA context right here so we don't have
3369 * to do it in interrupt path - note that this doesn't
3370 * waste much memory and avoids the jugglery required to
3371 * allocate it in IRQ path. */
3372 if (alloc_dma_rcv_ctx(ohci, &ohci->ir_legacy_context,
3373 DMA_CTX_ISO, 0, IR_NUM_DESC,
3374 IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
3375 OHCI1394_IsoRcvContextBase) < 0) {
3376 FAIL(-ENOMEM, "Cannot allocate IR Legacy DMA context");
3377 }
3378
3379 /* We hopefully don't have to pre-allocate IT DMA like we did
3380 * for IR DMA above. Allocate it on-demand and mark inactive. */
3381 ohci->it_legacy_context.ohci = NULL;
3382 spin_lock_init(&ohci->event_lock);
3383
3384 /*
3385 * interrupts are disabled, all right, but... due to SA_SHIRQ we
3386 * might get called anyway. We'll see no event, of course, but
3387 * we need to get to that "no event", so enough should be initialized
3388 * by that point.
3389 */
3390 if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
3391 OHCI1394_DRIVER_NAME, ohci))
3392 FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq);
3393
3394 ohci->init_state = OHCI_INIT_HAVE_IRQ;
3395 ohci_initialize(ohci);
3396
3397 /* Set certain csr values */
3398 host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi);
3399 host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo);
3400 host->csr.cyc_clk_acc = 100; /* how do we determine clk accuracy? */
3401 host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;
3402 host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;
3403
3404 /* Tell the highlevel this host is ready */
3405 if (hpsb_add_host(host))
3406 FAIL(-ENOMEM, "Failed to register host with highlevel");
3407
3408 ohci->init_state = OHCI_INIT_DONE;
3409
3410 return 0;
3411 #undef FAIL
3412 }
3413
3414 static void ohci1394_pci_remove(struct pci_dev *pdev)
3415 {
3416 struct ti_ohci *ohci;
3417 struct device *dev;
3418
3419 ohci = pci_get_drvdata(pdev);
3420 if (!ohci)
3421 return;
3422
3423 dev = get_device(&ohci->host->device);
3424
3425 switch (ohci->init_state) {
3426 case OHCI_INIT_DONE:
3427 hpsb_remove_host(ohci->host);
3428
3429 /* Clear out BUS Options */
3430 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
3431 reg_write(ohci, OHCI1394_BusOptions,
3432 (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) |
3433 0x00ff0000);
3434 memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN);
3435
3436 case OHCI_INIT_HAVE_IRQ:
3437 /* Clear interrupt registers */
3438 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3439 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3440 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
3441 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
3442 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
3443 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
3444
3445 /* Disable IRM Contender */
3446 set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4));
3447
3448 /* Clear link control register */
3449 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
3450
3451 /* Let all other nodes know to ignore us */
3452 ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
3453
3454 /* Soft reset before we start - this disables
3455 * interrupts and clears linkEnable and LPS. */
3456 ohci_soft_reset(ohci);
3457 free_irq(ohci->dev->irq, ohci);
3458
3459 case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE:
3460 /* The ohci_soft_reset() stops all DMA contexts, so we
3461 * dont need to do this. */
3462 /* Free AR dma */
3463 free_dma_rcv_ctx(&ohci->ar_req_context);
3464 free_dma_rcv_ctx(&ohci->ar_resp_context);
3465
3466 /* Free AT dma */
3467 free_dma_trm_ctx(&ohci->at_req_context);
3468 free_dma_trm_ctx(&ohci->at_resp_context);
3469
3470 /* Free IR dma */
3471 free_dma_rcv_ctx(&ohci->ir_legacy_context);
3472
3473 /* Free IT dma */
3474 free_dma_trm_ctx(&ohci->it_legacy_context);
3475
3476 /* Free IR legacy dma */
3477 free_dma_rcv_ctx(&ohci->ir_legacy_context);
3478
3479
3480 case OHCI_INIT_HAVE_SELFID_BUFFER:
3481 pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
3482 ohci->selfid_buf_cpu,
3483 ohci->selfid_buf_bus);
3484 OHCI_DMA_FREE("consistent selfid_buf");
3485
3486 case OHCI_INIT_HAVE_CONFIG_ROM_BUFFER:
3487 pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
3488 ohci->csr_config_rom_cpu,
3489 ohci->csr_config_rom_bus);
3490 OHCI_DMA_FREE("consistent csr_config_rom");
3491
3492 case OHCI_INIT_HAVE_IOMAPPING:
3493 iounmap(ohci->registers);
3494
3495 case OHCI_INIT_HAVE_MEM_REGION:
3496 #ifndef PCMCIA
3497 release_mem_region(pci_resource_start(ohci->dev, 0),
3498 OHCI1394_REGISTER_SIZE);
3499 #endif
3500
3501 #ifdef CONFIG_PPC_PMAC
3502 /* On UniNorth, power down the cable and turn off the chip
3503 * clock when the module is removed to save power on
3504 * laptops. Turning it back ON is done by the arch code when
3505 * pci_enable_device() is called */
3506 {
3507 struct device_node* of_node;
3508
3509 of_node = pci_device_to_OF_node(ohci->dev);
3510 if (of_node) {
3511 pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0);
3512 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, of_node, 0, 0);
3513 }
3514 }
3515 #endif /* CONFIG_PPC_PMAC */
3516
3517 case OHCI_INIT_ALLOC_HOST:
3518 pci_set_drvdata(ohci->dev, NULL);
3519 }
3520
3521 if (dev)
3522 put_device(dev);
3523 }
3524
3525
3526 static int ohci1394_pci_resume (struct pci_dev *pdev)
3527 {
3528 #ifdef CONFIG_PPC_PMAC
3529 if (_machine == _MACH_Pmac) {
3530 struct device_node *of_node;
3531
3532 /* Re-enable 1394 */
3533 of_node = pci_device_to_OF_node (pdev);
3534 if (of_node)
3535 pmac_call_feature (PMAC_FTR_1394_ENABLE, of_node, 0, 1);
3536 }
3537 #endif /* CONFIG_PPC_PMAC */
3538
3539 pci_enable_device(pdev);
3540
3541 return 0;
3542 }
3543
3544
3545 static int ohci1394_pci_suspend (struct pci_dev *pdev, pm_message_t state)
3546 {
3547 #ifdef CONFIG_PPC_PMAC
3548 if (_machine == _MACH_Pmac) {
3549 struct device_node *of_node;
3550
3551 /* Disable 1394 */
3552 of_node = pci_device_to_OF_node (pdev);
3553 if (of_node)
3554 pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0);
3555 }
3556 #endif
3557
3558 return 0;
3559 }
3560
3561
3562 #define PCI_CLASS_FIREWIRE_OHCI ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10)
3563
3564 static struct pci_device_id ohci1394_pci_tbl[] = {
3565 {
3566 .class = PCI_CLASS_FIREWIRE_OHCI,
3567 .class_mask = PCI_ANY_ID,
3568 .vendor = PCI_ANY_ID,
3569 .device = PCI_ANY_ID,
3570 .subvendor = PCI_ANY_ID,
3571 .subdevice = PCI_ANY_ID,
3572 },
3573 { 0, },
3574 };
3575
3576 MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl);
3577
3578 static struct pci_driver ohci1394_pci_driver = {
3579 .name = OHCI1394_DRIVER_NAME,
3580 .id_table = ohci1394_pci_tbl,
3581 .probe = ohci1394_pci_probe,
3582 .remove = ohci1394_pci_remove,
3583 .resume = ohci1394_pci_resume,
3584 .suspend = ohci1394_pci_suspend,
3585 };
3586
3587 /***********************************
3588 * OHCI1394 Video Interface *
3589 ***********************************/
3590
3591 /* essentially the only purpose of this code is to allow another
3592 module to hook into ohci's interrupt handler */
3593
3594 int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
3595 {
3596 int i=0;
3597
3598 /* stop the channel program if it's still running */
3599 reg_write(ohci, reg, 0x8000);
3600
3601 /* Wait until it effectively stops */
3602 while (reg_read(ohci, reg) & 0x400) {
3603 i++;
3604 if (i>5000) {
3605 PRINT(KERN_ERR,
3606 "Runaway loop while stopping context: %s...", msg ? msg : "");
3607 return 1;
3608 }
3609
3610 mb();
3611 udelay(10);
3612 }
3613 if (msg) PRINT(KERN_ERR, "%s: dma prg stopped", msg);
3614 return 0;
3615 }
3616
3617 void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type,
3618 void (*func)(unsigned long), unsigned long data)
3619 {
3620 tasklet_init(&tasklet->tasklet, func, data);
3621 tasklet->type = type;
3622 /* We init the tasklet->link field, so we can list_del() it
3623 * without worrying whether it was added to the list or not. */
3624 INIT_LIST_HEAD(&tasklet->link);
3625 }
3626
3627 int ohci1394_register_iso_tasklet(struct ti_ohci *ohci,
3628 struct ohci1394_iso_tasklet *tasklet)
3629 {
3630 unsigned long flags, *usage;
3631 int n, i, r = -EBUSY;
3632
3633 if (tasklet->type == OHCI_ISO_TRANSMIT) {
3634 n = ohci->nb_iso_xmit_ctx;
3635 usage = &ohci->it_ctx_usage;
3636 }
3637 else {
3638 n = ohci->nb_iso_rcv_ctx;
3639 usage = &ohci->ir_ctx_usage;
3640
3641 /* only one receive context can be multichannel (OHCI sec 10.4.1) */
3642 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3643 if (test_and_set_bit(0, &ohci->ir_multichannel_used)) {
3644 return r;
3645 }
3646 }
3647 }
3648
3649 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3650
3651 for (i = 0; i < n; i++)
3652 if (!test_and_set_bit(i, usage)) {
3653 tasklet->context = i;
3654 list_add_tail(&tasklet->link, &ohci->iso_tasklet_list);
3655 r = 0;
3656 break;
3657 }
3658
3659 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3660
3661 return r;
3662 }
3663
3664 void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci,
3665 struct ohci1394_iso_tasklet *tasklet)
3666 {
3667 unsigned long flags;
3668
3669 tasklet_kill(&tasklet->tasklet);
3670
3671 spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags);
3672
3673 if (tasklet->type == OHCI_ISO_TRANSMIT)
3674 clear_bit(tasklet->context, &ohci->it_ctx_usage);
3675 else {
3676 clear_bit(tasklet->context, &ohci->ir_ctx_usage);
3677
3678 if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) {
3679 clear_bit(0, &ohci->ir_multichannel_used);
3680 }
3681 }
3682
3683 list_del(&tasklet->link);
3684
3685 spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags);
3686 }
3687
3688 EXPORT_SYMBOL(ohci1394_stop_context);
3689 EXPORT_SYMBOL(ohci1394_init_iso_tasklet);
3690 EXPORT_SYMBOL(ohci1394_register_iso_tasklet);
3691 EXPORT_SYMBOL(ohci1394_unregister_iso_tasklet);
3692
3693 /***********************************
3694 * General module initialization *
3695 ***********************************/
3696
3697 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
3698 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers");
3699 MODULE_LICENSE("GPL");
3700
3701 static void __exit ohci1394_cleanup (void)
3702 {
3703 pci_unregister_driver(&ohci1394_pci_driver);
3704 }
3705
3706 static int __init ohci1394_init(void)
3707 {
3708 return pci_register_driver(&ohci1394_pci_driver);
3709 }
3710
3711 module_init(ohci1394_init);
3712 module_exit(ohci1394_cleanup);
Support for the Chinese Samsung S3C2440 based development boards