drivers/spi/spi_mpc83xx.c

   1 /*
   2  * MPC83xx SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/bug.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/completion.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/irq.h>
  25 #include <linux/device.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/spi_bitbang.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/fsl_devices.h>
  30 #include <linux/of.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_spi.h>
  35
  36 #include <sysdev/fsl_soc.h>
  37 #include <asm/irq.h>
  38
  39 /* SPI Controller registers */
  40 struct mpc83xx_spi_reg {
  41         u8 res1[0x20];
  42         __be32 mode;
  43         __be32 event;
  44         __be32 mask;
  45         __be32 command;
  46         __be32 transmit;
  47         __be32 receive;
  48 };
  49
  50 /* SPI Controller mode register definitions */
  51 #define SPMODE_LOOP             (1 << 30)
  52 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  53 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  54 #define SPMODE_DIV16            (1 << 27)
  55 #define SPMODE_REV              (1 << 26)
  56 #define SPMODE_MS               (1 << 25)
  57 #define SPMODE_ENABLE           (1 << 24)
  58 #define SPMODE_LEN(x)           ((x) << 20)
  59 #define SPMODE_PM(x)            ((x) << 16)
  60 #define SPMODE_OP               (1 << 14)
  61 #define SPMODE_CG(x)            ((x) << 7)
  62
  63 /*
  64  * Default for SPI Mode:
  65  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  66  */
  67 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  68                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  69
  70 /* SPIE register values */
  71 #define SPIE_NE         0x00000200      /* Not empty */
  72 #define SPIE_NF         0x00000100      /* Not full */
  73
  74 /* SPIM register values */
  75 #define SPIM_NE         0x00000200      /* Not empty */
  76 #define SPIM_NF         0x00000100      /* Not full */
  77
  78 /* SPI Controller driver's private data. */
  79 struct mpc83xx_spi {
  80         struct mpc83xx_spi_reg __iomem *base;
  81
  82         /* rx & tx bufs from the spi_transfer */
  83         const void *tx;
  84         void *rx;
  85
  86         /* functions to deal with different sized buffers */
  87         void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
  88         u32(*get_tx) (struct mpc83xx_spi *);
  89
  90         unsigned int count;
  91         unsigned int irq;
  92
  93         unsigned nsecs;         /* (clock cycle time)/2 */
  94
  95         u32 spibrg;             /* SPIBRG input clock */
  96         u32 rx_shift;           /* RX data reg shift when in qe mode */
  97         u32 tx_shift;           /* TX data reg shift when in qe mode */
  98
  99         bool qe_mode;
 100
 101         u8 busy;
 102
 103         struct workqueue_struct *workqueue;
 104         struct work_struct work;
 105
 106         struct list_head queue;
 107         spinlock_t lock;
 108
 109         struct completion done;
 110 };
 111
 112 struct spi_mpc83xx_cs {
 113         /* functions to deal with different sized buffers */
 114         void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
 115         u32 (*get_tx) (struct mpc83xx_spi *);
 116         u32 rx_shift;           /* RX data reg shift when in qe mode */
 117         u32 tx_shift;           /* TX data reg shift when in qe mode */
 118         u32 hw_mode;            /* Holds HW mode register settings */
 119 };
 120
 121 static inline void mpc83xx_spi_write_reg(__be32 __iomem *reg, u32 val)
 122 {
 123         out_be32(reg, val);
 124 }
 125
 126 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem *reg)
 127 {
 128         return in_be32(reg);
 129 }
 130
 131 #define MPC83XX_SPI_RX_BUF(type)                                          \
 132 static                                                                    \
 133 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
 134 {                                                                         \
 135         type *rx = mpc83xx_spi->rx;                                       \
 136         *rx++ = (type)(data >> mpc83xx_spi->rx_shift);                    \
 137         mpc83xx_spi->rx = rx;                                             \
 138 }
 139
 140 #define MPC83XX_SPI_TX_BUF(type)                                \
 141 static                                                          \
 142 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)  \
 143 {                                                               \
 144         u32 data;                                               \
 145         const type *tx = mpc83xx_spi->tx;                       \
 146         if (!tx)                                                \
 147                 return 0;                                       \
 148         data = *tx++ << mpc83xx_spi->tx_shift;                  \
 149         mpc83xx_spi->tx = tx;                                   \
 150         return data;                                            \
 151 }
 152
 153 MPC83XX_SPI_RX_BUF(u8)
 154 MPC83XX_SPI_RX_BUF(u16)
 155 MPC83XX_SPI_RX_BUF(u32)
 156 MPC83XX_SPI_TX_BUF(u8)
 157 MPC83XX_SPI_TX_BUF(u16)
 158 MPC83XX_SPI_TX_BUF(u32)
 159
 160 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
 161 {
 162         struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
 163         struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
 164         bool pol = spi->mode & SPI_CS_HIGH;
 165         struct spi_mpc83xx_cs   *cs = spi->controller_state;
 166
 167         if (value == BITBANG_CS_INACTIVE) {
 168                 if (pdata->cs_control)
 169                         pdata->cs_control(spi, !pol);
 170         }
 171
 172         if (value == BITBANG_CS_ACTIVE) {
 173                 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 174
 175                 mpc83xx_spi->rx_shift = cs->rx_shift;
 176                 mpc83xx_spi->tx_shift = cs->tx_shift;
 177                 mpc83xx_spi->get_rx = cs->get_rx;
 178                 mpc83xx_spi->get_tx = cs->get_tx;
 179
 180                 if (cs->hw_mode != regval) {
 181                         unsigned long flags;
 182                         __be32 __iomem *mode = &mpc83xx_spi->base->mode;
 183
 184                         regval = cs->hw_mode;
 185                         /* Turn off IRQs locally to minimize time that
 186                          * SPI is disabled
 187                          */
 188                         local_irq_save(flags);
 189                         /* Turn off SPI unit prior changing mode */
 190                         mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
 191                         mpc83xx_spi_write_reg(mode, regval);
 192                         local_irq_restore(flags);
 193                 }
 194                 if (pdata->cs_control)
 195                         pdata->cs_control(spi, pol);
 196         }
 197 }
 198
 199 static
 200 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 201 {
 202         struct mpc83xx_spi *mpc83xx_spi;
 203         u32 regval;
 204         u8 bits_per_word, pm;
 205         u32 hz;
 206         struct spi_mpc83xx_cs   *cs = spi->controller_state;
 207
 208         mpc83xx_spi = spi_master_get_devdata(spi->master);
 209
 210         if (t) {
 211                 bits_per_word = t->bits_per_word;
 212                 hz = t->speed_hz;
 213         } else {
 214                 bits_per_word = 0;
 215                 hz = 0;
 216         }
 217
 218         /* spi_transfer level calls that work per-word */
 219         if (!bits_per_word)
 220                 bits_per_word = spi->bits_per_word;
 221
 222         /* Make sure its a bit width we support [4..16, 32] */
 223         if ((bits_per_word < 4)
 224             || ((bits_per_word > 16) && (bits_per_word != 32)))
 225                 return -EINVAL;
 226
 227         if (!hz)
 228                 hz = spi->max_speed_hz;
 229
 230         cs->rx_shift = 0;
 231         cs->tx_shift = 0;
 232         if (bits_per_word <= 8) {
 233                 cs->get_rx = mpc83xx_spi_rx_buf_u8;
 234                 cs->get_tx = mpc83xx_spi_tx_buf_u8;
 235                 if (mpc83xx_spi->qe_mode) {
 236                         cs->rx_shift = 16;
 237                         cs->tx_shift = 24;
 238                 }
 239         } else if (bits_per_word <= 16) {
 240                 cs->get_rx = mpc83xx_spi_rx_buf_u16;
 241                 cs->get_tx = mpc83xx_spi_tx_buf_u16;
 242                 if (mpc83xx_spi->qe_mode) {
 243                         cs->rx_shift = 16;
 244                         cs->tx_shift = 16;
 245                 }
 246         } else if (bits_per_word <= 32) {
 247                 cs->get_rx = mpc83xx_spi_rx_buf_u32;
 248                 cs->get_tx = mpc83xx_spi_tx_buf_u32;
 249         } else
 250                 return -EINVAL;
 251
 252         if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
 253                 cs->tx_shift = 0;
 254                 if (bits_per_word <= 8)
 255                         cs->rx_shift = 8;
 256                 else
 257                         cs->rx_shift = 0;
 258         }
 259
 260         mpc83xx_spi->rx_shift = cs->rx_shift;
 261         mpc83xx_spi->tx_shift = cs->tx_shift;
 262         mpc83xx_spi->get_rx = cs->get_rx;
 263         mpc83xx_spi->get_tx = cs->get_tx;
 264
 265         if (bits_per_word == 32)
 266                 bits_per_word = 0;
 267         else
 268                 bits_per_word = bits_per_word - 1;
 269
 270         /* mask out bits we are going to set */
 271         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 272                                   | SPMODE_PM(0xF));
 273
 274         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 275
 276         if ((mpc83xx_spi->spibrg / hz) > 64) {
 277                 cs->hw_mode |= SPMODE_DIV16;
 278                 pm = mpc83xx_spi->spibrg / (hz * 64);
 279
 280                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
 281                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 282                           hz, mpc83xx_spi->spibrg / 1024);
 283                 if (pm > 16)
 284                         pm = 16;
 285         } else
 286                 pm = mpc83xx_spi->spibrg / (hz * 4);
 287         if (pm)
 288                 pm--;
 289
 290         cs->hw_mode |= SPMODE_PM(pm);
 291         regval =  mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 292         if (cs->hw_mode != regval) {
 293                 unsigned long flags;
 294                 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
 295
 296                 regval = cs->hw_mode;
 297                 /* Turn off IRQs locally to minimize time
 298                  * that SPI is disabled
 299                  */
 300                 local_irq_save(flags);
 301                 /* Turn off SPI unit prior changing mode */
 302                 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
 303                 mpc83xx_spi_write_reg(mode, regval);
 304                 local_irq_restore(flags);
 305         }
 306         return 0;
 307 }
 308
 309 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 310 {
 311         struct mpc83xx_spi *mpc83xx_spi;
 312         u32 word, len, bits_per_word;
 313
 314         mpc83xx_spi = spi_master_get_devdata(spi->master);
 315
 316         mpc83xx_spi->tx = t->tx_buf;
 317         mpc83xx_spi->rx = t->rx_buf;
 318         bits_per_word = spi->bits_per_word;
 319         if (t->bits_per_word)
 320                 bits_per_word = t->bits_per_word;
 321         len = t->len;
 322         if (bits_per_word > 8) {
 323                 /* invalid length? */
 324                 if (len & 1)
 325                         return -EINVAL;
 326                 len /= 2;
 327         }
 328         if (bits_per_word > 16) {
 329                 /* invalid length? */
 330                 if (len & 1)
 331                         return -EINVAL;
 332                 len /= 2;
 333         }
 334         mpc83xx_spi->count = len;
 335
 336         INIT_COMPLETION(mpc83xx_spi->done);
 337
 338         /* enable rx ints */
 339         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
 340
 341         /* transmit word */
 342         word = mpc83xx_spi->get_tx(mpc83xx_spi);
 343         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 344
 345         wait_for_completion(&mpc83xx_spi->done);
 346
 347         /* disable rx ints */
 348         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 349
 350         return mpc83xx_spi->count;
 351 }
 352
 353 static void mpc83xx_spi_work(struct work_struct *work)
 354 {
 355         struct mpc83xx_spi *mpc83xx_spi =
 356                 container_of(work, struct mpc83xx_spi, work);
 357
 358         spin_lock_irq(&mpc83xx_spi->lock);
 359         mpc83xx_spi->busy = 1;
 360         while (!list_empty(&mpc83xx_spi->queue)) {
 361                 struct spi_message *m;
 362                 struct spi_device *spi;
 363                 struct spi_transfer *t = NULL;
 364                 unsigned cs_change;
 365                 int status, nsecs = 50;
 366
 367                 m = container_of(mpc83xx_spi->queue.next,
 368                                 struct spi_message, queue);
 369                 list_del_init(&m->queue);
 370                 spin_unlock_irq(&mpc83xx_spi->lock);
 371
 372                 spi = m->spi;
 373                 cs_change = 1;
 374                 status = 0;
 375                 list_for_each_entry(t, &m->transfers, transfer_list) {
 376                         if (t->bits_per_word || t->speed_hz) {
 377                                 /* Don't allow changes if CS is active */
 378                                 status = -EINVAL;
 379
 380                                 if (cs_change)
 381                                         status = mpc83xx_spi_setup_transfer(spi, t);
 382                                 if (status < 0)
 383                                         break;
 384                         }
 385
 386                         if (cs_change) {
 387                                 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 388                                 ndelay(nsecs);
 389                         }
 390                         cs_change = t->cs_change;
 391                         if (t->len)
 392                                 status = mpc83xx_spi_bufs(spi, t);
 393                         if (status) {
 394                                 status = -EMSGSIZE;
 395                                 break;
 396                         }
 397                         m->actual_length += t->len;
 398
 399                         if (t->delay_usecs)
 400                                 udelay(t->delay_usecs);
 401
 402                         if (cs_change) {
 403                                 ndelay(nsecs);
 404                                 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 405                                 ndelay(nsecs);
 406                         }
 407                 }
 408
 409                 m->status = status;
 410                 m->complete(m->context);
 411
 412                 if (status || !cs_change) {
 413                         ndelay(nsecs);
 414                         mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 415                 }
 416
 417                 mpc83xx_spi_setup_transfer(spi, NULL);
 418
 419                 spin_lock_irq(&mpc83xx_spi->lock);
 420         }
 421         mpc83xx_spi->busy = 0;
 422         spin_unlock_irq(&mpc83xx_spi->lock);
 423 }
 424
 425 static int mpc83xx_spi_setup(struct spi_device *spi)
 426 {
 427         struct mpc83xx_spi *mpc83xx_spi;
 428         int retval;
 429         u32 hw_mode;
 430         struct spi_mpc83xx_cs   *cs = spi->controller_state;
 431
 432         if (!spi->max_speed_hz)
 433                 return -EINVAL;
 434
 435         if (!cs) {
 436                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 437                 if (!cs)
 438                         return -ENOMEM;
 439                 spi->controller_state = cs;
 440         }
 441         mpc83xx_spi = spi_master_get_devdata(spi->master);
 442
 443         hw_mode = cs->hw_mode; /* Save orginal settings */
 444         cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 445         /* mask out bits we are going to set */
 446         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 447                          | SPMODE_REV | SPMODE_LOOP);
 448
 449         if (spi->mode & SPI_CPHA)
 450                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 451         if (spi->mode & SPI_CPOL)
 452                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 453         if (!(spi->mode & SPI_LSB_FIRST))
 454                 cs->hw_mode |= SPMODE_REV;
 455         if (spi->mode & SPI_LOOP)
 456                 cs->hw_mode |= SPMODE_LOOP;
 457
 458         retval = mpc83xx_spi_setup_transfer(spi, NULL);
 459         if (retval < 0) {
 460                 cs->hw_mode = hw_mode; /* Restore settings */
 461                 return retval;
 462         }
 463
 464 #if 0 /* Don't think this is needed */
 465         /* NOTE we _need_ to call chipselect() early, ideally with adapter
 466          * setup, unless the hardware defaults cooperate to avoid confusion
 467          * between normal (active low) and inverted chipselects.
 468          */
 469
 470         /* deselect chip (low or high) */
 471         spin_lock(&mpc83xx_spi->lock);
 472         if (!mpc83xx_spi->busy)
 473                 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 474         spin_unlock(&mpc83xx_spi->lock);
 475 #endif
 476         return 0;
 477 }
 478
 479 static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
 480 {
 481         struct mpc83xx_spi *mpc83xx_spi = context_data;
 482         u32 event;
 483         irqreturn_t ret = IRQ_NONE;
 484
 485         /* Get interrupt events(tx/rx) */
 486         event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
 487
 488         /* We need handle RX first */
 489         if (event & SPIE_NE) {
 490                 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
 491
 492                 if (mpc83xx_spi->rx)
 493                         mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
 494
 495                 ret = IRQ_HANDLED;
 496         }
 497
 498         if ((event & SPIE_NF) == 0)
 499                 /* spin until TX is done */
 500                 while (((event =
 501                          mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
 502                                                 SPIE_NF) == 0)
 503                         cpu_relax();
 504
 505         mpc83xx_spi->count -= 1;
 506         if (mpc83xx_spi->count) {
 507                 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
 508                 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 509         } else {
 510                 complete(&mpc83xx_spi->done);
 511         }
 512
 513         /* Clear the events */
 514         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
 515
 516         return ret;
 517 }
 518 static int mpc83xx_spi_transfer(struct spi_device *spi,
 519                                 struct spi_message *m)
 520 {
 521         struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
 522         unsigned long flags;
 523
 524         m->actual_length = 0;
 525         m->status = -EINPROGRESS;
 526
 527         spin_lock_irqsave(&mpc83xx_spi->lock, flags);
 528         list_add_tail(&m->queue, &mpc83xx_spi->queue);
 529         queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
 530         spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
 531
 532         return 0;
 533 }
 534
 535
 536 static void mpc83xx_spi_cleanup(struct spi_device *spi)
 537 {
 538         kfree(spi->controller_state);
 539 }
 540
 541 static struct spi_master * __devinit
 542 mpc83xx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
 543 {
 544         struct fsl_spi_platform_data *pdata = dev->platform_data;
 545         struct spi_master *master;
 546         struct mpc83xx_spi *mpc83xx_spi;
 547         u32 regval;
 548         int ret = 0;
 549
 550         master = spi_alloc_master(dev, sizeof(struct mpc83xx_spi));
 551         if (master == NULL) {
 552                 ret = -ENOMEM;
 553                 goto err;
 554         }
 555
 556         dev_set_drvdata(dev, master);
 557
 558         /* the spi->mode bits understood by this driver: */
 559         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
 560                         | SPI_LSB_FIRST | SPI_LOOP;
 561
 562         master->setup = mpc83xx_spi_setup;
 563         master->transfer = mpc83xx_spi_transfer;
 564         master->cleanup = mpc83xx_spi_cleanup;
 565
 566         mpc83xx_spi = spi_master_get_devdata(master);
 567         mpc83xx_spi->qe_mode = pdata->qe_mode;
 568         mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 569         mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 570         mpc83xx_spi->spibrg = pdata->sysclk;
 571
 572         mpc83xx_spi->rx_shift = 0;
 573         mpc83xx_spi->tx_shift = 0;
 574         if (mpc83xx_spi->qe_mode) {
 575                 mpc83xx_spi->rx_shift = 16;
 576                 mpc83xx_spi->tx_shift = 24;
 577         }
 578
 579         init_completion(&mpc83xx_spi->done);
 580
 581         mpc83xx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
 582         if (mpc83xx_spi->base == NULL) {
 583                 ret = -ENOMEM;
 584                 goto put_master;
 585         }
 586
 587         mpc83xx_spi->irq = irq;
 588
 589         /* Register for SPI Interrupt */
 590         ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
 591                           0, "mpc83xx_spi", mpc83xx_spi);
 592
 593         if (ret != 0)
 594                 goto unmap_io;
 595
 596         master->bus_num = pdata->bus_num;
 597         master->num_chipselect = pdata->max_chipselect;
 598
 599         /* SPI controller initializations */
 600         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 601         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 602         mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
 603         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
 604
 605         /* Enable SPI interface */
 606         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 607         if (pdata->qe_mode)
 608                 regval |= SPMODE_OP;
 609
 610         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 611         spin_lock_init(&mpc83xx_spi->lock);
 612         init_completion(&mpc83xx_spi->done);
 613         INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
 614         INIT_LIST_HEAD(&mpc83xx_spi->queue);
 615
 616         mpc83xx_spi->workqueue = create_singlethread_workqueue(
 617                 dev_name(master->dev.parent));
 618         if (mpc83xx_spi->workqueue == NULL) {
 619                 ret = -EBUSY;
 620                 goto free_irq;
 621         }
 622
 623         ret = spi_register_master(master);
 624         if (ret < 0)
 625                 goto unreg_master;
 626
 627         printk(KERN_INFO
 628                "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
 629                dev_name(dev), mpc83xx_spi->base, mpc83xx_spi->irq);
 630
 631         return master;
 632
 633 unreg_master:
 634         destroy_workqueue(mpc83xx_spi->workqueue);
 635 free_irq:
 636         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 637 unmap_io:
 638         iounmap(mpc83xx_spi->base);
 639 put_master:
 640         spi_master_put(master);
 641 err:
 642         return ERR_PTR(ret);
 643 }
 644
 645 static int __devexit mpc83xx_spi_remove(struct device *dev)
 646 {
 647         struct mpc83xx_spi *mpc83xx_spi;
 648         struct spi_master *master;
 649
 650         master = dev_get_drvdata(dev);
 651         mpc83xx_spi = spi_master_get_devdata(master);
 652
 653         flush_workqueue(mpc83xx_spi->workqueue);
 654         destroy_workqueue(mpc83xx_spi->workqueue);
 655         spi_unregister_master(master);
 656
 657         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 658         iounmap(mpc83xx_spi->base);
 659
 660         return 0;
 661 }
 662
 663 struct mpc83xx_spi_probe_info {
 664         struct fsl_spi_platform_data pdata;
 665         int *gpios;
 666         bool *alow_flags;
 667 };
 668
 669 static struct mpc83xx_spi_probe_info *
 670 to_of_pinfo(struct fsl_spi_platform_data *pdata)
 671 {
 672         return container_of(pdata, struct mpc83xx_spi_probe_info, pdata);
 673 }
 674
 675 static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
 676 {
 677         struct device *dev = spi->dev.parent;
 678         struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
 679         u16 cs = spi->chip_select;
 680         int gpio = pinfo->gpios[cs];
 681         bool alow = pinfo->alow_flags[cs];
 682
 683         gpio_set_value(gpio, on ^ alow);
 684 }
 685
 686 static int of_mpc83xx_spi_get_chipselects(struct device *dev)
 687 {
 688         struct device_node *np = dev_archdata_get_node(&dev->archdata);
 689         struct fsl_spi_platform_data *pdata = dev->platform_data;
 690         struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 691         unsigned int ngpios;
 692         int i = 0;
 693         int ret;
 694
 695         ngpios = of_gpio_count(np);
 696         if (!ngpios) {
 697                 /*
 698                  * SPI w/o chip-select line. One SPI device is still permitted
 699                  * though.
 700                  */
 701                 pdata->max_chipselect = 1;
 702                 return 0;
 703         }
 704
 705         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
 706         if (!pinfo->gpios)
 707                 return -ENOMEM;
 708         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 709
 710         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
 711                                     GFP_KERNEL);
 712         if (!pinfo->alow_flags) {
 713                 ret = -ENOMEM;
 714                 goto err_alloc_flags;
 715         }
 716
 717         for (; i < ngpios; i++) {
 718                 int gpio;
 719                 enum of_gpio_flags flags;
 720
 721                 gpio = of_get_gpio_flags(np, i, &flags);
 722                 if (!gpio_is_valid(gpio)) {
 723                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 724                         goto err_loop;
 725                 }
 726
 727                 ret = gpio_request(gpio, dev_name(dev));
 728                 if (ret) {
 729                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 730                         goto err_loop;
 731                 }
 732
 733                 pinfo->gpios[i] = gpio;
 734                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 735
 736                 ret = gpio_direction_output(pinfo->gpios[i],
 737                                             pinfo->alow_flags[i]);
 738                 if (ret) {
 739                         dev_err(dev, "can't set output direction for gpio "
 740                                 "#%d: %d\n", i, ret);
 741                         goto err_loop;
 742                 }
 743         }
 744
 745         pdata->max_chipselect = ngpios;
 746         pdata->cs_control = mpc83xx_spi_cs_control;
 747
 748         return 0;
 749
 750 err_loop:
 751         while (i >= 0) {
 752                 if (gpio_is_valid(pinfo->gpios[i]))
 753                         gpio_free(pinfo->gpios[i]);
 754                 i--;
 755         }
 756
 757         kfree(pinfo->alow_flags);
 758         pinfo->alow_flags = NULL;
 759 err_alloc_flags:
 760         kfree(pinfo->gpios);
 761         pinfo->gpios = NULL;
 762         return ret;
 763 }
 764
 765 static int of_mpc83xx_spi_free_chipselects(struct device *dev)
 766 {
 767         struct fsl_spi_platform_data *pdata = dev->platform_data;
 768         struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 769         int i;
 770
 771         if (!pinfo->gpios)
 772                 return 0;
 773
 774         for (i = 0; i < pdata->max_chipselect; i++) {
 775                 if (gpio_is_valid(pinfo->gpios[i]))
 776                         gpio_free(pinfo->gpios[i]);
 777         }
 778
 779         kfree(pinfo->gpios);
 780         kfree(pinfo->alow_flags);
 781         return 0;
 782 }
 783
 784 static int __devinit of_mpc83xx_spi_probe(struct of_device *ofdev,
 785                                           const struct of_device_id *ofid)
 786 {
 787         struct device *dev = &ofdev->dev;
 788         struct device_node *np = ofdev->node;
 789         struct mpc83xx_spi_probe_info *pinfo;
 790         struct fsl_spi_platform_data *pdata;
 791         struct spi_master *master;
 792         struct resource mem;
 793         struct resource irq;
 794         const void *prop;
 795         int ret = -ENOMEM;
 796
 797         pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
 798         if (!pinfo)
 799                 return -ENOMEM;
 800
 801         pdata = &pinfo->pdata;
 802         dev->platform_data = pdata;
 803
 804         /* Allocate bus num dynamically. */
 805         pdata->bus_num = -1;
 806
 807         /* SPI controller is either clocked from QE or SoC clock. */
 808         pdata->sysclk = get_brgfreq();
 809         if (pdata->sysclk == -1) {
 810                 pdata->sysclk = fsl_get_sys_freq();
 811                 if (pdata->sysclk == -1) {
 812                         ret = -ENODEV;
 813                         goto err_clk;
 814                 }
 815         }
 816
 817         prop = of_get_property(np, "mode", NULL);
 818         if (prop && !strcmp(prop, "cpu-qe"))
 819                 pdata->qe_mode = 1;
 820
 821         ret = of_mpc83xx_spi_get_chipselects(dev);
 822         if (ret)
 823                 goto err;
 824
 825         ret = of_address_to_resource(np, 0, &mem);
 826         if (ret)
 827                 goto err;
 828
 829         ret = of_irq_to_resource(np, 0, &irq);
 830         if (!ret) {
 831                 ret = -EINVAL;
 832                 goto err;
 833         }
 834
 835         master = mpc83xx_spi_probe(dev, &mem, irq.start);
 836         if (IS_ERR(master)) {
 837                 ret = PTR_ERR(master);
 838                 goto err;
 839         }
 840
 841         of_register_spi_devices(master, np);
 842
 843         return 0;
 844
 845 err:
 846         of_mpc83xx_spi_free_chipselects(dev);
 847 err_clk:
 848         kfree(pinfo);
 849         return ret;
 850 }
 851
 852 static int __devexit of_mpc83xx_spi_remove(struct of_device *ofdev)
 853 {
 854         int ret;
 855
 856         ret = mpc83xx_spi_remove(&ofdev->dev);
 857         if (ret)
 858                 return ret;
 859         of_mpc83xx_spi_free_chipselects(&ofdev->dev);
 860         return 0;
 861 }
 862
 863 static const struct of_device_id of_mpc83xx_spi_match[] = {
 864         { .compatible = "fsl,spi" },
 865         {},
 866 };
 867 MODULE_DEVICE_TABLE(of, of_mpc83xx_spi_match);
 868
 869 static struct of_platform_driver of_mpc83xx_spi_driver = {
 870         .name           = "mpc83xx_spi",
 871         .match_table    = of_mpc83xx_spi_match,
 872         .probe          = of_mpc83xx_spi_probe,
 873         .remove         = __devexit_p(of_mpc83xx_spi_remove),
 874 };
 875
 876 #ifdef CONFIG_MPC832x_RDB
 877 /*
 878  *                              XXX XXX XXX
 879  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 880  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 881  * tree can work with OpenFirmware driver. But for now we support old trees
 882  * as well.
 883  */
 884 static int __devinit plat_mpc83xx_spi_probe(struct platform_device *pdev)
 885 {
 886         struct resource *mem;
 887         unsigned int irq;
 888         struct spi_master *master;
 889
 890         if (!pdev->dev.platform_data)
 891                 return -EINVAL;
 892
 893         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 894         if (!mem)
 895                 return -EINVAL;
 896
 897         irq = platform_get_irq(pdev, 0);
 898         if (!irq)
 899                 return -EINVAL;
 900
 901         master = mpc83xx_spi_probe(&pdev->dev, mem, irq);
 902         if (IS_ERR(master))
 903                 return PTR_ERR(master);
 904         return 0;
 905 }
 906
 907 static int __devexit plat_mpc83xx_spi_remove(struct platform_device *pdev)
 908 {
 909         return mpc83xx_spi_remove(&pdev->dev);
 910 }
 911
 912 MODULE_ALIAS("platform:mpc83xx_spi");
 913 static struct platform_driver mpc83xx_spi_driver = {
 914         .probe = plat_mpc83xx_spi_probe,
 915         .remove = __exit_p(plat_mpc83xx_spi_remove),
 916         .driver = {
 917                 .name = "mpc83xx_spi",
 918                 .owner = THIS_MODULE,
 919         },
 920 };
 921
 922 static bool legacy_driver_failed;
 923
 924 static void __init legacy_driver_register(void)
 925 {
 926         legacy_driver_failed = platform_driver_register(&mpc83xx_spi_driver);
 927 }
 928
 929 static void __exit legacy_driver_unregister(void)
 930 {
 931         if (legacy_driver_failed)
 932                 return;
 933         platform_driver_unregister(&mpc83xx_spi_driver);
 934 }
 935 #else
 936 static void __init legacy_driver_register(void) {}
 937 static void __exit legacy_driver_unregister(void) {}
 938 #endif /* CONFIG_MPC832x_RDB */
 939
 940 static int __init mpc83xx_spi_init(void)
 941 {
 942         legacy_driver_register();
 943         return of_register_platform_driver(&of_mpc83xx_spi_driver);
 944 }
 945
 946 static void __exit mpc83xx_spi_exit(void)
 947 {
 948         of_unregister_platform_driver(&of_mpc83xx_spi_driver);
 949         legacy_driver_unregister();
 950 }
 951
 952 module_init(mpc83xx_spi_init);
 953 module_exit(mpc83xx_spi_exit);
 954
 955 MODULE_AUTHOR("Kumar Gala");
 956 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
 957 MODULE_LICENSE("GPL");