drivers/net/wireless/ath9k/core.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef CORE_H
  18 #define CORE_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <net/mac80211.h>
  23 #include <linux/leds.h>
  24 #include <linux/rfkill.h>
  25
  26 #include "ath9k.h"
  27 #include "rc.h"
  28
  29 struct ath_node;
  30
  31 /* Macro to expand scalars to 64-bit objects */
  32
  33 #define ito64(x) (sizeof(x) == 8) ?                     \
  34         (((unsigned long long int)(x)) & (0xff)) :      \
  35         (sizeof(x) == 16) ?                             \
  36         (((unsigned long long int)(x)) & 0xffff) :      \
  37         ((sizeof(x) == 32) ?                            \
  38          (((unsigned long long int)(x)) & 0xffffffff) : \
  39          (unsigned long long int)(x))
  40
  41 /* increment with wrap-around */
  42 #define INCR(_l, _sz)   do {                    \
  43                 (_l)++;                         \
  44                 (_l) &= ((_sz) - 1);            \
  45         } while (0)
  46
  47 /* decrement with wrap-around */
  48 #define DECR(_l,  _sz)  do {                    \
  49                 (_l)--;                         \
  50                 (_l) &= ((_sz) - 1);            \
  51         } while (0)
  52
  53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
  54
  55 #define ASSERT(exp) do {                        \
  56                 if (unlikely(!(exp))) {         \
  57                         BUG();                  \
  58                 }                               \
  59         } while (0)
  60
  61 #define TSF_TO_TU(_h,_l) \
  62         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  63
  64 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  65
  66 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  67
  68 enum ATH_DEBUG {
  69         ATH_DBG_RESET           = 0x00000001,
  70         ATH_DBG_REG_IO          = 0x00000002,
  71         ATH_DBG_QUEUE           = 0x00000004,
  72         ATH_DBG_EEPROM          = 0x00000008,
  73         ATH_DBG_CALIBRATE       = 0x00000010,
  74         ATH_DBG_CHANNEL         = 0x00000020,
  75         ATH_DBG_INTERRUPT       = 0x00000040,
  76         ATH_DBG_REGULATORY      = 0x00000080,
  77         ATH_DBG_ANI             = 0x00000100,
  78         ATH_DBG_POWER_MGMT      = 0x00000200,
  79         ATH_DBG_XMIT            = 0x00000400,
  80         ATH_DBG_BEACON          = 0x00001000,
  81         ATH_DBG_CONFIG          = 0x00002000,
  82         ATH_DBG_KEYCACHE        = 0x00004000,
  83         ATH_DBG_FATAL           = 0x00008000,
  84         ATH_DBG_ANY             = 0xffffffff
  85 };
  86
  87 #define DBG_DEFAULT (ATH_DBG_FATAL)
  88
  89 #ifdef CONFIG_ATH9K_DEBUG
  90
  91 /**
  92  * struct ath_interrupt_stats - Contains statistics about interrupts
  93  * @total: Total no. of interrupts generated so far
  94  * @rxok: RX with no errors
  95  * @rxeol: RX with no more RXDESC available
  96  * @rxorn: RX FIFO overrun
  97  * @txok: TX completed at the requested rate
  98  * @txurn: TX FIFO underrun
  99  * @mib: MIB regs reaching its threshold
 100  * @rxphyerr: RX with phy errors
 101  * @rx_keycache_miss: RX with key cache misses
 102  * @swba: Software Beacon Alert
 103  * @bmiss: Beacon Miss
 104  * @bnr: Beacon Not Ready
 105  * @cst: Carrier Sense TImeout
 106  * @gtt: Global TX Timeout
 107  * @tim: RX beacon TIM occurrence
 108  * @cabend: RX End of CAB traffic
 109  * @dtimsync: DTIM sync lossage
 110  * @dtim: RX Beacon with DTIM
 111  */
 112 struct ath_interrupt_stats {
 113         u32 total;
 114         u32 rxok;
 115         u32 rxeol;
 116         u32 rxorn;
 117         u32 txok;
 118         u32 txeol;
 119         u32 txurn;
 120         u32 mib;
 121         u32 rxphyerr;
 122         u32 rx_keycache_miss;
 123         u32 swba;
 124         u32 bmiss;
 125         u32 bnr;
 126         u32 cst;
 127         u32 gtt;
 128         u32 tim;
 129         u32 cabend;
 130         u32 dtimsync;
 131         u32 dtim;
 132 };
 133
 134 struct ath_stats {
 135         struct ath_interrupt_stats istats;
 136 };
 137
 138 struct ath9k_debug {
 139         int debug_mask;
 140         struct dentry *debugfs_root;
 141         struct dentry *debugfs_phy;
 142         struct dentry *debugfs_dma;
 143         struct dentry *debugfs_interrupt;
 144         struct ath_stats stats;
 145 };
 146
 147 void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
 148 int ath9k_init_debug(struct ath_softc *sc);
 149 void ath9k_exit_debug(struct ath_softc *sc);
 150 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
 151
 152 #else
 153
 154 static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
 155                            const char *fmt, ...)
 156 {
 157 }
 158
 159 static inline int ath9k_init_debug(struct ath_softc *sc)
 160 {
 161         return 0;
 162 }
 163
 164 static inline void ath9k_exit_debug(struct ath_softc *sc)
 165 {
 166 }
 167
 168 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
 169                                             enum ath9k_int status)
 170 {
 171 }
 172
 173 #endif /* CONFIG_ATH9K_DEBUG */
 174
 175 struct ath_config {
 176         u32 ath_aggr_prot;
 177         u16 txpowlimit;
 178         u16 txpowlimit_override;
 179         u8 cabqReadytime;
 180         u8 swBeaconProcess;
 181 };
 182
 183 /*************************/
 184 /* Descriptor Management */
 185 /*************************/
 186
 187 #define ATH_TXBUF_RESET(_bf) do {                               \
 188                 (_bf)->bf_status = 0;                           \
 189                 (_bf)->bf_lastbf = NULL;                        \
 190                 (_bf)->bf_lastfrm = NULL;                       \
 191                 (_bf)->bf_next = NULL;                          \
 192                 memset(&((_bf)->bf_state), 0,                   \
 193                             sizeof(struct ath_buf_state));      \
 194         } while (0)
 195
 196 enum buffer_type {
 197         BUF_DATA                = BIT(0),
 198         BUF_AGGR                = BIT(1),
 199         BUF_AMPDU               = BIT(2),
 200         BUF_HT                  = BIT(3),
 201         BUF_RETRY               = BIT(4),
 202         BUF_XRETRY              = BIT(5),
 203         BUF_SHORT_PREAMBLE      = BIT(6),
 204         BUF_BAR                 = BIT(7),
 205         BUF_PSPOLL              = BIT(8),
 206         BUF_AGGR_BURST          = BIT(9),
 207         BUF_CALC_AIRTIME        = BIT(10),
 208 };
 209
 210 struct ath_buf_state {
 211         int bfs_nframes;                /* # frames in aggregate */
 212         u16 bfs_al;                     /* length of aggregate */
 213         u16 bfs_frmlen;                 /* length of frame */
 214         int bfs_seqno;                  /* sequence number */
 215         int bfs_tidno;                  /* tid of this frame */
 216         int bfs_retries;                /* current retries */
 217         u32 bf_type;                    /* BUF_* (enum buffer_type) */
 218         u32 bfs_keyix;
 219         enum ath9k_key_type bfs_keytype;
 220 };
 221
 222 #define bf_nframes              bf_state.bfs_nframes
 223 #define bf_al                   bf_state.bfs_al
 224 #define bf_frmlen               bf_state.bfs_frmlen
 225 #define bf_retries              bf_state.bfs_retries
 226 #define bf_seqno                bf_state.bfs_seqno
 227 #define bf_tidno                bf_state.bfs_tidno
 228 #define bf_rcs                  bf_state.bfs_rcs
 229 #define bf_keyix                bf_state.bfs_keyix
 230 #define bf_keytype              bf_state.bfs_keytype
 231 #define bf_isdata(bf)           (bf->bf_state.bf_type & BUF_DATA)
 232 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
 233 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 234 #define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 235 #define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 236 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 237 #define bf_isshpreamble(bf)     (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
 238 #define bf_isbar(bf)            (bf->bf_state.bf_type & BUF_BAR)
 239 #define bf_ispspoll(bf)         (bf->bf_state.bf_type & BUF_PSPOLL)
 240 #define bf_isaggrburst(bf)      (bf->bf_state.bf_type & BUF_AGGR_BURST)
 241
 242 /*
 243  * Abstraction of a contiguous buffer to transmit/receive.  There is only
 244  * a single hw descriptor encapsulated here.
 245  */
 246 struct ath_buf {
 247         struct list_head list;
 248         struct list_head *last;
 249         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 250                                            an aggregate) */
 251         struct ath_buf *bf_lastfrm;     /* last buf of this frame */
 252         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 253         void *bf_mpdu;                  /* enclosing frame structure */
 254         struct ath_desc *bf_desc;       /* virtual addr of desc */
 255         dma_addr_t bf_daddr;            /* physical addr of desc */
 256         dma_addr_t bf_buf_addr;         /* physical addr of data buffer */
 257         u32 bf_status;
 258         u16 bf_flags;                   /* tx descriptor flags */
 259         struct ath_buf_state bf_state;  /* buffer state */
 260         dma_addr_t bf_dmacontext;
 261 };
 262
 263 #define ATH_RXBUF_RESET(_bf)    ((_bf)->bf_status = 0)
 264
 265 /* hw processing complete, desc processed by hal */
 266 #define ATH_BUFSTATUS_DONE      0x00000001
 267 /* hw processing complete, desc hold for hw */
 268 #define ATH_BUFSTATUS_STALE     0x00000002
 269 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
 270 #define ATH_BUFSTATUS_FREE      0x00000004
 271
 272 /* DMA state for tx/rx descriptors */
 273
 274 struct ath_descdma {
 275         const char *dd_name;
 276         struct ath_desc *dd_desc;       /* descriptors  */
 277         dma_addr_t dd_desc_paddr;       /* physical addr of dd_desc  */
 278         u32 dd_desc_len;                /* size of dd_desc  */
 279         struct ath_buf *dd_bufptr;      /* associated buffers */
 280         dma_addr_t dd_dmacontext;
 281 };
 282
 283 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 284                       struct list_head *head, const char *name,
 285                       int nbuf, int ndesc);
 286 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 287                          struct list_head *head);
 288
 289 /***********/
 290 /* RX / TX */
 291 /***********/
 292
 293 #define ATH_MAX_ANTENNA         3
 294 #define ATH_RXBUF               512
 295 #define WME_NUM_TID             16
 296 #define ATH_TXBUF               512
 297 #define ATH_TXMAXTRY            13
 298 #define ATH_11N_TXMAXTRY        10
 299 #define ATH_MGT_TXMAXTRY        4
 300 #define WME_BA_BMP_SIZE         64
 301 #define WME_MAX_BA              WME_BA_BMP_SIZE
 302 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 303
 304 #define TID_TO_WME_AC(_tid)                             \
 305         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 306          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 307          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 308          WME_AC_VO)
 309
 310 #define WME_AC_BE   0
 311 #define WME_AC_BK   1
 312 #define WME_AC_VI   2
 313 #define WME_AC_VO   3
 314 #define WME_NUM_AC  4
 315
 316 #define ADDBA_EXCHANGE_ATTEMPTS    10
 317 #define ATH_AGGR_DELIM_SZ          4
 318 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 319 /* number of delimiters for encryption padding */
 320 #define ATH_AGGR_ENCRYPTDELIM      10
 321 /* minimum h/w qdepth to be sustained to maximize aggregation */
 322 #define ATH_AGGR_MIN_QDEPTH        2
 323 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 324 #define IEEE80211_SEQ_SEQ_SHIFT    4
 325 #define IEEE80211_SEQ_MAX          4096
 326 #define IEEE80211_MIN_AMPDU_BUF    0x8
 327 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
 328
 329 /* return whether a bit at index _n in bitmap _bm is set
 330  * _sz is the size of the bitmap  */
 331 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 332                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 333
 334 /* return block-ack bitmap index given sequence and starting sequence */
 335 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 336
 337 /* returns delimiter padding required given the packet length */
 338 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 339         (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 340           (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 341
 342 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 343         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 344
 345 #define ATH_DS_BA_SEQ(_ds)         ((_ds)->ds_us.tx.ts_seqnum)
 346 #define ATH_DS_BA_BITMAP(_ds)      (&(_ds)->ds_us.tx.ba_low)
 347 #define ATH_DS_TX_BA(_ds)          ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 348 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 349
 350 enum ATH_AGGR_STATUS {
 351         ATH_AGGR_DONE,
 352         ATH_AGGR_BAW_CLOSED,
 353         ATH_AGGR_LIMITED,
 354         ATH_AGGR_SHORTPKT,
 355         ATH_AGGR_8K_LIMITED,
 356 };
 357
 358 struct ath_txq {
 359         u32 axq_qnum;                   /* hardware q number */
 360         u32 *axq_link;                  /* link ptr in last TX desc */
 361         struct list_head axq_q;         /* transmit queue */
 362         spinlock_t axq_lock;
 363         unsigned long axq_lockflags;    /* intr state when must cli */
 364         u32 axq_depth;                  /* queue depth */
 365         u8 axq_aggr_depth;              /* aggregates queued */
 366         u32 axq_totalqueued;            /* total ever queued */
 367         bool stopped;                   /* Is mac80211 queue stopped ? */
 368         struct ath_buf *axq_linkbuf;    /* virtual addr of last buffer*/
 369
 370         /* first desc of the last descriptor that contains CTS */
 371         struct ath_desc *axq_lastdsWithCTS;
 372
 373         /* final desc of the gating desc that determines whether
 374            lastdsWithCTS has been DMA'ed or not */
 375         struct ath_desc *axq_gatingds;
 376
 377         struct list_head axq_acq;
 378 };
 379
 380 #define AGGR_CLEANUP         BIT(1)
 381 #define AGGR_ADDBA_COMPLETE  BIT(2)
 382 #define AGGR_ADDBA_PROGRESS  BIT(3)
 383
 384 /* per TID aggregate tx state for a destination */
 385 struct ath_atx_tid {
 386         struct list_head list;          /* round-robin tid entry */
 387         struct list_head buf_q;         /* pending buffers */
 388         struct ath_node *an;
 389         struct ath_atx_ac *ac;
 390         struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
 391         u16 seq_start;
 392         u16 seq_next;
 393         u16 baw_size;
 394         int tidno;
 395         int baw_head;                   /* first un-acked tx buffer */
 396         int baw_tail;                   /* next unused tx buffer slot */
 397         int sched;
 398         int paused;
 399         u8 state;
 400         int addba_exchangeattempts;
 401 };
 402
 403 /* per access-category aggregate tx state for a destination */
 404 struct ath_atx_ac {
 405         int sched;                      /* dest-ac is scheduled */
 406         int qnum;                       /* H/W queue number associated
 407                                            with this AC */
 408         struct list_head list;          /* round-robin txq entry */
 409         struct list_head tid_q;         /* queue of TIDs with buffers */
 410 };
 411
 412 /* per-frame tx control block */
 413 struct ath_tx_control {
 414         struct ath_txq *txq;
 415         int if_id;
 416 };
 417
 418 /* per frame tx status block */
 419 struct ath_xmit_status {
 420         int retries;    /* number of retries to successufully
 421                            transmit this frame */
 422         int flags;      /* status of transmit */
 423 #define ATH_TX_ERROR        0x01
 424 #define ATH_TX_XRETRY       0x02
 425 #define ATH_TX_BAR          0x04
 426 };
 427
 428 /* All RSSI values are noise floor adjusted */
 429 struct ath_tx_stat {
 430         int rssi;
 431         int rssictl[ATH_MAX_ANTENNA];
 432         int rssiextn[ATH_MAX_ANTENNA];
 433         int rateieee;
 434         int rateKbps;
 435         int ratecode;
 436         int flags;
 437         u32 airtime;    /* time on air per final tx rate */
 438 };
 439
 440 struct aggr_rifs_param {
 441         int param_max_frames;
 442         int param_max_len;
 443         int param_rl;
 444         int param_al;
 445         struct ath_rc_series *param_rcs;
 446 };
 447
 448 struct ath_node {
 449         struct ath_softc *an_sc;
 450         struct ath_atx_tid tid[WME_NUM_TID];
 451         struct ath_atx_ac ac[WME_NUM_AC];
 452         u16 maxampdu;
 453         u8 mpdudensity;
 454 };
 455
 456 struct ath_tx {
 457         u16 seq_no;
 458         u32 txqsetup;
 459         int hwq_map[ATH9K_WME_AC_VO+1];
 460         spinlock_t txbuflock;
 461         struct list_head txbuf;
 462         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 463         struct ath_descdma txdma;
 464 };
 465
 466 struct ath_rx {
 467         u8 defant;
 468         u8 rxotherant;
 469         u32 *rxlink;
 470         int bufsize;
 471         unsigned int rxfilter;
 472         spinlock_t rxflushlock;
 473         spinlock_t rxbuflock;
 474         struct list_head rxbuf;
 475         struct ath_descdma rxdma;
 476 };
 477
 478 int ath_startrecv(struct ath_softc *sc);
 479 bool ath_stoprecv(struct ath_softc *sc);
 480 void ath_flushrecv(struct ath_softc *sc);
 481 u32 ath_calcrxfilter(struct ath_softc *sc);
 482 int ath_rx_init(struct ath_softc *sc, int nbufs);
 483 void ath_rx_cleanup(struct ath_softc *sc);
 484 int ath_rx_tasklet(struct ath_softc *sc, int flush);
 485 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 486 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 487 int ath_tx_setup(struct ath_softc *sc, int haltype);
 488 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
 489 void ath_tx_draintxq(struct ath_softc *sc,
 490                      struct ath_txq *txq, bool retry_tx);
 491 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 492 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 493 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
 494 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 495 int ath_tx_init(struct ath_softc *sc, int nbufs);
 496 int ath_tx_cleanup(struct ath_softc *sc);
 497 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
 498 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
 499 int ath_txq_update(struct ath_softc *sc, int qnum,
 500                    struct ath9k_tx_queue_info *q);
 501 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
 502                  struct ath_tx_control *txctl);
 503 void ath_tx_tasklet(struct ath_softc *sc);
 504 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
 505 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
 506 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
 507 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid);
 508 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
 509 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno);
 510 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 511                       u16 tid, u16 *ssn);
 512 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 513 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 514
 515 /********/
 516 /* VAPs */
 517 /********/
 518
 519 /*
 520  * Define the scheme that we select MAC address for multiple
 521  * BSS on the same radio. The very first VAP will just use the MAC
 522  * address from the EEPROM. For the next 3 VAPs, we set the
 523  * U/L bit (bit 1) in MAC address, and use the next two bits as the
 524  * index of the VAP.
 525  */
 526
 527 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
 528         ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
 529
 530 struct ath_vap {
 531         int av_bslot;
 532         enum nl80211_iftype av_opmode;
 533         struct ath_buf *av_bcbuf;
 534         struct ath_tx_control av_btxctl;
 535 };
 536
 537 /*******************/
 538 /* Beacon Handling */
 539 /*******************/
 540
 541 /*
 542  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 543  * number of BSSIDs) if a given beacon does not go out even after waiting this
 544  * number of beacon intervals, the game's up.
 545  */
 546 #define BSTUCK_THRESH                   (9 * ATH_BCBUF)
 547 #define ATH_BCBUF                       1
 548 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 549 #define ATH_DEFAULT_BMISS_LIMIT         10
 550 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 551
 552 struct ath_beacon_config {
 553         u16 beacon_interval;
 554         u16 listen_interval;
 555         u16 dtim_period;
 556         u16 bmiss_timeout;
 557         u8 dtim_count;
 558         u8 tim_offset;
 559         union {
 560                 u64 last_tsf;
 561                 u8 last_tstamp[8];
 562         } u; /* last received beacon/probe response timestamp of this BSS. */
 563 };
 564
 565 struct ath_beacon {
 566         enum {
 567                 OK,             /* no change needed */
 568                 UPDATE,         /* update pending */
 569                 COMMIT          /* beacon sent, commit change */
 570         } updateslot;           /* slot time update fsm */
 571
 572         u32 beaconq;
 573         u32 bmisscnt;
 574         u32 ast_be_xmit;
 575         u64 bc_tstamp;
 576         int bslot[ATH_BCBUF];
 577         int slottime;
 578         int slotupdate;
 579         struct ath9k_tx_queue_info beacon_qi;
 580         struct ath_descdma bdma;
 581         struct ath_txq *cabq;
 582         struct list_head bbuf;
 583 };
 584
 585 void ath9k_beacon_tasklet(unsigned long data);
 586 void ath_beacon_config(struct ath_softc *sc, int if_id);
 587 int ath_beaconq_setup(struct ath_hal *ah);
 588 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
 589 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
 590 void ath_beacon_sync(struct ath_softc *sc, int if_id);
 591
 592 /*******/
 593 /* ANI */
 594 /*******/
 595
 596 /* ANI values for STA only.
 597    FIXME: Add appropriate values for AP later */
 598
 599 #define ATH_ANI_POLLINTERVAL    100     /* 100 milliseconds between ANI poll */
 600 #define ATH_SHORT_CALINTERVAL   1000    /* 1 second between calibrations */
 601 #define ATH_LONG_CALINTERVAL    30000   /* 30 seconds between calibrations */
 602 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
 603
 604 struct ath_ani {
 605         bool sc_caldone;
 606         int16_t sc_noise_floor;
 607         unsigned int sc_longcal_timer;
 608         unsigned int sc_shortcal_timer;
 609         unsigned int sc_resetcal_timer;
 610         unsigned int sc_checkani_timer;
 611         struct timer_list timer;
 612 };
 613
 614 /********************/
 615 /*   LED Control    */
 616 /********************/
 617
 618 #define ATH_LED_PIN     1
 619
 620 enum ath_led_type {
 621         ATH_LED_RADIO,
 622         ATH_LED_ASSOC,
 623         ATH_LED_TX,
 624         ATH_LED_RX
 625 };
 626
 627 struct ath_led {
 628         struct ath_softc *sc;
 629         struct led_classdev led_cdev;
 630         enum ath_led_type led_type;
 631         char name[32];
 632         bool registered;
 633 };
 634
 635 /* Rfkill */
 636 #define ATH_RFKILL_POLL_INTERVAL        2000 /* msecs */
 637
 638 struct ath_rfkill {
 639         struct rfkill *rfkill;
 640         struct delayed_work rfkill_poll;
 641         char rfkill_name[32];
 642 };
 643
 644 /********************/
 645 /* Main driver core */
 646 /********************/
 647
 648 /*
 649  * Default cache line size, in bytes.
 650  * Used when PCI device not fully initialized by bootrom/BIOS
 651 */
 652 #define DEFAULT_CACHELINE       32
 653 #define ATH_DEFAULT_NOISE_FLOOR -95
 654 #define ATH_REGCLASSIDS_MAX     10
 655 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 656 #define ATH_MAX_SW_RETRIES      10
 657 #define ATH_CHAN_MAX            255
 658 #define IEEE80211_WEP_NKID      4       /* number of key ids */
 659 #define IEEE80211_RATE_VAL      0x7f
 660 /*
 661  * The key cache is used for h/w cipher state and also for
 662  * tracking station state such as the current tx antenna.
 663  * We also setup a mapping table between key cache slot indices
 664  * and station state to short-circuit node lookups on rx.
 665  * Different parts have different size key caches.  We handle
 666  * up to ATH_KEYMAX entries (could dynamically allocate state).
 667  */
 668 #define ATH_KEYMAX              128     /* max key cache size we handle */
 669
 670 #define ATH_IF_ID_ANY           0xff
 671 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 672 #define ATH_RSSI_DUMMY_MARKER   0x127
 673 #define ATH_RATE_DUMMY_MARKER   0
 674
 675 enum PROT_MODE {
 676         PROT_M_NONE = 0,
 677         PROT_M_RTSCTS,
 678         PROT_M_CTSONLY
 679 };
 680
 681 #define SC_OP_INVALID           BIT(0)
 682 #define SC_OP_BEACONS           BIT(1)
 683 #define SC_OP_RXAGGR            BIT(2)
 684 #define SC_OP_TXAGGR            BIT(3)
 685 #define SC_OP_CHAINMASK_UPDATE  BIT(4)
 686 #define SC_OP_FULL_RESET        BIT(5)
 687 #define SC_OP_NO_RESET          BIT(6)
 688 #define SC_OP_PREAMBLE_SHORT    BIT(7)
 689 #define SC_OP_PROTECT_ENABLE    BIT(8)
 690 #define SC_OP_RXFLUSH           BIT(9)
 691 #define SC_OP_LED_ASSOCIATED    BIT(10)
 692 #define SC_OP_RFKILL_REGISTERED BIT(11)
 693 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
 694 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
 695
 696 struct ath_bus_ops {
 697         void            (*read_cachesize)(struct ath_softc *sc, int *csz);
 698         void            (*cleanup)(struct ath_softc *sc);
 699         bool            (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data);
 700 };
 701
 702 struct ath_softc {
 703         struct ieee80211_hw *hw;
 704         struct device *dev;
 705         struct tasklet_struct intr_tq;
 706         struct tasklet_struct bcon_tasklet;
 707         struct ath_hal *sc_ah;
 708         void __iomem *mem;
 709         int irq;
 710         spinlock_t sc_resetlock;
 711         struct mutex mutex;
 712
 713         u8 sc_curbssid[ETH_ALEN];
 714         u8 sc_myaddr[ETH_ALEN];
 715         u8 sc_bssidmask[ETH_ALEN];
 716         u32 sc_intrstatus;
 717         u32 sc_flags; /* SC_OP_* */
 718         u16 sc_curtxpow;
 719         u16 sc_curaid;
 720         u16 sc_cachelsz;
 721         u8 sc_nbcnvaps;
 722         u16 sc_nvaps;
 723         u8 sc_tx_chainmask;
 724         u8 sc_rx_chainmask;
 725         u32 sc_keymax;
 726         DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
 727         u8 sc_splitmic;
 728         enum ath9k_int sc_imask;
 729         enum PROT_MODE sc_protmode;
 730         enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
 731         enum ath9k_ht_macmode tx_chan_width;
 732
 733         struct ath_config sc_config;
 734         struct ath_rx rx;
 735         struct ath_tx tx;
 736         struct ath_beacon beacon;
 737         struct ieee80211_vif *sc_vaps[ATH_BCBUF];
 738         struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
 739         struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
 740         struct ath_rate_table *cur_rate_table;
 741         struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
 742         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 743         struct ath_led radio_led;
 744         struct ath_led assoc_led;
 745         struct ath_led tx_led;
 746         struct ath_led rx_led;
 747         struct ath_rfkill rf_kill;
 748         struct ath_ani sc_ani;
 749         struct ath9k_node_stats sc_halstats;
 750 #ifdef CONFIG_ATH9K_DEBUG
 751         struct ath9k_debug sc_debug;
 752 #endif
 753         struct ath_bus_ops *bus_ops;
 754 };
 755
 756 int ath_reset(struct ath_softc *sc, bool retry_tx);
 757 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
 758 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 759 int ath_cabq_update(struct ath_softc *);
 760
 761 static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
 762 {
 763         sc->bus_ops->read_cachesize(sc, csz);
 764 }
 765
 766 static inline void ath_bus_cleanup(struct ath_softc *sc)
 767 {
 768         sc->bus_ops->cleanup(sc);
 769 }
 770
 771 extern struct ieee80211_ops ath9k_ops;
 772
 773 irqreturn_t ath_isr(int irq, void *dev);
 774 void ath_cleanup(struct ath_softc *sc);
 775 int ath_attach(u16 devid, struct ath_softc *sc);
 776 void ath_detach(struct ath_softc *sc);
 777 const char *ath_mac_bb_name(u32 mac_bb_version);
 778 const char *ath_rf_name(u16 rf_version);
 779
 780 #ifdef CONFIG_PCI
 781 int ath_pci_init(void);
 782 void ath_pci_exit(void);
 783 #else
 784 static inline int ath_pci_init(void) { return 0; };
 785 static inline void ath_pci_exit(void) {};
 786 #endif
 787
 788 #ifdef CONFIG_ATHEROS_AR71XX
 789 int ath_ahb_init(void);
 790 void ath_ahb_exit(void);
 791 #else
 792 static inline int ath_ahb_init(void) { return 0; };
 793 static inline void ath_ahb_exit(void) {};
 794 #endif
 795
 796 #endif /* CORE_H */