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USB: implement "soft" unbinding
[linux-2.6/mini2440.git] / sound / pci / es1968.c
blob1bf298d214b90462cfe7b5253c7d4d0f6c097fd1
1 /*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
97 #include <asm/io.h>
98 #include <linux/delay.h>
99 #include <linux/interrupt.h>
100 #include <linux/init.h>
101 #include <linux/pci.h>
102 #include <linux/dma-mapping.h>
103 #include <linux/slab.h>
104 #include <linux/gameport.h>
105 #include <linux/moduleparam.h>
106 #include <linux/mutex.h>
107
108 #include <sound/core.h>
109 #include <sound/pcm.h>
110 #include <sound/mpu401.h>
111 #include <sound/ac97_codec.h>
112 #include <sound/initval.h>
113
114 #define CARD_NAME "ESS Maestro1/2"
115 #define DRIVER_NAME "ES1968"
116
117 MODULE_DESCRIPTION("ESS Maestro");
118 MODULE_LICENSE("GPL");
119 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
120 "{ESS,Maestro 2},"
121 "{ESS,Maestro 1},"
122 "{TerraTec,DMX}}");
123
124 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
125 #define SUPPORT_JOYSTICK 1
126 #endif
127
128 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
129 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
130 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
131 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
132 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
133 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
134 static int clock[SNDRV_CARDS];
135 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
136 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
137 #ifdef SUPPORT_JOYSTICK
138 static int joystick[SNDRV_CARDS];
139 #endif
140
141 module_param_array(index, int, NULL, 0444);
142 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
143 module_param_array(id, charp, NULL, 0444);
144 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
145 module_param_array(enable, bool, NULL, 0444);
146 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
147 module_param_array(total_bufsize, int, NULL, 0444);
148 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
149 module_param_array(pcm_substreams_p, int, NULL, 0444);
150 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
151 module_param_array(pcm_substreams_c, int, NULL, 0444);
152 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
153 module_param_array(clock, int, NULL, 0444);
154 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
155 module_param_array(use_pm, int, NULL, 0444);
156 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
157 module_param_array(enable_mpu, int, NULL, 0444);
158 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
159 #ifdef SUPPORT_JOYSTICK
160 module_param_array(joystick, bool, NULL, 0444);
161 MODULE_PARM_DESC(joystick, "Enable joystick.");
162 #endif
163
164
165 #define NR_APUS 64
166 #define NR_APU_REGS 16
167
168 /* NEC Versas ? */
169 #define NEC_VERSA_SUBID1 0x80581033
170 #define NEC_VERSA_SUBID2 0x803c1033
171
172 /* Mode Flags */
173 #define ESS_FMT_STEREO 0x01
174 #define ESS_FMT_16BIT 0x02
175
176 #define DAC_RUNNING 1
177 #define ADC_RUNNING 2
178
179 /* Values for the ESM_LEGACY_AUDIO_CONTROL */
180
181 #define ESS_DISABLE_AUDIO 0x8000
182 #define ESS_ENABLE_SERIAL_IRQ 0x4000
183 #define IO_ADRESS_ALIAS 0x0020
184 #define MPU401_IRQ_ENABLE 0x0010
185 #define MPU401_IO_ENABLE 0x0008
186 #define GAME_IO_ENABLE 0x0004
187 #define FM_IO_ENABLE 0x0002
188 #define SB_IO_ENABLE 0x0001
189
190 /* Values for the ESM_CONFIG_A */
191
192 #define PIC_SNOOP1 0x4000
193 #define PIC_SNOOP2 0x2000
194 #define SAFEGUARD 0x0800
195 #define DMA_CLEAR 0x0700
196 #define DMA_DDMA 0x0000
197 #define DMA_TDMA 0x0100
198 #define DMA_PCPCI 0x0200
199 #define POST_WRITE 0x0080
200 #define PCI_TIMING 0x0040
201 #define SWAP_LR 0x0020
202 #define SUBTR_DECODE 0x0002
203
204 /* Values for the ESM_CONFIG_B */
205
206 #define SPDIF_CONFB 0x0100
207 #define HWV_CONFB 0x0080
208 #define DEBOUNCE 0x0040
209 #define GPIO_CONFB 0x0020
210 #define CHI_CONFB 0x0010
211 #define IDMA_CONFB 0x0008 /*undoc */
212 #define MIDI_FIX 0x0004 /*undoc */
213 #define IRQ_TO_ISA 0x0001 /*undoc */
214
215 /* Values for Ring Bus Control B */
216 #define RINGB_2CODEC_ID_MASK 0x0003
217 #define RINGB_DIS_VALIDATION 0x0008
218 #define RINGB_EN_SPDIF 0x0010
219 #define RINGB_EN_2CODEC 0x0020
220 #define RINGB_SING_BIT_DUAL 0x0040
221
222 /* ****Port Adresses**** */
223
224 /* Write & Read */
225 #define ESM_INDEX 0x02
226 #define ESM_DATA 0x00
227
228 /* AC97 + RingBus */
229 #define ESM_AC97_INDEX 0x30
230 #define ESM_AC97_DATA 0x32
231 #define ESM_RING_BUS_DEST 0x34
232 #define ESM_RING_BUS_CONTR_A 0x36
233 #define ESM_RING_BUS_CONTR_B 0x38
234 #define ESM_RING_BUS_SDO 0x3A
235
236 /* WaveCache*/
237 #define WC_INDEX 0x10
238 #define WC_DATA 0x12
239 #define WC_CONTROL 0x14
240
241 /* ASSP*/
242 #define ASSP_INDEX 0x80
243 #define ASSP_MEMORY 0x82
244 #define ASSP_DATA 0x84
245 #define ASSP_CONTROL_A 0xA2
246 #define ASSP_CONTROL_B 0xA4
247 #define ASSP_CONTROL_C 0xA6
248 #define ASSP_HOSTW_INDEX 0xA8
249 #define ASSP_HOSTW_DATA 0xAA
250 #define ASSP_HOSTW_IRQ 0xAC
251 /* Midi */
252 #define ESM_MPU401_PORT 0x98
253 /* Others */
254 #define ESM_PORT_HOST_IRQ 0x18
255
256 #define IDR0_DATA_PORT 0x00
257 #define IDR1_CRAM_POINTER 0x01
258 #define IDR2_CRAM_DATA 0x02
259 #define IDR3_WAVE_DATA 0x03
260 #define IDR4_WAVE_PTR_LOW 0x04
261 #define IDR5_WAVE_PTR_HI 0x05
262 #define IDR6_TIMER_CTRL 0x06
263 #define IDR7_WAVE_ROMRAM 0x07
264
265 #define WRITEABLE_MAP 0xEFFFFF
266 #define READABLE_MAP 0x64003F
267
268 /* PCI Register */
269
270 #define ESM_LEGACY_AUDIO_CONTROL 0x40
271 #define ESM_ACPI_COMMAND 0x54
272 #define ESM_CONFIG_A 0x50
273 #define ESM_CONFIG_B 0x52
274 #define ESM_DDMA 0x60
275
276 /* Bob Bits */
277 #define ESM_BOB_ENABLE 0x0001
278 #define ESM_BOB_START 0x0001
279
280 /* Host IRQ Control Bits */
281 #define ESM_RESET_MAESTRO 0x8000
282 #define ESM_RESET_DIRECTSOUND 0x4000
283 #define ESM_HIRQ_ClkRun 0x0100
284 #define ESM_HIRQ_HW_VOLUME 0x0040
285 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */
286 #define ESM_HIRQ_ASSP 0x0010
287 #define ESM_HIRQ_DSIE 0x0004
288 #define ESM_HIRQ_MPU401 0x0002
289 #define ESM_HIRQ_SB 0x0001
290
291 /* Host IRQ Status Bits */
292 #define ESM_MPU401_IRQ 0x02
293 #define ESM_SB_IRQ 0x01
294 #define ESM_SOUND_IRQ 0x04
295 #define ESM_ASSP_IRQ 0x10
296 #define ESM_HWVOL_IRQ 0x40
297
298 #define ESS_SYSCLK 50000000
299 #define ESM_BOB_FREQ 200
300 #define ESM_BOB_FREQ_MAX 800
301
302 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
303 #define ESM_FREQ_ESM2 (50000000L / 1024L)
304
305 /* APU Modes: reg 0x00, bit 4-7 */
306 #define ESM_APU_MODE_SHIFT 4
307 #define ESM_APU_MODE_MASK (0xf << 4)
308 #define ESM_APU_OFF 0x00
309 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
310 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
311 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
312 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
313 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
314 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
315 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
316 #define ESM_APU_CORRELATOR 0x08 /* Correlator */
317 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
318 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
319 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
320 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
321 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
322 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
323 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
324
325 /* reg 0x00 */
326 #define ESM_APU_FILTER_Q_SHIFT 0
327 #define ESM_APU_FILTER_Q_MASK (3 << 0)
328 /* APU Filtey Q Control */
329 #define ESM_APU_FILTER_LESSQ 0x00
330 #define ESM_APU_FILTER_MOREQ 0x03
331
332 #define ESM_APU_FILTER_TYPE_SHIFT 2
333 #define ESM_APU_FILTER_TYPE_MASK (3 << 2)
334 #define ESM_APU_ENV_TYPE_SHIFT 8
335 #define ESM_APU_ENV_TYPE_MASK (3 << 8)
336 #define ESM_APU_ENV_STATE_SHIFT 10
337 #define ESM_APU_ENV_STATE_MASK (3 << 10)
338 #define ESM_APU_END_CURVE (1 << 12)
339 #define ESM_APU_INT_ON_LOOP (1 << 13)
340 #define ESM_APU_DMA_ENABLE (1 << 14)
341
342 /* reg 0x02 */
343 #define ESM_APU_SUBMIX_GROUP_SHIRT 0
344 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
345 #define ESM_APU_SUBMIX_MODE (1 << 3)
346 #define ESM_APU_6dB (1 << 4)
347 #define ESM_APU_DUAL_EFFECT (1 << 5)
348 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6
349 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
350
351 /* reg 0x03 */
352 #define ESM_APU_STEP_SIZE_MASK 0x0fff
353
354 /* reg 0x04 */
355 #define ESM_APU_PHASE_SHIFT 0
356 #define ESM_APU_PHASE_MASK (0xff << 0)
357 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
358 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
359
360 /* reg 0x05 - wave start offset */
361 /* reg 0x06 - wave end offset */
362 /* reg 0x07 - wave loop length */
363
364 /* reg 0x08 */
365 #define ESM_APU_EFFECT_GAIN_SHIFT 0
366 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
367 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8
368 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
369 #define ESM_APU_TREMOLO_RATE_SHIFT 12
370 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
371
372 /* reg 0x09 */
373 /* bit 0-7 amplitude dest? */
374 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8
375 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
376
377 /* reg 0x0a */
378 #define ESM_APU_POLAR_PAN_SHIFT 0
379 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
380 /* Polar Pan Control */
381 #define ESM_APU_PAN_CENTER_CIRCLE 0x00
382 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01
383 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
384
385 #define ESM_APU_FILTER_TUNING_SHIFT 8
386 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
387
388 /* reg 0x0b */
389 #define ESM_APU_DATA_SRC_A_SHIFT 0
390 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
391 #define ESM_APU_INV_POL_A (1 << 7)
392 #define ESM_APU_DATA_SRC_B_SHIFT 8
393 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
394 #define ESM_APU_INV_POL_B (1 << 15)
395
396 #define ESM_APU_VIBRATO_RATE_SHIFT 0
397 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
398 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4
399 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
400 #define ESM_APU_VIBRATO_PHASE_SHIFT 8
401 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
402
403 /* reg 0x0c */
404 #define ESM_APU_RADIUS_SELECT (1 << 6)
405
406 /* APU Filter Control */
407 #define ESM_APU_FILTER_2POLE_LOPASS 0x00
408 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01
409 #define ESM_APU_FILTER_2POLE_HIPASS 0x02
410 #define ESM_APU_FILTER_1POLE_LOPASS 0x03
411 #define ESM_APU_FILTER_1POLE_HIPASS 0x04
412 #define ESM_APU_FILTER_OFF 0x05
413
414 /* APU ATFP Type */
415 #define ESM_APU_ATFP_AMPLITUDE 0x00
416 #define ESM_APU_ATFP_TREMELO 0x01
417 #define ESM_APU_ATFP_FILTER 0x02
418 #define ESM_APU_ATFP_PAN 0x03
419
420 /* APU ATFP Flags */
421 #define ESM_APU_ATFP_FLG_OFF 0x00
422 #define ESM_APU_ATFP_FLG_WAIT 0x01
423 #define ESM_APU_ATFP_FLG_DONE 0x02
424 #define ESM_APU_ATFP_FLG_INPROCESS 0x03
425
426
427 /* capture mixing buffer size */
428 #define ESM_MEM_ALIGN 0x1000
429 #define ESM_MIXBUF_SIZE 0x400
430
431 #define ESM_MODE_PLAY 0
432 #define ESM_MODE_CAPTURE 1
433
434
435 /* APU use in the driver */
436 enum snd_enum_apu_type {
437 ESM_APU_PCM_PLAY,
438 ESM_APU_PCM_CAPTURE,
439 ESM_APU_PCM_RATECONV,
440 ESM_APU_FREE
441 };
442
443 /* chip type */
444 enum {
445 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
446 };
447
448 /* DMA Hack! */
449 struct esm_memory {
450 struct snd_dma_buffer buf;
451 int empty; /* status */
452 struct list_head list;
453 };
454
455 /* Playback Channel */
456 struct esschan {
457 int running;
458
459 u8 apu[4];
460 u8 apu_mode[4];
461
462 /* playback/capture pcm buffer */
463 struct esm_memory *memory;
464 /* capture mixer buffer */
465 struct esm_memory *mixbuf;
466
467 unsigned int hwptr; /* current hw pointer in bytes */
468 unsigned int count; /* sample counter in bytes */
469 unsigned int dma_size; /* total buffer size in bytes */
470 unsigned int frag_size; /* period size in bytes */
471 unsigned int wav_shift;
472 u16 base[4]; /* offset for ptr */
473
474 /* stereo/16bit flag */
475 unsigned char fmt;
476 int mode; /* playback / capture */
477
478 int bob_freq; /* required timer frequency */
479
480 struct snd_pcm_substream *substream;
481
482 /* linked list */
483 struct list_head list;
484
485 #ifdef CONFIG_PM
486 u16 wc_map[4];
487 #endif
488 };
489
490 struct es1968 {
491 /* Module Config */
492 int total_bufsize; /* in bytes */
493
494 int playback_streams, capture_streams;
495
496 unsigned int clock; /* clock */
497 /* for clock measurement */
498 unsigned int in_measurement: 1;
499 unsigned int measure_apu;
500 unsigned int measure_lastpos;
501 unsigned int measure_count;
502
503 /* buffer */
504 struct snd_dma_buffer dma;
505
506 /* Resources... */
507 int irq;
508 unsigned long io_port;
509 int type;
510 struct pci_dev *pci;
511 struct snd_card *card;
512 struct snd_pcm *pcm;
513 int do_pm; /* power-management enabled */
514
515 /* DMA memory block */
516 struct list_head buf_list;
517
518 /* ALSA Stuff */
519 struct snd_ac97 *ac97;
520 struct snd_kcontrol *master_switch; /* for h/w volume control */
521 struct snd_kcontrol *master_volume;
522
523 struct snd_rawmidi *rmidi;
524
525 spinlock_t reg_lock;
526 spinlock_t ac97_lock;
527 struct tasklet_struct hwvol_tq;
528 unsigned int in_suspend;
529
530 /* Maestro Stuff */
531 u16 maestro_map[32];
532 int bobclient; /* active timer instancs */
533 int bob_freq; /* timer frequency */
534 struct mutex memory_mutex; /* memory lock */
535
536 /* APU states */
537 unsigned char apu[NR_APUS];
538
539 /* active substreams */
540 struct list_head substream_list;
541 spinlock_t substream_lock;
542
543 #ifdef CONFIG_PM
544 u16 apu_map[NR_APUS][NR_APU_REGS];
545 #endif
546
547 #ifdef SUPPORT_JOYSTICK
548 struct gameport *gameport;
549 #endif
550 };
551
552 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
553
554 static struct pci_device_id snd_es1968_ids[] = {
555 /* Maestro 1 */
556 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
557 /* Maestro 2 */
558 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
559 /* Maestro 2E */
560 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
561 { 0, }
562 };
563
564 MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
565
566 /* *********************
567 * Low Level Funcs! *
568 *********************/
569
570 /* no spinlock */
571 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
572 {
573 outw(reg, chip->io_port + ESM_INDEX);
574 outw(data, chip->io_port + ESM_DATA);
575 chip->maestro_map[reg] = data;
576 }
577
578 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
579 {
580 unsigned long flags;
581 spin_lock_irqsave(&chip->reg_lock, flags);
582 __maestro_write(chip, reg, data);
583 spin_unlock_irqrestore(&chip->reg_lock, flags);
584 }
585
586 /* no spinlock */
587 static u16 __maestro_read(struct es1968 *chip, u16 reg)
588 {
589 if (READABLE_MAP & (1 << reg)) {
590 outw(reg, chip->io_port + ESM_INDEX);
591 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
592 }
593 return chip->maestro_map[reg];
594 }
595
596 static inline u16 maestro_read(struct es1968 *chip, u16 reg)
597 {
598 unsigned long flags;
599 u16 result;
600 spin_lock_irqsave(&chip->reg_lock, flags);
601 result = __maestro_read(chip, reg);
602 spin_unlock_irqrestore(&chip->reg_lock, flags);
603 return result;
604 }
605
606 /* Wait for the codec bus to be free */
607 static int snd_es1968_ac97_wait(struct es1968 *chip)
608 {
609 int timeout = 100000;
610
611 while (timeout-- > 0) {
612 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
613 return 0;
614 cond_resched();
615 }
616 snd_printd("es1968: ac97 timeout\n");
617 return 1; /* timeout */
618 }
619
620 static int snd_es1968_ac97_wait_poll(struct es1968 *chip)
621 {
622 int timeout = 100000;
623
624 while (timeout-- > 0) {
625 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
626 return 0;
627 }
628 snd_printd("es1968: ac97 timeout\n");
629 return 1; /* timeout */
630 }
631
632 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
633 {
634 struct es1968 *chip = ac97->private_data;
635 unsigned long flags;
636
637 snd_es1968_ac97_wait(chip);
638
639 /* Write the bus */
640 spin_lock_irqsave(&chip->ac97_lock, flags);
641 outw(val, chip->io_port + ESM_AC97_DATA);
642 /*msleep(1);*/
643 outb(reg, chip->io_port + ESM_AC97_INDEX);
644 /*msleep(1);*/
645 spin_unlock_irqrestore(&chip->ac97_lock, flags);
646 }
647
648 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
649 {
650 u16 data = 0;
651 struct es1968 *chip = ac97->private_data;
652 unsigned long flags;
653
654 snd_es1968_ac97_wait(chip);
655
656 spin_lock_irqsave(&chip->ac97_lock, flags);
657 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
658 /*msleep(1);*/
659
660 if (!snd_es1968_ac97_wait_poll(chip)) {
661 data = inw(chip->io_port + ESM_AC97_DATA);
662 /*msleep(1);*/
663 }
664 spin_unlock_irqrestore(&chip->ac97_lock, flags);
665
666 return data;
667 }
668
669 /* no spinlock */
670 static void apu_index_set(struct es1968 *chip, u16 index)
671 {
672 int i;
673 __maestro_write(chip, IDR1_CRAM_POINTER, index);
674 for (i = 0; i < 1000; i++)
675 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
676 return;
677 snd_printd("es1968: APU register select failed. (Timeout)\n");
678 }
679
680 /* no spinlock */
681 static void apu_data_set(struct es1968 *chip, u16 data)
682 {
683 int i;
684 for (i = 0; i < 1000; i++) {
685 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
686 return;
687 __maestro_write(chip, IDR0_DATA_PORT, data);
688 }
689 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
690 }
691
692 /* no spinlock */
693 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
694 {
695 snd_assert(channel < NR_APUS, return);
696 #ifdef CONFIG_PM
697 chip->apu_map[channel][reg] = data;
698 #endif
699 reg |= (channel << 4);
700 apu_index_set(chip, reg);
701 apu_data_set(chip, data);
702 }
703
704 static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
705 {
706 unsigned long flags;
707 spin_lock_irqsave(&chip->reg_lock, flags);
708 __apu_set_register(chip, channel, reg, data);
709 spin_unlock_irqrestore(&chip->reg_lock, flags);
710 }
711
712 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
713 {
714 snd_assert(channel < NR_APUS, return 0);
715 reg |= (channel << 4);
716 apu_index_set(chip, reg);
717 return __maestro_read(chip, IDR0_DATA_PORT);
718 }
719
720 static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
721 {
722 unsigned long flags;
723 u16 v;
724 spin_lock_irqsave(&chip->reg_lock, flags);
725 v = __apu_get_register(chip, channel, reg);
726 spin_unlock_irqrestore(&chip->reg_lock, flags);
727 return v;
728 }
729
730 #if 0 /* ASSP is not supported */
731
732 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
733 {
734 unsigned long flags;
735
736 spin_lock_irqsave(&chip->reg_lock, flags);
737 outl(reg, chip->io_port + ASSP_INDEX);
738 outl(value, chip->io_port + ASSP_DATA);
739 spin_unlock_irqrestore(&chip->reg_lock, flags);
740 }
741
742 static u32 assp_get_register(struct es1968 *chip, u32 reg)
743 {
744 unsigned long flags;
745 u32 value;
746
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 outl(reg, chip->io_port + ASSP_INDEX);
749 value = inl(chip->io_port + ASSP_DATA);
750 spin_unlock_irqrestore(&chip->reg_lock, flags);
751
752 return value;
753 }
754
755 #endif
756
757 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
758 {
759 unsigned long flags;
760
761 spin_lock_irqsave(&chip->reg_lock, flags);
762 outw(reg, chip->io_port + WC_INDEX);
763 outw(value, chip->io_port + WC_DATA);
764 spin_unlock_irqrestore(&chip->reg_lock, flags);
765 }
766
767 static u16 wave_get_register(struct es1968 *chip, u16 reg)
768 {
769 unsigned long flags;
770 u16 value;
771
772 spin_lock_irqsave(&chip->reg_lock, flags);
773 outw(reg, chip->io_port + WC_INDEX);
774 value = inw(chip->io_port + WC_DATA);
775 spin_unlock_irqrestore(&chip->reg_lock, flags);
776
777 return value;
778 }
779
780 /* *******************
781 * Bob the Timer! *
782 *******************/
783
784 static void snd_es1968_bob_stop(struct es1968 *chip)
785 {
786 u16 reg;
787
788 reg = __maestro_read(chip, 0x11);
789 reg &= ~ESM_BOB_ENABLE;
790 __maestro_write(chip, 0x11, reg);
791 reg = __maestro_read(chip, 0x17);
792 reg &= ~ESM_BOB_START;
793 __maestro_write(chip, 0x17, reg);
794 }
795
796 static void snd_es1968_bob_start(struct es1968 *chip)
797 {
798 int prescale;
799 int divide;
800
801 /* compute ideal interrupt frequency for buffer size & play rate */
802 /* first, find best prescaler value to match freq */
803 for (prescale = 5; prescale < 12; prescale++)
804 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
805 break;
806
807 /* next, back off prescaler whilst getting divider into optimum range */
808 divide = 1;
809 while ((prescale > 5) && (divide < 32)) {
810 prescale--;
811 divide <<= 1;
812 }
813 divide >>= 1;
814
815 /* now fine-tune the divider for best match */
816 for (; divide < 31; divide++)
817 if (chip->bob_freq >
818 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
819
820 /* divide = 0 is illegal, but don't let prescale = 4! */
821 if (divide == 0) {
822 divide++;
823 if (prescale > 5)
824 prescale--;
825 } else if (divide > 1)
826 divide--;
827
828 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
829
830 /* Now set IDR 11/17 */
831 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
832 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
833 }
834
835 /* call with substream spinlock */
836 static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
837 {
838 chip->bobclient++;
839 if (chip->bobclient == 1) {
840 chip->bob_freq = freq;
841 snd_es1968_bob_start(chip);
842 } else if (chip->bob_freq < freq) {
843 snd_es1968_bob_stop(chip);
844 chip->bob_freq = freq;
845 snd_es1968_bob_start(chip);
846 }
847 }
848
849 /* call with substream spinlock */
850 static void snd_es1968_bob_dec(struct es1968 *chip)
851 {
852 chip->bobclient--;
853 if (chip->bobclient <= 0)
854 snd_es1968_bob_stop(chip);
855 else if (chip->bob_freq > ESM_BOB_FREQ) {
856 /* check reduction of timer frequency */
857 int max_freq = ESM_BOB_FREQ;
858 struct esschan *es;
859 list_for_each_entry(es, &chip->substream_list, list) {
860 if (max_freq < es->bob_freq)
861 max_freq = es->bob_freq;
862 }
863 if (max_freq != chip->bob_freq) {
864 snd_es1968_bob_stop(chip);
865 chip->bob_freq = max_freq;
866 snd_es1968_bob_start(chip);
867 }
868 }
869 }
870
871 static int
872 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
873 struct snd_pcm_runtime *runtime)
874 {
875 /* we acquire 4 interrupts per period for precise control.. */
876 int freq = runtime->rate * 4;
877 if (es->fmt & ESS_FMT_STEREO)
878 freq <<= 1;
879 if (es->fmt & ESS_FMT_16BIT)
880 freq <<= 1;
881 freq /= es->frag_size;
882 if (freq < ESM_BOB_FREQ)
883 freq = ESM_BOB_FREQ;
884 else if (freq > ESM_BOB_FREQ_MAX)
885 freq = ESM_BOB_FREQ_MAX;
886 return freq;
887 }
888
889
890 /*************
891 * PCM Part *
892 *************/
893
894 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
895 {
896 u32 rate = (freq << 16) / chip->clock;
897 #if 0 /* XXX: do we need this? */
898 if (rate > 0x10000)
899 rate = 0x10000;
900 #endif
901 return rate;
902 }
903
904 /* get current pointer */
905 static inline unsigned int
906 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
907 {
908 unsigned int offset;
909
910 offset = apu_get_register(chip, es->apu[0], 5);
911
912 offset -= es->base[0];
913
914 return (offset & 0xFFFE); /* hardware is in words */
915 }
916
917 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
918 {
919 apu_set_register(chip, apu, 2,
920 (apu_get_register(chip, apu, 2) & 0x00FF) |
921 ((freq & 0xff) << 8) | 0x10);
922 apu_set_register(chip, apu, 3, freq >> 8);
923 }
924
925 /* spin lock held */
926 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
927 {
928 /* set the APU mode */
929 __apu_set_register(esm, apu, 0,
930 (__apu_get_register(esm, apu, 0) & 0xff0f) |
931 (mode << 4));
932 }
933
934 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
935 {
936 spin_lock(&chip->reg_lock);
937 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
938 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
939 if (es->mode == ESM_MODE_CAPTURE) {
940 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
941 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
942 }
943 if (es->fmt & ESS_FMT_STEREO) {
944 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
945 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
946 if (es->mode == ESM_MODE_CAPTURE) {
947 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
948 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
949 }
950 }
951 spin_unlock(&chip->reg_lock);
952 }
953
954 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
955 {
956 spin_lock(&chip->reg_lock);
957 snd_es1968_trigger_apu(chip, es->apu[0], 0);
958 snd_es1968_trigger_apu(chip, es->apu[1], 0);
959 if (es->mode == ESM_MODE_CAPTURE) {
960 snd_es1968_trigger_apu(chip, es->apu[2], 0);
961 snd_es1968_trigger_apu(chip, es->apu[3], 0);
962 }
963 spin_unlock(&chip->reg_lock);
964 }
965
966 /* set the wavecache control reg */
967 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
968 int channel, u32 addr, int capture)
969 {
970 u32 tmpval = (addr - 0x10) & 0xFFF8;
971
972 if (! capture) {
973 if (!(es->fmt & ESS_FMT_16BIT))
974 tmpval |= 4; /* 8bit */
975 if (es->fmt & ESS_FMT_STEREO)
976 tmpval |= 2; /* stereo */
977 }
978
979 /* set the wavecache control reg */
980 wave_set_register(chip, es->apu[channel] << 3, tmpval);
981
982 #ifdef CONFIG_PM
983 es->wc_map[channel] = tmpval;
984 #endif
985 }
986
987
988 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
989 struct snd_pcm_runtime *runtime)
990 {
991 u32 pa;
992 int high_apu = 0;
993 int channel, apu;
994 int i, size;
995 unsigned long flags;
996 u32 freq;
997
998 size = es->dma_size >> es->wav_shift;
999
1000 if (es->fmt & ESS_FMT_STEREO)
1001 high_apu++;
1002
1003 for (channel = 0; channel <= high_apu; channel++) {
1004 apu = es->apu[channel];
1005
1006 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1007
1008 /* Offset to PCMBAR */
1009 pa = es->memory->buf.addr;
1010 pa -= chip->dma.addr;
1011 pa >>= 1; /* words */
1012
1013 pa |= 0x00400000; /* System RAM (Bit 22) */
1014
1015 if (es->fmt & ESS_FMT_STEREO) {
1016 /* Enable stereo */
1017 if (channel)
1018 pa |= 0x00800000; /* (Bit 23) */
1019 if (es->fmt & ESS_FMT_16BIT)
1020 pa >>= 1;
1021 }
1022
1023 /* base offset of dma calcs when reading the pointer
1024 on this left one */
1025 es->base[channel] = pa & 0xFFFF;
1026
1027 for (i = 0; i < 16; i++)
1028 apu_set_register(chip, apu, i, 0x0000);
1029
1030 /* Load the buffer into the wave engine */
1031 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1032 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1033 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1034 /* setting loop == sample len */
1035 apu_set_register(chip, apu, 7, size);
1036
1037 /* clear effects/env.. */
1038 apu_set_register(chip, apu, 8, 0x0000);
1039 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1040 apu_set_register(chip, apu, 9, 0xD000);
1041
1042 /* clear routing stuff */
1043 apu_set_register(chip, apu, 11, 0x0000);
1044 /* dma on, no envelopes, filter to all 1s) */
1045 apu_set_register(chip, apu, 0, 0x400F);
1046
1047 if (es->fmt & ESS_FMT_16BIT)
1048 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1049 else
1050 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1051
1052 if (es->fmt & ESS_FMT_STEREO) {
1053 /* set panning: left or right */
1054 /* Check: different panning. On my Canyon 3D Chipset the
1055 Channels are swapped. I don't know, about the output
1056 to the SPDif Link. Perhaps you have to change this
1057 and not the APU Regs 4-5. */
1058 apu_set_register(chip, apu, 10,
1059 0x8F00 | (channel ? 0 : 0x10));
1060 es->apu_mode[channel] += 1; /* stereo */
1061 } else
1062 apu_set_register(chip, apu, 10, 0x8F08);
1063 }
1064
1065 spin_lock_irqsave(&chip->reg_lock, flags);
1066 /* clear WP interrupts */
1067 outw(1, chip->io_port + 0x04);
1068 /* enable WP ints */
1069 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1070 spin_unlock_irqrestore(&chip->reg_lock, flags);
1071
1072 freq = runtime->rate;
1073 /* set frequency */
1074 if (freq > 48000)
1075 freq = 48000;
1076 if (freq < 4000)
1077 freq = 4000;
1078
1079 /* hmmm.. */
1080 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1081 freq >>= 1;
1082
1083 freq = snd_es1968_compute_rate(chip, freq);
1084
1085 /* Load the frequency, turn on 6dB */
1086 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1087 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1088 }
1089
1090
1091 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1092 unsigned int pa, unsigned int bsize,
1093 int mode, int route)
1094 {
1095 int i, apu = es->apu[channel];
1096
1097 es->apu_mode[channel] = mode;
1098
1099 /* set the wavecache control reg */
1100 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1101
1102 /* Offset to PCMBAR */
1103 pa -= chip->dma.addr;
1104 pa >>= 1; /* words */
1105
1106 /* base offset of dma calcs when reading the pointer
1107 on this left one */
1108 es->base[channel] = pa & 0xFFFF;
1109 pa |= 0x00400000; /* bit 22 -> System RAM */
1110
1111 /* Begin loading the APU */
1112 for (i = 0; i < 16; i++)
1113 apu_set_register(chip, apu, i, 0x0000);
1114
1115 /* need to enable subgroups.. and we should probably
1116 have different groups for different /dev/dsps.. */
1117 apu_set_register(chip, apu, 2, 0x8);
1118
1119 /* Load the buffer into the wave engine */
1120 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1121 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1122 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1123 apu_set_register(chip, apu, 7, bsize);
1124 /* clear effects/env.. */
1125 apu_set_register(chip, apu, 8, 0x00F0);
1126 /* amplitude now? sure. why not. */
1127 apu_set_register(chip, apu, 9, 0x0000);
1128 /* set filter tune, radius, polar pan */
1129 apu_set_register(chip, apu, 10, 0x8F08);
1130 /* route input */
1131 apu_set_register(chip, apu, 11, route);
1132 /* dma on, no envelopes, filter to all 1s) */
1133 apu_set_register(chip, apu, 0, 0x400F);
1134 }
1135
1136 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1137 struct snd_pcm_runtime *runtime)
1138 {
1139 int size;
1140 u32 freq;
1141 unsigned long flags;
1142
1143 size = es->dma_size >> es->wav_shift;
1144
1145 /* APU assignments:
1146 0 = mono/left SRC
1147 1 = right SRC
1148 2 = mono/left Input Mixer
1149 3 = right Input Mixer
1150 */
1151 /* data seems to flow from the codec, through an apu into
1152 the 'mixbuf' bit of page, then through the SRC apu
1153 and out to the real 'buffer'. ok. sure. */
1154
1155 /* input mixer (left/mono) */
1156 /* parallel in crap, see maestro reg 0xC [8-11] */
1157 init_capture_apu(chip, es, 2,
1158 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1159 ESM_APU_INPUTMIXER, 0x14);
1160 /* SRC (left/mono); get input from inputing apu */
1161 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1162 ESM_APU_SRCONVERTOR, es->apu[2]);
1163 if (es->fmt & ESS_FMT_STEREO) {
1164 /* input mixer (right) */
1165 init_capture_apu(chip, es, 3,
1166 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1167 ESM_MIXBUF_SIZE/4, /* in words */
1168 ESM_APU_INPUTMIXER, 0x15);
1169 /* SRC (right) */
1170 init_capture_apu(chip, es, 1,
1171 es->memory->buf.addr + size*2, size,
1172 ESM_APU_SRCONVERTOR, es->apu[3]);
1173 }
1174
1175 freq = runtime->rate;
1176 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1177 if (freq > 47999)
1178 freq = 47999;
1179 if (freq < 4000)
1180 freq = 4000;
1181
1182 freq = snd_es1968_compute_rate(chip, freq);
1183
1184 /* Load the frequency, turn on 6dB */
1185 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1186 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1187
1188 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1189 freq = 0x10000;
1190 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1191 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1192
1193 spin_lock_irqsave(&chip->reg_lock, flags);
1194 /* clear WP interrupts */
1195 outw(1, chip->io_port + 0x04);
1196 /* enable WP ints */
1197 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1198 spin_unlock_irqrestore(&chip->reg_lock, flags);
1199 }
1200
1201 /*******************
1202 * ALSA Interface *
1203 *******************/
1204
1205 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1206 {
1207 struct es1968 *chip = snd_pcm_substream_chip(substream);
1208 struct snd_pcm_runtime *runtime = substream->runtime;
1209 struct esschan *es = runtime->private_data;
1210
1211 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1212 es->frag_size = snd_pcm_lib_period_bytes(substream);
1213
1214 es->wav_shift = 1; /* maestro handles always 16bit */
1215 es->fmt = 0;
1216 if (snd_pcm_format_width(runtime->format) == 16)
1217 es->fmt |= ESS_FMT_16BIT;
1218 if (runtime->channels > 1) {
1219 es->fmt |= ESS_FMT_STEREO;
1220 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1221 es->wav_shift++;
1222 }
1223 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1224
1225 switch (es->mode) {
1226 case ESM_MODE_PLAY:
1227 snd_es1968_playback_setup(chip, es, runtime);
1228 break;
1229 case ESM_MODE_CAPTURE:
1230 snd_es1968_capture_setup(chip, es, runtime);
1231 break;
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1238 {
1239 struct es1968 *chip = snd_pcm_substream_chip(substream);
1240 struct esschan *es = substream->runtime->private_data;
1241
1242 spin_lock(&chip->substream_lock);
1243 switch (cmd) {
1244 case SNDRV_PCM_TRIGGER_START:
1245 case SNDRV_PCM_TRIGGER_RESUME:
1246 if (es->running)
1247 break;
1248 snd_es1968_bob_inc(chip, es->bob_freq);
1249 es->count = 0;
1250 es->hwptr = 0;
1251 snd_es1968_pcm_start(chip, es);
1252 es->running = 1;
1253 break;
1254 case SNDRV_PCM_TRIGGER_STOP:
1255 case SNDRV_PCM_TRIGGER_SUSPEND:
1256 if (! es->running)
1257 break;
1258 snd_es1968_pcm_stop(chip, es);
1259 es->running = 0;
1260 snd_es1968_bob_dec(chip);
1261 break;
1262 }
1263 spin_unlock(&chip->substream_lock);
1264 return 0;
1265 }
1266
1267 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1268 {
1269 struct es1968 *chip = snd_pcm_substream_chip(substream);
1270 struct esschan *es = substream->runtime->private_data;
1271 unsigned int ptr;
1272
1273 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1274
1275 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1276 }
1277
1278 static struct snd_pcm_hardware snd_es1968_playback = {
1279 .info = (SNDRV_PCM_INFO_MMAP |
1280 SNDRV_PCM_INFO_MMAP_VALID |
1281 SNDRV_PCM_INFO_INTERLEAVED |
1282 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1283 /*SNDRV_PCM_INFO_PAUSE |*/
1284 SNDRV_PCM_INFO_RESUME),
1285 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1286 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1287 .rate_min = 4000,
1288 .rate_max = 48000,
1289 .channels_min = 1,
1290 .channels_max = 2,
1291 .buffer_bytes_max = 65536,
1292 .period_bytes_min = 256,
1293 .period_bytes_max = 65536,
1294 .periods_min = 1,
1295 .periods_max = 1024,
1296 .fifo_size = 0,
1297 };
1298
1299 static struct snd_pcm_hardware snd_es1968_capture = {
1300 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1301 SNDRV_PCM_INFO_MMAP |
1302 SNDRV_PCM_INFO_MMAP_VALID |
1303 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1304 /*SNDRV_PCM_INFO_PAUSE |*/
1305 SNDRV_PCM_INFO_RESUME),
1306 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1307 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1308 .rate_min = 4000,
1309 .rate_max = 48000,
1310 .channels_min = 1,
1311 .channels_max = 2,
1312 .buffer_bytes_max = 65536,
1313 .period_bytes_min = 256,
1314 .period_bytes_max = 65536,
1315 .periods_min = 1,
1316 .periods_max = 1024,
1317 .fifo_size = 0,
1318 };
1319
1320 /* *************************
1321 * DMA memory management *
1322 *************************/
1323
1324 /* Because the Maestro can only take addresses relative to the PCM base address
1325 register :( */
1326
1327 static int calc_available_memory_size(struct es1968 *chip)
1328 {
1329 int max_size = 0;
1330 struct esm_memory *buf;
1331
1332 mutex_lock(&chip->memory_mutex);
1333 list_for_each_entry(buf, &chip->buf_list, list) {
1334 if (buf->empty && buf->buf.bytes > max_size)
1335 max_size = buf->buf.bytes;
1336 }
1337 mutex_unlock(&chip->memory_mutex);
1338 if (max_size >= 128*1024)
1339 max_size = 127*1024;
1340 return max_size;
1341 }
1342
1343 /* allocate a new memory chunk with the specified size */
1344 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1345 {
1346 struct esm_memory *buf;
1347
1348 size = ALIGN(size, ESM_MEM_ALIGN);
1349 mutex_lock(&chip->memory_mutex);
1350 list_for_each_entry(buf, &chip->buf_list, list) {
1351 if (buf->empty && buf->buf.bytes >= size)
1352 goto __found;
1353 }
1354 mutex_unlock(&chip->memory_mutex);
1355 return NULL;
1356
1357 __found:
1358 if (buf->buf.bytes > size) {
1359 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1360 if (chunk == NULL) {
1361 mutex_unlock(&chip->memory_mutex);
1362 return NULL;
1363 }
1364 chunk->buf = buf->buf;
1365 chunk->buf.bytes -= size;
1366 chunk->buf.area += size;
1367 chunk->buf.addr += size;
1368 chunk->empty = 1;
1369 buf->buf.bytes = size;
1370 list_add(&chunk->list, &buf->list);
1371 }
1372 buf->empty = 0;
1373 mutex_unlock(&chip->memory_mutex);
1374 return buf;
1375 }
1376
1377 /* free a memory chunk */
1378 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1379 {
1380 struct esm_memory *chunk;
1381
1382 mutex_lock(&chip->memory_mutex);
1383 buf->empty = 1;
1384 if (buf->list.prev != &chip->buf_list) {
1385 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1386 if (chunk->empty) {
1387 chunk->buf.bytes += buf->buf.bytes;
1388 list_del(&buf->list);
1389 kfree(buf);
1390 buf = chunk;
1391 }
1392 }
1393 if (buf->list.next != &chip->buf_list) {
1394 chunk = list_entry(buf->list.next, struct esm_memory, list);
1395 if (chunk->empty) {
1396 buf->buf.bytes += chunk->buf.bytes;
1397 list_del(&chunk->list);
1398 kfree(chunk);
1399 }
1400 }
1401 mutex_unlock(&chip->memory_mutex);
1402 }
1403
1404 static void snd_es1968_free_dmabuf(struct es1968 *chip)
1405 {
1406 struct list_head *p;
1407
1408 if (! chip->dma.area)
1409 return;
1410 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1411 while ((p = chip->buf_list.next) != &chip->buf_list) {
1412 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1413 list_del(p);
1414 kfree(chunk);
1415 }
1416 }
1417
1418 static int __devinit
1419 snd_es1968_init_dmabuf(struct es1968 *chip)
1420 {
1421 int err;
1422 struct esm_memory *chunk;
1423
1424 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1425 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1426 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1427 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1428 snd_dma_pci_data(chip->pci),
1429 chip->total_bufsize, &chip->dma);
1430 if (err < 0 || ! chip->dma.area) {
1431 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
1432 chip->total_bufsize);
1433 return -ENOMEM;
1434 }
1435 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1436 snd_dma_free_pages(&chip->dma);
1437 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
1438 return -ENOMEM;
1439 }
1440 }
1441
1442 INIT_LIST_HEAD(&chip->buf_list);
1443 /* allocate an empty chunk */
1444 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1445 if (chunk == NULL) {
1446 snd_es1968_free_dmabuf(chip);
1447 return -ENOMEM;
1448 }
1449 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1450 chunk->buf = chip->dma;
1451 chunk->buf.area += ESM_MEM_ALIGN;
1452 chunk->buf.addr += ESM_MEM_ALIGN;
1453 chunk->buf.bytes -= ESM_MEM_ALIGN;
1454 chunk->empty = 1;
1455 list_add(&chunk->list, &chip->buf_list);
1456
1457 return 0;
1458 }
1459
1460 /* setup the dma_areas */
1461 /* buffer is extracted from the pre-allocated memory chunk */
1462 static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1463 struct snd_pcm_hw_params *hw_params)
1464 {
1465 struct es1968 *chip = snd_pcm_substream_chip(substream);
1466 struct snd_pcm_runtime *runtime = substream->runtime;
1467 struct esschan *chan = runtime->private_data;
1468 int size = params_buffer_bytes(hw_params);
1469
1470 if (chan->memory) {
1471 if (chan->memory->buf.bytes >= size) {
1472 runtime->dma_bytes = size;
1473 return 0;
1474 }
1475 snd_es1968_free_memory(chip, chan->memory);
1476 }
1477 chan->memory = snd_es1968_new_memory(chip, size);
1478 if (chan->memory == NULL) {
1479 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1480 return -ENOMEM;
1481 }
1482 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1483 return 1; /* area was changed */
1484 }
1485
1486 /* remove dma areas if allocated */
1487 static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1488 {
1489 struct es1968 *chip = snd_pcm_substream_chip(substream);
1490 struct snd_pcm_runtime *runtime = substream->runtime;
1491 struct esschan *chan;
1492
1493 if (runtime->private_data == NULL)
1494 return 0;
1495 chan = runtime->private_data;
1496 if (chan->memory) {
1497 snd_es1968_free_memory(chip, chan->memory);
1498 chan->memory = NULL;
1499 }
1500 return 0;
1501 }
1502
1503
1504 /*
1505 * allocate APU pair
1506 */
1507 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1508 {
1509 int apu;
1510
1511 for (apu = 0; apu < NR_APUS; apu += 2) {
1512 if (chip->apu[apu] == ESM_APU_FREE &&
1513 chip->apu[apu + 1] == ESM_APU_FREE) {
1514 chip->apu[apu] = chip->apu[apu + 1] = type;
1515 return apu;
1516 }
1517 }
1518 return -EBUSY;
1519 }
1520
1521 /*
1522 * release APU pair
1523 */
1524 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1525 {
1526 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1527 }
1528
1529
1530 /******************
1531 * PCM open/close *
1532 ******************/
1533
1534 static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1535 {
1536 struct es1968 *chip = snd_pcm_substream_chip(substream);
1537 struct snd_pcm_runtime *runtime = substream->runtime;
1538 struct esschan *es;
1539 int apu1;
1540
1541 /* search 2 APUs */
1542 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1543 if (apu1 < 0)
1544 return apu1;
1545
1546 es = kzalloc(sizeof(*es), GFP_KERNEL);
1547 if (!es) {
1548 snd_es1968_free_apu_pair(chip, apu1);
1549 return -ENOMEM;
1550 }
1551
1552 es->apu[0] = apu1;
1553 es->apu[1] = apu1 + 1;
1554 es->apu_mode[0] = 0;
1555 es->apu_mode[1] = 0;
1556 es->running = 0;
1557 es->substream = substream;
1558 es->mode = ESM_MODE_PLAY;
1559
1560 runtime->private_data = es;
1561 runtime->hw = snd_es1968_playback;
1562 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1563 calc_available_memory_size(chip);
1564
1565 spin_lock_irq(&chip->substream_lock);
1566 list_add(&es->list, &chip->substream_list);
1567 spin_unlock_irq(&chip->substream_lock);
1568
1569 return 0;
1570 }
1571
1572 static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1573 {
1574 struct snd_pcm_runtime *runtime = substream->runtime;
1575 struct es1968 *chip = snd_pcm_substream_chip(substream);
1576 struct esschan *es;
1577 int apu1, apu2;
1578
1579 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1580 if (apu1 < 0)
1581 return apu1;
1582 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1583 if (apu2 < 0) {
1584 snd_es1968_free_apu_pair(chip, apu1);
1585 return apu2;
1586 }
1587
1588 es = kzalloc(sizeof(*es), GFP_KERNEL);
1589 if (!es) {
1590 snd_es1968_free_apu_pair(chip, apu1);
1591 snd_es1968_free_apu_pair(chip, apu2);
1592 return -ENOMEM;
1593 }
1594
1595 es->apu[0] = apu1;
1596 es->apu[1] = apu1 + 1;
1597 es->apu[2] = apu2;
1598 es->apu[3] = apu2 + 1;
1599 es->apu_mode[0] = 0;
1600 es->apu_mode[1] = 0;
1601 es->apu_mode[2] = 0;
1602 es->apu_mode[3] = 0;
1603 es->running = 0;
1604 es->substream = substream;
1605 es->mode = ESM_MODE_CAPTURE;
1606
1607 /* get mixbuffer */
1608 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1609 snd_es1968_free_apu_pair(chip, apu1);
1610 snd_es1968_free_apu_pair(chip, apu2);
1611 kfree(es);
1612 return -ENOMEM;
1613 }
1614 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1615
1616 runtime->private_data = es;
1617 runtime->hw = snd_es1968_capture;
1618 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1619 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1620 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1621
1622 spin_lock_irq(&chip->substream_lock);
1623 list_add(&es->list, &chip->substream_list);
1624 spin_unlock_irq(&chip->substream_lock);
1625
1626 return 0;
1627 }
1628
1629 static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1630 {
1631 struct es1968 *chip = snd_pcm_substream_chip(substream);
1632 struct esschan *es;
1633
1634 if (substream->runtime->private_data == NULL)
1635 return 0;
1636 es = substream->runtime->private_data;
1637 spin_lock_irq(&chip->substream_lock);
1638 list_del(&es->list);
1639 spin_unlock_irq(&chip->substream_lock);
1640 snd_es1968_free_apu_pair(chip, es->apu[0]);
1641 kfree(es);
1642
1643 return 0;
1644 }
1645
1646 static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1647 {
1648 struct es1968 *chip = snd_pcm_substream_chip(substream);
1649 struct esschan *es;
1650
1651 if (substream->runtime->private_data == NULL)
1652 return 0;
1653 es = substream->runtime->private_data;
1654 spin_lock_irq(&chip->substream_lock);
1655 list_del(&es->list);
1656 spin_unlock_irq(&chip->substream_lock);
1657 snd_es1968_free_memory(chip, es->mixbuf);
1658 snd_es1968_free_apu_pair(chip, es->apu[0]);
1659 snd_es1968_free_apu_pair(chip, es->apu[2]);
1660 kfree(es);
1661
1662 return 0;
1663 }
1664
1665 static struct snd_pcm_ops snd_es1968_playback_ops = {
1666 .open = snd_es1968_playback_open,
1667 .close = snd_es1968_playback_close,
1668 .ioctl = snd_pcm_lib_ioctl,
1669 .hw_params = snd_es1968_hw_params,
1670 .hw_free = snd_es1968_hw_free,
1671 .prepare = snd_es1968_pcm_prepare,
1672 .trigger = snd_es1968_pcm_trigger,
1673 .pointer = snd_es1968_pcm_pointer,
1674 };
1675
1676 static struct snd_pcm_ops snd_es1968_capture_ops = {
1677 .open = snd_es1968_capture_open,
1678 .close = snd_es1968_capture_close,
1679 .ioctl = snd_pcm_lib_ioctl,
1680 .hw_params = snd_es1968_hw_params,
1681 .hw_free = snd_es1968_hw_free,
1682 .prepare = snd_es1968_pcm_prepare,
1683 .trigger = snd_es1968_pcm_trigger,
1684 .pointer = snd_es1968_pcm_pointer,
1685 };
1686
1687
1688 /*
1689 * measure clock
1690 */
1691 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1692
1693 static void __devinit es1968_measure_clock(struct es1968 *chip)
1694 {
1695 int i, apu;
1696 unsigned int pa, offset, t;
1697 struct esm_memory *memory;
1698 struct timeval start_time, stop_time;
1699
1700 if (chip->clock == 0)
1701 chip->clock = 48000; /* default clock value */
1702
1703 /* search 2 APUs (although one apu is enough) */
1704 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1705 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
1706 return;
1707 }
1708 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1709 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
1710 snd_es1968_free_apu_pair(chip, apu);
1711 return;
1712 }
1713
1714 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1715
1716 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1717
1718 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1719 pa |= 0x00400000; /* System RAM (Bit 22) */
1720
1721 /* initialize apu */
1722 for (i = 0; i < 16; i++)
1723 apu_set_register(chip, apu, i, 0x0000);
1724
1725 apu_set_register(chip, apu, 0, 0x400f);
1726 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1727 apu_set_register(chip, apu, 5, pa & 0xffff);
1728 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1729 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1730 apu_set_register(chip, apu, 8, 0x0000);
1731 apu_set_register(chip, apu, 9, 0xD000);
1732 apu_set_register(chip, apu, 10, 0x8F08);
1733 apu_set_register(chip, apu, 11, 0x0000);
1734 spin_lock_irq(&chip->reg_lock);
1735 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1736 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1737 spin_unlock_irq(&chip->reg_lock);
1738
1739 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1740
1741 chip->in_measurement = 1;
1742 chip->measure_apu = apu;
1743 spin_lock_irq(&chip->reg_lock);
1744 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1745 __apu_set_register(chip, apu, 5, pa & 0xffff);
1746 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1747 do_gettimeofday(&start_time);
1748 spin_unlock_irq(&chip->reg_lock);
1749 msleep(50);
1750 spin_lock_irq(&chip->reg_lock);
1751 offset = __apu_get_register(chip, apu, 5);
1752 do_gettimeofday(&stop_time);
1753 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1754 snd_es1968_bob_dec(chip);
1755 chip->in_measurement = 0;
1756 spin_unlock_irq(&chip->reg_lock);
1757
1758 /* check the current position */
1759 offset -= (pa & 0xffff);
1760 offset &= 0xfffe;
1761 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1762
1763 t = stop_time.tv_sec - start_time.tv_sec;
1764 t *= 1000000;
1765 if (stop_time.tv_usec < start_time.tv_usec)
1766 t -= start_time.tv_usec - stop_time.tv_usec;
1767 else
1768 t += stop_time.tv_usec - start_time.tv_usec;
1769 if (t == 0) {
1770 snd_printk(KERN_ERR "?? calculation error..\n");
1771 } else {
1772 offset *= 1000;
1773 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1774 if (offset < 47500 || offset > 48500) {
1775 if (offset >= 40000 && offset <= 50000)
1776 chip->clock = (chip->clock * offset) / 48000;
1777 }
1778 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1779 }
1780 snd_es1968_free_memory(chip, memory);
1781 snd_es1968_free_apu_pair(chip, apu);
1782 }
1783
1784
1785 /*
1786 */
1787
1788 static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1789 {
1790 struct es1968 *esm = pcm->private_data;
1791 snd_es1968_free_dmabuf(esm);
1792 esm->pcm = NULL;
1793 }
1794
1795 static int __devinit
1796 snd_es1968_pcm(struct es1968 *chip, int device)
1797 {
1798 struct snd_pcm *pcm;
1799 int err;
1800
1801 /* get DMA buffer */
1802 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1803 return err;
1804
1805 /* set PCMBAR */
1806 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1807 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1808 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1809 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1810
1811 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1812 chip->playback_streams,
1813 chip->capture_streams, &pcm)) < 0)
1814 return err;
1815
1816 pcm->private_data = chip;
1817 pcm->private_free = snd_es1968_pcm_free;
1818
1819 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1820 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1821
1822 pcm->info_flags = 0;
1823
1824 strcpy(pcm->name, "ESS Maestro");
1825
1826 chip->pcm = pcm;
1827
1828 return 0;
1829 }
1830 /*
1831 * suppress jitter on some maestros when playing stereo
1832 */
1833 static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es)
1834 {
1835 unsigned int cp1;
1836 unsigned int cp2;
1837 unsigned int diff;
1838
1839 cp1 = __apu_get_register(chip, 0, 5);
1840 cp2 = __apu_get_register(chip, 1, 5);
1841 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1842
1843 if (diff > 1)
1844 __maestro_write(chip, IDR0_DATA_PORT, cp1);
1845 }
1846
1847 /*
1848 * update pointer
1849 */
1850 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1851 {
1852 unsigned int hwptr;
1853 unsigned int diff;
1854 struct snd_pcm_substream *subs = es->substream;
1855
1856 if (subs == NULL || !es->running)
1857 return;
1858
1859 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1860 hwptr %= es->dma_size;
1861
1862 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1863
1864 es->hwptr = hwptr;
1865 es->count += diff;
1866
1867 if (es->count > es->frag_size) {
1868 spin_unlock(&chip->substream_lock);
1869 snd_pcm_period_elapsed(subs);
1870 spin_lock(&chip->substream_lock);
1871 es->count %= es->frag_size;
1872 }
1873 }
1874
1875 /*
1876 */
1877 static void es1968_update_hw_volume(unsigned long private_data)
1878 {
1879 struct es1968 *chip = (struct es1968 *) private_data;
1880 int x, val;
1881 unsigned long flags;
1882
1883 /* Figure out which volume control button was pushed,
1884 based on differences from the default register
1885 values. */
1886 x = inb(chip->io_port + 0x1c) & 0xee;
1887 /* Reset the volume control registers. */
1888 outb(0x88, chip->io_port + 0x1c);
1889 outb(0x88, chip->io_port + 0x1d);
1890 outb(0x88, chip->io_port + 0x1e);
1891 outb(0x88, chip->io_port + 0x1f);
1892
1893 if (chip->in_suspend)
1894 return;
1895
1896 if (! chip->master_switch || ! chip->master_volume)
1897 return;
1898
1899 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1900 spin_lock_irqsave(&chip->ac97_lock, flags);
1901 val = chip->ac97->regs[AC97_MASTER];
1902 switch (x) {
1903 case 0x88:
1904 /* mute */
1905 val ^= 0x8000;
1906 chip->ac97->regs[AC97_MASTER] = val;
1907 outw(val, chip->io_port + ESM_AC97_DATA);
1908 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1909 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1910 &chip->master_switch->id);
1911 break;
1912 case 0xaa:
1913 /* volume up */
1914 if ((val & 0x7f) > 0)
1915 val--;
1916 if ((val & 0x7f00) > 0)
1917 val -= 0x0100;
1918 chip->ac97->regs[AC97_MASTER] = val;
1919 outw(val, chip->io_port + ESM_AC97_DATA);
1920 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1921 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1922 &chip->master_volume->id);
1923 break;
1924 case 0x66:
1925 /* volume down */
1926 if ((val & 0x7f) < 0x1f)
1927 val++;
1928 if ((val & 0x7f00) < 0x1f00)
1929 val += 0x0100;
1930 chip->ac97->regs[AC97_MASTER] = val;
1931 outw(val, chip->io_port + ESM_AC97_DATA);
1932 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1933 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1934 &chip->master_volume->id);
1935 break;
1936 }
1937 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1938 }
1939
1940 /*
1941 * interrupt handler
1942 */
1943 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1944 {
1945 struct es1968 *chip = dev_id;
1946 u32 event;
1947
1948 if (!(event = inb(chip->io_port + 0x1A)))
1949 return IRQ_NONE;
1950
1951 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1952
1953 if (event & ESM_HWVOL_IRQ)
1954 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1955
1956 /* else ack 'em all, i imagine */
1957 outb(0xFF, chip->io_port + 0x1A);
1958
1959 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1960 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1961 }
1962
1963 if (event & ESM_SOUND_IRQ) {
1964 struct esschan *es;
1965 spin_lock(&chip->substream_lock);
1966 list_for_each_entry(es, &chip->substream_list, list) {
1967 if (es->running) {
1968 snd_es1968_update_pcm(chip, es);
1969 if (es->fmt & ESS_FMT_STEREO)
1970 snd_es1968_suppress_jitter(chip, es);
1971 }
1972 }
1973 spin_unlock(&chip->substream_lock);
1974 if (chip->in_measurement) {
1975 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1976 if (curp < chip->measure_lastpos)
1977 chip->measure_count++;
1978 chip->measure_lastpos = curp;
1979 }
1980 }
1981
1982 return IRQ_HANDLED;
1983 }
1984
1985 /*
1986 * Mixer stuff
1987 */
1988
1989 static int __devinit
1990 snd_es1968_mixer(struct es1968 *chip)
1991 {
1992 struct snd_ac97_bus *pbus;
1993 struct snd_ac97_template ac97;
1994 struct snd_ctl_elem_id elem_id;
1995 int err;
1996 static struct snd_ac97_bus_ops ops = {
1997 .write = snd_es1968_ac97_write,
1998 .read = snd_es1968_ac97_read,
1999 };
2000
2001 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2002 return err;
2003 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2004
2005 memset(&ac97, 0, sizeof(ac97));
2006 ac97.private_data = chip;
2007 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2008 return err;
2009
2010 /* attach master switch / volumes for h/w volume control */
2011 memset(&elem_id, 0, sizeof(elem_id));
2012 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2013 strcpy(elem_id.name, "Master Playback Switch");
2014 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2015 memset(&elem_id, 0, sizeof(elem_id));
2016 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2017 strcpy(elem_id.name, "Master Playback Volume");
2018 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2019
2020 return 0;
2021 }
2022
2023 /*
2024 * reset ac97 codec
2025 */
2026
2027 static void snd_es1968_ac97_reset(struct es1968 *chip)
2028 {
2029 unsigned long ioaddr = chip->io_port;
2030
2031 unsigned short save_ringbus_a;
2032 unsigned short save_68;
2033 unsigned short w;
2034 unsigned int vend;
2035
2036 /* save configuration */
2037 save_ringbus_a = inw(ioaddr + 0x36);
2038
2039 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2040 /* set command/status address i/o to 1st codec */
2041 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2042 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2043
2044 /* disable ac link */
2045 outw(0x0000, ioaddr + 0x36);
2046 save_68 = inw(ioaddr + 0x68);
2047 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2048 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2049 if (w & 1)
2050 save_68 |= 0x10;
2051 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2052 outw(0x0001, ioaddr + 0x68); /* gpio write */
2053 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2054 udelay(20);
2055 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2056 msleep(20);
2057
2058 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2059 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2060 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2061 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2062
2063 /* now the second codec */
2064 /* disable ac link */
2065 outw(0x0000, ioaddr + 0x36);
2066 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2067 save_68 = inw(ioaddr + 0x68);
2068 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2069 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2070 udelay(20);
2071 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2072 msleep(500);
2073 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2074 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2075 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2076
2077 #if 0 /* the loop here needs to be much better if we want it.. */
2078 snd_printk(KERN_INFO "trying software reset\n");
2079 /* try and do a software reset */
2080 outb(0x80 | 0x7c, ioaddr + 0x30);
2081 for (w = 0;; w++) {
2082 if ((inw(ioaddr + 0x30) & 1) == 0) {
2083 if (inb(ioaddr + 0x32) != 0)
2084 break;
2085
2086 outb(0x80 | 0x7d, ioaddr + 0x30);
2087 if (((inw(ioaddr + 0x30) & 1) == 0)
2088 && (inb(ioaddr + 0x32) != 0))
2089 break;
2090 outb(0x80 | 0x7f, ioaddr + 0x30);
2091 if (((inw(ioaddr + 0x30) & 1) == 0)
2092 && (inb(ioaddr + 0x32) != 0))
2093 break;
2094 }
2095
2096 if (w > 10000) {
2097 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2098 msleep(500); /* oh my.. */
2099 outb(inb(ioaddr + 0x37) & ~0x08,
2100 ioaddr + 0x37);
2101 udelay(1);
2102 outw(0x80, ioaddr + 0x30);
2103 for (w = 0; w < 10000; w++) {
2104 if ((inw(ioaddr + 0x30) & 1) == 0)
2105 break;
2106 }
2107 }
2108 }
2109 #endif
2110 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2111 /* turn on external amp? */
2112 outw(0xf9ff, ioaddr + 0x64);
2113 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2114 outw(0x0209, ioaddr + 0x60);
2115 }
2116
2117 /* restore.. */
2118 outw(save_ringbus_a, ioaddr + 0x36);
2119
2120 /* Turn on the 978 docking chip.
2121 First frob the "master output enable" bit,
2122 then set most of the playback volume control registers to max. */
2123 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2124 outb(0xff, ioaddr+0xc3);
2125 outb(0xff, ioaddr+0xc4);
2126 outb(0xff, ioaddr+0xc6);
2127 outb(0xff, ioaddr+0xc8);
2128 outb(0x3f, ioaddr+0xcf);
2129 outb(0x3f, ioaddr+0xd0);
2130 }
2131
2132 static void snd_es1968_reset(struct es1968 *chip)
2133 {
2134 /* Reset */
2135 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2136 chip->io_port + ESM_PORT_HOST_IRQ);
2137 udelay(10);
2138 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2139 udelay(10);
2140 }
2141
2142 /*
2143 * initialize maestro chip
2144 */
2145 static void snd_es1968_chip_init(struct es1968 *chip)
2146 {
2147 struct pci_dev *pci = chip->pci;
2148 int i;
2149 unsigned long iobase = chip->io_port;
2150 u16 w;
2151 u32 n;
2152
2153 /* We used to muck around with pci config space that
2154 * we had no business messing with. We don't know enough
2155 * about the machine to know which DMA mode is appropriate,
2156 * etc. We were guessing wrong on some machines and making
2157 * them unhappy. We now trust in the BIOS to do things right,
2158 * which almost certainly means a new host of problems will
2159 * arise with broken BIOS implementations. screw 'em.
2160 * We're already intolerant of machines that don't assign
2161 * IRQs.
2162 */
2163
2164 /* Config Reg A */
2165 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2166
2167 w &= ~DMA_CLEAR; /* Clear DMA bits */
2168 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2169 w &= ~SAFEGUARD; /* Safeguard off */
2170 w |= POST_WRITE; /* Posted write */
2171 w |= PCI_TIMING; /* PCI timing on */
2172 /* XXX huh? claims to be reserved.. */
2173 w &= ~SWAP_LR; /* swap left/right
2174 seems to only have effect on SB
2175 Emulation */
2176 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2177
2178 pci_write_config_word(pci, ESM_CONFIG_A, w);
2179
2180 /* Config Reg B */
2181
2182 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2183
2184 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2185 /* XXX how do we know which to use? */
2186 w &= ~(1 << 14); /* External clock */
2187
2188 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2189 w |= HWV_CONFB; /* HWV on */
2190 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2191 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2192 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2193 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2194 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2195 w &= ~(1 << 1); /* reserved, always write 0 */
2196 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2197
2198 pci_write_config_word(pci, ESM_CONFIG_B, w);
2199
2200 /* DDMA off */
2201
2202 pci_read_config_word(pci, ESM_DDMA, &w);
2203 w &= ~(1 << 0);
2204 pci_write_config_word(pci, ESM_DDMA, w);
2205
2206 /*
2207 * Legacy mode
2208 */
2209
2210 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2211
2212 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2213 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2214 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2215
2216 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2217
2218 /* Set up 978 docking control chip. */
2219 pci_read_config_word(pci, 0x58, &w);
2220 w|=1<<2; /* Enable 978. */
2221 w|=1<<3; /* Turn on 978 hardware volume control. */
2222 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2223 pci_write_config_word(pci, 0x58, w);
2224
2225 /* Sound Reset */
2226
2227 snd_es1968_reset(chip);
2228
2229 /*
2230 * Ring Bus Setup
2231 */
2232
2233 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2234 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2235 udelay(20);
2236 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2237 udelay(20);
2238
2239 /*
2240 * Reset the CODEC
2241 */
2242
2243 snd_es1968_ac97_reset(chip);
2244
2245 /* Ring Bus Control B */
2246
2247 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2248 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2249 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2250 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2251
2252 /* Set hardware volume control registers to midpoints.
2253 We can tell which button was pushed based on how they change. */
2254 outb(0x88, iobase+0x1c);
2255 outb(0x88, iobase+0x1d);
2256 outb(0x88, iobase+0x1e);
2257 outb(0x88, iobase+0x1f);
2258
2259 /* it appears some maestros (dell 7500) only work if these are set,
2260 regardless of wether we use the assp or not. */
2261
2262 outb(0, iobase + ASSP_CONTROL_B);
2263 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2264 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2265
2266 /*
2267 * set up wavecache
2268 */
2269 for (i = 0; i < 16; i++) {
2270 /* Write 0 into the buffer area 0x1E0->1EF */
2271 outw(0x01E0 + i, iobase + WC_INDEX);
2272 outw(0x0000, iobase + WC_DATA);
2273
2274 /* The 1.10 test program seem to write 0 into the buffer area
2275 * 0x1D0-0x1DF too.*/
2276 outw(0x01D0 + i, iobase + WC_INDEX);
2277 outw(0x0000, iobase + WC_DATA);
2278 }
2279 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2280 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2281 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2282 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2283 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2284 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2285 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2286 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2287
2288
2289 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2290 /* Now back to the DirectSound stuff */
2291 /* audio serial configuration.. ? */
2292 maestro_write(chip, 0x08, 0xB004);
2293 maestro_write(chip, 0x09, 0x001B);
2294 maestro_write(chip, 0x0A, 0x8000);
2295 maestro_write(chip, 0x0B, 0x3F37);
2296 maestro_write(chip, 0x0C, 0x0098);
2297
2298 /* parallel in, has something to do with recording :) */
2299 maestro_write(chip, 0x0C,
2300 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2301 /* parallel out */
2302 maestro_write(chip, 0x0C,
2303 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2304
2305 maestro_write(chip, 0x0D, 0x7632);
2306
2307 /* Wave cache control on - test off, sg off,
2308 enable, enable extra chans 1Mb */
2309
2310 w = inw(iobase + WC_CONTROL);
2311
2312 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2313 w |= 0xA000; /* reserved... I don't know */
2314 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2315 Seems to crash the Computer if enabled... */
2316 w |= 0x0100; /* Wave Cache Operation Enabled */
2317 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2318 w &= ~0x0060; /* Clear Wavtable Size */
2319 w |= 0x0020; /* Wavetable Size : 1MB */
2320 /* Bit 4 is reserved */
2321 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2322 /* Bit 1 is reserved */
2323 w &= ~0x0001; /* Test Mode off */
2324
2325 outw(w, iobase + WC_CONTROL);
2326
2327 /* Now clear the APU control ram */
2328 for (i = 0; i < NR_APUS; i++) {
2329 for (w = 0; w < NR_APU_REGS; w++)
2330 apu_set_register(chip, i, w, 0);
2331
2332 }
2333 }
2334
2335 /* Enable IRQ's */
2336 static void snd_es1968_start_irq(struct es1968 *chip)
2337 {
2338 unsigned short w;
2339 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2340 if (chip->rmidi)
2341 w |= ESM_HIRQ_MPU401;
2342 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2343 }
2344
2345 #ifdef CONFIG_PM
2346 /*
2347 * PM support
2348 */
2349 static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
2350 {
2351 struct snd_card *card = pci_get_drvdata(pci);
2352 struct es1968 *chip = card->private_data;
2353
2354 if (! chip->do_pm)
2355 return 0;
2356
2357 chip->in_suspend = 1;
2358 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2359 snd_pcm_suspend_all(chip->pcm);
2360 snd_ac97_suspend(chip->ac97);
2361 snd_es1968_bob_stop(chip);
2362
2363 pci_disable_device(pci);
2364 pci_save_state(pci);
2365 pci_set_power_state(pci, pci_choose_state(pci, state));
2366 return 0;
2367 }
2368
2369 static int es1968_resume(struct pci_dev *pci)
2370 {
2371 struct snd_card *card = pci_get_drvdata(pci);
2372 struct es1968 *chip = card->private_data;
2373 struct esschan *es;
2374
2375 if (! chip->do_pm)
2376 return 0;
2377
2378 /* restore all our config */
2379 pci_set_power_state(pci, PCI_D0);
2380 pci_restore_state(pci);
2381 if (pci_enable_device(pci) < 0) {
2382 printk(KERN_ERR "es1968: pci_enable_device failed, "
2383 "disabling device\n");
2384 snd_card_disconnect(card);
2385 return -EIO;
2386 }
2387 pci_set_master(pci);
2388
2389 snd_es1968_chip_init(chip);
2390
2391 /* need to restore the base pointers.. */
2392 if (chip->dma.addr) {
2393 /* set PCMBAR */
2394 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2395 }
2396
2397 snd_es1968_start_irq(chip);
2398
2399 /* restore ac97 state */
2400 snd_ac97_resume(chip->ac97);
2401
2402 list_for_each_entry(es, &chip->substream_list, list) {
2403 switch (es->mode) {
2404 case ESM_MODE_PLAY:
2405 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2406 break;
2407 case ESM_MODE_CAPTURE:
2408 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2409 break;
2410 }
2411 }
2412
2413 /* start timer again */
2414 if (chip->bobclient)
2415 snd_es1968_bob_start(chip);
2416
2417 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2418 chip->in_suspend = 0;
2419 return 0;
2420 }
2421 #endif /* CONFIG_PM */
2422
2423 #ifdef SUPPORT_JOYSTICK
2424 #define JOYSTICK_ADDR 0x200
2425 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
2426 {
2427 struct gameport *gp;
2428 struct resource *r;
2429 u16 val;
2430
2431 if (!joystick[dev])
2432 return -ENODEV;
2433
2434 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2435 if (!r)
2436 return -EBUSY;
2437
2438 chip->gameport = gp = gameport_allocate_port();
2439 if (!gp) {
2440 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
2441 release_and_free_resource(r);
2442 return -ENOMEM;
2443 }
2444
2445 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2446 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2447
2448 gameport_set_name(gp, "ES1968 Gameport");
2449 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2450 gameport_set_dev_parent(gp, &chip->pci->dev);
2451 gp->io = JOYSTICK_ADDR;
2452 gameport_set_port_data(gp, r);
2453
2454 gameport_register_port(gp);
2455
2456 return 0;
2457 }
2458
2459 static void snd_es1968_free_gameport(struct es1968 *chip)
2460 {
2461 if (chip->gameport) {
2462 struct resource *r = gameport_get_port_data(chip->gameport);
2463
2464 gameport_unregister_port(chip->gameport);
2465 chip->gameport = NULL;
2466
2467 release_and_free_resource(r);
2468 }
2469 }
2470 #else
2471 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2472 static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2473 #endif
2474
2475 static int snd_es1968_free(struct es1968 *chip)
2476 {
2477 if (chip->io_port) {
2478 if (chip->irq >= 0)
2479 synchronize_irq(chip->irq);
2480 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2481 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2482 }
2483
2484 if (chip->irq >= 0)
2485 free_irq(chip->irq, chip);
2486 snd_es1968_free_gameport(chip);
2487 chip->master_switch = NULL;
2488 chip->master_volume = NULL;
2489 pci_release_regions(chip->pci);
2490 pci_disable_device(chip->pci);
2491 kfree(chip);
2492 return 0;
2493 }
2494
2495 static int snd_es1968_dev_free(struct snd_device *device)
2496 {
2497 struct es1968 *chip = device->device_data;
2498 return snd_es1968_free(chip);
2499 }
2500
2501 struct ess_device_list {
2502 unsigned short type; /* chip type */
2503 unsigned short vendor; /* subsystem vendor id */
2504 };
2505
2506 static struct ess_device_list pm_whitelist[] __devinitdata = {
2507 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2508 { TYPE_MAESTRO2E, 0x1028 },
2509 { TYPE_MAESTRO2E, 0x103c },
2510 { TYPE_MAESTRO2E, 0x1179 },
2511 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2512 { TYPE_MAESTRO2E, 0x1558 },
2513 };
2514
2515 static struct ess_device_list mpu_blacklist[] __devinitdata = {
2516 { TYPE_MAESTRO2, 0x125d },
2517 };
2518
2519 static int __devinit snd_es1968_create(struct snd_card *card,
2520 struct pci_dev *pci,
2521 int total_bufsize,
2522 int play_streams,
2523 int capt_streams,
2524 int chip_type,
2525 int do_pm,
2526 struct es1968 **chip_ret)
2527 {
2528 static struct snd_device_ops ops = {
2529 .dev_free = snd_es1968_dev_free,
2530 };
2531 struct es1968 *chip;
2532 int i, err;
2533
2534 *chip_ret = NULL;
2535
2536 /* enable PCI device */
2537 if ((err = pci_enable_device(pci)) < 0)
2538 return err;
2539 /* check, if we can restrict PCI DMA transfers to 28 bits */
2540 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2541 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2542 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2543 pci_disable_device(pci);
2544 return -ENXIO;
2545 }
2546
2547 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2548 if (! chip) {
2549 pci_disable_device(pci);
2550 return -ENOMEM;
2551 }
2552
2553 /* Set Vars */
2554 chip->type = chip_type;
2555 spin_lock_init(&chip->reg_lock);
2556 spin_lock_init(&chip->substream_lock);
2557 INIT_LIST_HEAD(&chip->buf_list);
2558 INIT_LIST_HEAD(&chip->substream_list);
2559 spin_lock_init(&chip->ac97_lock);
2560 mutex_init(&chip->memory_mutex);
2561 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2562 chip->card = card;
2563 chip->pci = pci;
2564 chip->irq = -1;
2565 chip->total_bufsize = total_bufsize; /* in bytes */
2566 chip->playback_streams = play_streams;
2567 chip->capture_streams = capt_streams;
2568
2569 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2570 kfree(chip);
2571 pci_disable_device(pci);
2572 return err;
2573 }
2574 chip->io_port = pci_resource_start(pci, 0);
2575 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2576 "ESS Maestro", chip)) {
2577 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2578 snd_es1968_free(chip);
2579 return -EBUSY;
2580 }
2581 chip->irq = pci->irq;
2582
2583 /* Clear Maestro_map */
2584 for (i = 0; i < 32; i++)
2585 chip->maestro_map[i] = 0;
2586
2587 /* Clear Apu Map */
2588 for (i = 0; i < NR_APUS; i++)
2589 chip->apu[i] = ESM_APU_FREE;
2590
2591 /* just to be sure */
2592 pci_set_master(pci);
2593
2594 if (do_pm > 1) {
2595 /* disable power-management if not on the whitelist */
2596 unsigned short vend;
2597 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2598 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2599 if (chip->type == pm_whitelist[i].type &&
2600 vend == pm_whitelist[i].vendor) {
2601 do_pm = 1;
2602 break;
2603 }
2604 }
2605 if (do_pm > 1) {
2606 /* not matched; disabling pm */
2607 printk(KERN_INFO "es1968: not attempting power management.\n");
2608 do_pm = 0;
2609 }
2610 }
2611 chip->do_pm = do_pm;
2612
2613 snd_es1968_chip_init(chip);
2614
2615 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2616 snd_es1968_free(chip);
2617 return err;
2618 }
2619
2620 snd_card_set_dev(card, &pci->dev);
2621
2622 *chip_ret = chip;
2623
2624 return 0;
2625 }
2626
2627
2628 /*
2629 */
2630 static int __devinit snd_es1968_probe(struct pci_dev *pci,
2631 const struct pci_device_id *pci_id)
2632 {
2633 static int dev;
2634 struct snd_card *card;
2635 struct es1968 *chip;
2636 unsigned int i;
2637 int err;
2638
2639 if (dev >= SNDRV_CARDS)
2640 return -ENODEV;
2641 if (!enable[dev]) {
2642 dev++;
2643 return -ENOENT;
2644 }
2645
2646 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2647 if (!card)
2648 return -ENOMEM;
2649
2650 if (total_bufsize[dev] < 128)
2651 total_bufsize[dev] = 128;
2652 if (total_bufsize[dev] > 4096)
2653 total_bufsize[dev] = 4096;
2654 if ((err = snd_es1968_create(card, pci,
2655 total_bufsize[dev] * 1024, /* in bytes */
2656 pcm_substreams_p[dev],
2657 pcm_substreams_c[dev],
2658 pci_id->driver_data,
2659 use_pm[dev],
2660 &chip)) < 0) {
2661 snd_card_free(card);
2662 return err;
2663 }
2664 card->private_data = chip;
2665
2666 switch (chip->type) {
2667 case TYPE_MAESTRO2E:
2668 strcpy(card->driver, "ES1978");
2669 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2670 break;
2671 case TYPE_MAESTRO2:
2672 strcpy(card->driver, "ES1968");
2673 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2674 break;
2675 case TYPE_MAESTRO:
2676 strcpy(card->driver, "ESM1");
2677 strcpy(card->shortname, "ESS Maestro 1");
2678 break;
2679 }
2680
2681 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2682 snd_card_free(card);
2683 return err;
2684 }
2685
2686 if ((err = snd_es1968_mixer(chip)) < 0) {
2687 snd_card_free(card);
2688 return err;
2689 }
2690
2691 if (enable_mpu[dev] == 2) {
2692 /* check the black list */
2693 unsigned short vend;
2694 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2695 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2696 if (chip->type == mpu_blacklist[i].type &&
2697 vend == mpu_blacklist[i].vendor) {
2698 enable_mpu[dev] = 0;
2699 break;
2700 }
2701 }
2702 }
2703 if (enable_mpu[dev]) {
2704 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2705 chip->io_port + ESM_MPU401_PORT,
2706 MPU401_INFO_INTEGRATED,
2707 chip->irq, 0, &chip->rmidi)) < 0) {
2708 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2709 }
2710 }
2711
2712 snd_es1968_create_gameport(chip, dev);
2713
2714 snd_es1968_start_irq(chip);
2715
2716 chip->clock = clock[dev];
2717 if (! chip->clock)
2718 es1968_measure_clock(chip);
2719
2720 sprintf(card->longname, "%s at 0x%lx, irq %i",
2721 card->shortname, chip->io_port, chip->irq);
2722
2723 if ((err = snd_card_register(card)) < 0) {
2724 snd_card_free(card);
2725 return err;
2726 }
2727 pci_set_drvdata(pci, card);
2728 dev++;
2729 return 0;
2730 }
2731
2732 static void __devexit snd_es1968_remove(struct pci_dev *pci)
2733 {
2734 snd_card_free(pci_get_drvdata(pci));
2735 pci_set_drvdata(pci, NULL);
2736 }
2737
2738 static struct pci_driver driver = {
2739 .name = "ES1968 (ESS Maestro)",
2740 .id_table = snd_es1968_ids,
2741 .probe = snd_es1968_probe,
2742 .remove = __devexit_p(snd_es1968_remove),
2743 #ifdef CONFIG_PM
2744 .suspend = es1968_suspend,
2745 .resume = es1968_resume,
2746 #endif
2747 };
2748
2749 static int __init alsa_card_es1968_init(void)
2750 {
2751 return pci_register_driver(&driver);
2752 }
2753
2754 static void __exit alsa_card_es1968_exit(void)
2755 {
2756 pci_unregister_driver(&driver);
2757 }
2758
2759 module_init(alsa_card_es1968_init)
2760 module_exit(alsa_card_es1968_exit)
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