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kcalloc: remove runtime division
[linux-2.6/mini2440.git] / drivers / char / synclinkmp.c
blobc0490cbd0db2e99bf0e149ef99b03d2506711c6c
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266 char char_buf[MAX_ASYNC_BUFFER_SIZE];
267 bool drop_rts_on_tx_done;
268
269 struct _input_signal_events input_signal_events;
270
271 /* SPPP/Cisco HDLC device parts */
272 int netcount;
273 int dosyncppp;
274 spinlock_t netlock;
275
276 #if SYNCLINK_GENERIC_HDLC
277 struct net_device *netdev;
278 #endif
279
280 } SLMP_INFO;
281
282 #define MGSL_MAGIC 0x5401
283
284 /*
285 * define serial signal status change macros
286 */
287 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
288 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
289 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
290 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
291
292 /* Common Register macros */
293 #define LPR 0x00
294 #define PABR0 0x02
295 #define PABR1 0x03
296 #define WCRL 0x04
297 #define WCRM 0x05
298 #define WCRH 0x06
299 #define DPCR 0x08
300 #define DMER 0x09
301 #define ISR0 0x10
302 #define ISR1 0x11
303 #define ISR2 0x12
304 #define IER0 0x14
305 #define IER1 0x15
306 #define IER2 0x16
307 #define ITCR 0x18
308 #define INTVR 0x1a
309 #define IMVR 0x1c
310
311 /* MSCI Register macros */
312 #define TRB 0x20
313 #define TRBL 0x20
314 #define TRBH 0x21
315 #define SR0 0x22
316 #define SR1 0x23
317 #define SR2 0x24
318 #define SR3 0x25
319 #define FST 0x26
320 #define IE0 0x28
321 #define IE1 0x29
322 #define IE2 0x2a
323 #define FIE 0x2b
324 #define CMD 0x2c
325 #define MD0 0x2e
326 #define MD1 0x2f
327 #define MD2 0x30
328 #define CTL 0x31
329 #define SA0 0x32
330 #define SA1 0x33
331 #define IDL 0x34
332 #define TMC 0x35
333 #define RXS 0x36
334 #define TXS 0x37
335 #define TRC0 0x38
336 #define TRC1 0x39
337 #define RRC 0x3a
338 #define CST0 0x3c
339 #define CST1 0x3d
340
341 /* Timer Register Macros */
342 #define TCNT 0x60
343 #define TCNTL 0x60
344 #define TCNTH 0x61
345 #define TCONR 0x62
346 #define TCONRL 0x62
347 #define TCONRH 0x63
348 #define TMCS 0x64
349 #define TEPR 0x65
350
351 /* DMA Controller Register macros */
352 #define DARL 0x80
353 #define DARH 0x81
354 #define DARB 0x82
355 #define BAR 0x80
356 #define BARL 0x80
357 #define BARH 0x81
358 #define BARB 0x82
359 #define SAR 0x84
360 #define SARL 0x84
361 #define SARH 0x85
362 #define SARB 0x86
363 #define CPB 0x86
364 #define CDA 0x88
365 #define CDAL 0x88
366 #define CDAH 0x89
367 #define EDA 0x8a
368 #define EDAL 0x8a
369 #define EDAH 0x8b
370 #define BFL 0x8c
371 #define BFLL 0x8c
372 #define BFLH 0x8d
373 #define BCR 0x8e
374 #define BCRL 0x8e
375 #define BCRH 0x8f
376 #define DSR 0x90
377 #define DMR 0x91
378 #define FCT 0x93
379 #define DIR 0x94
380 #define DCMD 0x95
381
382 /* combine with timer or DMA register address */
383 #define TIMER0 0x00
384 #define TIMER1 0x08
385 #define TIMER2 0x10
386 #define TIMER3 0x18
387 #define RXDMA 0x00
388 #define TXDMA 0x20
389
390 /* SCA Command Codes */
391 #define NOOP 0x00
392 #define TXRESET 0x01
393 #define TXENABLE 0x02
394 #define TXDISABLE 0x03
395 #define TXCRCINIT 0x04
396 #define TXCRCEXCL 0x05
397 #define TXEOM 0x06
398 #define TXABORT 0x07
399 #define MPON 0x08
400 #define TXBUFCLR 0x09
401 #define RXRESET 0x11
402 #define RXENABLE 0x12
403 #define RXDISABLE 0x13
404 #define RXCRCINIT 0x14
405 #define RXREJECT 0x15
406 #define SEARCHMP 0x16
407 #define RXCRCEXCL 0x17
408 #define RXCRCCALC 0x18
409 #define CHRESET 0x21
410 #define HUNT 0x31
411
412 /* DMA command codes */
413 #define SWABORT 0x01
414 #define FEICLEAR 0x02
415
416 /* IE0 */
417 #define TXINTE BIT7
418 #define RXINTE BIT6
419 #define TXRDYE BIT1
420 #define RXRDYE BIT0
421
422 /* IE1 & SR1 */
423 #define UDRN BIT7
424 #define IDLE BIT6
425 #define SYNCD BIT4
426 #define FLGD BIT4
427 #define CCTS BIT3
428 #define CDCD BIT2
429 #define BRKD BIT1
430 #define ABTD BIT1
431 #define GAPD BIT1
432 #define BRKE BIT0
433 #define IDLD BIT0
434
435 /* IE2 & SR2 */
436 #define EOM BIT7
437 #define PMP BIT6
438 #define SHRT BIT6
439 #define PE BIT5
440 #define ABT BIT5
441 #define FRME BIT4
442 #define RBIT BIT4
443 #define OVRN BIT3
444 #define CRCE BIT2
445
446
447 /*
448 * Global linked list of SyncLink devices
449 */
450 static SLMP_INFO *synclinkmp_device_list = NULL;
451 static int synclinkmp_adapter_count = -1;
452 static int synclinkmp_device_count = 0;
453
454 /*
455 * Set this param to non-zero to load eax with the
456 * .text section address and breakpoint on module load.
457 * This is useful for use with gdb and add-symbol-file command.
458 */
459 static int break_on_load = 0;
460
461 /*
462 * Driver major number, defaults to zero to get auto
463 * assigned major number. May be forced as module parameter.
464 */
465 static int ttymajor = 0;
466
467 /*
468 * Array of user specified options for ISA adapters.
469 */
470 static int debug_level = 0;
471 static int maxframe[MAX_DEVICES] = {0,};
472 static int dosyncppp[MAX_DEVICES] = {0,};
473
474 module_param(break_on_load, bool, 0);
475 module_param(ttymajor, int, 0);
476 module_param(debug_level, int, 0);
477 module_param_array(maxframe, int, NULL, 0);
478 module_param_array(dosyncppp, int, NULL, 0);
479
480 static char *driver_name = "SyncLink MultiPort driver";
481 static char *driver_version = "$Revision: 4.38 $";
482
483 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
484 static void synclinkmp_remove_one(struct pci_dev *dev);
485
486 static struct pci_device_id synclinkmp_pci_tbl[] = {
487 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
488 { 0, }, /* terminate list */
489 };
490 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
491
492 MODULE_LICENSE("GPL");
493
494 static struct pci_driver synclinkmp_pci_driver = {
495 .name = "synclinkmp",
496 .id_table = synclinkmp_pci_tbl,
497 .probe = synclinkmp_init_one,
498 .remove = __devexit_p(synclinkmp_remove_one),
499 };
500
501
502 static struct tty_driver *serial_driver;
503
504 /* number of characters left in xmit buffer before we ask for more */
505 #define WAKEUP_CHARS 256
506
507
508 /* tty callbacks */
509
510 static int open(struct tty_struct *tty, struct file * filp);
511 static void close(struct tty_struct *tty, struct file * filp);
512 static void hangup(struct tty_struct *tty);
513 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
514
515 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
516 static int put_char(struct tty_struct *tty, unsigned char ch);
517 static void send_xchar(struct tty_struct *tty, char ch);
518 static void wait_until_sent(struct tty_struct *tty, int timeout);
519 static int write_room(struct tty_struct *tty);
520 static void flush_chars(struct tty_struct *tty);
521 static void flush_buffer(struct tty_struct *tty);
522 static void tx_hold(struct tty_struct *tty);
523 static void tx_release(struct tty_struct *tty);
524
525 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
526 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
527 static int chars_in_buffer(struct tty_struct *tty);
528 static void throttle(struct tty_struct * tty);
529 static void unthrottle(struct tty_struct * tty);
530 static int set_break(struct tty_struct *tty, int break_state);
531
532 #if SYNCLINK_GENERIC_HDLC
533 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
534 static void hdlcdev_tx_done(SLMP_INFO *info);
535 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
536 static int hdlcdev_init(SLMP_INFO *info);
537 static void hdlcdev_exit(SLMP_INFO *info);
538 #endif
539
540 /* ioctl handlers */
541
542 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
543 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
544 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
545 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
546 static int set_txidle(SLMP_INFO *info, int idle_mode);
547 static int tx_enable(SLMP_INFO *info, int enable);
548 static int tx_abort(SLMP_INFO *info);
549 static int rx_enable(SLMP_INFO *info, int enable);
550 static int modem_input_wait(SLMP_INFO *info,int arg);
551 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
552 static int tiocmget(struct tty_struct *tty, struct file *file);
553 static int tiocmset(struct tty_struct *tty, struct file *file,
554 unsigned int set, unsigned int clear);
555 static int set_break(struct tty_struct *tty, int break_state);
556
557 static void add_device(SLMP_INFO *info);
558 static void device_init(int adapter_num, struct pci_dev *pdev);
559 static int claim_resources(SLMP_INFO *info);
560 static void release_resources(SLMP_INFO *info);
561
562 static int startup(SLMP_INFO *info);
563 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
564 static void shutdown(SLMP_INFO *info);
565 static void program_hw(SLMP_INFO *info);
566 static void change_params(SLMP_INFO *info);
567
568 static bool init_adapter(SLMP_INFO *info);
569 static bool register_test(SLMP_INFO *info);
570 static bool irq_test(SLMP_INFO *info);
571 static bool loopback_test(SLMP_INFO *info);
572 static int adapter_test(SLMP_INFO *info);
573 static bool memory_test(SLMP_INFO *info);
574
575 static void reset_adapter(SLMP_INFO *info);
576 static void reset_port(SLMP_INFO *info);
577 static void async_mode(SLMP_INFO *info);
578 static void hdlc_mode(SLMP_INFO *info);
579
580 static void rx_stop(SLMP_INFO *info);
581 static void rx_start(SLMP_INFO *info);
582 static void rx_reset_buffers(SLMP_INFO *info);
583 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
584 static bool rx_get_frame(SLMP_INFO *info);
585
586 static void tx_start(SLMP_INFO *info);
587 static void tx_stop(SLMP_INFO *info);
588 static void tx_load_fifo(SLMP_INFO *info);
589 static void tx_set_idle(SLMP_INFO *info);
590 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
591
592 static void get_signals(SLMP_INFO *info);
593 static void set_signals(SLMP_INFO *info);
594 static void enable_loopback(SLMP_INFO *info, int enable);
595 static void set_rate(SLMP_INFO *info, u32 data_rate);
596
597 static int bh_action(SLMP_INFO *info);
598 static void bh_handler(struct work_struct *work);
599 static void bh_receive(SLMP_INFO *info);
600 static void bh_transmit(SLMP_INFO *info);
601 static void bh_status(SLMP_INFO *info);
602 static void isr_timer(SLMP_INFO *info);
603 static void isr_rxint(SLMP_INFO *info);
604 static void isr_rxrdy(SLMP_INFO *info);
605 static void isr_txint(SLMP_INFO *info);
606 static void isr_txrdy(SLMP_INFO *info);
607 static void isr_rxdmaok(SLMP_INFO *info);
608 static void isr_rxdmaerror(SLMP_INFO *info);
609 static void isr_txdmaok(SLMP_INFO *info);
610 static void isr_txdmaerror(SLMP_INFO *info);
611 static void isr_io_pin(SLMP_INFO *info, u16 status);
612
613 static int alloc_dma_bufs(SLMP_INFO *info);
614 static void free_dma_bufs(SLMP_INFO *info);
615 static int alloc_buf_list(SLMP_INFO *info);
616 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
617 static int alloc_tmp_rx_buf(SLMP_INFO *info);
618 static void free_tmp_rx_buf(SLMP_INFO *info);
619
620 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
621 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
622 static void tx_timeout(unsigned long context);
623 static void status_timeout(unsigned long context);
624
625 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
626 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
627 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
628 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
629 static unsigned char read_status_reg(SLMP_INFO * info);
630 static void write_control_reg(SLMP_INFO * info);
631
632
633 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
634 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
635 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
636
637 static u32 misc_ctrl_value = 0x007e4040;
638 static u32 lcr1_brdr_value = 0x00800028;
639
640 static u32 read_ahead_count = 8;
641
642 /* DPCR, DMA Priority Control
643 *
644 * 07..05 Not used, must be 0
645 * 04 BRC, bus release condition: 0=all transfers complete
646 * 1=release after 1 xfer on all channels
647 * 03 CCC, channel change condition: 0=every cycle
648 * 1=after each channel completes all xfers
649 * 02..00 PR<2..0>, priority 100=round robin
650 *
651 * 00000100 = 0x00
652 */
653 static unsigned char dma_priority = 0x04;
654
655 // Number of bytes that can be written to shared RAM
656 // in a single write operation
657 static u32 sca_pci_load_interval = 64;
658
659 /*
660 * 1st function defined in .text section. Calling this function in
661 * init_module() followed by a breakpoint allows a remote debugger
662 * (gdb) to get the .text address for the add-symbol-file command.
663 * This allows remote debugging of dynamically loadable modules.
664 */
665 static void* synclinkmp_get_text_ptr(void);
666 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
667
668 static inline int sanity_check(SLMP_INFO *info,
669 char *name, const char *routine)
670 {
671 #ifdef SANITY_CHECK
672 static const char *badmagic =
673 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
674 static const char *badinfo =
675 "Warning: null synclinkmp_struct for (%s) in %s\n";
676
677 if (!info) {
678 printk(badinfo, name, routine);
679 return 1;
680 }
681 if (info->magic != MGSL_MAGIC) {
682 printk(badmagic, name, routine);
683 return 1;
684 }
685 #else
686 if (!info)
687 return 1;
688 #endif
689 return 0;
690 }
691
692 /**
693 * line discipline callback wrappers
694 *
695 * The wrappers maintain line discipline references
696 * while calling into the line discipline.
697 *
698 * ldisc_receive_buf - pass receive data to line discipline
699 */
700
701 static void ldisc_receive_buf(struct tty_struct *tty,
702 const __u8 *data, char *flags, int count)
703 {
704 struct tty_ldisc *ld;
705 if (!tty)
706 return;
707 ld = tty_ldisc_ref(tty);
708 if (ld) {
709 if (ld->ops->receive_buf)
710 ld->ops->receive_buf(tty, data, flags, count);
711 tty_ldisc_deref(ld);
712 }
713 }
714
715 /* tty callbacks */
716
717 /* Called when a port is opened. Init and enable port.
718 */
719 static int open(struct tty_struct *tty, struct file *filp)
720 {
721 SLMP_INFO *info;
722 int retval, line;
723 unsigned long flags;
724
725 line = tty->index;
726 if ((line < 0) || (line >= synclinkmp_device_count)) {
727 printk("%s(%d): open with invalid line #%d.\n",
728 __FILE__,__LINE__,line);
729 return -ENODEV;
730 }
731
732 info = synclinkmp_device_list;
733 while(info && info->line != line)
734 info = info->next_device;
735 if (sanity_check(info, tty->name, "open"))
736 return -ENODEV;
737 if ( info->init_error ) {
738 printk("%s(%d):%s device is not allocated, init error=%d\n",
739 __FILE__,__LINE__,info->device_name,info->init_error);
740 return -ENODEV;
741 }
742
743 tty->driver_data = info;
744 info->port.tty = tty;
745
746 if (debug_level >= DEBUG_LEVEL_INFO)
747 printk("%s(%d):%s open(), old ref count = %d\n",
748 __FILE__,__LINE__,tty->driver->name, info->port.count);
749
750 /* If port is closing, signal caller to try again */
751 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
752 if (info->port.flags & ASYNC_CLOSING)
753 interruptible_sleep_on(&info->port.close_wait);
754 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
755 -EAGAIN : -ERESTARTSYS);
756 goto cleanup;
757 }
758
759 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
760
761 spin_lock_irqsave(&info->netlock, flags);
762 if (info->netcount) {
763 retval = -EBUSY;
764 spin_unlock_irqrestore(&info->netlock, flags);
765 goto cleanup;
766 }
767 info->port.count++;
768 spin_unlock_irqrestore(&info->netlock, flags);
769
770 if (info->port.count == 1) {
771 /* 1st open on this device, init hardware */
772 retval = startup(info);
773 if (retval < 0)
774 goto cleanup;
775 }
776
777 retval = block_til_ready(tty, filp, info);
778 if (retval) {
779 if (debug_level >= DEBUG_LEVEL_INFO)
780 printk("%s(%d):%s block_til_ready() returned %d\n",
781 __FILE__,__LINE__, info->device_name, retval);
782 goto cleanup;
783 }
784
785 if (debug_level >= DEBUG_LEVEL_INFO)
786 printk("%s(%d):%s open() success\n",
787 __FILE__,__LINE__, info->device_name);
788 retval = 0;
789
790 cleanup:
791 if (retval) {
792 if (tty->count == 1)
793 info->port.tty = NULL; /* tty layer will release tty struct */
794 if(info->port.count)
795 info->port.count--;
796 }
797
798 return retval;
799 }
800
801 /* Called when port is closed. Wait for remaining data to be
802 * sent. Disable port and free resources.
803 */
804 static void close(struct tty_struct *tty, struct file *filp)
805 {
806 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
807
808 if (sanity_check(info, tty->name, "close"))
809 return;
810
811 if (debug_level >= DEBUG_LEVEL_INFO)
812 printk("%s(%d):%s close() entry, count=%d\n",
813 __FILE__,__LINE__, info->device_name, info->port.count);
814
815 if (!info->port.count)
816 return;
817
818 if (tty_hung_up_p(filp))
819 goto cleanup;
820
821 if ((tty->count == 1) && (info->port.count != 1)) {
822 /*
823 * tty->count is 1 and the tty structure will be freed.
824 * info->port.count should be one in this case.
825 * if it's not, correct it so that the port is shutdown.
826 */
827 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
828 "info->port.count is %d\n",
829 __FILE__,__LINE__, info->device_name, info->port.count);
830 info->port.count = 1;
831 }
832
833 info->port.count--;
834
835 /* if at least one open remaining, leave hardware active */
836 if (info->port.count)
837 goto cleanup;
838
839 info->port.flags |= ASYNC_CLOSING;
840
841 /* set tty->closing to notify line discipline to
842 * only process XON/XOFF characters. Only the N_TTY
843 * discipline appears to use this (ppp does not).
844 */
845 tty->closing = 1;
846
847 /* wait for transmit data to clear all layers */
848
849 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
850 if (debug_level >= DEBUG_LEVEL_INFO)
851 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
852 __FILE__,__LINE__, info->device_name );
853 tty_wait_until_sent(tty, info->port.closing_wait);
854 }
855
856 if (info->port.flags & ASYNC_INITIALIZED)
857 wait_until_sent(tty, info->timeout);
858
859 flush_buffer(tty);
860
861 tty_ldisc_flush(tty);
862
863 shutdown(info);
864
865 tty->closing = 0;
866 info->port.tty = NULL;
867
868 if (info->port.blocked_open) {
869 if (info->port.close_delay) {
870 msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
871 }
872 wake_up_interruptible(&info->port.open_wait);
873 }
874
875 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
876
877 wake_up_interruptible(&info->port.close_wait);
878
879 cleanup:
880 if (debug_level >= DEBUG_LEVEL_INFO)
881 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
882 tty->driver->name, info->port.count);
883 }
884
885 /* Called by tty_hangup() when a hangup is signaled.
886 * This is the same as closing all open descriptors for the port.
887 */
888 static void hangup(struct tty_struct *tty)
889 {
890 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
891
892 if (debug_level >= DEBUG_LEVEL_INFO)
893 printk("%s(%d):%s hangup()\n",
894 __FILE__,__LINE__, info->device_name );
895
896 if (sanity_check(info, tty->name, "hangup"))
897 return;
898
899 flush_buffer(tty);
900 shutdown(info);
901
902 info->port.count = 0;
903 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
904 info->port.tty = NULL;
905
906 wake_up_interruptible(&info->port.open_wait);
907 }
908
909 /* Set new termios settings
910 */
911 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
912 {
913 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
914 unsigned long flags;
915
916 if (debug_level >= DEBUG_LEVEL_INFO)
917 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
918 tty->driver->name );
919
920 change_params(info);
921
922 /* Handle transition to B0 status */
923 if (old_termios->c_cflag & CBAUD &&
924 !(tty->termios->c_cflag & CBAUD)) {
925 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
926 spin_lock_irqsave(&info->lock,flags);
927 set_signals(info);
928 spin_unlock_irqrestore(&info->lock,flags);
929 }
930
931 /* Handle transition away from B0 status */
932 if (!(old_termios->c_cflag & CBAUD) &&
933 tty->termios->c_cflag & CBAUD) {
934 info->serial_signals |= SerialSignal_DTR;
935 if (!(tty->termios->c_cflag & CRTSCTS) ||
936 !test_bit(TTY_THROTTLED, &tty->flags)) {
937 info->serial_signals |= SerialSignal_RTS;
938 }
939 spin_lock_irqsave(&info->lock,flags);
940 set_signals(info);
941 spin_unlock_irqrestore(&info->lock,flags);
942 }
943
944 /* Handle turning off CRTSCTS */
945 if (old_termios->c_cflag & CRTSCTS &&
946 !(tty->termios->c_cflag & CRTSCTS)) {
947 tty->hw_stopped = 0;
948 tx_release(tty);
949 }
950 }
951
952 /* Send a block of data
953 *
954 * Arguments:
955 *
956 * tty pointer to tty information structure
957 * buf pointer to buffer containing send data
958 * count size of send data in bytes
959 *
960 * Return Value: number of characters written
961 */
962 static int write(struct tty_struct *tty,
963 const unsigned char *buf, int count)
964 {
965 int c, ret = 0;
966 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
967 unsigned long flags;
968
969 if (debug_level >= DEBUG_LEVEL_INFO)
970 printk("%s(%d):%s write() count=%d\n",
971 __FILE__,__LINE__,info->device_name,count);
972
973 if (sanity_check(info, tty->name, "write"))
974 goto cleanup;
975
976 if (!info->tx_buf)
977 goto cleanup;
978
979 if (info->params.mode == MGSL_MODE_HDLC) {
980 if (count > info->max_frame_size) {
981 ret = -EIO;
982 goto cleanup;
983 }
984 if (info->tx_active)
985 goto cleanup;
986 if (info->tx_count) {
987 /* send accumulated data from send_char() calls */
988 /* as frame and wait before accepting more data. */
989 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
990 goto start;
991 }
992 ret = info->tx_count = count;
993 tx_load_dma_buffer(info, buf, count);
994 goto start;
995 }
996
997 for (;;) {
998 c = min_t(int, count,
999 min(info->max_frame_size - info->tx_count - 1,
1000 info->max_frame_size - info->tx_put));
1001 if (c <= 0)
1002 break;
1003
1004 memcpy(info->tx_buf + info->tx_put, buf, c);
1005
1006 spin_lock_irqsave(&info->lock,flags);
1007 info->tx_put += c;
1008 if (info->tx_put >= info->max_frame_size)
1009 info->tx_put -= info->max_frame_size;
1010 info->tx_count += c;
1011 spin_unlock_irqrestore(&info->lock,flags);
1012
1013 buf += c;
1014 count -= c;
1015 ret += c;
1016 }
1017
1018 if (info->params.mode == MGSL_MODE_HDLC) {
1019 if (count) {
1020 ret = info->tx_count = 0;
1021 goto cleanup;
1022 }
1023 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1024 }
1025 start:
1026 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1027 spin_lock_irqsave(&info->lock,flags);
1028 if (!info->tx_active)
1029 tx_start(info);
1030 spin_unlock_irqrestore(&info->lock,flags);
1031 }
1032
1033 cleanup:
1034 if (debug_level >= DEBUG_LEVEL_INFO)
1035 printk( "%s(%d):%s write() returning=%d\n",
1036 __FILE__,__LINE__,info->device_name,ret);
1037 return ret;
1038 }
1039
1040 /* Add a character to the transmit buffer.
1041 */
1042 static int put_char(struct tty_struct *tty, unsigned char ch)
1043 {
1044 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1045 unsigned long flags;
1046 int ret = 0;
1047
1048 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1049 printk( "%s(%d):%s put_char(%d)\n",
1050 __FILE__,__LINE__,info->device_name,ch);
1051 }
1052
1053 if (sanity_check(info, tty->name, "put_char"))
1054 return 0;
1055
1056 if (!info->tx_buf)
1057 return 0;
1058
1059 spin_lock_irqsave(&info->lock,flags);
1060
1061 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1062 !info->tx_active ) {
1063
1064 if (info->tx_count < info->max_frame_size - 1) {
1065 info->tx_buf[info->tx_put++] = ch;
1066 if (info->tx_put >= info->max_frame_size)
1067 info->tx_put -= info->max_frame_size;
1068 info->tx_count++;
1069 ret = 1;
1070 }
1071 }
1072
1073 spin_unlock_irqrestore(&info->lock,flags);
1074 return ret;
1075 }
1076
1077 /* Send a high-priority XON/XOFF character
1078 */
1079 static void send_xchar(struct tty_struct *tty, char ch)
1080 {
1081 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1082 unsigned long flags;
1083
1084 if (debug_level >= DEBUG_LEVEL_INFO)
1085 printk("%s(%d):%s send_xchar(%d)\n",
1086 __FILE__,__LINE__, info->device_name, ch );
1087
1088 if (sanity_check(info, tty->name, "send_xchar"))
1089 return;
1090
1091 info->x_char = ch;
1092 if (ch) {
1093 /* Make sure transmit interrupts are on */
1094 spin_lock_irqsave(&info->lock,flags);
1095 if (!info->tx_enabled)
1096 tx_start(info);
1097 spin_unlock_irqrestore(&info->lock,flags);
1098 }
1099 }
1100
1101 /* Wait until the transmitter is empty.
1102 */
1103 static void wait_until_sent(struct tty_struct *tty, int timeout)
1104 {
1105 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1106 unsigned long orig_jiffies, char_time;
1107
1108 if (!info )
1109 return;
1110
1111 if (debug_level >= DEBUG_LEVEL_INFO)
1112 printk("%s(%d):%s wait_until_sent() entry\n",
1113 __FILE__,__LINE__, info->device_name );
1114
1115 if (sanity_check(info, tty->name, "wait_until_sent"))
1116 return;
1117
1118 lock_kernel();
1119
1120 if (!(info->port.flags & ASYNC_INITIALIZED))
1121 goto exit;
1122
1123 orig_jiffies = jiffies;
1124
1125 /* Set check interval to 1/5 of estimated time to
1126 * send a character, and make it at least 1. The check
1127 * interval should also be less than the timeout.
1128 * Note: use tight timings here to satisfy the NIST-PCTS.
1129 */
1130
1131 if ( info->params.data_rate ) {
1132 char_time = info->timeout/(32 * 5);
1133 if (!char_time)
1134 char_time++;
1135 } else
1136 char_time = 1;
1137
1138 if (timeout)
1139 char_time = min_t(unsigned long, char_time, timeout);
1140
1141 if ( info->params.mode == MGSL_MODE_HDLC ) {
1142 while (info->tx_active) {
1143 msleep_interruptible(jiffies_to_msecs(char_time));
1144 if (signal_pending(current))
1145 break;
1146 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1147 break;
1148 }
1149 } else {
1150 //TODO: determine if there is something similar to USC16C32
1151 // TXSTATUS_ALL_SENT status
1152 while ( info->tx_active && info->tx_enabled) {
1153 msleep_interruptible(jiffies_to_msecs(char_time));
1154 if (signal_pending(current))
1155 break;
1156 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1157 break;
1158 }
1159 }
1160
1161 exit:
1162 unlock_kernel();
1163 if (debug_level >= DEBUG_LEVEL_INFO)
1164 printk("%s(%d):%s wait_until_sent() exit\n",
1165 __FILE__,__LINE__, info->device_name );
1166 }
1167
1168 /* Return the count of free bytes in transmit buffer
1169 */
1170 static int write_room(struct tty_struct *tty)
1171 {
1172 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1173 int ret;
1174
1175 if (sanity_check(info, tty->name, "write_room"))
1176 return 0;
1177
1178 lock_kernel();
1179 if (info->params.mode == MGSL_MODE_HDLC) {
1180 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1181 } else {
1182 ret = info->max_frame_size - info->tx_count - 1;
1183 if (ret < 0)
1184 ret = 0;
1185 }
1186 unlock_kernel();
1187
1188 if (debug_level >= DEBUG_LEVEL_INFO)
1189 printk("%s(%d):%s write_room()=%d\n",
1190 __FILE__, __LINE__, info->device_name, ret);
1191
1192 return ret;
1193 }
1194
1195 /* enable transmitter and send remaining buffered characters
1196 */
1197 static void flush_chars(struct tty_struct *tty)
1198 {
1199 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1200 unsigned long flags;
1201
1202 if ( debug_level >= DEBUG_LEVEL_INFO )
1203 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1204 __FILE__,__LINE__,info->device_name,info->tx_count);
1205
1206 if (sanity_check(info, tty->name, "flush_chars"))
1207 return;
1208
1209 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1210 !info->tx_buf)
1211 return;
1212
1213 if ( debug_level >= DEBUG_LEVEL_INFO )
1214 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1215 __FILE__,__LINE__,info->device_name );
1216
1217 spin_lock_irqsave(&info->lock,flags);
1218
1219 if (!info->tx_active) {
1220 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1221 info->tx_count ) {
1222 /* operating in synchronous (frame oriented) mode */
1223 /* copy data from circular tx_buf to */
1224 /* transmit DMA buffer. */
1225 tx_load_dma_buffer(info,
1226 info->tx_buf,info->tx_count);
1227 }
1228 tx_start(info);
1229 }
1230
1231 spin_unlock_irqrestore(&info->lock,flags);
1232 }
1233
1234 /* Discard all data in the send buffer
1235 */
1236 static void flush_buffer(struct tty_struct *tty)
1237 {
1238 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1239 unsigned long flags;
1240
1241 if (debug_level >= DEBUG_LEVEL_INFO)
1242 printk("%s(%d):%s flush_buffer() entry\n",
1243 __FILE__,__LINE__, info->device_name );
1244
1245 if (sanity_check(info, tty->name, "flush_buffer"))
1246 return;
1247
1248 spin_lock_irqsave(&info->lock,flags);
1249 info->tx_count = info->tx_put = info->tx_get = 0;
1250 del_timer(&info->tx_timer);
1251 spin_unlock_irqrestore(&info->lock,flags);
1252
1253 tty_wakeup(tty);
1254 }
1255
1256 /* throttle (stop) transmitter
1257 */
1258 static void tx_hold(struct tty_struct *tty)
1259 {
1260 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1261 unsigned long flags;
1262
1263 if (sanity_check(info, tty->name, "tx_hold"))
1264 return;
1265
1266 if ( debug_level >= DEBUG_LEVEL_INFO )
1267 printk("%s(%d):%s tx_hold()\n",
1268 __FILE__,__LINE__,info->device_name);
1269
1270 spin_lock_irqsave(&info->lock,flags);
1271 if (info->tx_enabled)
1272 tx_stop(info);
1273 spin_unlock_irqrestore(&info->lock,flags);
1274 }
1275
1276 /* release (start) transmitter
1277 */
1278 static void tx_release(struct tty_struct *tty)
1279 {
1280 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1281 unsigned long flags;
1282
1283 if (sanity_check(info, tty->name, "tx_release"))
1284 return;
1285
1286 if ( debug_level >= DEBUG_LEVEL_INFO )
1287 printk("%s(%d):%s tx_release()\n",
1288 __FILE__,__LINE__,info->device_name);
1289
1290 spin_lock_irqsave(&info->lock,flags);
1291 if (!info->tx_enabled)
1292 tx_start(info);
1293 spin_unlock_irqrestore(&info->lock,flags);
1294 }
1295
1296 /* Service an IOCTL request
1297 *
1298 * Arguments:
1299 *
1300 * tty pointer to tty instance data
1301 * file pointer to associated file object for device
1302 * cmd IOCTL command code
1303 * arg command argument/context
1304 *
1305 * Return Value: 0 if success, otherwise error code
1306 */
1307 static int do_ioctl(struct tty_struct *tty, struct file *file,
1308 unsigned int cmd, unsigned long arg)
1309 {
1310 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1311 int error;
1312 struct mgsl_icount cnow; /* kernel counter temps */
1313 struct serial_icounter_struct __user *p_cuser; /* user space */
1314 unsigned long flags;
1315 void __user *argp = (void __user *)arg;
1316
1317 if (debug_level >= DEBUG_LEVEL_INFO)
1318 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1319 info->device_name, cmd );
1320
1321 if (sanity_check(info, tty->name, "ioctl"))
1322 return -ENODEV;
1323
1324 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1325 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1326 if (tty->flags & (1 << TTY_IO_ERROR))
1327 return -EIO;
1328 }
1329
1330 switch (cmd) {
1331 case MGSL_IOCGPARAMS:
1332 return get_params(info, argp);
1333 case MGSL_IOCSPARAMS:
1334 return set_params(info, argp);
1335 case MGSL_IOCGTXIDLE:
1336 return get_txidle(info, argp);
1337 case MGSL_IOCSTXIDLE:
1338 return set_txidle(info, (int)arg);
1339 case MGSL_IOCTXENABLE:
1340 return tx_enable(info, (int)arg);
1341 case MGSL_IOCRXENABLE:
1342 return rx_enable(info, (int)arg);
1343 case MGSL_IOCTXABORT:
1344 return tx_abort(info);
1345 case MGSL_IOCGSTATS:
1346 return get_stats(info, argp);
1347 case MGSL_IOCWAITEVENT:
1348 return wait_mgsl_event(info, argp);
1349 case MGSL_IOCLOOPTXDONE:
1350 return 0; // TODO: Not supported, need to document
1351 /* Wait for modem input (DCD,RI,DSR,CTS) change
1352 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1353 */
1354 case TIOCMIWAIT:
1355 return modem_input_wait(info,(int)arg);
1356
1357 /*
1358 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1359 * Return: write counters to the user passed counter struct
1360 * NB: both 1->0 and 0->1 transitions are counted except for
1361 * RI where only 0->1 is counted.
1362 */
1363 case TIOCGICOUNT:
1364 spin_lock_irqsave(&info->lock,flags);
1365 cnow = info->icount;
1366 spin_unlock_irqrestore(&info->lock,flags);
1367 p_cuser = argp;
1368 PUT_USER(error,cnow.cts, &p_cuser->cts);
1369 if (error) return error;
1370 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1371 if (error) return error;
1372 PUT_USER(error,cnow.rng, &p_cuser->rng);
1373 if (error) return error;
1374 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1375 if (error) return error;
1376 PUT_USER(error,cnow.rx, &p_cuser->rx);
1377 if (error) return error;
1378 PUT_USER(error,cnow.tx, &p_cuser->tx);
1379 if (error) return error;
1380 PUT_USER(error,cnow.frame, &p_cuser->frame);
1381 if (error) return error;
1382 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1383 if (error) return error;
1384 PUT_USER(error,cnow.parity, &p_cuser->parity);
1385 if (error) return error;
1386 PUT_USER(error,cnow.brk, &p_cuser->brk);
1387 if (error) return error;
1388 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1389 if (error) return error;
1390 return 0;
1391 default:
1392 return -ENOIOCTLCMD;
1393 }
1394 return 0;
1395 }
1396
1397 static int ioctl(struct tty_struct *tty, struct file *file,
1398 unsigned int cmd, unsigned long arg)
1399 {
1400 int ret;
1401 lock_kernel();
1402 ret = do_ioctl(tty, file, cmd, arg);
1403 unlock_kernel();
1404 return ret;
1405 }
1406
1407 /*
1408 * /proc fs routines....
1409 */
1410
1411 static inline int line_info(char *buf, SLMP_INFO *info)
1412 {
1413 char stat_buf[30];
1414 int ret;
1415 unsigned long flags;
1416
1417 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1418 "\tIRQ=%d MaxFrameSize=%u\n",
1419 info->device_name,
1420 info->phys_sca_base,
1421 info->phys_memory_base,
1422 info->phys_statctrl_base,
1423 info->phys_lcr_base,
1424 info->irq_level,
1425 info->max_frame_size );
1426
1427 /* output current serial signal states */
1428 spin_lock_irqsave(&info->lock,flags);
1429 get_signals(info);
1430 spin_unlock_irqrestore(&info->lock,flags);
1431
1432 stat_buf[0] = 0;
1433 stat_buf[1] = 0;
1434 if (info->serial_signals & SerialSignal_RTS)
1435 strcat(stat_buf, "|RTS");
1436 if (info->serial_signals & SerialSignal_CTS)
1437 strcat(stat_buf, "|CTS");
1438 if (info->serial_signals & SerialSignal_DTR)
1439 strcat(stat_buf, "|DTR");
1440 if (info->serial_signals & SerialSignal_DSR)
1441 strcat(stat_buf, "|DSR");
1442 if (info->serial_signals & SerialSignal_DCD)
1443 strcat(stat_buf, "|CD");
1444 if (info->serial_signals & SerialSignal_RI)
1445 strcat(stat_buf, "|RI");
1446
1447 if (info->params.mode == MGSL_MODE_HDLC) {
1448 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1449 info->icount.txok, info->icount.rxok);
1450 if (info->icount.txunder)
1451 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1452 if (info->icount.txabort)
1453 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1454 if (info->icount.rxshort)
1455 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1456 if (info->icount.rxlong)
1457 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1458 if (info->icount.rxover)
1459 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1460 if (info->icount.rxcrc)
1461 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1462 } else {
1463 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1464 info->icount.tx, info->icount.rx);
1465 if (info->icount.frame)
1466 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1467 if (info->icount.parity)
1468 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1469 if (info->icount.brk)
1470 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1471 if (info->icount.overrun)
1472 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1473 }
1474
1475 /* Append serial signal status to end */
1476 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1477
1478 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1479 info->tx_active,info->bh_requested,info->bh_running,
1480 info->pending_bh);
1481
1482 return ret;
1483 }
1484
1485 /* Called to print information about devices
1486 */
1487 static int read_proc(char *page, char **start, off_t off, int count,
1488 int *eof, void *data)
1489 {
1490 int len = 0, l;
1491 off_t begin = 0;
1492 SLMP_INFO *info;
1493
1494 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1495
1496 info = synclinkmp_device_list;
1497 while( info ) {
1498 l = line_info(page + len, info);
1499 len += l;
1500 if (len+begin > off+count)
1501 goto done;
1502 if (len+begin < off) {
1503 begin += len;
1504 len = 0;
1505 }
1506 info = info->next_device;
1507 }
1508
1509 *eof = 1;
1510 done:
1511 if (off >= len+begin)
1512 return 0;
1513 *start = page + (off-begin);
1514 return ((count < begin+len-off) ? count : begin+len-off);
1515 }
1516
1517 /* Return the count of bytes in transmit buffer
1518 */
1519 static int chars_in_buffer(struct tty_struct *tty)
1520 {
1521 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1522
1523 if (sanity_check(info, tty->name, "chars_in_buffer"))
1524 return 0;
1525
1526 if (debug_level >= DEBUG_LEVEL_INFO)
1527 printk("%s(%d):%s chars_in_buffer()=%d\n",
1528 __FILE__, __LINE__, info->device_name, info->tx_count);
1529
1530 return info->tx_count;
1531 }
1532
1533 /* Signal remote device to throttle send data (our receive data)
1534 */
1535 static void throttle(struct tty_struct * tty)
1536 {
1537 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1538 unsigned long flags;
1539
1540 if (debug_level >= DEBUG_LEVEL_INFO)
1541 printk("%s(%d):%s throttle() entry\n",
1542 __FILE__,__LINE__, info->device_name );
1543
1544 if (sanity_check(info, tty->name, "throttle"))
1545 return;
1546
1547 if (I_IXOFF(tty))
1548 send_xchar(tty, STOP_CHAR(tty));
1549
1550 if (tty->termios->c_cflag & CRTSCTS) {
1551 spin_lock_irqsave(&info->lock,flags);
1552 info->serial_signals &= ~SerialSignal_RTS;
1553 set_signals(info);
1554 spin_unlock_irqrestore(&info->lock,flags);
1555 }
1556 }
1557
1558 /* Signal remote device to stop throttling send data (our receive data)
1559 */
1560 static void unthrottle(struct tty_struct * tty)
1561 {
1562 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1563 unsigned long flags;
1564
1565 if (debug_level >= DEBUG_LEVEL_INFO)
1566 printk("%s(%d):%s unthrottle() entry\n",
1567 __FILE__,__LINE__, info->device_name );
1568
1569 if (sanity_check(info, tty->name, "unthrottle"))
1570 return;
1571
1572 if (I_IXOFF(tty)) {
1573 if (info->x_char)
1574 info->x_char = 0;
1575 else
1576 send_xchar(tty, START_CHAR(tty));
1577 }
1578
1579 if (tty->termios->c_cflag & CRTSCTS) {
1580 spin_lock_irqsave(&info->lock,flags);
1581 info->serial_signals |= SerialSignal_RTS;
1582 set_signals(info);
1583 spin_unlock_irqrestore(&info->lock,flags);
1584 }
1585 }
1586
1587 /* set or clear transmit break condition
1588 * break_state -1=set break condition, 0=clear
1589 */
1590 static int set_break(struct tty_struct *tty, int break_state)
1591 {
1592 unsigned char RegValue;
1593 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1594 unsigned long flags;
1595
1596 if (debug_level >= DEBUG_LEVEL_INFO)
1597 printk("%s(%d):%s set_break(%d)\n",
1598 __FILE__,__LINE__, info->device_name, break_state);
1599
1600 if (sanity_check(info, tty->name, "set_break"))
1601 return -EINVAL;
1602
1603 spin_lock_irqsave(&info->lock,flags);
1604 RegValue = read_reg(info, CTL);
1605 if (break_state == -1)
1606 RegValue |= BIT3;
1607 else
1608 RegValue &= ~BIT3;
1609 write_reg(info, CTL, RegValue);
1610 spin_unlock_irqrestore(&info->lock,flags);
1611 return 0;
1612 }
1613
1614 #if SYNCLINK_GENERIC_HDLC
1615
1616 /**
1617 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1618 * set encoding and frame check sequence (FCS) options
1619 *
1620 * dev pointer to network device structure
1621 * encoding serial encoding setting
1622 * parity FCS setting
1623 *
1624 * returns 0 if success, otherwise error code
1625 */
1626 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1627 unsigned short parity)
1628 {
1629 SLMP_INFO *info = dev_to_port(dev);
1630 unsigned char new_encoding;
1631 unsigned short new_crctype;
1632
1633 /* return error if TTY interface open */
1634 if (info->port.count)
1635 return -EBUSY;
1636
1637 switch (encoding)
1638 {
1639 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1640 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1641 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1642 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1643 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1644 default: return -EINVAL;
1645 }
1646
1647 switch (parity)
1648 {
1649 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1650 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1651 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1652 default: return -EINVAL;
1653 }
1654
1655 info->params.encoding = new_encoding;
1656 info->params.crc_type = new_crctype;
1657
1658 /* if network interface up, reprogram hardware */
1659 if (info->netcount)
1660 program_hw(info);
1661
1662 return 0;
1663 }
1664
1665 /**
1666 * called by generic HDLC layer to send frame
1667 *
1668 * skb socket buffer containing HDLC frame
1669 * dev pointer to network device structure
1670 *
1671 * returns 0 if success, otherwise error code
1672 */
1673 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1674 {
1675 SLMP_INFO *info = dev_to_port(dev);
1676 unsigned long flags;
1677
1678 if (debug_level >= DEBUG_LEVEL_INFO)
1679 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1680
1681 /* stop sending until this frame completes */
1682 netif_stop_queue(dev);
1683
1684 /* copy data to device buffers */
1685 info->tx_count = skb->len;
1686 tx_load_dma_buffer(info, skb->data, skb->len);
1687
1688 /* update network statistics */
1689 dev->stats.tx_packets++;
1690 dev->stats.tx_bytes += skb->len;
1691
1692 /* done with socket buffer, so free it */
1693 dev_kfree_skb(skb);
1694
1695 /* save start time for transmit timeout detection */
1696 dev->trans_start = jiffies;
1697
1698 /* start hardware transmitter if necessary */
1699 spin_lock_irqsave(&info->lock,flags);
1700 if (!info->tx_active)
1701 tx_start(info);
1702 spin_unlock_irqrestore(&info->lock,flags);
1703
1704 return 0;
1705 }
1706
1707 /**
1708 * called by network layer when interface enabled
1709 * claim resources and initialize hardware
1710 *
1711 * dev pointer to network device structure
1712 *
1713 * returns 0 if success, otherwise error code
1714 */
1715 static int hdlcdev_open(struct net_device *dev)
1716 {
1717 SLMP_INFO *info = dev_to_port(dev);
1718 int rc;
1719 unsigned long flags;
1720
1721 if (debug_level >= DEBUG_LEVEL_INFO)
1722 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1723
1724 /* generic HDLC layer open processing */
1725 if ((rc = hdlc_open(dev)))
1726 return rc;
1727
1728 /* arbitrate between network and tty opens */
1729 spin_lock_irqsave(&info->netlock, flags);
1730 if (info->port.count != 0 || info->netcount != 0) {
1731 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1732 spin_unlock_irqrestore(&info->netlock, flags);
1733 return -EBUSY;
1734 }
1735 info->netcount=1;
1736 spin_unlock_irqrestore(&info->netlock, flags);
1737
1738 /* claim resources and init adapter */
1739 if ((rc = startup(info)) != 0) {
1740 spin_lock_irqsave(&info->netlock, flags);
1741 info->netcount=0;
1742 spin_unlock_irqrestore(&info->netlock, flags);
1743 return rc;
1744 }
1745
1746 /* assert DTR and RTS, apply hardware settings */
1747 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1748 program_hw(info);
1749
1750 /* enable network layer transmit */
1751 dev->trans_start = jiffies;
1752 netif_start_queue(dev);
1753
1754 /* inform generic HDLC layer of current DCD status */
1755 spin_lock_irqsave(&info->lock, flags);
1756 get_signals(info);
1757 spin_unlock_irqrestore(&info->lock, flags);
1758 if (info->serial_signals & SerialSignal_DCD)
1759 netif_carrier_on(dev);
1760 else
1761 netif_carrier_off(dev);
1762 return 0;
1763 }
1764
1765 /**
1766 * called by network layer when interface is disabled
1767 * shutdown hardware and release resources
1768 *
1769 * dev pointer to network device structure
1770 *
1771 * returns 0 if success, otherwise error code
1772 */
1773 static int hdlcdev_close(struct net_device *dev)
1774 {
1775 SLMP_INFO *info = dev_to_port(dev);
1776 unsigned long flags;
1777
1778 if (debug_level >= DEBUG_LEVEL_INFO)
1779 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1780
1781 netif_stop_queue(dev);
1782
1783 /* shutdown adapter and release resources */
1784 shutdown(info);
1785
1786 hdlc_close(dev);
1787
1788 spin_lock_irqsave(&info->netlock, flags);
1789 info->netcount=0;
1790 spin_unlock_irqrestore(&info->netlock, flags);
1791
1792 return 0;
1793 }
1794
1795 /**
1796 * called by network layer to process IOCTL call to network device
1797 *
1798 * dev pointer to network device structure
1799 * ifr pointer to network interface request structure
1800 * cmd IOCTL command code
1801 *
1802 * returns 0 if success, otherwise error code
1803 */
1804 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1805 {
1806 const size_t size = sizeof(sync_serial_settings);
1807 sync_serial_settings new_line;
1808 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1809 SLMP_INFO *info = dev_to_port(dev);
1810 unsigned int flags;
1811
1812 if (debug_level >= DEBUG_LEVEL_INFO)
1813 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1814
1815 /* return error if TTY interface open */
1816 if (info->port.count)
1817 return -EBUSY;
1818
1819 if (cmd != SIOCWANDEV)
1820 return hdlc_ioctl(dev, ifr, cmd);
1821
1822 switch(ifr->ifr_settings.type) {
1823 case IF_GET_IFACE: /* return current sync_serial_settings */
1824
1825 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1826 if (ifr->ifr_settings.size < size) {
1827 ifr->ifr_settings.size = size; /* data size wanted */
1828 return -ENOBUFS;
1829 }
1830
1831 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1832 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1833 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1834 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1835
1836 switch (flags){
1837 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1838 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1839 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1840 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1841 default: new_line.clock_type = CLOCK_DEFAULT;
1842 }
1843
1844 new_line.clock_rate = info->params.clock_speed;
1845 new_line.loopback = info->params.loopback ? 1:0;
1846
1847 if (copy_to_user(line, &new_line, size))
1848 return -EFAULT;
1849 return 0;
1850
1851 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1852
1853 if(!capable(CAP_NET_ADMIN))
1854 return -EPERM;
1855 if (copy_from_user(&new_line, line, size))
1856 return -EFAULT;
1857
1858 switch (new_line.clock_type)
1859 {
1860 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1861 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1862 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1863 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1864 case CLOCK_DEFAULT: flags = info->params.flags &
1865 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1866 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1867 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1868 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1869 default: return -EINVAL;
1870 }
1871
1872 if (new_line.loopback != 0 && new_line.loopback != 1)
1873 return -EINVAL;
1874
1875 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1876 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1877 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1878 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1879 info->params.flags |= flags;
1880
1881 info->params.loopback = new_line.loopback;
1882
1883 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1884 info->params.clock_speed = new_line.clock_rate;
1885 else
1886 info->params.clock_speed = 0;
1887
1888 /* if network interface up, reprogram hardware */
1889 if (info->netcount)
1890 program_hw(info);
1891 return 0;
1892
1893 default:
1894 return hdlc_ioctl(dev, ifr, cmd);
1895 }
1896 }
1897
1898 /**
1899 * called by network layer when transmit timeout is detected
1900 *
1901 * dev pointer to network device structure
1902 */
1903 static void hdlcdev_tx_timeout(struct net_device *dev)
1904 {
1905 SLMP_INFO *info = dev_to_port(dev);
1906 unsigned long flags;
1907
1908 if (debug_level >= DEBUG_LEVEL_INFO)
1909 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1910
1911 dev->stats.tx_errors++;
1912 dev->stats.tx_aborted_errors++;
1913
1914 spin_lock_irqsave(&info->lock,flags);
1915 tx_stop(info);
1916 spin_unlock_irqrestore(&info->lock,flags);
1917
1918 netif_wake_queue(dev);
1919 }
1920
1921 /**
1922 * called by device driver when transmit completes
1923 * reenable network layer transmit if stopped
1924 *
1925 * info pointer to device instance information
1926 */
1927 static void hdlcdev_tx_done(SLMP_INFO *info)
1928 {
1929 if (netif_queue_stopped(info->netdev))
1930 netif_wake_queue(info->netdev);
1931 }
1932
1933 /**
1934 * called by device driver when frame received
1935 * pass frame to network layer
1936 *
1937 * info pointer to device instance information
1938 * buf pointer to buffer contianing frame data
1939 * size count of data bytes in buf
1940 */
1941 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1942 {
1943 struct sk_buff *skb = dev_alloc_skb(size);
1944 struct net_device *dev = info->netdev;
1945
1946 if (debug_level >= DEBUG_LEVEL_INFO)
1947 printk("hdlcdev_rx(%s)\n",dev->name);
1948
1949 if (skb == NULL) {
1950 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1951 dev->name);
1952 dev->stats.rx_dropped++;
1953 return;
1954 }
1955
1956 memcpy(skb_put(skb, size), buf, size);
1957
1958 skb->protocol = hdlc_type_trans(skb, dev);
1959
1960 dev->stats.rx_packets++;
1961 dev->stats.rx_bytes += size;
1962
1963 netif_rx(skb);
1964
1965 dev->last_rx = jiffies;
1966 }
1967
1968 /**
1969 * called by device driver when adding device instance
1970 * do generic HDLC initialization
1971 *
1972 * info pointer to device instance information
1973 *
1974 * returns 0 if success, otherwise error code
1975 */
1976 static int hdlcdev_init(SLMP_INFO *info)
1977 {
1978 int rc;
1979 struct net_device *dev;
1980 hdlc_device *hdlc;
1981
1982 /* allocate and initialize network and HDLC layer objects */
1983
1984 if (!(dev = alloc_hdlcdev(info))) {
1985 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1986 return -ENOMEM;
1987 }
1988
1989 /* for network layer reporting purposes only */
1990 dev->mem_start = info->phys_sca_base;
1991 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1992 dev->irq = info->irq_level;
1993
1994 /* network layer callbacks and settings */
1995 dev->do_ioctl = hdlcdev_ioctl;
1996 dev->open = hdlcdev_open;
1997 dev->stop = hdlcdev_close;
1998 dev->tx_timeout = hdlcdev_tx_timeout;
1999 dev->watchdog_timeo = 10*HZ;
2000 dev->tx_queue_len = 50;
2001
2002 /* generic HDLC layer callbacks and settings */
2003 hdlc = dev_to_hdlc(dev);
2004 hdlc->attach = hdlcdev_attach;
2005 hdlc->xmit = hdlcdev_xmit;
2006
2007 /* register objects with HDLC layer */
2008 if ((rc = register_hdlc_device(dev))) {
2009 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2010 free_netdev(dev);
2011 return rc;
2012 }
2013
2014 info->netdev = dev;
2015 return 0;
2016 }
2017
2018 /**
2019 * called by device driver when removing device instance
2020 * do generic HDLC cleanup
2021 *
2022 * info pointer to device instance information
2023 */
2024 static void hdlcdev_exit(SLMP_INFO *info)
2025 {
2026 unregister_hdlc_device(info->netdev);
2027 free_netdev(info->netdev);
2028 info->netdev = NULL;
2029 }
2030
2031 #endif /* CONFIG_HDLC */
2032
2033
2034 /* Return next bottom half action to perform.
2035 * Return Value: BH action code or 0 if nothing to do.
2036 */
2037 static int bh_action(SLMP_INFO *info)
2038 {
2039 unsigned long flags;
2040 int rc = 0;
2041
2042 spin_lock_irqsave(&info->lock,flags);
2043
2044 if (info->pending_bh & BH_RECEIVE) {
2045 info->pending_bh &= ~BH_RECEIVE;
2046 rc = BH_RECEIVE;
2047 } else if (info->pending_bh & BH_TRANSMIT) {
2048 info->pending_bh &= ~BH_TRANSMIT;
2049 rc = BH_TRANSMIT;
2050 } else if (info->pending_bh & BH_STATUS) {
2051 info->pending_bh &= ~BH_STATUS;
2052 rc = BH_STATUS;
2053 }
2054
2055 if (!rc) {
2056 /* Mark BH routine as complete */
2057 info->bh_running = false;
2058 info->bh_requested = false;
2059 }
2060
2061 spin_unlock_irqrestore(&info->lock,flags);
2062
2063 return rc;
2064 }
2065
2066 /* Perform bottom half processing of work items queued by ISR.
2067 */
2068 static void bh_handler(struct work_struct *work)
2069 {
2070 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2071 int action;
2072
2073 if (!info)
2074 return;
2075
2076 if ( debug_level >= DEBUG_LEVEL_BH )
2077 printk( "%s(%d):%s bh_handler() entry\n",
2078 __FILE__,__LINE__,info->device_name);
2079
2080 info->bh_running = true;
2081
2082 while((action = bh_action(info)) != 0) {
2083
2084 /* Process work item */
2085 if ( debug_level >= DEBUG_LEVEL_BH )
2086 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2087 __FILE__,__LINE__,info->device_name, action);
2088
2089 switch (action) {
2090
2091 case BH_RECEIVE:
2092 bh_receive(info);
2093 break;
2094 case BH_TRANSMIT:
2095 bh_transmit(info);
2096 break;
2097 case BH_STATUS:
2098 bh_status(info);
2099 break;
2100 default:
2101 /* unknown work item ID */
2102 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2103 __FILE__,__LINE__,info->device_name,action);
2104 break;
2105 }
2106 }
2107
2108 if ( debug_level >= DEBUG_LEVEL_BH )
2109 printk( "%s(%d):%s bh_handler() exit\n",
2110 __FILE__,__LINE__,info->device_name);
2111 }
2112
2113 static void bh_receive(SLMP_INFO *info)
2114 {
2115 if ( debug_level >= DEBUG_LEVEL_BH )
2116 printk( "%s(%d):%s bh_receive()\n",
2117 __FILE__,__LINE__,info->device_name);
2118
2119 while( rx_get_frame(info) );
2120 }
2121
2122 static void bh_transmit(SLMP_INFO *info)
2123 {
2124 struct tty_struct *tty = info->port.tty;
2125
2126 if ( debug_level >= DEBUG_LEVEL_BH )
2127 printk( "%s(%d):%s bh_transmit() entry\n",
2128 __FILE__,__LINE__,info->device_name);
2129
2130 if (tty)
2131 tty_wakeup(tty);
2132 }
2133
2134 static void bh_status(SLMP_INFO *info)
2135 {
2136 if ( debug_level >= DEBUG_LEVEL_BH )
2137 printk( "%s(%d):%s bh_status() entry\n",
2138 __FILE__,__LINE__,info->device_name);
2139
2140 info->ri_chkcount = 0;
2141 info->dsr_chkcount = 0;
2142 info->dcd_chkcount = 0;
2143 info->cts_chkcount = 0;
2144 }
2145
2146 static void isr_timer(SLMP_INFO * info)
2147 {
2148 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2149
2150 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2151 write_reg(info, IER2, 0);
2152
2153 /* TMCS, Timer Control/Status Register
2154 *
2155 * 07 CMF, Compare match flag (read only) 1=match
2156 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2157 * 05 Reserved, must be 0
2158 * 04 TME, Timer Enable
2159 * 03..00 Reserved, must be 0
2160 *
2161 * 0000 0000
2162 */
2163 write_reg(info, (unsigned char)(timer + TMCS), 0);
2164
2165 info->irq_occurred = true;
2166
2167 if ( debug_level >= DEBUG_LEVEL_ISR )
2168 printk("%s(%d):%s isr_timer()\n",
2169 __FILE__,__LINE__,info->device_name);
2170 }
2171
2172 static void isr_rxint(SLMP_INFO * info)
2173 {
2174 struct tty_struct *tty = info->port.tty;
2175 struct mgsl_icount *icount = &info->icount;
2176 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2177 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2178
2179 /* clear status bits */
2180 if (status)
2181 write_reg(info, SR1, status);
2182
2183 if (status2)
2184 write_reg(info, SR2, status2);
2185
2186 if ( debug_level >= DEBUG_LEVEL_ISR )
2187 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2188 __FILE__,__LINE__,info->device_name,status,status2);
2189
2190 if (info->params.mode == MGSL_MODE_ASYNC) {
2191 if (status & BRKD) {
2192 icount->brk++;
2193
2194 /* process break detection if tty control
2195 * is not set to ignore it
2196 */
2197 if ( tty ) {
2198 if (!(status & info->ignore_status_mask1)) {
2199 if (info->read_status_mask1 & BRKD) {
2200 tty_insert_flip_char(tty, 0, TTY_BREAK);
2201 if (info->port.flags & ASYNC_SAK)
2202 do_SAK(tty);
2203 }
2204 }
2205 }
2206 }
2207 }
2208 else {
2209 if (status & (FLGD|IDLD)) {
2210 if (status & FLGD)
2211 info->icount.exithunt++;
2212 else if (status & IDLD)
2213 info->icount.rxidle++;
2214 wake_up_interruptible(&info->event_wait_q);
2215 }
2216 }
2217
2218 if (status & CDCD) {
2219 /* simulate a common modem status change interrupt
2220 * for our handler
2221 */
2222 get_signals( info );
2223 isr_io_pin(info,
2224 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2225 }
2226 }
2227
2228 /*
2229 * handle async rx data interrupts
2230 */
2231 static void isr_rxrdy(SLMP_INFO * info)
2232 {
2233 u16 status;
2234 unsigned char DataByte;
2235 struct tty_struct *tty = info->port.tty;
2236 struct mgsl_icount *icount = &info->icount;
2237
2238 if ( debug_level >= DEBUG_LEVEL_ISR )
2239 printk("%s(%d):%s isr_rxrdy\n",
2240 __FILE__,__LINE__,info->device_name);
2241
2242 while((status = read_reg(info,CST0)) & BIT0)
2243 {
2244 int flag = 0;
2245 bool over = false;
2246 DataByte = read_reg(info,TRB);
2247
2248 icount->rx++;
2249
2250 if ( status & (PE + FRME + OVRN) ) {
2251 printk("%s(%d):%s rxerr=%04X\n",
2252 __FILE__,__LINE__,info->device_name,status);
2253
2254 /* update error statistics */
2255 if (status & PE)
2256 icount->parity++;
2257 else if (status & FRME)
2258 icount->frame++;
2259 else if (status & OVRN)
2260 icount->overrun++;
2261
2262 /* discard char if tty control flags say so */
2263 if (status & info->ignore_status_mask2)
2264 continue;
2265
2266 status &= info->read_status_mask2;
2267
2268 if ( tty ) {
2269 if (status & PE)
2270 flag = TTY_PARITY;
2271 else if (status & FRME)
2272 flag = TTY_FRAME;
2273 if (status & OVRN) {
2274 /* Overrun is special, since it's
2275 * reported immediately, and doesn't
2276 * affect the current character
2277 */
2278 over = true;
2279 }
2280 }
2281 } /* end of if (error) */
2282
2283 if ( tty ) {
2284 tty_insert_flip_char(tty, DataByte, flag);
2285 if (over)
2286 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2287 }
2288 }
2289
2290 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2291 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2292 __FILE__,__LINE__,info->device_name,
2293 icount->rx,icount->brk,icount->parity,
2294 icount->frame,icount->overrun);
2295 }
2296
2297 if ( tty )
2298 tty_flip_buffer_push(tty);
2299 }
2300
2301 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2302 {
2303 if ( debug_level >= DEBUG_LEVEL_ISR )
2304 printk("%s(%d):%s isr_txeom status=%02x\n",
2305 __FILE__,__LINE__,info->device_name,status);
2306
2307 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2308 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2309 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2310
2311 if (status & UDRN) {
2312 write_reg(info, CMD, TXRESET);
2313 write_reg(info, CMD, TXENABLE);
2314 } else
2315 write_reg(info, CMD, TXBUFCLR);
2316
2317 /* disable and clear tx interrupts */
2318 info->ie0_value &= ~TXRDYE;
2319 info->ie1_value &= ~(IDLE + UDRN);
2320 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2321 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2322
2323 if ( info->tx_active ) {
2324 if (info->params.mode != MGSL_MODE_ASYNC) {
2325 if (status & UDRN)
2326 info->icount.txunder++;
2327 else if (status & IDLE)
2328 info->icount.txok++;
2329 }
2330
2331 info->tx_active = false;
2332 info->tx_count = info->tx_put = info->tx_get = 0;
2333
2334 del_timer(&info->tx_timer);
2335
2336 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2337 info->serial_signals &= ~SerialSignal_RTS;
2338 info->drop_rts_on_tx_done = false;
2339 set_signals(info);
2340 }
2341
2342 #if SYNCLINK_GENERIC_HDLC
2343 if (info->netcount)
2344 hdlcdev_tx_done(info);
2345 else
2346 #endif
2347 {
2348 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2349 tx_stop(info);
2350 return;
2351 }
2352 info->pending_bh |= BH_TRANSMIT;
2353 }
2354 }
2355 }
2356
2357
2358 /*
2359 * handle tx status interrupts
2360 */
2361 static void isr_txint(SLMP_INFO * info)
2362 {
2363 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2364
2365 /* clear status bits */
2366 write_reg(info, SR1, status);
2367
2368 if ( debug_level >= DEBUG_LEVEL_ISR )
2369 printk("%s(%d):%s isr_txint status=%02x\n",
2370 __FILE__,__LINE__,info->device_name,status);
2371
2372 if (status & (UDRN + IDLE))
2373 isr_txeom(info, status);
2374
2375 if (status & CCTS) {
2376 /* simulate a common modem status change interrupt
2377 * for our handler
2378 */
2379 get_signals( info );
2380 isr_io_pin(info,
2381 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2382
2383 }
2384 }
2385
2386 /*
2387 * handle async tx data interrupts
2388 */
2389 static void isr_txrdy(SLMP_INFO * info)
2390 {
2391 if ( debug_level >= DEBUG_LEVEL_ISR )
2392 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2393 __FILE__,__LINE__,info->device_name,info->tx_count);
2394
2395 if (info->params.mode != MGSL_MODE_ASYNC) {
2396 /* disable TXRDY IRQ, enable IDLE IRQ */
2397 info->ie0_value &= ~TXRDYE;
2398 info->ie1_value |= IDLE;
2399 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2400 return;
2401 }
2402
2403 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2404 tx_stop(info);
2405 return;
2406 }
2407
2408 if ( info->tx_count )
2409 tx_load_fifo( info );
2410 else {
2411 info->tx_active = false;
2412 info->ie0_value &= ~TXRDYE;
2413 write_reg(info, IE0, info->ie0_value);
2414 }
2415
2416 if (info->tx_count < WAKEUP_CHARS)
2417 info->pending_bh |= BH_TRANSMIT;
2418 }
2419
2420 static void isr_rxdmaok(SLMP_INFO * info)
2421 {
2422 /* BIT7 = EOT (end of transfer)
2423 * BIT6 = EOM (end of message/frame)
2424 */
2425 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2426
2427 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2428 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2429
2430 if ( debug_level >= DEBUG_LEVEL_ISR )
2431 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2432 __FILE__,__LINE__,info->device_name,status);
2433
2434 info->pending_bh |= BH_RECEIVE;
2435 }
2436
2437 static void isr_rxdmaerror(SLMP_INFO * info)
2438 {
2439 /* BIT5 = BOF (buffer overflow)
2440 * BIT4 = COF (counter overflow)
2441 */
2442 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2443
2444 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2445 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2446
2447 if ( debug_level >= DEBUG_LEVEL_ISR )
2448 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2449 __FILE__,__LINE__,info->device_name,status);
2450
2451 info->rx_overflow = true;
2452 info->pending_bh |= BH_RECEIVE;
2453 }
2454
2455 static void isr_txdmaok(SLMP_INFO * info)
2456 {
2457 unsigned char status_reg1 = read_reg(info, SR1);
2458
2459 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2460 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2461 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2462
2463 if ( debug_level >= DEBUG_LEVEL_ISR )
2464 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2465 __FILE__,__LINE__,info->device_name,status_reg1);
2466
2467 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2468 write_reg16(info, TRC0, 0);
2469 info->ie0_value |= TXRDYE;
2470 write_reg(info, IE0, info->ie0_value);
2471 }
2472
2473 static void isr_txdmaerror(SLMP_INFO * info)
2474 {
2475 /* BIT5 = BOF (buffer overflow)
2476 * BIT4 = COF (counter overflow)
2477 */
2478 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2479
2480 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2481 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2482
2483 if ( debug_level >= DEBUG_LEVEL_ISR )
2484 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2485 __FILE__,__LINE__,info->device_name,status);
2486 }
2487
2488 /* handle input serial signal changes
2489 */
2490 static void isr_io_pin( SLMP_INFO *info, u16 status )
2491 {
2492 struct mgsl_icount *icount;
2493
2494 if ( debug_level >= DEBUG_LEVEL_ISR )
2495 printk("%s(%d):isr_io_pin status=%04X\n",
2496 __FILE__,__LINE__,status);
2497
2498 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2499 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2500 icount = &info->icount;
2501 /* update input line counters */
2502 if (status & MISCSTATUS_RI_LATCHED) {
2503 icount->rng++;
2504 if ( status & SerialSignal_RI )
2505 info->input_signal_events.ri_up++;
2506 else
2507 info->input_signal_events.ri_down++;
2508 }
2509 if (status & MISCSTATUS_DSR_LATCHED) {
2510 icount->dsr++;
2511 if ( status & SerialSignal_DSR )
2512 info->input_signal_events.dsr_up++;
2513 else
2514 info->input_signal_events.dsr_down++;
2515 }
2516 if (status & MISCSTATUS_DCD_LATCHED) {
2517 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2518 info->ie1_value &= ~CDCD;
2519 write_reg(info, IE1, info->ie1_value);
2520 }
2521 icount->dcd++;
2522 if (status & SerialSignal_DCD) {
2523 info->input_signal_events.dcd_up++;
2524 } else
2525 info->input_signal_events.dcd_down++;
2526 #if SYNCLINK_GENERIC_HDLC
2527 if (info->netcount) {
2528 if (status & SerialSignal_DCD)
2529 netif_carrier_on(info->netdev);
2530 else
2531 netif_carrier_off(info->netdev);
2532 }
2533 #endif
2534 }
2535 if (status & MISCSTATUS_CTS_LATCHED)
2536 {
2537 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2538 info->ie1_value &= ~CCTS;
2539 write_reg(info, IE1, info->ie1_value);
2540 }
2541 icount->cts++;
2542 if ( status & SerialSignal_CTS )
2543 info->input_signal_events.cts_up++;
2544 else
2545 info->input_signal_events.cts_down++;
2546 }
2547 wake_up_interruptible(&info->status_event_wait_q);
2548 wake_up_interruptible(&info->event_wait_q);
2549
2550 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2551 (status & MISCSTATUS_DCD_LATCHED) ) {
2552 if ( debug_level >= DEBUG_LEVEL_ISR )
2553 printk("%s CD now %s...", info->device_name,
2554 (status & SerialSignal_DCD) ? "on" : "off");
2555 if (status & SerialSignal_DCD)
2556 wake_up_interruptible(&info->port.open_wait);
2557 else {
2558 if ( debug_level >= DEBUG_LEVEL_ISR )
2559 printk("doing serial hangup...");
2560 if (info->port.tty)
2561 tty_hangup(info->port.tty);
2562 }
2563 }
2564
2565 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2566 (status & MISCSTATUS_CTS_LATCHED) ) {
2567 if ( info->port.tty ) {
2568 if (info->port.tty->hw_stopped) {
2569 if (status & SerialSignal_CTS) {
2570 if ( debug_level >= DEBUG_LEVEL_ISR )
2571 printk("CTS tx start...");
2572 info->port.tty->hw_stopped = 0;
2573 tx_start(info);
2574 info->pending_bh |= BH_TRANSMIT;
2575 return;
2576 }
2577 } else {
2578 if (!(status & SerialSignal_CTS)) {
2579 if ( debug_level >= DEBUG_LEVEL_ISR )
2580 printk("CTS tx stop...");
2581 info->port.tty->hw_stopped = 1;
2582 tx_stop(info);
2583 }
2584 }
2585 }
2586 }
2587 }
2588
2589 info->pending_bh |= BH_STATUS;
2590 }
2591
2592 /* Interrupt service routine entry point.
2593 *
2594 * Arguments:
2595 * irq interrupt number that caused interrupt
2596 * dev_id device ID supplied during interrupt registration
2597 * regs interrupted processor context
2598 */
2599 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2600 {
2601 SLMP_INFO *info = dev_id;
2602 unsigned char status, status0, status1=0;
2603 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2604 unsigned char timerstatus0, timerstatus1=0;
2605 unsigned char shift;
2606 unsigned int i;
2607 unsigned short tmp;
2608
2609 if ( debug_level >= DEBUG_LEVEL_ISR )
2610 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2611 __FILE__, __LINE__, info->irq_level);
2612
2613 spin_lock(&info->lock);
2614
2615 for(;;) {
2616
2617 /* get status for SCA0 (ports 0-1) */
2618 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2619 status0 = (unsigned char)tmp;
2620 dmastatus0 = (unsigned char)(tmp>>8);
2621 timerstatus0 = read_reg(info, ISR2);
2622
2623 if ( debug_level >= DEBUG_LEVEL_ISR )
2624 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2625 __FILE__, __LINE__, info->device_name,
2626 status0, dmastatus0, timerstatus0);
2627
2628 if (info->port_count == 4) {
2629 /* get status for SCA1 (ports 2-3) */
2630 tmp = read_reg16(info->port_array[2], ISR0);
2631 status1 = (unsigned char)tmp;
2632 dmastatus1 = (unsigned char)(tmp>>8);
2633 timerstatus1 = read_reg(info->port_array[2], ISR2);
2634
2635 if ( debug_level >= DEBUG_LEVEL_ISR )
2636 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2637 __FILE__,__LINE__,info->device_name,
2638 status1,dmastatus1,timerstatus1);
2639 }
2640
2641 if (!status0 && !dmastatus0 && !timerstatus0 &&
2642 !status1 && !dmastatus1 && !timerstatus1)
2643 break;
2644
2645 for(i=0; i < info->port_count ; i++) {
2646 if (info->port_array[i] == NULL)
2647 continue;
2648 if (i < 2) {
2649 status = status0;
2650 dmastatus = dmastatus0;
2651 } else {
2652 status = status1;
2653 dmastatus = dmastatus1;
2654 }
2655
2656 shift = i & 1 ? 4 :0;
2657
2658 if (status & BIT0 << shift)
2659 isr_rxrdy(info->port_array[i]);
2660 if (status & BIT1 << shift)
2661 isr_txrdy(info->port_array[i]);
2662 if (status & BIT2 << shift)
2663 isr_rxint(info->port_array[i]);
2664 if (status & BIT3 << shift)
2665 isr_txint(info->port_array[i]);
2666
2667 if (dmastatus & BIT0 << shift)
2668 isr_rxdmaerror(info->port_array[i]);
2669 if (dmastatus & BIT1 << shift)
2670 isr_rxdmaok(info->port_array[i]);
2671 if (dmastatus & BIT2 << shift)
2672 isr_txdmaerror(info->port_array[i]);
2673 if (dmastatus & BIT3 << shift)
2674 isr_txdmaok(info->port_array[i]);
2675 }
2676
2677 if (timerstatus0 & (BIT5 | BIT4))
2678 isr_timer(info->port_array[0]);
2679 if (timerstatus0 & (BIT7 | BIT6))
2680 isr_timer(info->port_array[1]);
2681 if (timerstatus1 & (BIT5 | BIT4))
2682 isr_timer(info->port_array[2]);
2683 if (timerstatus1 & (BIT7 | BIT6))
2684 isr_timer(info->port_array[3]);
2685 }
2686
2687 for(i=0; i < info->port_count ; i++) {
2688 SLMP_INFO * port = info->port_array[i];
2689
2690 /* Request bottom half processing if there's something
2691 * for it to do and the bh is not already running.
2692 *
2693 * Note: startup adapter diags require interrupts.
2694 * do not request bottom half processing if the
2695 * device is not open in a normal mode.
2696 */
2697 if ( port && (port->port.count || port->netcount) &&
2698 port->pending_bh && !port->bh_running &&
2699 !port->bh_requested ) {
2700 if ( debug_level >= DEBUG_LEVEL_ISR )
2701 printk("%s(%d):%s queueing bh task.\n",
2702 __FILE__,__LINE__,port->device_name);
2703 schedule_work(&port->task);
2704 port->bh_requested = true;
2705 }
2706 }
2707
2708 spin_unlock(&info->lock);
2709
2710 if ( debug_level >= DEBUG_LEVEL_ISR )
2711 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2712 __FILE__, __LINE__, info->irq_level);
2713 return IRQ_HANDLED;
2714 }
2715
2716 /* Initialize and start device.
2717 */
2718 static int startup(SLMP_INFO * info)
2719 {
2720 if ( debug_level >= DEBUG_LEVEL_INFO )
2721 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2722
2723 if (info->port.flags & ASYNC_INITIALIZED)
2724 return 0;
2725
2726 if (!info->tx_buf) {
2727 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2728 if (!info->tx_buf) {
2729 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2730 __FILE__,__LINE__,info->device_name);
2731 return -ENOMEM;
2732 }
2733 }
2734
2735 info->pending_bh = 0;
2736
2737 memset(&info->icount, 0, sizeof(info->icount));
2738
2739 /* program hardware for current parameters */
2740 reset_port(info);
2741
2742 change_params(info);
2743
2744 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2745
2746 if (info->port.tty)
2747 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2748
2749 info->port.flags |= ASYNC_INITIALIZED;
2750
2751 return 0;
2752 }
2753
2754 /* Called by close() and hangup() to shutdown hardware
2755 */
2756 static void shutdown(SLMP_INFO * info)
2757 {
2758 unsigned long flags;
2759
2760 if (!(info->port.flags & ASYNC_INITIALIZED))
2761 return;
2762
2763 if (debug_level >= DEBUG_LEVEL_INFO)
2764 printk("%s(%d):%s synclinkmp_shutdown()\n",
2765 __FILE__,__LINE__, info->device_name );
2766
2767 /* clear status wait queue because status changes */
2768 /* can't happen after shutting down the hardware */
2769 wake_up_interruptible(&info->status_event_wait_q);
2770 wake_up_interruptible(&info->event_wait_q);
2771
2772 del_timer(&info->tx_timer);
2773 del_timer(&info->status_timer);
2774
2775 kfree(info->tx_buf);
2776 info->tx_buf = NULL;
2777
2778 spin_lock_irqsave(&info->lock,flags);
2779
2780 reset_port(info);
2781
2782 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2783 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2784 set_signals(info);
2785 }
2786
2787 spin_unlock_irqrestore(&info->lock,flags);
2788
2789 if (info->port.tty)
2790 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2791
2792 info->port.flags &= ~ASYNC_INITIALIZED;
2793 }
2794
2795 static void program_hw(SLMP_INFO *info)
2796 {
2797 unsigned long flags;
2798
2799 spin_lock_irqsave(&info->lock,flags);
2800
2801 rx_stop(info);
2802 tx_stop(info);
2803
2804 info->tx_count = info->tx_put = info->tx_get = 0;
2805
2806 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2807 hdlc_mode(info);
2808 else
2809 async_mode(info);
2810
2811 set_signals(info);
2812
2813 info->dcd_chkcount = 0;
2814 info->cts_chkcount = 0;
2815 info->ri_chkcount = 0;
2816 info->dsr_chkcount = 0;
2817
2818 info->ie1_value |= (CDCD|CCTS);
2819 write_reg(info, IE1, info->ie1_value);
2820
2821 get_signals(info);
2822
2823 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2824 rx_start(info);
2825
2826 spin_unlock_irqrestore(&info->lock,flags);
2827 }
2828
2829 /* Reconfigure adapter based on new parameters
2830 */
2831 static void change_params(SLMP_INFO *info)
2832 {
2833 unsigned cflag;
2834 int bits_per_char;
2835
2836 if (!info->port.tty || !info->port.tty->termios)
2837 return;
2838
2839 if (debug_level >= DEBUG_LEVEL_INFO)
2840 printk("%s(%d):%s change_params()\n",
2841 __FILE__,__LINE__, info->device_name );
2842
2843 cflag = info->port.tty->termios->c_cflag;
2844
2845 /* if B0 rate (hangup) specified then negate DTR and RTS */
2846 /* otherwise assert DTR and RTS */
2847 if (cflag & CBAUD)
2848 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2849 else
2850 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2851
2852 /* byte size and parity */
2853
2854 switch (cflag & CSIZE) {
2855 case CS5: info->params.data_bits = 5; break;
2856 case CS6: info->params.data_bits = 6; break;
2857 case CS7: info->params.data_bits = 7; break;
2858 case CS8: info->params.data_bits = 8; break;
2859 /* Never happens, but GCC is too dumb to figure it out */
2860 default: info->params.data_bits = 7; break;
2861 }
2862
2863 if (cflag & CSTOPB)
2864 info->params.stop_bits = 2;
2865 else
2866 info->params.stop_bits = 1;
2867
2868 info->params.parity = ASYNC_PARITY_NONE;
2869 if (cflag & PARENB) {
2870 if (cflag & PARODD)
2871 info->params.parity = ASYNC_PARITY_ODD;
2872 else
2873 info->params.parity = ASYNC_PARITY_EVEN;
2874 #ifdef CMSPAR
2875 if (cflag & CMSPAR)
2876 info->params.parity = ASYNC_PARITY_SPACE;
2877 #endif
2878 }
2879
2880 /* calculate number of jiffies to transmit a full
2881 * FIFO (32 bytes) at specified data rate
2882 */
2883 bits_per_char = info->params.data_bits +
2884 info->params.stop_bits + 1;
2885
2886 /* if port data rate is set to 460800 or less then
2887 * allow tty settings to override, otherwise keep the
2888 * current data rate.
2889 */
2890 if (info->params.data_rate <= 460800) {
2891 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2892 }
2893
2894 if ( info->params.data_rate ) {
2895 info->timeout = (32*HZ*bits_per_char) /
2896 info->params.data_rate;
2897 }
2898 info->timeout += HZ/50; /* Add .02 seconds of slop */
2899
2900 if (cflag & CRTSCTS)
2901 info->port.flags |= ASYNC_CTS_FLOW;
2902 else
2903 info->port.flags &= ~ASYNC_CTS_FLOW;
2904
2905 if (cflag & CLOCAL)
2906 info->port.flags &= ~ASYNC_CHECK_CD;
2907 else
2908 info->port.flags |= ASYNC_CHECK_CD;
2909
2910 /* process tty input control flags */
2911
2912 info->read_status_mask2 = OVRN;
2913 if (I_INPCK(info->port.tty))
2914 info->read_status_mask2 |= PE | FRME;
2915 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2916 info->read_status_mask1 |= BRKD;
2917 if (I_IGNPAR(info->port.tty))
2918 info->ignore_status_mask2 |= PE | FRME;
2919 if (I_IGNBRK(info->port.tty)) {
2920 info->ignore_status_mask1 |= BRKD;
2921 /* If ignoring parity and break indicators, ignore
2922 * overruns too. (For real raw support).
2923 */
2924 if (I_IGNPAR(info->port.tty))
2925 info->ignore_status_mask2 |= OVRN;
2926 }
2927
2928 program_hw(info);
2929 }
2930
2931 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2932 {
2933 int err;
2934
2935 if (debug_level >= DEBUG_LEVEL_INFO)
2936 printk("%s(%d):%s get_params()\n",
2937 __FILE__,__LINE__, info->device_name);
2938
2939 if (!user_icount) {
2940 memset(&info->icount, 0, sizeof(info->icount));
2941 } else {
2942 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2943 if (err)
2944 return -EFAULT;
2945 }
2946
2947 return 0;
2948 }
2949
2950 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2951 {
2952 int err;
2953 if (debug_level >= DEBUG_LEVEL_INFO)
2954 printk("%s(%d):%s get_params()\n",
2955 __FILE__,__LINE__, info->device_name);
2956
2957 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2958 if (err) {
2959 if ( debug_level >= DEBUG_LEVEL_INFO )
2960 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2961 __FILE__,__LINE__,info->device_name);
2962 return -EFAULT;
2963 }
2964
2965 return 0;
2966 }
2967
2968 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2969 {
2970 unsigned long flags;
2971 MGSL_PARAMS tmp_params;
2972 int err;
2973
2974 if (debug_level >= DEBUG_LEVEL_INFO)
2975 printk("%s(%d):%s set_params\n",
2976 __FILE__,__LINE__,info->device_name );
2977 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2978 if (err) {
2979 if ( debug_level >= DEBUG_LEVEL_INFO )
2980 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2981 __FILE__,__LINE__,info->device_name);
2982 return -EFAULT;
2983 }
2984
2985 spin_lock_irqsave(&info->lock,flags);
2986 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2987 spin_unlock_irqrestore(&info->lock,flags);
2988
2989 change_params(info);
2990
2991 return 0;
2992 }
2993
2994 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2995 {
2996 int err;
2997
2998 if (debug_level >= DEBUG_LEVEL_INFO)
2999 printk("%s(%d):%s get_txidle()=%d\n",
3000 __FILE__,__LINE__, info->device_name, info->idle_mode);
3001
3002 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3003 if (err) {
3004 if ( debug_level >= DEBUG_LEVEL_INFO )
3005 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3006 __FILE__,__LINE__,info->device_name);
3007 return -EFAULT;
3008 }
3009
3010 return 0;
3011 }
3012
3013 static int set_txidle(SLMP_INFO * info, int idle_mode)
3014 {
3015 unsigned long flags;
3016
3017 if (debug_level >= DEBUG_LEVEL_INFO)
3018 printk("%s(%d):%s set_txidle(%d)\n",
3019 __FILE__,__LINE__,info->device_name, idle_mode );
3020
3021 spin_lock_irqsave(&info->lock,flags);
3022 info->idle_mode = idle_mode;
3023 tx_set_idle( info );
3024 spin_unlock_irqrestore(&info->lock,flags);
3025 return 0;
3026 }
3027
3028 static int tx_enable(SLMP_INFO * info, int enable)
3029 {
3030 unsigned long flags;
3031
3032 if (debug_level >= DEBUG_LEVEL_INFO)
3033 printk("%s(%d):%s tx_enable(%d)\n",
3034 __FILE__,__LINE__,info->device_name, enable);
3035
3036 spin_lock_irqsave(&info->lock,flags);
3037 if ( enable ) {
3038 if ( !info->tx_enabled ) {
3039 tx_start(info);
3040 }
3041 } else {
3042 if ( info->tx_enabled )
3043 tx_stop(info);
3044 }
3045 spin_unlock_irqrestore(&info->lock,flags);
3046 return 0;
3047 }
3048
3049 /* abort send HDLC frame
3050 */
3051 static int tx_abort(SLMP_INFO * info)
3052 {
3053 unsigned long flags;
3054
3055 if (debug_level >= DEBUG_LEVEL_INFO)
3056 printk("%s(%d):%s tx_abort()\n",
3057 __FILE__,__LINE__,info->device_name);
3058
3059 spin_lock_irqsave(&info->lock,flags);
3060 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3061 info->ie1_value &= ~UDRN;
3062 info->ie1_value |= IDLE;
3063 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3064 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3065
3066 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3067 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3068
3069 write_reg(info, CMD, TXABORT);
3070 }
3071 spin_unlock_irqrestore(&info->lock,flags);
3072 return 0;
3073 }
3074
3075 static int rx_enable(SLMP_INFO * info, int enable)
3076 {
3077 unsigned long flags;
3078
3079 if (debug_level >= DEBUG_LEVEL_INFO)
3080 printk("%s(%d):%s rx_enable(%d)\n",
3081 __FILE__,__LINE__,info->device_name,enable);
3082
3083 spin_lock_irqsave(&info->lock,flags);
3084 if ( enable ) {
3085 if ( !info->rx_enabled )
3086 rx_start(info);
3087 } else {
3088 if ( info->rx_enabled )
3089 rx_stop(info);
3090 }
3091 spin_unlock_irqrestore(&info->lock,flags);
3092 return 0;
3093 }
3094
3095 /* wait for specified event to occur
3096 */
3097 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3098 {
3099 unsigned long flags;
3100 int s;
3101 int rc=0;
3102 struct mgsl_icount cprev, cnow;
3103 int events;
3104 int mask;
3105 struct _input_signal_events oldsigs, newsigs;
3106 DECLARE_WAITQUEUE(wait, current);
3107
3108 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3109 if (rc) {
3110 return -EFAULT;
3111 }
3112
3113 if (debug_level >= DEBUG_LEVEL_INFO)
3114 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3115 __FILE__,__LINE__,info->device_name,mask);
3116
3117 spin_lock_irqsave(&info->lock,flags);
3118
3119 /* return immediately if state matches requested events */
3120 get_signals(info);
3121 s = info->serial_signals;
3122
3123 events = mask &
3124 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3125 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3126 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3127 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3128 if (events) {
3129 spin_unlock_irqrestore(&info->lock,flags);
3130 goto exit;
3131 }
3132
3133 /* save current irq counts */
3134 cprev = info->icount;
3135 oldsigs = info->input_signal_events;
3136
3137 /* enable hunt and idle irqs if needed */
3138 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3139 unsigned char oldval = info->ie1_value;
3140 unsigned char newval = oldval +
3141 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3142 (mask & MgslEvent_IdleReceived ? IDLD:0);
3143 if ( oldval != newval ) {
3144 info->ie1_value = newval;
3145 write_reg(info, IE1, info->ie1_value);
3146 }
3147 }
3148
3149 set_current_state(TASK_INTERRUPTIBLE);
3150 add_wait_queue(&info->event_wait_q, &wait);
3151
3152 spin_unlock_irqrestore(&info->lock,flags);
3153
3154 for(;;) {
3155 schedule();
3156 if (signal_pending(current)) {
3157 rc = -ERESTARTSYS;
3158 break;
3159 }
3160
3161 /* get current irq counts */
3162 spin_lock_irqsave(&info->lock,flags);
3163 cnow = info->icount;
3164 newsigs = info->input_signal_events;
3165 set_current_state(TASK_INTERRUPTIBLE);
3166 spin_unlock_irqrestore(&info->lock,flags);
3167
3168 /* if no change, wait aborted for some reason */
3169 if (newsigs.dsr_up == oldsigs.dsr_up &&
3170 newsigs.dsr_down == oldsigs.dsr_down &&
3171 newsigs.dcd_up == oldsigs.dcd_up &&
3172 newsigs.dcd_down == oldsigs.dcd_down &&
3173 newsigs.cts_up == oldsigs.cts_up &&
3174 newsigs.cts_down == oldsigs.cts_down &&
3175 newsigs.ri_up == oldsigs.ri_up &&
3176 newsigs.ri_down == oldsigs.ri_down &&
3177 cnow.exithunt == cprev.exithunt &&
3178 cnow.rxidle == cprev.rxidle) {
3179 rc = -EIO;
3180 break;
3181 }
3182
3183 events = mask &
3184 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3185 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3186 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3187 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3188 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3189 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3190 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3191 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3192 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3193 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3194 if (events)
3195 break;
3196
3197 cprev = cnow;
3198 oldsigs = newsigs;
3199 }
3200
3201 remove_wait_queue(&info->event_wait_q, &wait);
3202 set_current_state(TASK_RUNNING);
3203
3204
3205 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3206 spin_lock_irqsave(&info->lock,flags);
3207 if (!waitqueue_active(&info->event_wait_q)) {
3208 /* disable enable exit hunt mode/idle rcvd IRQs */
3209 info->ie1_value &= ~(FLGD|IDLD);
3210 write_reg(info, IE1, info->ie1_value);
3211 }
3212 spin_unlock_irqrestore(&info->lock,flags);
3213 }
3214 exit:
3215 if ( rc == 0 )
3216 PUT_USER(rc, events, mask_ptr);
3217
3218 return rc;
3219 }
3220
3221 static int modem_input_wait(SLMP_INFO *info,int arg)
3222 {
3223 unsigned long flags;
3224 int rc;
3225 struct mgsl_icount cprev, cnow;
3226 DECLARE_WAITQUEUE(wait, current);
3227
3228 /* save current irq counts */
3229 spin_lock_irqsave(&info->lock,flags);
3230 cprev = info->icount;
3231 add_wait_queue(&info->status_event_wait_q, &wait);
3232 set_current_state(TASK_INTERRUPTIBLE);
3233 spin_unlock_irqrestore(&info->lock,flags);
3234
3235 for(;;) {
3236 schedule();
3237 if (signal_pending(current)) {
3238 rc = -ERESTARTSYS;
3239 break;
3240 }
3241
3242 /* get new irq counts */
3243 spin_lock_irqsave(&info->lock,flags);
3244 cnow = info->icount;
3245 set_current_state(TASK_INTERRUPTIBLE);
3246 spin_unlock_irqrestore(&info->lock,flags);
3247
3248 /* if no change, wait aborted for some reason */
3249 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3250 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3251 rc = -EIO;
3252 break;
3253 }
3254
3255 /* check for change in caller specified modem input */
3256 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3257 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3258 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3259 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3260 rc = 0;
3261 break;
3262 }
3263
3264 cprev = cnow;
3265 }
3266 remove_wait_queue(&info->status_event_wait_q, &wait);
3267 set_current_state(TASK_RUNNING);
3268 return rc;
3269 }
3270
3271 /* return the state of the serial control and status signals
3272 */
3273 static int tiocmget(struct tty_struct *tty, struct file *file)
3274 {
3275 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3276 unsigned int result;
3277 unsigned long flags;
3278
3279 spin_lock_irqsave(&info->lock,flags);
3280 get_signals(info);
3281 spin_unlock_irqrestore(&info->lock,flags);
3282
3283 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3284 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3285 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3286 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3287 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3288 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3289
3290 if (debug_level >= DEBUG_LEVEL_INFO)
3291 printk("%s(%d):%s tiocmget() value=%08X\n",
3292 __FILE__,__LINE__, info->device_name, result );
3293 return result;
3294 }
3295
3296 /* set modem control signals (DTR/RTS)
3297 */
3298 static int tiocmset(struct tty_struct *tty, struct file *file,
3299 unsigned int set, unsigned int clear)
3300 {
3301 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3302 unsigned long flags;
3303
3304 if (debug_level >= DEBUG_LEVEL_INFO)
3305 printk("%s(%d):%s tiocmset(%x,%x)\n",
3306 __FILE__,__LINE__,info->device_name, set, clear);
3307
3308 if (set & TIOCM_RTS)
3309 info->serial_signals |= SerialSignal_RTS;
3310 if (set & TIOCM_DTR)
3311 info->serial_signals |= SerialSignal_DTR;
3312 if (clear & TIOCM_RTS)
3313 info->serial_signals &= ~SerialSignal_RTS;
3314 if (clear & TIOCM_DTR)
3315 info->serial_signals &= ~SerialSignal_DTR;
3316
3317 spin_lock_irqsave(&info->lock,flags);
3318 set_signals(info);
3319 spin_unlock_irqrestore(&info->lock,flags);
3320
3321 return 0;
3322 }
3323
3324
3325
3326 /* Block the current process until the specified port is ready to open.
3327 */
3328 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3329 SLMP_INFO *info)
3330 {
3331 DECLARE_WAITQUEUE(wait, current);
3332 int retval;
3333 bool do_clocal = false;
3334 bool extra_count = false;
3335 unsigned long flags;
3336
3337 if (debug_level >= DEBUG_LEVEL_INFO)
3338 printk("%s(%d):%s block_til_ready()\n",
3339 __FILE__,__LINE__, tty->driver->name );
3340
3341 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3342 /* nonblock mode is set or port is not enabled */
3343 /* just verify that callout device is not active */
3344 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3345 return 0;
3346 }
3347
3348 if (tty->termios->c_cflag & CLOCAL)
3349 do_clocal = true;
3350
3351 /* Wait for carrier detect and the line to become
3352 * free (i.e., not in use by the callout). While we are in
3353 * this loop, info->port.count is dropped by one, so that
3354 * close() knows when to free things. We restore it upon
3355 * exit, either normal or abnormal.
3356 */
3357
3358 retval = 0;
3359 add_wait_queue(&info->port.open_wait, &wait);
3360
3361 if (debug_level >= DEBUG_LEVEL_INFO)
3362 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3363 __FILE__,__LINE__, tty->driver->name, info->port.count );
3364
3365 spin_lock_irqsave(&info->lock, flags);
3366 if (!tty_hung_up_p(filp)) {
3367 extra_count = true;
3368 info->port.count--;
3369 }
3370 spin_unlock_irqrestore(&info->lock, flags);
3371 info->port.blocked_open++;
3372
3373 while (1) {
3374 if ((tty->termios->c_cflag & CBAUD)) {
3375 spin_lock_irqsave(&info->lock,flags);
3376 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3377 set_signals(info);
3378 spin_unlock_irqrestore(&info->lock,flags);
3379 }
3380
3381 set_current_state(TASK_INTERRUPTIBLE);
3382
3383 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3384 retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3385 -EAGAIN : -ERESTARTSYS;
3386 break;
3387 }
3388
3389 spin_lock_irqsave(&info->lock,flags);
3390 get_signals(info);
3391 spin_unlock_irqrestore(&info->lock,flags);
3392
3393 if (!(info->port.flags & ASYNC_CLOSING) &&
3394 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3395 break;
3396 }
3397
3398 if (signal_pending(current)) {
3399 retval = -ERESTARTSYS;
3400 break;
3401 }
3402
3403 if (debug_level >= DEBUG_LEVEL_INFO)
3404 printk("%s(%d):%s block_til_ready() count=%d\n",
3405 __FILE__,__LINE__, tty->driver->name, info->port.count );
3406
3407 schedule();
3408 }
3409
3410 set_current_state(TASK_RUNNING);
3411 remove_wait_queue(&info->port.open_wait, &wait);
3412
3413 if (extra_count)
3414 info->port.count++;
3415 info->port.blocked_open--;
3416
3417 if (debug_level >= DEBUG_LEVEL_INFO)
3418 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3419 __FILE__,__LINE__, tty->driver->name, info->port.count );
3420
3421 if (!retval)
3422 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3423
3424 return retval;
3425 }
3426
3427 static int alloc_dma_bufs(SLMP_INFO *info)
3428 {
3429 unsigned short BuffersPerFrame;
3430 unsigned short BufferCount;
3431
3432 // Force allocation to start at 64K boundary for each port.
3433 // This is necessary because *all* buffer descriptors for a port
3434 // *must* be in the same 64K block. All descriptors on a port
3435 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3436 // into the CBP register.
3437 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3438
3439 /* Calculate the number of DMA buffers necessary to hold the */
3440 /* largest allowable frame size. Note: If the max frame size is */
3441 /* not an even multiple of the DMA buffer size then we need to */
3442 /* round the buffer count per frame up one. */
3443
3444 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3445 if ( info->max_frame_size % SCABUFSIZE )
3446 BuffersPerFrame++;
3447
3448 /* calculate total number of data buffers (SCABUFSIZE) possible
3449 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3450 * for the descriptor list (BUFFERLISTSIZE).
3451 */
3452 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3453
3454 /* limit number of buffers to maximum amount of descriptors */
3455 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3456 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3457
3458 /* use enough buffers to transmit one max size frame */
3459 info->tx_buf_count = BuffersPerFrame + 1;
3460
3461 /* never use more than half the available buffers for transmit */
3462 if (info->tx_buf_count > (BufferCount/2))
3463 info->tx_buf_count = BufferCount/2;
3464
3465 if (info->tx_buf_count > SCAMAXDESC)
3466 info->tx_buf_count = SCAMAXDESC;
3467
3468 /* use remaining buffers for receive */
3469 info->rx_buf_count = BufferCount - info->tx_buf_count;
3470
3471 if (info->rx_buf_count > SCAMAXDESC)
3472 info->rx_buf_count = SCAMAXDESC;
3473
3474 if ( debug_level >= DEBUG_LEVEL_INFO )
3475 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3476 __FILE__,__LINE__, info->device_name,
3477 info->tx_buf_count,info->rx_buf_count);
3478
3479 if ( alloc_buf_list( info ) < 0 ||
3480 alloc_frame_bufs(info,
3481 info->rx_buf_list,
3482 info->rx_buf_list_ex,
3483 info->rx_buf_count) < 0 ||
3484 alloc_frame_bufs(info,
3485 info->tx_buf_list,
3486 info->tx_buf_list_ex,
3487 info->tx_buf_count) < 0 ||
3488 alloc_tmp_rx_buf(info) < 0 ) {
3489 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3490 __FILE__,__LINE__, info->device_name);
3491 return -ENOMEM;
3492 }
3493
3494 rx_reset_buffers( info );
3495
3496 return 0;
3497 }
3498
3499 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3500 */
3501 static int alloc_buf_list(SLMP_INFO *info)
3502 {
3503 unsigned int i;
3504
3505 /* build list in adapter shared memory */
3506 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3507 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3508 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3509
3510 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3511
3512 /* Save virtual address pointers to the receive and */
3513 /* transmit buffer lists. (Receive 1st). These pointers will */
3514 /* be used by the processor to access the lists. */
3515 info->rx_buf_list = (SCADESC *)info->buffer_list;
3516
3517 info->tx_buf_list = (SCADESC *)info->buffer_list;
3518 info->tx_buf_list += info->rx_buf_count;
3519
3520 /* Build links for circular buffer entry lists (tx and rx)
3521 *
3522 * Note: links are physical addresses read by the SCA device
3523 * to determine the next buffer entry to use.
3524 */
3525
3526 for ( i = 0; i < info->rx_buf_count; i++ ) {
3527 /* calculate and store physical address of this buffer entry */
3528 info->rx_buf_list_ex[i].phys_entry =
3529 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3530
3531 /* calculate and store physical address of */
3532 /* next entry in cirular list of entries */
3533 info->rx_buf_list[i].next = info->buffer_list_phys;
3534 if ( i < info->rx_buf_count - 1 )
3535 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3536
3537 info->rx_buf_list[i].length = SCABUFSIZE;
3538 }
3539
3540 for ( i = 0; i < info->tx_buf_count; i++ ) {
3541 /* calculate and store physical address of this buffer entry */
3542 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3543 ((info->rx_buf_count + i) * sizeof(SCADESC));
3544
3545 /* calculate and store physical address of */
3546 /* next entry in cirular list of entries */
3547
3548 info->tx_buf_list[i].next = info->buffer_list_phys +
3549 info->rx_buf_count * sizeof(SCADESC);
3550
3551 if ( i < info->tx_buf_count - 1 )
3552 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3553 }
3554
3555 return 0;
3556 }
3557
3558 /* Allocate the frame DMA buffers used by the specified buffer list.
3559 */
3560 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3561 {
3562 int i;
3563 unsigned long phys_addr;
3564
3565 for ( i = 0; i < count; i++ ) {
3566 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3567 phys_addr = info->port_array[0]->last_mem_alloc;
3568 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3569
3570 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3571 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3572 }
3573
3574 return 0;
3575 }
3576
3577 static void free_dma_bufs(SLMP_INFO *info)
3578 {
3579 info->buffer_list = NULL;
3580 info->rx_buf_list = NULL;
3581 info->tx_buf_list = NULL;
3582 }
3583
3584 /* allocate buffer large enough to hold max_frame_size.
3585 * This buffer is used to pass an assembled frame to the line discipline.
3586 */
3587 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3588 {
3589 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3590 if (info->tmp_rx_buf == NULL)
3591 return -ENOMEM;
3592 return 0;
3593 }
3594
3595 static void free_tmp_rx_buf(SLMP_INFO *info)
3596 {
3597 kfree(info->tmp_rx_buf);
3598 info->tmp_rx_buf = NULL;
3599 }
3600
3601 static int claim_resources(SLMP_INFO *info)
3602 {
3603 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3604 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3605 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3606 info->init_error = DiagStatus_AddressConflict;
3607 goto errout;
3608 }
3609 else
3610 info->shared_mem_requested = true;
3611
3612 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3613 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3614 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3615 info->init_error = DiagStatus_AddressConflict;
3616 goto errout;
3617 }
3618 else
3619 info->lcr_mem_requested = true;
3620
3621 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3622 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3623 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3624 info->init_error = DiagStatus_AddressConflict;
3625 goto errout;
3626 }
3627 else
3628 info->sca_base_requested = true;
3629
3630 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3631 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3632 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3633 info->init_error = DiagStatus_AddressConflict;
3634 goto errout;
3635 }
3636 else
3637 info->sca_statctrl_requested = true;
3638
3639 info->memory_base = ioremap_nocache(info->phys_memory_base,
3640 SCA_MEM_SIZE);
3641 if (!info->memory_base) {
3642 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3643 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3644 info->init_error = DiagStatus_CantAssignPciResources;
3645 goto errout;
3646 }
3647
3648 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3649 if (!info->lcr_base) {
3650 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3651 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3652 info->init_error = DiagStatus_CantAssignPciResources;
3653 goto errout;
3654 }
3655 info->lcr_base += info->lcr_offset;
3656
3657 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3658 if (!info->sca_base) {
3659 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3660 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3661 info->init_error = DiagStatus_CantAssignPciResources;
3662 goto errout;
3663 }
3664 info->sca_base += info->sca_offset;
3665
3666 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3667 PAGE_SIZE);
3668 if (!info->statctrl_base) {
3669 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3670 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3671 info->init_error = DiagStatus_CantAssignPciResources;
3672 goto errout;
3673 }
3674 info->statctrl_base += info->statctrl_offset;
3675
3676 if ( !memory_test(info) ) {
3677 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3678 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3679 info->init_error = DiagStatus_MemoryError;
3680 goto errout;
3681 }
3682
3683 return 0;
3684
3685 errout:
3686 release_resources( info );
3687 return -ENODEV;
3688 }
3689
3690 static void release_resources(SLMP_INFO *info)
3691 {
3692 if ( debug_level >= DEBUG_LEVEL_INFO )
3693 printk( "%s(%d):%s release_resources() entry\n",
3694 __FILE__,__LINE__,info->device_name );
3695
3696 if ( info->irq_requested ) {
3697 free_irq(info->irq_level, info);
3698 info->irq_requested = false;
3699 }
3700
3701 if ( info->shared_mem_requested ) {
3702 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3703 info->shared_mem_requested = false;
3704 }
3705 if ( info->lcr_mem_requested ) {
3706 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3707 info->lcr_mem_requested = false;
3708 }
3709 if ( info->sca_base_requested ) {
3710 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3711 info->sca_base_requested = false;
3712 }
3713 if ( info->sca_statctrl_requested ) {
3714 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3715 info->sca_statctrl_requested = false;
3716 }
3717
3718 if (info->memory_base){
3719 iounmap(info->memory_base);
3720 info->memory_base = NULL;
3721 }
3722
3723 if (info->sca_base) {
3724 iounmap(info->sca_base - info->sca_offset);
3725 info->sca_base=NULL;
3726 }
3727
3728 if (info->statctrl_base) {
3729 iounmap(info->statctrl_base - info->statctrl_offset);
3730 info->statctrl_base=NULL;
3731 }
3732
3733 if (info->lcr_base){
3734 iounmap(info->lcr_base - info->lcr_offset);
3735 info->lcr_base = NULL;
3736 }
3737
3738 if ( debug_level >= DEBUG_LEVEL_INFO )
3739 printk( "%s(%d):%s release_resources() exit\n",
3740 __FILE__,__LINE__,info->device_name );
3741 }
3742
3743 /* Add the specified device instance data structure to the
3744 * global linked list of devices and increment the device count.
3745 */
3746 static void add_device(SLMP_INFO *info)
3747 {
3748 info->next_device = NULL;
3749 info->line = synclinkmp_device_count;
3750 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3751
3752 if (info->line < MAX_DEVICES) {
3753 if (maxframe[info->line])
3754 info->max_frame_size = maxframe[info->line];
3755 info->dosyncppp = dosyncppp[info->line];
3756 }
3757
3758 synclinkmp_device_count++;
3759
3760 if ( !synclinkmp_device_list )
3761 synclinkmp_device_list = info;
3762 else {
3763 SLMP_INFO *current_dev = synclinkmp_device_list;
3764 while( current_dev->next_device )
3765 current_dev = current_dev->next_device;
3766 current_dev->next_device = info;
3767 }
3768
3769 if ( info->max_frame_size < 4096 )
3770 info->max_frame_size = 4096;
3771 else if ( info->max_frame_size > 65535 )
3772 info->max_frame_size = 65535;
3773
3774 printk( "SyncLink MultiPort %s: "
3775 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3776 info->device_name,
3777 info->phys_sca_base,
3778 info->phys_memory_base,
3779 info->phys_statctrl_base,
3780 info->phys_lcr_base,
3781 info->irq_level,
3782 info->max_frame_size );
3783
3784 #if SYNCLINK_GENERIC_HDLC
3785 hdlcdev_init(info);
3786 #endif
3787 }
3788
3789 /* Allocate and initialize a device instance structure
3790 *
3791 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3792 */
3793 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3794 {
3795 SLMP_INFO *info;
3796
3797 info = kzalloc(sizeof(SLMP_INFO),
3798 GFP_KERNEL);
3799
3800 if (!info) {
3801 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3802 __FILE__,__LINE__, adapter_num, port_num);
3803 } else {
3804 tty_port_init(&info->port);
3805 info->magic = MGSL_MAGIC;
3806 INIT_WORK(&info->task, bh_handler);
3807 info->max_frame_size = 4096;
3808 info->port.close_delay = 5*HZ/10;
3809 info->port.closing_wait = 30*HZ;
3810 init_waitqueue_head(&info->status_event_wait_q);
3811 init_waitqueue_head(&info->event_wait_q);
3812 spin_lock_init(&info->netlock);
3813 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3814 info->idle_mode = HDLC_TXIDLE_FLAGS;
3815 info->adapter_num = adapter_num;
3816 info->port_num = port_num;
3817
3818 /* Copy configuration info to device instance data */
3819 info->irq_level = pdev->irq;
3820 info->phys_lcr_base = pci_resource_start(pdev,0);
3821 info->phys_sca_base = pci_resource_start(pdev,2);
3822 info->phys_memory_base = pci_resource_start(pdev,3);
3823 info->phys_statctrl_base = pci_resource_start(pdev,4);
3824
3825 /* Because veremap only works on page boundaries we must map
3826 * a larger area than is actually implemented for the LCR
3827 * memory range. We map a full page starting at the page boundary.
3828 */
3829 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3830 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3831
3832 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3833 info->phys_sca_base &= ~(PAGE_SIZE-1);
3834
3835 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3836 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3837
3838 info->bus_type = MGSL_BUS_TYPE_PCI;
3839 info->irq_flags = IRQF_SHARED;
3840
3841 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3842 setup_timer(&info->status_timer, status_timeout,
3843 (unsigned long)info);
3844
3845 /* Store the PCI9050 misc control register value because a flaw
3846 * in the PCI9050 prevents LCR registers from being read if
3847 * BIOS assigns an LCR base address with bit 7 set.
3848 *
3849 * Only the misc control register is accessed for which only
3850 * write access is needed, so set an initial value and change
3851 * bits to the device instance data as we write the value
3852 * to the actual misc control register.
3853 */
3854 info->misc_ctrl_value = 0x087e4546;
3855
3856 /* initial port state is unknown - if startup errors
3857 * occur, init_error will be set to indicate the
3858 * problem. Once the port is fully initialized,
3859 * this value will be set to 0 to indicate the
3860 * port is available.
3861 */
3862 info->init_error = -1;
3863 }
3864
3865 return info;
3866 }
3867
3868 static void device_init(int adapter_num, struct pci_dev *pdev)
3869 {
3870 SLMP_INFO *port_array[SCA_MAX_PORTS];
3871 int port;
3872
3873 /* allocate device instances for up to SCA_MAX_PORTS devices */
3874 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3875 port_array[port] = alloc_dev(adapter_num,port,pdev);
3876 if( port_array[port] == NULL ) {
3877 for ( --port; port >= 0; --port )
3878 kfree(port_array[port]);
3879 return;
3880 }
3881 }
3882
3883 /* give copy of port_array to all ports and add to device list */
3884 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3885 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3886 add_device( port_array[port] );
3887 spin_lock_init(&port_array[port]->lock);
3888 }
3889
3890 /* Allocate and claim adapter resources */
3891 if ( !claim_resources(port_array[0]) ) {
3892
3893 alloc_dma_bufs(port_array[0]);
3894
3895 /* copy resource information from first port to others */
3896 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3897 port_array[port]->lock = port_array[0]->lock;
3898 port_array[port]->irq_level = port_array[0]->irq_level;
3899 port_array[port]->memory_base = port_array[0]->memory_base;
3900 port_array[port]->sca_base = port_array[0]->sca_base;
3901 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3902 port_array[port]->lcr_base = port_array[0]->lcr_base;
3903 alloc_dma_bufs(port_array[port]);
3904 }
3905
3906 if ( request_irq(port_array[0]->irq_level,
3907 synclinkmp_interrupt,
3908 port_array[0]->irq_flags,
3909 port_array[0]->device_name,
3910 port_array[0]) < 0 ) {
3911 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3912 __FILE__,__LINE__,
3913 port_array[0]->device_name,
3914 port_array[0]->irq_level );
3915 }
3916 else {
3917 port_array[0]->irq_requested = true;
3918 adapter_test(port_array[0]);
3919 }
3920 }
3921 }
3922
3923 static const struct tty_operations ops = {
3924 .open = open,
3925 .close = close,
3926 .write = write,
3927 .put_char = put_char,
3928 .flush_chars = flush_chars,
3929 .write_room = write_room,
3930 .chars_in_buffer = chars_in_buffer,
3931 .flush_buffer = flush_buffer,
3932 .ioctl = ioctl,
3933 .throttle = throttle,
3934 .unthrottle = unthrottle,
3935 .send_xchar = send_xchar,
3936 .break_ctl = set_break,
3937 .wait_until_sent = wait_until_sent,
3938 .read_proc = read_proc,
3939 .set_termios = set_termios,
3940 .stop = tx_hold,
3941 .start = tx_release,
3942 .hangup = hangup,
3943 .tiocmget = tiocmget,
3944 .tiocmset = tiocmset,
3945 };
3946
3947 static void synclinkmp_cleanup(void)
3948 {
3949 int rc;
3950 SLMP_INFO *info;
3951 SLMP_INFO *tmp;
3952
3953 printk("Unloading %s %s\n", driver_name, driver_version);
3954
3955 if (serial_driver) {
3956 if ((rc = tty_unregister_driver(serial_driver)))
3957 printk("%s(%d) failed to unregister tty driver err=%d\n",
3958 __FILE__,__LINE__,rc);
3959 put_tty_driver(serial_driver);
3960 }
3961
3962 /* reset devices */
3963 info = synclinkmp_device_list;
3964 while(info) {
3965 reset_port(info);
3966 info = info->next_device;
3967 }
3968
3969 /* release devices */
3970 info = synclinkmp_device_list;
3971 while(info) {
3972 #if SYNCLINK_GENERIC_HDLC
3973 hdlcdev_exit(info);
3974 #endif
3975 free_dma_bufs(info);
3976 free_tmp_rx_buf(info);
3977 if ( info->port_num == 0 ) {
3978 if (info->sca_base)
3979 write_reg(info, LPR, 1); /* set low power mode */
3980 release_resources(info);
3981 }
3982 tmp = info;
3983 info = info->next_device;
3984 kfree(tmp);
3985 }
3986
3987 pci_unregister_driver(&synclinkmp_pci_driver);
3988 }
3989
3990 /* Driver initialization entry point.
3991 */
3992
3993 static int __init synclinkmp_init(void)
3994 {
3995 int rc;
3996
3997 if (break_on_load) {
3998 synclinkmp_get_text_ptr();
3999 BREAKPOINT();
4000 }
4001
4002 printk("%s %s\n", driver_name, driver_version);
4003
4004 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4005 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4006 return rc;
4007 }
4008
4009 serial_driver = alloc_tty_driver(128);
4010 if (!serial_driver) {
4011 rc = -ENOMEM;
4012 goto error;
4013 }
4014
4015 /* Initialize the tty_driver structure */
4016
4017 serial_driver->owner = THIS_MODULE;
4018 serial_driver->driver_name = "synclinkmp";
4019 serial_driver->name = "ttySLM";
4020 serial_driver->major = ttymajor;
4021 serial_driver->minor_start = 64;
4022 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4023 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4024 serial_driver->init_termios = tty_std_termios;
4025 serial_driver->init_termios.c_cflag =
4026 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4027 serial_driver->init_termios.c_ispeed = 9600;
4028 serial_driver->init_termios.c_ospeed = 9600;
4029 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4030 tty_set_operations(serial_driver, &ops);
4031 if ((rc = tty_register_driver(serial_driver)) < 0) {
4032 printk("%s(%d):Couldn't register serial driver\n",
4033 __FILE__,__LINE__);
4034 put_tty_driver(serial_driver);
4035 serial_driver = NULL;
4036 goto error;
4037 }
4038
4039 printk("%s %s, tty major#%d\n",
4040 driver_name, driver_version,
4041 serial_driver->major);
4042
4043 return 0;
4044
4045 error:
4046 synclinkmp_cleanup();
4047 return rc;
4048 }
4049
4050 static void __exit synclinkmp_exit(void)
4051 {
4052 synclinkmp_cleanup();
4053 }
4054
4055 module_init(synclinkmp_init);
4056 module_exit(synclinkmp_exit);
4057
4058 /* Set the port for internal loopback mode.
4059 * The TxCLK and RxCLK signals are generated from the BRG and
4060 * the TxD is looped back to the RxD internally.
4061 */
4062 static void enable_loopback(SLMP_INFO *info, int enable)
4063 {
4064 if (enable) {
4065 /* MD2 (Mode Register 2)
4066 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4067 */
4068 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4069
4070 /* degate external TxC clock source */
4071 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4072 write_control_reg(info);
4073
4074 /* RXS/TXS (Rx/Tx clock source)
4075 * 07 Reserved, must be 0
4076 * 06..04 Clock Source, 100=BRG
4077 * 03..00 Clock Divisor, 0000=1
4078 */
4079 write_reg(info, RXS, 0x40);
4080 write_reg(info, TXS, 0x40);
4081
4082 } else {
4083 /* MD2 (Mode Register 2)
4084 * 01..00 CNCT<1..0> Channel connection, 0=normal
4085 */
4086 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4087
4088 /* RXS/TXS (Rx/Tx clock source)
4089 * 07 Reserved, must be 0
4090 * 06..04 Clock Source, 000=RxC/TxC Pin
4091 * 03..00 Clock Divisor, 0000=1
4092 */
4093 write_reg(info, RXS, 0x00);
4094 write_reg(info, TXS, 0x00);
4095 }
4096
4097 /* set LinkSpeed if available, otherwise default to 2Mbps */
4098 if (info->params.clock_speed)
4099 set_rate(info, info->params.clock_speed);
4100 else
4101 set_rate(info, 3686400);
4102 }
4103
4104 /* Set the baud rate register to the desired speed
4105 *
4106 * data_rate data rate of clock in bits per second
4107 * A data rate of 0 disables the AUX clock.
4108 */
4109 static void set_rate( SLMP_INFO *info, u32 data_rate )
4110 {
4111 u32 TMCValue;
4112 unsigned char BRValue;
4113 u32 Divisor=0;
4114
4115 /* fBRG = fCLK/(TMC * 2^BR)
4116 */
4117 if (data_rate != 0) {
4118 Divisor = 14745600/data_rate;
4119 if (!Divisor)
4120 Divisor = 1;
4121
4122 TMCValue = Divisor;
4123
4124 BRValue = 0;
4125 if (TMCValue != 1 && TMCValue != 2) {
4126 /* BRValue of 0 provides 50/50 duty cycle *only* when
4127 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4128 * 50/50 duty cycle.
4129 */
4130 BRValue = 1;
4131 TMCValue >>= 1;
4132 }
4133
4134 /* while TMCValue is too big for TMC register, divide
4135 * by 2 and increment BR exponent.
4136 */
4137 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4138 TMCValue >>= 1;
4139
4140 write_reg(info, TXS,
4141 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4142 write_reg(info, RXS,
4143 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4144 write_reg(info, TMC, (unsigned char)TMCValue);
4145 }
4146 else {
4147 write_reg(info, TXS,0);
4148 write_reg(info, RXS,0);
4149 write_reg(info, TMC, 0);
4150 }
4151 }
4152
4153 /* Disable receiver
4154 */
4155 static void rx_stop(SLMP_INFO *info)
4156 {
4157 if (debug_level >= DEBUG_LEVEL_ISR)
4158 printk("%s(%d):%s rx_stop()\n",
4159 __FILE__,__LINE__, info->device_name );
4160
4161 write_reg(info, CMD, RXRESET);
4162
4163 info->ie0_value &= ~RXRDYE;
4164 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4165
4166 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4167 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4168 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4169
4170 info->rx_enabled = false;
4171 info->rx_overflow = false;
4172 }
4173
4174 /* enable the receiver
4175 */
4176 static void rx_start(SLMP_INFO *info)
4177 {
4178 int i;
4179
4180 if (debug_level >= DEBUG_LEVEL_ISR)
4181 printk("%s(%d):%s rx_start()\n",
4182 __FILE__,__LINE__, info->device_name );
4183
4184 write_reg(info, CMD, RXRESET);
4185
4186 if ( info->params.mode == MGSL_MODE_HDLC ) {
4187 /* HDLC, disabe IRQ on rxdata */
4188 info->ie0_value &= ~RXRDYE;
4189 write_reg(info, IE0, info->ie0_value);
4190
4191 /* Reset all Rx DMA buffers and program rx dma */
4192 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4193 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4194
4195 for (i = 0; i < info->rx_buf_count; i++) {
4196 info->rx_buf_list[i].status = 0xff;
4197
4198 // throttle to 4 shared memory writes at a time to prevent
4199 // hogging local bus (keep latency time for DMA requests low).
4200 if (!(i % 4))
4201 read_status_reg(info);
4202 }
4203 info->current_rx_buf = 0;
4204
4205 /* set current/1st descriptor address */
4206 write_reg16(info, RXDMA + CDA,
4207 info->rx_buf_list_ex[0].phys_entry);
4208
4209 /* set new last rx descriptor address */
4210 write_reg16(info, RXDMA + EDA,
4211 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4212
4213 /* set buffer length (shared by all rx dma data buffers) */
4214 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4215
4216 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4217 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4218 } else {
4219 /* async, enable IRQ on rxdata */
4220 info->ie0_value |= RXRDYE;
4221 write_reg(info, IE0, info->ie0_value);
4222 }
4223
4224 write_reg(info, CMD, RXENABLE);
4225
4226 info->rx_overflow = false;
4227 info->rx_enabled = true;
4228 }
4229
4230 /* Enable the transmitter and send a transmit frame if
4231 * one is loaded in the DMA buffers.
4232 */
4233 static void tx_start(SLMP_INFO *info)
4234 {
4235 if (debug_level >= DEBUG_LEVEL_ISR)
4236 printk("%s(%d):%s tx_start() tx_count=%d\n",
4237 __FILE__,__LINE__, info->device_name,info->tx_count );
4238
4239 if (!info->tx_enabled ) {
4240 write_reg(info, CMD, TXRESET);
4241 write_reg(info, CMD, TXENABLE);
4242 info->tx_enabled = true;
4243 }
4244
4245 if ( info->tx_count ) {
4246
4247 /* If auto RTS enabled and RTS is inactive, then assert */
4248 /* RTS and set a flag indicating that the driver should */
4249 /* negate RTS when the transmission completes. */
4250
4251 info->drop_rts_on_tx_done = false;
4252
4253 if (info->params.mode != MGSL_MODE_ASYNC) {
4254
4255 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4256 get_signals( info );
4257 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4258 info->serial_signals |= SerialSignal_RTS;
4259 set_signals( info );
4260 info->drop_rts_on_tx_done = true;
4261 }
4262 }
4263
4264 write_reg16(info, TRC0,
4265 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4266
4267 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4268 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4269
4270 /* set TX CDA (current descriptor address) */
4271 write_reg16(info, TXDMA + CDA,
4272 info->tx_buf_list_ex[0].phys_entry);
4273
4274 /* set TX EDA (last descriptor address) */
4275 write_reg16(info, TXDMA + EDA,
4276 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4277
4278 /* enable underrun IRQ */
4279 info->ie1_value &= ~IDLE;
4280 info->ie1_value |= UDRN;
4281 write_reg(info, IE1, info->ie1_value);
4282 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4283
4284 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4285 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4286
4287 mod_timer(&info->tx_timer, jiffies +
4288 msecs_to_jiffies(5000));
4289 }
4290 else {
4291 tx_load_fifo(info);
4292 /* async, enable IRQ on txdata */
4293 info->ie0_value |= TXRDYE;
4294 write_reg(info, IE0, info->ie0_value);
4295 }
4296
4297 info->tx_active = true;
4298 }
4299 }
4300
4301 /* stop the transmitter and DMA
4302 */
4303 static void tx_stop( SLMP_INFO *info )
4304 {
4305 if (debug_level >= DEBUG_LEVEL_ISR)
4306 printk("%s(%d):%s tx_stop()\n",
4307 __FILE__,__LINE__, info->device_name );
4308
4309 del_timer(&info->tx_timer);
4310
4311 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4312 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4313
4314 write_reg(info, CMD, TXRESET);
4315
4316 info->ie1_value &= ~(UDRN + IDLE);
4317 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4318 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4319
4320 info->ie0_value &= ~TXRDYE;
4321 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4322
4323 info->tx_enabled = false;
4324 info->tx_active = false;
4325 }
4326
4327 /* Fill the transmit FIFO until the FIFO is full or
4328 * there is no more data to load.
4329 */
4330 static void tx_load_fifo(SLMP_INFO *info)
4331 {
4332 u8 TwoBytes[2];
4333
4334 /* do nothing is now tx data available and no XON/XOFF pending */
4335
4336 if ( !info->tx_count && !info->x_char )
4337 return;
4338
4339 /* load the Transmit FIFO until FIFOs full or all data sent */
4340
4341 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4342
4343 /* there is more space in the transmit FIFO and */
4344 /* there is more data in transmit buffer */
4345
4346 if ( (info->tx_count > 1) && !info->x_char ) {
4347 /* write 16-bits */
4348 TwoBytes[0] = info->tx_buf[info->tx_get++];
4349 if (info->tx_get >= info->max_frame_size)
4350 info->tx_get -= info->max_frame_size;
4351 TwoBytes[1] = info->tx_buf[info->tx_get++];
4352 if (info->tx_get >= info->max_frame_size)
4353 info->tx_get -= info->max_frame_size;
4354
4355 write_reg16(info, TRB, *((u16 *)TwoBytes));
4356
4357 info->tx_count -= 2;
4358 info->icount.tx += 2;
4359 } else {
4360 /* only 1 byte left to transmit or 1 FIFO slot left */
4361
4362 if (info->x_char) {
4363 /* transmit pending high priority char */
4364 write_reg(info, TRB, info->x_char);
4365 info->x_char = 0;
4366 } else {
4367 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4368 if (info->tx_get >= info->max_frame_size)
4369 info->tx_get -= info->max_frame_size;
4370 info->tx_count--;
4371 }
4372 info->icount.tx++;
4373 }
4374 }
4375 }
4376
4377 /* Reset a port to a known state
4378 */
4379 static void reset_port(SLMP_INFO *info)
4380 {
4381 if (info->sca_base) {
4382
4383 tx_stop(info);
4384 rx_stop(info);
4385
4386 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4387 set_signals(info);
4388
4389 /* disable all port interrupts */
4390 info->ie0_value = 0;
4391 info->ie1_value = 0;
4392 info->ie2_value = 0;
4393 write_reg(info, IE0, info->ie0_value);
4394 write_reg(info, IE1, info->ie1_value);
4395 write_reg(info, IE2, info->ie2_value);
4396
4397 write_reg(info, CMD, CHRESET);
4398 }
4399 }
4400
4401 /* Reset all the ports to a known state.
4402 */
4403 static void reset_adapter(SLMP_INFO *info)
4404 {
4405 int i;
4406
4407 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4408 if (info->port_array[i])
4409 reset_port(info->port_array[i]);
4410 }
4411 }
4412
4413 /* Program port for asynchronous communications.
4414 */
4415 static void async_mode(SLMP_INFO *info)
4416 {
4417
4418 unsigned char RegValue;
4419
4420 tx_stop(info);
4421 rx_stop(info);
4422
4423 /* MD0, Mode Register 0
4424 *
4425 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4426 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4427 * 03 Reserved, must be 0
4428 * 02 CRCCC, CRC Calculation, 0=disabled
4429 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4430 *
4431 * 0000 0000
4432 */
4433 RegValue = 0x00;
4434 if (info->params.stop_bits != 1)
4435 RegValue |= BIT1;
4436 write_reg(info, MD0, RegValue);
4437
4438 /* MD1, Mode Register 1
4439 *
4440 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4441 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4442 * 03..02 RXCHR<1..0>, rx char size
4443 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4444 *
4445 * 0100 0000
4446 */
4447 RegValue = 0x40;
4448 switch (info->params.data_bits) {
4449 case 7: RegValue |= BIT4 + BIT2; break;
4450 case 6: RegValue |= BIT5 + BIT3; break;
4451 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4452 }
4453 if (info->params.parity != ASYNC_PARITY_NONE) {
4454 RegValue |= BIT1;
4455 if (info->params.parity == ASYNC_PARITY_ODD)
4456 RegValue |= BIT0;
4457 }
4458 write_reg(info, MD1, RegValue);
4459
4460 /* MD2, Mode Register 2
4461 *
4462 * 07..02 Reserved, must be 0
4463 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4464 *
4465 * 0000 0000
4466 */
4467 RegValue = 0x00;
4468 if (info->params.loopback)
4469 RegValue |= (BIT1 + BIT0);
4470 write_reg(info, MD2, RegValue);
4471
4472 /* RXS, Receive clock source
4473 *
4474 * 07 Reserved, must be 0
4475 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4476 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4477 */
4478 RegValue=BIT6;
4479 write_reg(info, RXS, RegValue);
4480
4481 /* TXS, Transmit clock source
4482 *
4483 * 07 Reserved, must be 0
4484 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4485 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4486 */
4487 RegValue=BIT6;
4488 write_reg(info, TXS, RegValue);
4489
4490 /* Control Register
4491 *
4492 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4493 */
4494 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4495 write_control_reg(info);
4496
4497 tx_set_idle(info);
4498
4499 /* RRC Receive Ready Control 0
4500 *
4501 * 07..05 Reserved, must be 0
4502 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4503 */
4504 write_reg(info, RRC, 0x00);
4505
4506 /* TRC0 Transmit Ready Control 0
4507 *
4508 * 07..05 Reserved, must be 0
4509 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4510 */
4511 write_reg(info, TRC0, 0x10);
4512
4513 /* TRC1 Transmit Ready Control 1
4514 *
4515 * 07..05 Reserved, must be 0
4516 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4517 */
4518 write_reg(info, TRC1, 0x1e);
4519
4520 /* CTL, MSCI control register
4521 *
4522 * 07..06 Reserved, set to 0
4523 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4524 * 04 IDLC, idle control, 0=mark 1=idle register
4525 * 03 BRK, break, 0=off 1 =on (async)
4526 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4527 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4528 * 00 RTS, RTS output control, 0=active 1=inactive
4529 *
4530 * 0001 0001
4531 */
4532 RegValue = 0x10;
4533 if (!(info->serial_signals & SerialSignal_RTS))
4534 RegValue |= 0x01;
4535 write_reg(info, CTL, RegValue);
4536
4537 /* enable status interrupts */
4538 info->ie0_value |= TXINTE + RXINTE;
4539 write_reg(info, IE0, info->ie0_value);
4540
4541 /* enable break detect interrupt */
4542 info->ie1_value = BRKD;
4543 write_reg(info, IE1, info->ie1_value);
4544
4545 /* enable rx overrun interrupt */
4546 info->ie2_value = OVRN;
4547 write_reg(info, IE2, info->ie2_value);
4548
4549 set_rate( info, info->params.data_rate * 16 );
4550 }
4551
4552 /* Program the SCA for HDLC communications.
4553 */
4554 static void hdlc_mode(SLMP_INFO *info)
4555 {
4556 unsigned char RegValue;
4557 u32 DpllDivisor;
4558
4559 // Can't use DPLL because SCA outputs recovered clock on RxC when
4560 // DPLL mode selected. This causes output contention with RxC receiver.
4561 // Use of DPLL would require external hardware to disable RxC receiver
4562 // when DPLL mode selected.
4563 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4564
4565 /* disable DMA interrupts */
4566 write_reg(info, TXDMA + DIR, 0);
4567 write_reg(info, RXDMA + DIR, 0);
4568
4569 /* MD0, Mode Register 0
4570 *
4571 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4572 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4573 * 03 Reserved, must be 0
4574 * 02 CRCCC, CRC Calculation, 1=enabled
4575 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4576 * 00 CRC0, CRC initial value, 1 = all 1s
4577 *
4578 * 1000 0001
4579 */
4580 RegValue = 0x81;
4581 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4582 RegValue |= BIT4;
4583 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4584 RegValue |= BIT4;
4585 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4586 RegValue |= BIT2 + BIT1;
4587 write_reg(info, MD0, RegValue);
4588
4589 /* MD1, Mode Register 1
4590 *
4591 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4592 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4593 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4594 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4595 *
4596 * 0000 0000
4597 */
4598 RegValue = 0x00;
4599 write_reg(info, MD1, RegValue);
4600
4601 /* MD2, Mode Register 2
4602 *
4603 * 07 NRZFM, 0=NRZ, 1=FM
4604 * 06..05 CODE<1..0> Encoding, 00=NRZ
4605 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4606 * 02 Reserved, must be 0
4607 * 01..00 CNCT<1..0> Channel connection, 0=normal
4608 *
4609 * 0000 0000
4610 */
4611 RegValue = 0x00;
4612 switch(info->params.encoding) {
4613 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4614 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4615 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4616 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4617 #if 0
4618 case HDLC_ENCODING_NRZB: /* not supported */
4619 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4620 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4621 #endif
4622 }
4623 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4624 DpllDivisor = 16;
4625 RegValue |= BIT3;
4626 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4627 DpllDivisor = 8;
4628 } else {
4629 DpllDivisor = 32;
4630 RegValue |= BIT4;
4631 }
4632 write_reg(info, MD2, RegValue);
4633
4634
4635 /* RXS, Receive clock source
4636 *
4637 * 07 Reserved, must be 0
4638 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4639 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4640 */
4641 RegValue=0;
4642 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4643 RegValue |= BIT6;
4644 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4645 RegValue |= BIT6 + BIT5;
4646 write_reg(info, RXS, RegValue);
4647
4648 /* TXS, Transmit clock source
4649 *
4650 * 07 Reserved, must be 0
4651 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4652 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4653 */
4654 RegValue=0;
4655 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4656 RegValue |= BIT6;
4657 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4658 RegValue |= BIT6 + BIT5;
4659 write_reg(info, TXS, RegValue);
4660
4661 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4662 set_rate(info, info->params.clock_speed * DpllDivisor);
4663 else
4664 set_rate(info, info->params.clock_speed);
4665
4666 /* GPDATA (General Purpose I/O Data Register)
4667 *
4668 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4669 */
4670 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4671 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4672 else
4673 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4674 write_control_reg(info);
4675
4676 /* RRC Receive Ready Control 0
4677 *
4678 * 07..05 Reserved, must be 0
4679 * 04..00 RRC<4..0> Rx FIFO trigger active
4680 */
4681 write_reg(info, RRC, rx_active_fifo_level);
4682
4683 /* TRC0 Transmit Ready Control 0
4684 *
4685 * 07..05 Reserved, must be 0
4686 * 04..00 TRC<4..0> Tx FIFO trigger active
4687 */
4688 write_reg(info, TRC0, tx_active_fifo_level);
4689
4690 /* TRC1 Transmit Ready Control 1
4691 *
4692 * 07..05 Reserved, must be 0
4693 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4694 */
4695 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4696
4697 /* DMR, DMA Mode Register
4698 *
4699 * 07..05 Reserved, must be 0
4700 * 04 TMOD, Transfer Mode: 1=chained-block
4701 * 03 Reserved, must be 0
4702 * 02 NF, Number of Frames: 1=multi-frame
4703 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4704 * 00 Reserved, must be 0
4705 *
4706 * 0001 0100
4707 */
4708 write_reg(info, TXDMA + DMR, 0x14);
4709 write_reg(info, RXDMA + DMR, 0x14);
4710
4711 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4712 write_reg(info, RXDMA + CPB,
4713 (unsigned char)(info->buffer_list_phys >> 16));
4714
4715 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4716 write_reg(info, TXDMA + CPB,
4717 (unsigned char)(info->buffer_list_phys >> 16));
4718
4719 /* enable status interrupts. other code enables/disables
4720 * the individual sources for these two interrupt classes.
4721 */
4722 info->ie0_value |= TXINTE + RXINTE;
4723 write_reg(info, IE0, info->ie0_value);
4724
4725 /* CTL, MSCI control register
4726 *
4727 * 07..06 Reserved, set to 0
4728 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4729 * 04 IDLC, idle control, 0=mark 1=idle register
4730 * 03 BRK, break, 0=off 1 =on (async)
4731 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4732 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4733 * 00 RTS, RTS output control, 0=active 1=inactive
4734 *
4735 * 0001 0001
4736 */
4737 RegValue = 0x10;
4738 if (!(info->serial_signals & SerialSignal_RTS))
4739 RegValue |= 0x01;
4740 write_reg(info, CTL, RegValue);
4741
4742 /* preamble not supported ! */
4743
4744 tx_set_idle(info);
4745 tx_stop(info);
4746 rx_stop(info);
4747
4748 set_rate(info, info->params.clock_speed);
4749
4750 if (info->params.loopback)
4751 enable_loopback(info,1);
4752 }
4753
4754 /* Set the transmit HDLC idle mode
4755 */
4756 static void tx_set_idle(SLMP_INFO *info)
4757 {
4758 unsigned char RegValue = 0xff;
4759
4760 /* Map API idle mode to SCA register bits */
4761 switch(info->idle_mode) {
4762 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4763 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4764 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4765 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4766 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4767 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4768 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4769 }
4770
4771 write_reg(info, IDL, RegValue);
4772 }
4773
4774 /* Query the adapter for the state of the V24 status (input) signals.
4775 */
4776 static void get_signals(SLMP_INFO *info)
4777 {
4778 u16 status = read_reg(info, SR3);
4779 u16 gpstatus = read_status_reg(info);
4780 u16 testbit;
4781
4782 /* clear all serial signals except DTR and RTS */
4783 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4784
4785 /* set serial signal bits to reflect MISR */
4786
4787 if (!(status & BIT3))
4788 info->serial_signals |= SerialSignal_CTS;
4789
4790 if ( !(status & BIT2))
4791 info->serial_signals |= SerialSignal_DCD;
4792
4793 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4794 if (!(gpstatus & testbit))
4795 info->serial_signals |= SerialSignal_RI;
4796
4797 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4798 if (!(gpstatus & testbit))
4799 info->serial_signals |= SerialSignal_DSR;
4800 }
4801
4802 /* Set the state of DTR and RTS based on contents of
4803 * serial_signals member of device context.
4804 */
4805 static void set_signals(SLMP_INFO *info)
4806 {
4807 unsigned char RegValue;
4808 u16 EnableBit;
4809
4810 RegValue = read_reg(info, CTL);
4811 if (info->serial_signals & SerialSignal_RTS)
4812 RegValue &= ~BIT0;
4813 else
4814 RegValue |= BIT0;
4815 write_reg(info, CTL, RegValue);
4816
4817 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4818 EnableBit = BIT1 << (info->port_num*2);
4819 if (info->serial_signals & SerialSignal_DTR)
4820 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4821 else
4822 info->port_array[0]->ctrlreg_value |= EnableBit;
4823 write_control_reg(info);
4824 }
4825
4826 /*******************/
4827 /* DMA Buffer Code */
4828 /*******************/
4829
4830 /* Set the count for all receive buffers to SCABUFSIZE
4831 * and set the current buffer to the first buffer. This effectively
4832 * makes all buffers free and discards any data in buffers.
4833 */
4834 static void rx_reset_buffers(SLMP_INFO *info)
4835 {
4836 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4837 }
4838
4839 /* Free the buffers used by a received frame
4840 *
4841 * info pointer to device instance data
4842 * first index of 1st receive buffer of frame
4843 * last index of last receive buffer of frame
4844 */
4845 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4846 {
4847 bool done = false;
4848
4849 while(!done) {
4850 /* reset current buffer for reuse */
4851 info->rx_buf_list[first].status = 0xff;
4852
4853 if (first == last) {
4854 done = true;
4855 /* set new last rx descriptor address */
4856 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4857 }
4858
4859 first++;
4860 if (first == info->rx_buf_count)
4861 first = 0;
4862 }
4863
4864 /* set current buffer to next buffer after last buffer of frame */
4865 info->current_rx_buf = first;
4866 }
4867
4868 /* Return a received frame from the receive DMA buffers.
4869 * Only frames received without errors are returned.
4870 *
4871 * Return Value: true if frame returned, otherwise false
4872 */
4873 static bool rx_get_frame(SLMP_INFO *info)
4874 {
4875 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4876 unsigned short status;
4877 unsigned int framesize = 0;
4878 bool ReturnCode = false;
4879 unsigned long flags;
4880 struct tty_struct *tty = info->port.tty;
4881 unsigned char addr_field = 0xff;
4882 SCADESC *desc;
4883 SCADESC_EX *desc_ex;
4884
4885 CheckAgain:
4886 /* assume no frame returned, set zero length */
4887 framesize = 0;
4888 addr_field = 0xff;
4889
4890 /*
4891 * current_rx_buf points to the 1st buffer of the next available
4892 * receive frame. To find the last buffer of the frame look for
4893 * a non-zero status field in the buffer entries. (The status
4894 * field is set by the 16C32 after completing a receive frame.
4895 */
4896 StartIndex = EndIndex = info->current_rx_buf;
4897
4898 for ( ;; ) {
4899 desc = &info->rx_buf_list[EndIndex];
4900 desc_ex = &info->rx_buf_list_ex[EndIndex];
4901
4902 if (desc->status == 0xff)
4903 goto Cleanup; /* current desc still in use, no frames available */
4904
4905 if (framesize == 0 && info->params.addr_filter != 0xff)
4906 addr_field = desc_ex->virt_addr[0];
4907
4908 framesize += desc->length;
4909
4910 /* Status != 0 means last buffer of frame */
4911 if (desc->status)
4912 break;
4913
4914 EndIndex++;
4915 if (EndIndex == info->rx_buf_count)
4916 EndIndex = 0;
4917
4918 if (EndIndex == info->current_rx_buf) {
4919 /* all buffers have been 'used' but none mark */
4920 /* the end of a frame. Reset buffers and receiver. */
4921 if ( info->rx_enabled ){
4922 spin_lock_irqsave(&info->lock,flags);
4923 rx_start(info);
4924 spin_unlock_irqrestore(&info->lock,flags);
4925 }
4926 goto Cleanup;
4927 }
4928
4929 }
4930
4931 /* check status of receive frame */
4932
4933 /* frame status is byte stored after frame data
4934 *
4935 * 7 EOM (end of msg), 1 = last buffer of frame
4936 * 6 Short Frame, 1 = short frame
4937 * 5 Abort, 1 = frame aborted
4938 * 4 Residue, 1 = last byte is partial
4939 * 3 Overrun, 1 = overrun occurred during frame reception
4940 * 2 CRC, 1 = CRC error detected
4941 *
4942 */
4943 status = desc->status;
4944
4945 /* ignore CRC bit if not using CRC (bit is undefined) */
4946 /* Note:CRC is not save to data buffer */
4947 if (info->params.crc_type == HDLC_CRC_NONE)
4948 status &= ~BIT2;
4949
4950 if (framesize == 0 ||
4951 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4952 /* discard 0 byte frames, this seems to occur sometime
4953 * when remote is idling flags.
4954 */
4955 rx_free_frame_buffers(info, StartIndex, EndIndex);
4956 goto CheckAgain;
4957 }
4958
4959 if (framesize < 2)
4960 status |= BIT6;
4961
4962 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4963 /* received frame has errors,
4964 * update counts and mark frame size as 0
4965 */
4966 if (status & BIT6)
4967 info->icount.rxshort++;
4968 else if (status & BIT5)
4969 info->icount.rxabort++;
4970 else if (status & BIT3)
4971 info->icount.rxover++;
4972 else
4973 info->icount.rxcrc++;
4974
4975 framesize = 0;
4976 #if SYNCLINK_GENERIC_HDLC
4977 {
4978 info->netdev->stats.rx_errors++;
4979 info->netdev->stats.rx_frame_errors++;
4980 }
4981 #endif
4982 }
4983
4984 if ( debug_level >= DEBUG_LEVEL_BH )
4985 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4986 __FILE__,__LINE__,info->device_name,status,framesize);
4987
4988 if ( debug_level >= DEBUG_LEVEL_DATA )
4989 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4990 min_t(int, framesize,SCABUFSIZE),0);
4991
4992 if (framesize) {
4993 if (framesize > info->max_frame_size)
4994 info->icount.rxlong++;
4995 else {
4996 /* copy dma buffer(s) to contiguous intermediate buffer */
4997 int copy_count = framesize;
4998 int index = StartIndex;
4999 unsigned char *ptmp = info->tmp_rx_buf;
5000 info->tmp_rx_buf_count = framesize;
5001
5002 info->icount.rxok++;
5003
5004 while(copy_count) {
5005 int partial_count = min(copy_count,SCABUFSIZE);
5006 memcpy( ptmp,
5007 info->rx_buf_list_ex[index].virt_addr,
5008 partial_count );
5009 ptmp += partial_count;
5010 copy_count -= partial_count;
5011
5012 if ( ++index == info->rx_buf_count )
5013 index = 0;
5014 }
5015
5016 #if SYNCLINK_GENERIC_HDLC
5017 if (info->netcount)
5018 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5019 else
5020 #endif
5021 ldisc_receive_buf(tty,info->tmp_rx_buf,
5022 info->flag_buf, framesize);
5023 }
5024 }
5025 /* Free the buffers used by this frame. */
5026 rx_free_frame_buffers( info, StartIndex, EndIndex );
5027
5028 ReturnCode = true;
5029
5030 Cleanup:
5031 if ( info->rx_enabled && info->rx_overflow ) {
5032 /* Receiver is enabled, but needs to restarted due to
5033 * rx buffer overflow. If buffers are empty, restart receiver.
5034 */
5035 if (info->rx_buf_list[EndIndex].status == 0xff) {
5036 spin_lock_irqsave(&info->lock,flags);
5037 rx_start(info);
5038 spin_unlock_irqrestore(&info->lock,flags);
5039 }
5040 }
5041
5042 return ReturnCode;
5043 }
5044
5045 /* load the transmit DMA buffer with data
5046 */
5047 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5048 {
5049 unsigned short copy_count;
5050 unsigned int i = 0;
5051 SCADESC *desc;
5052 SCADESC_EX *desc_ex;
5053
5054 if ( debug_level >= DEBUG_LEVEL_DATA )
5055 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5056
5057 /* Copy source buffer to one or more DMA buffers, starting with
5058 * the first transmit dma buffer.
5059 */
5060 for(i=0;;)
5061 {
5062 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5063
5064 desc = &info->tx_buf_list[i];
5065 desc_ex = &info->tx_buf_list_ex[i];
5066
5067 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5068
5069 desc->length = copy_count;
5070 desc->status = 0;
5071
5072 buf += copy_count;
5073 count -= copy_count;
5074
5075 if (!count)
5076 break;
5077
5078 i++;
5079 if (i >= info->tx_buf_count)
5080 i = 0;
5081 }
5082
5083 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5084 info->last_tx_buf = ++i;
5085 }
5086
5087 static bool register_test(SLMP_INFO *info)
5088 {
5089 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5090 static unsigned int count = ARRAY_SIZE(testval);
5091 unsigned int i;
5092 bool rc = true;
5093 unsigned long flags;
5094
5095 spin_lock_irqsave(&info->lock,flags);
5096 reset_port(info);
5097
5098 /* assume failure */
5099 info->init_error = DiagStatus_AddressFailure;
5100
5101 /* Write bit patterns to various registers but do it out of */
5102 /* sync, then read back and verify values. */
5103
5104 for (i = 0 ; i < count ; i++) {
5105 write_reg(info, TMC, testval[i]);
5106 write_reg(info, IDL, testval[(i+1)%count]);
5107 write_reg(info, SA0, testval[(i+2)%count]);
5108 write_reg(info, SA1, testval[(i+3)%count]);
5109
5110 if ( (read_reg(info, TMC) != testval[i]) ||
5111 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5112 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5113 (read_reg(info, SA1) != testval[(i+3)%count]) )
5114 {
5115 rc = false;
5116 break;
5117 }
5118 }
5119
5120 reset_port(info);
5121 spin_unlock_irqrestore(&info->lock,flags);
5122
5123 return rc;
5124 }
5125
5126 static bool irq_test(SLMP_INFO *info)
5127 {
5128 unsigned long timeout;
5129 unsigned long flags;
5130
5131 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5132
5133 spin_lock_irqsave(&info->lock,flags);
5134 reset_port(info);
5135
5136 /* assume failure */
5137 info->init_error = DiagStatus_IrqFailure;
5138 info->irq_occurred = false;
5139
5140 /* setup timer0 on SCA0 to interrupt */
5141
5142 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5143 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5144
5145 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5146 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5147
5148
5149 /* TMCS, Timer Control/Status Register
5150 *
5151 * 07 CMF, Compare match flag (read only) 1=match
5152 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5153 * 05 Reserved, must be 0
5154 * 04 TME, Timer Enable
5155 * 03..00 Reserved, must be 0
5156 *
5157 * 0101 0000
5158 */
5159 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5160
5161 spin_unlock_irqrestore(&info->lock,flags);
5162
5163 timeout=100;
5164 while( timeout-- && !info->irq_occurred ) {
5165 msleep_interruptible(10);
5166 }
5167
5168 spin_lock_irqsave(&info->lock,flags);
5169 reset_port(info);
5170 spin_unlock_irqrestore(&info->lock,flags);
5171
5172 return info->irq_occurred;
5173 }
5174
5175 /* initialize individual SCA device (2 ports)
5176 */
5177 static bool sca_init(SLMP_INFO *info)
5178 {
5179 /* set wait controller to single mem partition (low), no wait states */
5180 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5181 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5182 write_reg(info, WCRL, 0); /* wait controller low range */
5183 write_reg(info, WCRM, 0); /* wait controller mid range */
5184 write_reg(info, WCRH, 0); /* wait controller high range */
5185
5186 /* DPCR, DMA Priority Control
5187 *
5188 * 07..05 Not used, must be 0
5189 * 04 BRC, bus release condition: 0=all transfers complete
5190 * 03 CCC, channel change condition: 0=every cycle
5191 * 02..00 PR<2..0>, priority 100=round robin
5192 *
5193 * 00000100 = 0x04
5194 */
5195 write_reg(info, DPCR, dma_priority);
5196
5197 /* DMA Master Enable, BIT7: 1=enable all channels */
5198 write_reg(info, DMER, 0x80);
5199
5200 /* enable all interrupt classes */
5201 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5202 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5203 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5204
5205 /* ITCR, interrupt control register
5206 * 07 IPC, interrupt priority, 0=MSCI->DMA
5207 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5208 * 04 VOS, Vector Output, 0=unmodified vector
5209 * 03..00 Reserved, must be 0
5210 */
5211 write_reg(info, ITCR, 0);
5212
5213 return true;
5214 }
5215
5216 /* initialize adapter hardware
5217 */
5218 static bool init_adapter(SLMP_INFO *info)
5219 {
5220 int i;
5221
5222 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5223 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5224 u32 readval;
5225
5226 info->misc_ctrl_value |= BIT30;
5227 *MiscCtrl = info->misc_ctrl_value;
5228
5229 /*
5230 * Force at least 170ns delay before clearing
5231 * reset bit. Each read from LCR takes at least
5232 * 30ns so 10 times for 300ns to be safe.
5233 */
5234 for(i=0;i<10;i++)
5235 readval = *MiscCtrl;
5236
5237 info->misc_ctrl_value &= ~BIT30;
5238 *MiscCtrl = info->misc_ctrl_value;
5239
5240 /* init control reg (all DTRs off, all clksel=input) */
5241 info->ctrlreg_value = 0xaa;
5242 write_control_reg(info);
5243
5244 {
5245 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5246 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5247
5248 switch(read_ahead_count)
5249 {
5250 case 16:
5251 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5252 break;
5253 case 8:
5254 lcr1_brdr_value |= BIT5 + BIT4;
5255 break;
5256 case 4:
5257 lcr1_brdr_value |= BIT5 + BIT3;
5258 break;
5259 case 0:
5260 lcr1_brdr_value |= BIT5;
5261 break;
5262 }
5263
5264 *LCR1BRDR = lcr1_brdr_value;
5265 *MiscCtrl = misc_ctrl_value;
5266 }
5267
5268 sca_init(info->port_array[0]);
5269 sca_init(info->port_array[2]);
5270
5271 return true;
5272 }
5273
5274 /* Loopback an HDLC frame to test the hardware
5275 * interrupt and DMA functions.
5276 */
5277 static bool loopback_test(SLMP_INFO *info)
5278 {
5279 #define TESTFRAMESIZE 20
5280
5281 unsigned long timeout;
5282 u16 count = TESTFRAMESIZE;
5283 unsigned char buf[TESTFRAMESIZE];
5284 bool rc = false;
5285 unsigned long flags;
5286
5287 struct tty_struct *oldtty = info->port.tty;
5288 u32 speed = info->params.clock_speed;
5289
5290 info->params.clock_speed = 3686400;
5291 info->port.tty = NULL;
5292
5293 /* assume failure */
5294 info->init_error = DiagStatus_DmaFailure;
5295
5296 /* build and send transmit frame */
5297 for (count = 0; count < TESTFRAMESIZE;++count)
5298 buf[count] = (unsigned char)count;
5299
5300 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5301
5302 /* program hardware for HDLC and enabled receiver */
5303 spin_lock_irqsave(&info->lock,flags);
5304 hdlc_mode(info);
5305 enable_loopback(info,1);
5306 rx_start(info);
5307 info->tx_count = count;
5308 tx_load_dma_buffer(info,buf,count);
5309 tx_start(info);
5310 spin_unlock_irqrestore(&info->lock,flags);
5311
5312 /* wait for receive complete */
5313 /* Set a timeout for waiting for interrupt. */
5314 for ( timeout = 100; timeout; --timeout ) {
5315 msleep_interruptible(10);
5316
5317 if (rx_get_frame(info)) {
5318 rc = true;
5319 break;
5320 }
5321 }
5322
5323 /* verify received frame length and contents */
5324 if (rc &&
5325 ( info->tmp_rx_buf_count != count ||
5326 memcmp(buf, info->tmp_rx_buf,count))) {
5327 rc = false;
5328 }
5329
5330 spin_lock_irqsave(&info->lock,flags);
5331 reset_adapter(info);
5332 spin_unlock_irqrestore(&info->lock,flags);
5333
5334 info->params.clock_speed = speed;
5335 info->port.tty = oldtty;
5336
5337 return rc;
5338 }
5339
5340 /* Perform diagnostics on hardware
5341 */
5342 static int adapter_test( SLMP_INFO *info )
5343 {
5344 unsigned long flags;
5345 if ( debug_level >= DEBUG_LEVEL_INFO )
5346 printk( "%s(%d):Testing device %s\n",
5347 __FILE__,__LINE__,info->device_name );
5348
5349 spin_lock_irqsave(&info->lock,flags);
5350 init_adapter(info);
5351 spin_unlock_irqrestore(&info->lock,flags);
5352
5353 info->port_array[0]->port_count = 0;
5354
5355 if ( register_test(info->port_array[0]) &&
5356 register_test(info->port_array[1])) {
5357
5358 info->port_array[0]->port_count = 2;
5359
5360 if ( register_test(info->port_array[2]) &&
5361 register_test(info->port_array[3]) )
5362 info->port_array[0]->port_count += 2;
5363 }
5364 else {
5365 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5366 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5367 return -ENODEV;
5368 }
5369
5370 if ( !irq_test(info->port_array[0]) ||
5371 !irq_test(info->port_array[1]) ||
5372 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5373 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5374 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5375 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5376 return -ENODEV;
5377 }
5378
5379 if (!loopback_test(info->port_array[0]) ||
5380 !loopback_test(info->port_array[1]) ||
5381 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5382 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5383 printk( "%s(%d):DMA test failure for device %s\n",
5384 __FILE__,__LINE__,info->device_name);
5385 return -ENODEV;
5386 }
5387
5388 if ( debug_level >= DEBUG_LEVEL_INFO )
5389 printk( "%s(%d):device %s passed diagnostics\n",
5390 __FILE__,__LINE__,info->device_name );
5391
5392 info->port_array[0]->init_error = 0;
5393 info->port_array[1]->init_error = 0;
5394 if ( info->port_count > 2 ) {
5395 info->port_array[2]->init_error = 0;
5396 info->port_array[3]->init_error = 0;
5397 }
5398
5399 return 0;
5400 }
5401
5402 /* Test the shared memory on a PCI adapter.
5403 */
5404 static bool memory_test(SLMP_INFO *info)
5405 {
5406 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5407 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5408 unsigned long count = ARRAY_SIZE(testval);
5409 unsigned long i;
5410 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5411 unsigned long * addr = (unsigned long *)info->memory_base;
5412
5413 /* Test data lines with test pattern at one location. */
5414
5415 for ( i = 0 ; i < count ; i++ ) {
5416 *addr = testval[i];
5417 if ( *addr != testval[i] )
5418 return false;
5419 }
5420
5421 /* Test address lines with incrementing pattern over */
5422 /* entire address range. */
5423
5424 for ( i = 0 ; i < limit ; i++ ) {
5425 *addr = i * 4;
5426 addr++;
5427 }
5428
5429 addr = (unsigned long *)info->memory_base;
5430
5431 for ( i = 0 ; i < limit ; i++ ) {
5432 if ( *addr != i * 4 )
5433 return false;
5434 addr++;
5435 }
5436
5437 memset( info->memory_base, 0, SCA_MEM_SIZE );
5438 return true;
5439 }
5440
5441 /* Load data into PCI adapter shared memory.
5442 *
5443 * The PCI9050 releases control of the local bus
5444 * after completing the current read or write operation.
5445 *
5446 * While the PCI9050 write FIFO not empty, the
5447 * PCI9050 treats all of the writes as a single transaction
5448 * and does not release the bus. This causes DMA latency problems
5449 * at high speeds when copying large data blocks to the shared memory.
5450 *
5451 * This function breaks a write into multiple transations by
5452 * interleaving a read which flushes the write FIFO and 'completes'
5453 * the write transation. This allows any pending DMA request to gain control
5454 * of the local bus in a timely fasion.
5455 */
5456 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5457 {
5458 /* A load interval of 16 allows for 4 32-bit writes at */
5459 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5460
5461 unsigned short interval = count / sca_pci_load_interval;
5462 unsigned short i;
5463
5464 for ( i = 0 ; i < interval ; i++ )
5465 {
5466 memcpy(dest, src, sca_pci_load_interval);
5467 read_status_reg(info);
5468 dest += sca_pci_load_interval;
5469 src += sca_pci_load_interval;
5470 }
5471
5472 memcpy(dest, src, count % sca_pci_load_interval);
5473 }
5474
5475 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5476 {
5477 int i;
5478 int linecount;
5479 if (xmit)
5480 printk("%s tx data:\n",info->device_name);
5481 else
5482 printk("%s rx data:\n",info->device_name);
5483
5484 while(count) {
5485 if (count > 16)
5486 linecount = 16;
5487 else
5488 linecount = count;
5489
5490 for(i=0;i<linecount;i++)
5491 printk("%02X ",(unsigned char)data[i]);
5492 for(;i<17;i++)
5493 printk(" ");
5494 for(i=0;i<linecount;i++) {
5495 if (data[i]>=040 && data[i]<=0176)
5496 printk("%c",data[i]);
5497 else
5498 printk(".");
5499 }
5500 printk("\n");
5501
5502 data += linecount;
5503 count -= linecount;
5504 }
5505 } /* end of trace_block() */
5506
5507 /* called when HDLC frame times out
5508 * update stats and do tx completion processing
5509 */
5510 static void tx_timeout(unsigned long context)
5511 {
5512 SLMP_INFO *info = (SLMP_INFO*)context;
5513 unsigned long flags;
5514
5515 if ( debug_level >= DEBUG_LEVEL_INFO )
5516 printk( "%s(%d):%s tx_timeout()\n",
5517 __FILE__,__LINE__,info->device_name);
5518 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5519 info->icount.txtimeout++;
5520 }
5521 spin_lock_irqsave(&info->lock,flags);
5522 info->tx_active = false;
5523 info->tx_count = info->tx_put = info->tx_get = 0;
5524
5525 spin_unlock_irqrestore(&info->lock,flags);
5526
5527 #if SYNCLINK_GENERIC_HDLC
5528 if (info->netcount)
5529 hdlcdev_tx_done(info);
5530 else
5531 #endif
5532 bh_transmit(info);
5533 }
5534
5535 /* called to periodically check the DSR/RI modem signal input status
5536 */
5537 static void status_timeout(unsigned long context)
5538 {
5539 u16 status = 0;
5540 SLMP_INFO *info = (SLMP_INFO*)context;
5541 unsigned long flags;
5542 unsigned char delta;
5543
5544
5545 spin_lock_irqsave(&info->lock,flags);
5546 get_signals(info);
5547 spin_unlock_irqrestore(&info->lock,flags);
5548
5549 /* check for DSR/RI state change */
5550
5551 delta = info->old_signals ^ info->serial_signals;
5552 info->old_signals = info->serial_signals;
5553
5554 if (delta & SerialSignal_DSR)
5555 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5556
5557 if (delta & SerialSignal_RI)
5558 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5559
5560 if (delta & SerialSignal_DCD)
5561 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5562
5563 if (delta & SerialSignal_CTS)
5564 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5565
5566 if (status)
5567 isr_io_pin(info,status);
5568
5569 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5570 }
5571
5572
5573 /* Register Access Routines -
5574 * All registers are memory mapped
5575 */
5576 #define CALC_REGADDR() \
5577 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5578 if (info->port_num > 1) \
5579 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5580 if ( info->port_num & 1) { \
5581 if (Addr > 0x7f) \
5582 RegAddr += 0x40; /* DMA access */ \
5583 else if (Addr > 0x1f && Addr < 0x60) \
5584 RegAddr += 0x20; /* MSCI access */ \
5585 }
5586
5587
5588 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5589 {
5590 CALC_REGADDR();
5591 return *RegAddr;
5592 }
5593 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5594 {
5595 CALC_REGADDR();
5596 *RegAddr = Value;
5597 }
5598
5599 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5600 {
5601 CALC_REGADDR();
5602 return *((u16 *)RegAddr);
5603 }
5604
5605 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5606 {
5607 CALC_REGADDR();
5608 *((u16 *)RegAddr) = Value;
5609 }
5610
5611 static unsigned char read_status_reg(SLMP_INFO * info)
5612 {
5613 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5614 return *RegAddr;
5615 }
5616
5617 static void write_control_reg(SLMP_INFO * info)
5618 {
5619 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5620 *RegAddr = info->port_array[0]->ctrlreg_value;
5621 }
5622
5623
5624 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5625 const struct pci_device_id *ent)
5626 {
5627 if (pci_enable_device(dev)) {
5628 printk("error enabling pci device %p\n", dev);
5629 return -EIO;
5630 }
5631 device_init( ++synclinkmp_adapter_count, dev );
5632 return 0;
5633 }
5634
5635 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5636 {
5637 }
Support for the Chinese Samsung S3C2440 based development boards