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ARM: OMAP: Remove compiler warning when i2c is not set
[linux-2.6/mini2440.git] / drivers / ata / ahci.c
blob1db93b6190744015e251c5d428b58a762cf3c39a
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54 static void ahci_disable_alpm(struct ata_port *ap);
55
56 enum {
57 AHCI_PCI_BAR = 5,
58 AHCI_MAX_PORTS = 32,
59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
61 AHCI_USE_CLUSTERING = 1,
62 AHCI_MAX_CMDS = 32,
63 AHCI_CMD_SZ = 32,
64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
65 AHCI_RX_FIS_SZ = 256,
66 AHCI_CMD_TBL_CDB = 0x40,
67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
75 AHCI_CMD_PREFETCH = (1 << 7),
76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
82
83 board_ahci = 0,
84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
88 board_ahci_sb700 = 5,
89
90 /* global controller registers */
91 HOST_CAP = 0x00, /* host capabilities */
92 HOST_CTL = 0x04, /* global host control */
93 HOST_IRQ_STAT = 0x08, /* interrupt status */
94 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
95 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
96
97 /* HOST_CTL bits */
98 HOST_RESET = (1 << 0), /* reset controller; self-clear */
99 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
100 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
101
102 /* HOST_CAP bits */
103 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
104 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
105 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
106 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
107 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
108 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
109 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
110 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
111
112 /* registers for each SATA port */
113 PORT_LST_ADDR = 0x00, /* command list DMA addr */
114 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
115 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
116 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
117 PORT_IRQ_STAT = 0x10, /* interrupt status */
118 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
119 PORT_CMD = 0x18, /* port command */
120 PORT_TFDATA = 0x20, /* taskfile data */
121 PORT_SIG = 0x24, /* device TF signature */
122 PORT_CMD_ISSUE = 0x38, /* command issue */
123 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
124 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
125 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
126 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
127 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
128
129 /* PORT_IRQ_{STAT,MASK} bits */
130 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
131 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
132 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
133 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
134 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
135 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
136 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
137 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
138
139 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
140 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
141 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
142 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
143 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
144 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
145 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
146 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
147 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
148
149 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
150 PORT_IRQ_IF_ERR |
151 PORT_IRQ_CONNECT |
152 PORT_IRQ_PHYRDY |
153 PORT_IRQ_UNK_FIS |
154 PORT_IRQ_BAD_PMP,
155 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
156 PORT_IRQ_TF_ERR |
157 PORT_IRQ_HBUS_DATA_ERR,
158 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
159 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
160 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
161
162 /* PORT_CMD bits */
163 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
164 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
165 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
166 PORT_CMD_PMP = (1 << 17), /* PMP attached */
167 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
168 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
169 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
170 PORT_CMD_CLO = (1 << 3), /* Command list override */
171 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
172 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
173 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
174
175 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
176 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
177 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
178 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
179
180 /* hpriv->flags bits */
181 AHCI_HFLAG_NO_NCQ = (1 << 0),
182 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
183 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
184 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
185 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
186 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
187 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
188 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
189
190 /* ap->flags bits */
191
192 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
193 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
194 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
195 ATA_FLAG_IPM,
196 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
197
198 ICH_MAP = 0x90, /* ICH MAP register */
199 };
200
201 struct ahci_cmd_hdr {
202 __le32 opts;
203 __le32 status;
204 __le32 tbl_addr;
205 __le32 tbl_addr_hi;
206 __le32 reserved[4];
207 };
208
209 struct ahci_sg {
210 __le32 addr;
211 __le32 addr_hi;
212 __le32 reserved;
213 __le32 flags_size;
214 };
215
216 struct ahci_host_priv {
217 unsigned int flags; /* AHCI_HFLAG_* */
218 u32 cap; /* cap to use */
219 u32 port_map; /* port map to use */
220 u32 saved_cap; /* saved initial cap */
221 u32 saved_port_map; /* saved initial port_map */
222 };
223
224 struct ahci_port_priv {
225 struct ata_link *active_link;
226 struct ahci_cmd_hdr *cmd_slot;
227 dma_addr_t cmd_slot_dma;
228 void *cmd_tbl;
229 dma_addr_t cmd_tbl_dma;
230 void *rx_fis;
231 dma_addr_t rx_fis_dma;
232 /* for NCQ spurious interrupt analysis */
233 unsigned int ncq_saw_d2h:1;
234 unsigned int ncq_saw_dmas:1;
235 unsigned int ncq_saw_sdb:1;
236 u32 intr_mask; /* interrupts to enable */
237 };
238
239 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
240 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
241 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
242 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
243 static void ahci_irq_clear(struct ata_port *ap);
244 static int ahci_port_start(struct ata_port *ap);
245 static void ahci_port_stop(struct ata_port *ap);
246 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
247 static void ahci_qc_prep(struct ata_queued_cmd *qc);
248 static u8 ahci_check_status(struct ata_port *ap);
249 static void ahci_freeze(struct ata_port *ap);
250 static void ahci_thaw(struct ata_port *ap);
251 static void ahci_pmp_attach(struct ata_port *ap);
252 static void ahci_pmp_detach(struct ata_port *ap);
253 static void ahci_error_handler(struct ata_port *ap);
254 static void ahci_vt8251_error_handler(struct ata_port *ap);
255 static void ahci_p5wdh_error_handler(struct ata_port *ap);
256 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
257 static int ahci_port_resume(struct ata_port *ap);
258 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
259 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
260 u32 opts);
261 #ifdef CONFIG_PM
262 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
263 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
264 static int ahci_pci_device_resume(struct pci_dev *pdev);
265 #endif
266
267 static struct class_device_attribute *ahci_shost_attrs[] = {
268 &class_device_attr_link_power_management_policy,
269 NULL
270 };
271
272 static struct scsi_host_template ahci_sht = {
273 .module = THIS_MODULE,
274 .name = DRV_NAME,
275 .ioctl = ata_scsi_ioctl,
276 .queuecommand = ata_scsi_queuecmd,
277 .change_queue_depth = ata_scsi_change_queue_depth,
278 .can_queue = AHCI_MAX_CMDS - 1,
279 .this_id = ATA_SHT_THIS_ID,
280 .sg_tablesize = AHCI_MAX_SG,
281 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
282 .emulated = ATA_SHT_EMULATED,
283 .use_clustering = AHCI_USE_CLUSTERING,
284 .proc_name = DRV_NAME,
285 .dma_boundary = AHCI_DMA_BOUNDARY,
286 .slave_configure = ata_scsi_slave_config,
287 .slave_destroy = ata_scsi_slave_destroy,
288 .bios_param = ata_std_bios_param,
289 .shost_attrs = ahci_shost_attrs,
290 };
291
292 static const struct ata_port_operations ahci_ops = {
293 .check_status = ahci_check_status,
294 .check_altstatus = ahci_check_status,
295 .dev_select = ata_noop_dev_select,
296
297 .tf_read = ahci_tf_read,
298
299 .qc_defer = sata_pmp_qc_defer_cmd_switch,
300 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue,
302
303 .irq_clear = ahci_irq_clear,
304
305 .scr_read = ahci_scr_read,
306 .scr_write = ahci_scr_write,
307
308 .freeze = ahci_freeze,
309 .thaw = ahci_thaw,
310
311 .error_handler = ahci_error_handler,
312 .post_internal_cmd = ahci_post_internal_cmd,
313
314 .pmp_attach = ahci_pmp_attach,
315 .pmp_detach = ahci_pmp_detach,
316
317 #ifdef CONFIG_PM
318 .port_suspend = ahci_port_suspend,
319 .port_resume = ahci_port_resume,
320 #endif
321 .enable_pm = ahci_enable_alpm,
322 .disable_pm = ahci_disable_alpm,
323
324 .port_start = ahci_port_start,
325 .port_stop = ahci_port_stop,
326 };
327
328 static const struct ata_port_operations ahci_vt8251_ops = {
329 .check_status = ahci_check_status,
330 .check_altstatus = ahci_check_status,
331 .dev_select = ata_noop_dev_select,
332
333 .tf_read = ahci_tf_read,
334
335 .qc_defer = sata_pmp_qc_defer_cmd_switch,
336 .qc_prep = ahci_qc_prep,
337 .qc_issue = ahci_qc_issue,
338
339 .irq_clear = ahci_irq_clear,
340
341 .scr_read = ahci_scr_read,
342 .scr_write = ahci_scr_write,
343
344 .freeze = ahci_freeze,
345 .thaw = ahci_thaw,
346
347 .error_handler = ahci_vt8251_error_handler,
348 .post_internal_cmd = ahci_post_internal_cmd,
349
350 .pmp_attach = ahci_pmp_attach,
351 .pmp_detach = ahci_pmp_detach,
352
353 #ifdef CONFIG_PM
354 .port_suspend = ahci_port_suspend,
355 .port_resume = ahci_port_resume,
356 #endif
357
358 .port_start = ahci_port_start,
359 .port_stop = ahci_port_stop,
360 };
361
362 static const struct ata_port_operations ahci_p5wdh_ops = {
363 .check_status = ahci_check_status,
364 .check_altstatus = ahci_check_status,
365 .dev_select = ata_noop_dev_select,
366
367 .tf_read = ahci_tf_read,
368
369 .qc_defer = sata_pmp_qc_defer_cmd_switch,
370 .qc_prep = ahci_qc_prep,
371 .qc_issue = ahci_qc_issue,
372
373 .irq_clear = ahci_irq_clear,
374
375 .scr_read = ahci_scr_read,
376 .scr_write = ahci_scr_write,
377
378 .freeze = ahci_freeze,
379 .thaw = ahci_thaw,
380
381 .error_handler = ahci_p5wdh_error_handler,
382 .post_internal_cmd = ahci_post_internal_cmd,
383
384 .pmp_attach = ahci_pmp_attach,
385 .pmp_detach = ahci_pmp_detach,
386
387 #ifdef CONFIG_PM
388 .port_suspend = ahci_port_suspend,
389 .port_resume = ahci_port_resume,
390 #endif
391
392 .port_start = ahci_port_start,
393 .port_stop = ahci_port_stop,
394 };
395
396 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
397
398 static const struct ata_port_info ahci_port_info[] = {
399 /* board_ahci */
400 {
401 .flags = AHCI_FLAG_COMMON,
402 .link_flags = AHCI_LFLAG_COMMON,
403 .pio_mask = 0x1f, /* pio0-4 */
404 .udma_mask = ATA_UDMA6,
405 .port_ops = &ahci_ops,
406 },
407 /* board_ahci_vt8251 */
408 {
409 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
410 .flags = AHCI_FLAG_COMMON,
411 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
412 .pio_mask = 0x1f, /* pio0-4 */
413 .udma_mask = ATA_UDMA6,
414 .port_ops = &ahci_vt8251_ops,
415 },
416 /* board_ahci_ign_iferr */
417 {
418 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
419 .flags = AHCI_FLAG_COMMON,
420 .link_flags = AHCI_LFLAG_COMMON,
421 .pio_mask = 0x1f, /* pio0-4 */
422 .udma_mask = ATA_UDMA6,
423 .port_ops = &ahci_ops,
424 },
425 /* board_ahci_sb600 */
426 {
427 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
428 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
429 .flags = AHCI_FLAG_COMMON,
430 .link_flags = AHCI_LFLAG_COMMON,
431 .pio_mask = 0x1f, /* pio0-4 */
432 .udma_mask = ATA_UDMA6,
433 .port_ops = &ahci_ops,
434 },
435 /* board_ahci_mv */
436 {
437 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
438 AHCI_HFLAG_MV_PATA),
439 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
440 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
441 .link_flags = AHCI_LFLAG_COMMON,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .udma_mask = ATA_UDMA6,
444 .port_ops = &ahci_ops,
445 },
446 /* board_ahci_sb700 */
447 {
448 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
449 AHCI_HFLAG_NO_PMP),
450 .flags = AHCI_FLAG_COMMON,
451 .link_flags = AHCI_LFLAG_COMMON,
452 .pio_mask = 0x1f, /* pio0-4 */
453 .udma_mask = ATA_UDMA6,
454 .port_ops = &ahci_ops,
455 },
456 };
457
458 static const struct pci_device_id ahci_pci_tbl[] = {
459 /* Intel */
460 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
461 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
462 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
463 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
464 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
465 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
466 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
468 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
469 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
470 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
472 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
473 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
474 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
475 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
479 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
480 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
484 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
485 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
486 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
487 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
488 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
489 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
490 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
491
492 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
493 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
494 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
495
496 /* ATI */
497 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
498 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
499 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
500 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
504
505 /* VIA */
506 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
507 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
508
509 /* NVIDIA */
510 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
511 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
512 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
520 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
532 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
555 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
556 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
566
567 /* SiS */
568 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
569 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
570 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
571
572 /* Marvell */
573 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
574
575 /* Generic, PCI class code for AHCI */
576 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
577 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
578
579 { } /* terminate list */
580 };
581
582
583 static struct pci_driver ahci_pci_driver = {
584 .name = DRV_NAME,
585 .id_table = ahci_pci_tbl,
586 .probe = ahci_init_one,
587 .remove = ata_pci_remove_one,
588 #ifdef CONFIG_PM
589 .suspend = ahci_pci_device_suspend,
590 .resume = ahci_pci_device_resume,
591 #endif
592 };
593
594
595 static inline int ahci_nr_ports(u32 cap)
596 {
597 return (cap & 0x1f) + 1;
598 }
599
600 static inline void __iomem *__ahci_port_base(struct ata_host *host,
601 unsigned int port_no)
602 {
603 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
604
605 return mmio + 0x100 + (port_no * 0x80);
606 }
607
608 static inline void __iomem *ahci_port_base(struct ata_port *ap)
609 {
610 return __ahci_port_base(ap->host, ap->port_no);
611 }
612
613 static void ahci_enable_ahci(void __iomem *mmio)
614 {
615 u32 tmp;
616
617 /* turn on AHCI_EN */
618 tmp = readl(mmio + HOST_CTL);
619 if (!(tmp & HOST_AHCI_EN)) {
620 tmp |= HOST_AHCI_EN;
621 writel(tmp, mmio + HOST_CTL);
622 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
623 WARN_ON(!(tmp & HOST_AHCI_EN));
624 }
625 }
626
627 /**
628 * ahci_save_initial_config - Save and fixup initial config values
629 * @pdev: target PCI device
630 * @hpriv: host private area to store config values
631 *
632 * Some registers containing configuration info might be setup by
633 * BIOS and might be cleared on reset. This function saves the
634 * initial values of those registers into @hpriv such that they
635 * can be restored after controller reset.
636 *
637 * If inconsistent, config values are fixed up by this function.
638 *
639 * LOCKING:
640 * None.
641 */
642 static void ahci_save_initial_config(struct pci_dev *pdev,
643 struct ahci_host_priv *hpriv)
644 {
645 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
646 u32 cap, port_map;
647 int i;
648
649 /* make sure AHCI mode is enabled before accessing CAP */
650 ahci_enable_ahci(mmio);
651
652 /* Values prefixed with saved_ are written back to host after
653 * reset. Values without are used for driver operation.
654 */
655 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
656 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
657
658 /* some chips have errata preventing 64bit use */
659 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
660 dev_printk(KERN_INFO, &pdev->dev,
661 "controller can't do 64bit DMA, forcing 32bit\n");
662 cap &= ~HOST_CAP_64;
663 }
664
665 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
666 dev_printk(KERN_INFO, &pdev->dev,
667 "controller can't do NCQ, turning off CAP_NCQ\n");
668 cap &= ~HOST_CAP_NCQ;
669 }
670
671 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
672 dev_printk(KERN_INFO, &pdev->dev,
673 "controller can't do PMP, turning off CAP_PMP\n");
674 cap &= ~HOST_CAP_PMP;
675 }
676
677 /*
678 * Temporary Marvell 6145 hack: PATA port presence
679 * is asserted through the standard AHCI port
680 * presence register, as bit 4 (counting from 0)
681 */
682 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
683 dev_printk(KERN_ERR, &pdev->dev,
684 "MV_AHCI HACK: port_map %x -> %x\n",
685 hpriv->port_map,
686 hpriv->port_map & 0xf);
687
688 port_map &= 0xf;
689 }
690
691 /* cross check port_map and cap.n_ports */
692 if (port_map) {
693 int map_ports = 0;
694
695 for (i = 0; i < AHCI_MAX_PORTS; i++)
696 if (port_map & (1 << i))
697 map_ports++;
698
699 /* If PI has more ports than n_ports, whine, clear
700 * port_map and let it be generated from n_ports.
701 */
702 if (map_ports > ahci_nr_ports(cap)) {
703 dev_printk(KERN_WARNING, &pdev->dev,
704 "implemented port map (0x%x) contains more "
705 "ports than nr_ports (%u), using nr_ports\n",
706 port_map, ahci_nr_ports(cap));
707 port_map = 0;
708 }
709 }
710
711 /* fabricate port_map from cap.nr_ports */
712 if (!port_map) {
713 port_map = (1 << ahci_nr_ports(cap)) - 1;
714 dev_printk(KERN_WARNING, &pdev->dev,
715 "forcing PORTS_IMPL to 0x%x\n", port_map);
716
717 /* write the fixed up value to the PI register */
718 hpriv->saved_port_map = port_map;
719 }
720
721 /* record values to use during operation */
722 hpriv->cap = cap;
723 hpriv->port_map = port_map;
724 }
725
726 /**
727 * ahci_restore_initial_config - Restore initial config
728 * @host: target ATA host
729 *
730 * Restore initial config stored by ahci_save_initial_config().
731 *
732 * LOCKING:
733 * None.
734 */
735 static void ahci_restore_initial_config(struct ata_host *host)
736 {
737 struct ahci_host_priv *hpriv = host->private_data;
738 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
739
740 writel(hpriv->saved_cap, mmio + HOST_CAP);
741 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
742 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
743 }
744
745 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
746 {
747 static const int offset[] = {
748 [SCR_STATUS] = PORT_SCR_STAT,
749 [SCR_CONTROL] = PORT_SCR_CTL,
750 [SCR_ERROR] = PORT_SCR_ERR,
751 [SCR_ACTIVE] = PORT_SCR_ACT,
752 [SCR_NOTIFICATION] = PORT_SCR_NTF,
753 };
754 struct ahci_host_priv *hpriv = ap->host->private_data;
755
756 if (sc_reg < ARRAY_SIZE(offset) &&
757 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
758 return offset[sc_reg];
759 return 0;
760 }
761
762 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
763 {
764 void __iomem *port_mmio = ahci_port_base(ap);
765 int offset = ahci_scr_offset(ap, sc_reg);
766
767 if (offset) {
768 *val = readl(port_mmio + offset);
769 return 0;
770 }
771 return -EINVAL;
772 }
773
774 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
775 {
776 void __iomem *port_mmio = ahci_port_base(ap);
777 int offset = ahci_scr_offset(ap, sc_reg);
778
779 if (offset) {
780 writel(val, port_mmio + offset);
781 return 0;
782 }
783 return -EINVAL;
784 }
785
786 static void ahci_start_engine(struct ata_port *ap)
787 {
788 void __iomem *port_mmio = ahci_port_base(ap);
789 u32 tmp;
790
791 /* start DMA */
792 tmp = readl(port_mmio + PORT_CMD);
793 tmp |= PORT_CMD_START;
794 writel(tmp, port_mmio + PORT_CMD);
795 readl(port_mmio + PORT_CMD); /* flush */
796 }
797
798 static int ahci_stop_engine(struct ata_port *ap)
799 {
800 void __iomem *port_mmio = ahci_port_base(ap);
801 u32 tmp;
802
803 tmp = readl(port_mmio + PORT_CMD);
804
805 /* check if the HBA is idle */
806 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
807 return 0;
808
809 /* setting HBA to idle */
810 tmp &= ~PORT_CMD_START;
811 writel(tmp, port_mmio + PORT_CMD);
812
813 /* wait for engine to stop. This could be as long as 500 msec */
814 tmp = ata_wait_register(port_mmio + PORT_CMD,
815 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
816 if (tmp & PORT_CMD_LIST_ON)
817 return -EIO;
818
819 return 0;
820 }
821
822 static void ahci_start_fis_rx(struct ata_port *ap)
823 {
824 void __iomem *port_mmio = ahci_port_base(ap);
825 struct ahci_host_priv *hpriv = ap->host->private_data;
826 struct ahci_port_priv *pp = ap->private_data;
827 u32 tmp;
828
829 /* set FIS registers */
830 if (hpriv->cap & HOST_CAP_64)
831 writel((pp->cmd_slot_dma >> 16) >> 16,
832 port_mmio + PORT_LST_ADDR_HI);
833 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
834
835 if (hpriv->cap & HOST_CAP_64)
836 writel((pp->rx_fis_dma >> 16) >> 16,
837 port_mmio + PORT_FIS_ADDR_HI);
838 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
839
840 /* enable FIS reception */
841 tmp = readl(port_mmio + PORT_CMD);
842 tmp |= PORT_CMD_FIS_RX;
843 writel(tmp, port_mmio + PORT_CMD);
844
845 /* flush */
846 readl(port_mmio + PORT_CMD);
847 }
848
849 static int ahci_stop_fis_rx(struct ata_port *ap)
850 {
851 void __iomem *port_mmio = ahci_port_base(ap);
852 u32 tmp;
853
854 /* disable FIS reception */
855 tmp = readl(port_mmio + PORT_CMD);
856 tmp &= ~PORT_CMD_FIS_RX;
857 writel(tmp, port_mmio + PORT_CMD);
858
859 /* wait for completion, spec says 500ms, give it 1000 */
860 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
861 PORT_CMD_FIS_ON, 10, 1000);
862 if (tmp & PORT_CMD_FIS_ON)
863 return -EBUSY;
864
865 return 0;
866 }
867
868 static void ahci_power_up(struct ata_port *ap)
869 {
870 struct ahci_host_priv *hpriv = ap->host->private_data;
871 void __iomem *port_mmio = ahci_port_base(ap);
872 u32 cmd;
873
874 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
875
876 /* spin up device */
877 if (hpriv->cap & HOST_CAP_SSS) {
878 cmd |= PORT_CMD_SPIN_UP;
879 writel(cmd, port_mmio + PORT_CMD);
880 }
881
882 /* wake up link */
883 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
884 }
885
886 static void ahci_disable_alpm(struct ata_port *ap)
887 {
888 struct ahci_host_priv *hpriv = ap->host->private_data;
889 void __iomem *port_mmio = ahci_port_base(ap);
890 u32 cmd;
891 struct ahci_port_priv *pp = ap->private_data;
892
893 /* IPM bits should be disabled by libata-core */
894 /* get the existing command bits */
895 cmd = readl(port_mmio + PORT_CMD);
896
897 /* disable ALPM and ASP */
898 cmd &= ~PORT_CMD_ASP;
899 cmd &= ~PORT_CMD_ALPE;
900
901 /* force the interface back to active */
902 cmd |= PORT_CMD_ICC_ACTIVE;
903
904 /* write out new cmd value */
905 writel(cmd, port_mmio + PORT_CMD);
906 cmd = readl(port_mmio + PORT_CMD);
907
908 /* wait 10ms to be sure we've come out of any low power state */
909 msleep(10);
910
911 /* clear out any PhyRdy stuff from interrupt status */
912 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
913
914 /* go ahead and clean out PhyRdy Change from Serror too */
915 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
916
917 /*
918 * Clear flag to indicate that we should ignore all PhyRdy
919 * state changes
920 */
921 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
922
923 /*
924 * Enable interrupts on Phy Ready.
925 */
926 pp->intr_mask |= PORT_IRQ_PHYRDY;
927 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
928
929 /*
930 * don't change the link pm policy - we can be called
931 * just to turn of link pm temporarily
932 */
933 }
934
935 static int ahci_enable_alpm(struct ata_port *ap,
936 enum link_pm policy)
937 {
938 struct ahci_host_priv *hpriv = ap->host->private_data;
939 void __iomem *port_mmio = ahci_port_base(ap);
940 u32 cmd;
941 struct ahci_port_priv *pp = ap->private_data;
942 u32 asp;
943
944 /* Make sure the host is capable of link power management */
945 if (!(hpriv->cap & HOST_CAP_ALPM))
946 return -EINVAL;
947
948 switch (policy) {
949 case MAX_PERFORMANCE:
950 case NOT_AVAILABLE:
951 /*
952 * if we came here with NOT_AVAILABLE,
953 * it just means this is the first time we
954 * have tried to enable - default to max performance,
955 * and let the user go to lower power modes on request.
956 */
957 ahci_disable_alpm(ap);
958 return 0;
959 case MIN_POWER:
960 /* configure HBA to enter SLUMBER */
961 asp = PORT_CMD_ASP;
962 break;
963 case MEDIUM_POWER:
964 /* configure HBA to enter PARTIAL */
965 asp = 0;
966 break;
967 default:
968 return -EINVAL;
969 }
970
971 /*
972 * Disable interrupts on Phy Ready. This keeps us from
973 * getting woken up due to spurious phy ready interrupts
974 * TBD - Hot plug should be done via polling now, is
975 * that even supported?
976 */
977 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
978 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
979
980 /*
981 * Set a flag to indicate that we should ignore all PhyRdy
982 * state changes since these can happen now whenever we
983 * change link state
984 */
985 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
986
987 /* get the existing command bits */
988 cmd = readl(port_mmio + PORT_CMD);
989
990 /*
991 * Set ASP based on Policy
992 */
993 cmd |= asp;
994
995 /*
996 * Setting this bit will instruct the HBA to aggressively
997 * enter a lower power link state when it's appropriate and
998 * based on the value set above for ASP
999 */
1000 cmd |= PORT_CMD_ALPE;
1001
1002 /* write out new cmd value */
1003 writel(cmd, port_mmio + PORT_CMD);
1004 cmd = readl(port_mmio + PORT_CMD);
1005
1006 /* IPM bits should be set by libata-core */
1007 return 0;
1008 }
1009
1010 #ifdef CONFIG_PM
1011 static void ahci_power_down(struct ata_port *ap)
1012 {
1013 struct ahci_host_priv *hpriv = ap->host->private_data;
1014 void __iomem *port_mmio = ahci_port_base(ap);
1015 u32 cmd, scontrol;
1016
1017 if (!(hpriv->cap & HOST_CAP_SSS))
1018 return;
1019
1020 /* put device into listen mode, first set PxSCTL.DET to 0 */
1021 scontrol = readl(port_mmio + PORT_SCR_CTL);
1022 scontrol &= ~0xf;
1023 writel(scontrol, port_mmio + PORT_SCR_CTL);
1024
1025 /* then set PxCMD.SUD to 0 */
1026 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1027 cmd &= ~PORT_CMD_SPIN_UP;
1028 writel(cmd, port_mmio + PORT_CMD);
1029 }
1030 #endif
1031
1032 static void ahci_start_port(struct ata_port *ap)
1033 {
1034 /* enable FIS reception */
1035 ahci_start_fis_rx(ap);
1036
1037 /* enable DMA */
1038 ahci_start_engine(ap);
1039 }
1040
1041 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1042 {
1043 int rc;
1044
1045 /* disable DMA */
1046 rc = ahci_stop_engine(ap);
1047 if (rc) {
1048 *emsg = "failed to stop engine";
1049 return rc;
1050 }
1051
1052 /* disable FIS reception */
1053 rc = ahci_stop_fis_rx(ap);
1054 if (rc) {
1055 *emsg = "failed stop FIS RX";
1056 return rc;
1057 }
1058
1059 return 0;
1060 }
1061
1062 static int ahci_reset_controller(struct ata_host *host)
1063 {
1064 struct pci_dev *pdev = to_pci_dev(host->dev);
1065 struct ahci_host_priv *hpriv = host->private_data;
1066 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1067 u32 tmp;
1068
1069 /* we must be in AHCI mode, before using anything
1070 * AHCI-specific, such as HOST_RESET.
1071 */
1072 ahci_enable_ahci(mmio);
1073
1074 /* global controller reset */
1075 tmp = readl(mmio + HOST_CTL);
1076 if ((tmp & HOST_RESET) == 0) {
1077 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1078 readl(mmio + HOST_CTL); /* flush */
1079 }
1080
1081 /* reset must complete within 1 second, or
1082 * the hardware should be considered fried.
1083 */
1084 ssleep(1);
1085
1086 tmp = readl(mmio + HOST_CTL);
1087 if (tmp & HOST_RESET) {
1088 dev_printk(KERN_ERR, host->dev,
1089 "controller reset failed (0x%x)\n", tmp);
1090 return -EIO;
1091 }
1092
1093 /* turn on AHCI mode */
1094 ahci_enable_ahci(mmio);
1095
1096 /* some registers might be cleared on reset. restore initial values */
1097 ahci_restore_initial_config(host);
1098
1099 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1100 u16 tmp16;
1101
1102 /* configure PCS */
1103 pci_read_config_word(pdev, 0x92, &tmp16);
1104 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1105 tmp16 |= hpriv->port_map;
1106 pci_write_config_word(pdev, 0x92, tmp16);
1107 }
1108 }
1109
1110 return 0;
1111 }
1112
1113 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1114 int port_no, void __iomem *mmio,
1115 void __iomem *port_mmio)
1116 {
1117 const char *emsg = NULL;
1118 int rc;
1119 u32 tmp;
1120
1121 /* make sure port is not active */
1122 rc = ahci_deinit_port(ap, &emsg);
1123 if (rc)
1124 dev_printk(KERN_WARNING, &pdev->dev,
1125 "%s (%d)\n", emsg, rc);
1126
1127 /* clear SError */
1128 tmp = readl(port_mmio + PORT_SCR_ERR);
1129 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1130 writel(tmp, port_mmio + PORT_SCR_ERR);
1131
1132 /* clear port IRQ */
1133 tmp = readl(port_mmio + PORT_IRQ_STAT);
1134 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1135 if (tmp)
1136 writel(tmp, port_mmio + PORT_IRQ_STAT);
1137
1138 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1139 }
1140
1141 static void ahci_init_controller(struct ata_host *host)
1142 {
1143 struct ahci_host_priv *hpriv = host->private_data;
1144 struct pci_dev *pdev = to_pci_dev(host->dev);
1145 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1146 int i;
1147 void __iomem *port_mmio;
1148 u32 tmp;
1149
1150 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1151 port_mmio = __ahci_port_base(host, 4);
1152
1153 writel(0, port_mmio + PORT_IRQ_MASK);
1154
1155 /* clear port IRQ */
1156 tmp = readl(port_mmio + PORT_IRQ_STAT);
1157 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1158 if (tmp)
1159 writel(tmp, port_mmio + PORT_IRQ_STAT);
1160 }
1161
1162 for (i = 0; i < host->n_ports; i++) {
1163 struct ata_port *ap = host->ports[i];
1164
1165 port_mmio = ahci_port_base(ap);
1166 if (ata_port_is_dummy(ap))
1167 continue;
1168
1169 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1170 }
1171
1172 tmp = readl(mmio + HOST_CTL);
1173 VPRINTK("HOST_CTL 0x%x\n", tmp);
1174 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1175 tmp = readl(mmio + HOST_CTL);
1176 VPRINTK("HOST_CTL 0x%x\n", tmp);
1177 }
1178
1179 static unsigned int ahci_dev_classify(struct ata_port *ap)
1180 {
1181 void __iomem *port_mmio = ahci_port_base(ap);
1182 struct ata_taskfile tf;
1183 u32 tmp;
1184
1185 tmp = readl(port_mmio + PORT_SIG);
1186 tf.lbah = (tmp >> 24) & 0xff;
1187 tf.lbam = (tmp >> 16) & 0xff;
1188 tf.lbal = (tmp >> 8) & 0xff;
1189 tf.nsect = (tmp) & 0xff;
1190
1191 return ata_dev_classify(&tf);
1192 }
1193
1194 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1195 u32 opts)
1196 {
1197 dma_addr_t cmd_tbl_dma;
1198
1199 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1200
1201 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1202 pp->cmd_slot[tag].status = 0;
1203 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1204 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1205 }
1206
1207 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1208 {
1209 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1210 struct ahci_host_priv *hpriv = ap->host->private_data;
1211 u32 tmp;
1212 int busy, rc;
1213
1214 /* do we need to kick the port? */
1215 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1216 if (!busy && !force_restart)
1217 return 0;
1218
1219 /* stop engine */
1220 rc = ahci_stop_engine(ap);
1221 if (rc)
1222 goto out_restart;
1223
1224 /* need to do CLO? */
1225 if (!busy) {
1226 rc = 0;
1227 goto out_restart;
1228 }
1229
1230 if (!(hpriv->cap & HOST_CAP_CLO)) {
1231 rc = -EOPNOTSUPP;
1232 goto out_restart;
1233 }
1234
1235 /* perform CLO */
1236 tmp = readl(port_mmio + PORT_CMD);
1237 tmp |= PORT_CMD_CLO;
1238 writel(tmp, port_mmio + PORT_CMD);
1239
1240 rc = 0;
1241 tmp = ata_wait_register(port_mmio + PORT_CMD,
1242 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1243 if (tmp & PORT_CMD_CLO)
1244 rc = -EIO;
1245
1246 /* restart engine */
1247 out_restart:
1248 ahci_start_engine(ap);
1249 return rc;
1250 }
1251
1252 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1253 struct ata_taskfile *tf, int is_cmd, u16 flags,
1254 unsigned long timeout_msec)
1255 {
1256 const u32 cmd_fis_len = 5; /* five dwords */
1257 struct ahci_port_priv *pp = ap->private_data;
1258 void __iomem *port_mmio = ahci_port_base(ap);
1259 u8 *fis = pp->cmd_tbl;
1260 u32 tmp;
1261
1262 /* prep the command */
1263 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1264 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1265
1266 /* issue & wait */
1267 writel(1, port_mmio + PORT_CMD_ISSUE);
1268
1269 if (timeout_msec) {
1270 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1271 1, timeout_msec);
1272 if (tmp & 0x1) {
1273 ahci_kick_engine(ap, 1);
1274 return -EBUSY;
1275 }
1276 } else
1277 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1278
1279 return 0;
1280 }
1281
1282 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1283 int pmp, unsigned long deadline)
1284 {
1285 struct ata_port *ap = link->ap;
1286 const char *reason = NULL;
1287 unsigned long now, msecs;
1288 struct ata_taskfile tf;
1289 int rc;
1290
1291 DPRINTK("ENTER\n");
1292
1293 if (ata_link_offline(link)) {
1294 DPRINTK("PHY reports no device\n");
1295 *class = ATA_DEV_NONE;
1296 return 0;
1297 }
1298
1299 /* prepare for SRST (AHCI-1.1 10.4.1) */
1300 rc = ahci_kick_engine(ap, 1);
1301 if (rc && rc != -EOPNOTSUPP)
1302 ata_link_printk(link, KERN_WARNING,
1303 "failed to reset engine (errno=%d)\n", rc);
1304
1305 ata_tf_init(link->device, &tf);
1306
1307 /* issue the first D2H Register FIS */
1308 msecs = 0;
1309 now = jiffies;
1310 if (time_after(now, deadline))
1311 msecs = jiffies_to_msecs(deadline - now);
1312
1313 tf.ctl |= ATA_SRST;
1314 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1315 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1316 rc = -EIO;
1317 reason = "1st FIS failed";
1318 goto fail;
1319 }
1320
1321 /* spec says at least 5us, but be generous and sleep for 1ms */
1322 msleep(1);
1323
1324 /* issue the second D2H Register FIS */
1325 tf.ctl &= ~ATA_SRST;
1326 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1327
1328 /* wait a while before checking status */
1329 ata_wait_after_reset(ap, deadline);
1330
1331 rc = ata_wait_ready(ap, deadline);
1332 /* link occupied, -ENODEV too is an error */
1333 if (rc) {
1334 reason = "device not ready";
1335 goto fail;
1336 }
1337 *class = ahci_dev_classify(ap);
1338
1339 DPRINTK("EXIT, class=%u\n", *class);
1340 return 0;
1341
1342 fail:
1343 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1344 return rc;
1345 }
1346
1347 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1348 unsigned long deadline)
1349 {
1350 int pmp = 0;
1351
1352 if (link->ap->flags & ATA_FLAG_PMP)
1353 pmp = SATA_PMP_CTRL_PORT;
1354
1355 return ahci_do_softreset(link, class, pmp, deadline);
1356 }
1357
1358 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1359 unsigned long deadline)
1360 {
1361 struct ata_port *ap = link->ap;
1362 struct ahci_port_priv *pp = ap->private_data;
1363 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1364 struct ata_taskfile tf;
1365 int rc;
1366
1367 DPRINTK("ENTER\n");
1368
1369 ahci_stop_engine(ap);
1370
1371 /* clear D2H reception area to properly wait for D2H FIS */
1372 ata_tf_init(link->device, &tf);
1373 tf.command = 0x80;
1374 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1375
1376 rc = sata_std_hardreset(link, class, deadline);
1377
1378 ahci_start_engine(ap);
1379
1380 if (rc == 0 && ata_link_online(link))
1381 *class = ahci_dev_classify(ap);
1382 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1383 *class = ATA_DEV_NONE;
1384
1385 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1386 return rc;
1387 }
1388
1389 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1390 unsigned long deadline)
1391 {
1392 struct ata_port *ap = link->ap;
1393 u32 serror;
1394 int rc;
1395
1396 DPRINTK("ENTER\n");
1397
1398 ahci_stop_engine(ap);
1399
1400 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1401 deadline);
1402
1403 /* vt8251 needs SError cleared for the port to operate */
1404 ahci_scr_read(ap, SCR_ERROR, &serror);
1405 ahci_scr_write(ap, SCR_ERROR, serror);
1406
1407 ahci_start_engine(ap);
1408
1409 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1410
1411 /* vt8251 doesn't clear BSY on signature FIS reception,
1412 * request follow-up softreset.
1413 */
1414 return rc ?: -EAGAIN;
1415 }
1416
1417 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1418 unsigned long deadline)
1419 {
1420 struct ata_port *ap = link->ap;
1421 struct ahci_port_priv *pp = ap->private_data;
1422 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1423 struct ata_taskfile tf;
1424 int rc;
1425
1426 ahci_stop_engine(ap);
1427
1428 /* clear D2H reception area to properly wait for D2H FIS */
1429 ata_tf_init(link->device, &tf);
1430 tf.command = 0x80;
1431 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1432
1433 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1434 deadline);
1435
1436 ahci_start_engine(ap);
1437
1438 if (rc || ata_link_offline(link))
1439 return rc;
1440
1441 /* spec mandates ">= 2ms" before checking status */
1442 msleep(150);
1443
1444 /* The pseudo configuration device on SIMG4726 attached to
1445 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1446 * hardreset if no device is attached to the first downstream
1447 * port && the pseudo device locks up on SRST w/ PMP==0. To
1448 * work around this, wait for !BSY only briefly. If BSY isn't
1449 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1450 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1451 *
1452 * Wait for two seconds. Devices attached to downstream port
1453 * which can't process the following IDENTIFY after this will
1454 * have to be reset again. For most cases, this should
1455 * suffice while making probing snappish enough.
1456 */
1457 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1458 if (rc)
1459 ahci_kick_engine(ap, 0);
1460
1461 return 0;
1462 }
1463
1464 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1465 {
1466 struct ata_port *ap = link->ap;
1467 void __iomem *port_mmio = ahci_port_base(ap);
1468 u32 new_tmp, tmp;
1469
1470 ata_std_postreset(link, class);
1471
1472 /* Make sure port's ATAPI bit is set appropriately */
1473 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1474 if (*class == ATA_DEV_ATAPI)
1475 new_tmp |= PORT_CMD_ATAPI;
1476 else
1477 new_tmp &= ~PORT_CMD_ATAPI;
1478 if (new_tmp != tmp) {
1479 writel(new_tmp, port_mmio + PORT_CMD);
1480 readl(port_mmio + PORT_CMD); /* flush */
1481 }
1482 }
1483
1484 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1485 unsigned long deadline)
1486 {
1487 return ahci_do_softreset(link, class, link->pmp, deadline);
1488 }
1489
1490 static u8 ahci_check_status(struct ata_port *ap)
1491 {
1492 void __iomem *mmio = ap->ioaddr.cmd_addr;
1493
1494 return readl(mmio + PORT_TFDATA) & 0xFF;
1495 }
1496
1497 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1498 {
1499 struct ahci_port_priv *pp = ap->private_data;
1500 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1501
1502 ata_tf_from_fis(d2h_fis, tf);
1503 }
1504
1505 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1506 {
1507 struct scatterlist *sg;
1508 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1509 unsigned int si;
1510
1511 VPRINTK("ENTER\n");
1512
1513 /*
1514 * Next, the S/G list.
1515 */
1516 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1517 dma_addr_t addr = sg_dma_address(sg);
1518 u32 sg_len = sg_dma_len(sg);
1519
1520 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1521 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1522 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1523 }
1524
1525 return si;
1526 }
1527
1528 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1529 {
1530 struct ata_port *ap = qc->ap;
1531 struct ahci_port_priv *pp = ap->private_data;
1532 int is_atapi = ata_is_atapi(qc->tf.protocol);
1533 void *cmd_tbl;
1534 u32 opts;
1535 const u32 cmd_fis_len = 5; /* five dwords */
1536 unsigned int n_elem;
1537
1538 /*
1539 * Fill in command table information. First, the header,
1540 * a SATA Register - Host to Device command FIS.
1541 */
1542 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1543
1544 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1545 if (is_atapi) {
1546 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1547 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1548 }
1549
1550 n_elem = 0;
1551 if (qc->flags & ATA_QCFLAG_DMAMAP)
1552 n_elem = ahci_fill_sg(qc, cmd_tbl);
1553
1554 /*
1555 * Fill in command slot information.
1556 */
1557 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1558 if (qc->tf.flags & ATA_TFLAG_WRITE)
1559 opts |= AHCI_CMD_WRITE;
1560 if (is_atapi)
1561 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1562
1563 ahci_fill_cmd_slot(pp, qc->tag, opts);
1564 }
1565
1566 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1567 {
1568 struct ahci_host_priv *hpriv = ap->host->private_data;
1569 struct ahci_port_priv *pp = ap->private_data;
1570 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1571 struct ata_link *link = NULL;
1572 struct ata_queued_cmd *active_qc;
1573 struct ata_eh_info *active_ehi;
1574 u32 serror;
1575
1576 /* determine active link */
1577 ata_port_for_each_link(link, ap)
1578 if (ata_link_active(link))
1579 break;
1580 if (!link)
1581 link = &ap->link;
1582
1583 active_qc = ata_qc_from_tag(ap, link->active_tag);
1584 active_ehi = &link->eh_info;
1585
1586 /* record irq stat */
1587 ata_ehi_clear_desc(host_ehi);
1588 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1589
1590 /* AHCI needs SError cleared; otherwise, it might lock up */
1591 ahci_scr_read(ap, SCR_ERROR, &serror);
1592 ahci_scr_write(ap, SCR_ERROR, serror);
1593 host_ehi->serror |= serror;
1594
1595 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1596 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1597 irq_stat &= ~PORT_IRQ_IF_ERR;
1598
1599 if (irq_stat & PORT_IRQ_TF_ERR) {
1600 /* If qc is active, charge it; otherwise, the active
1601 * link. There's no active qc on NCQ errors. It will
1602 * be determined by EH by reading log page 10h.
1603 */
1604 if (active_qc)
1605 active_qc->err_mask |= AC_ERR_DEV;
1606 else
1607 active_ehi->err_mask |= AC_ERR_DEV;
1608
1609 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1610 host_ehi->serror &= ~SERR_INTERNAL;
1611 }
1612
1613 if (irq_stat & PORT_IRQ_UNK_FIS) {
1614 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1615
1616 active_ehi->err_mask |= AC_ERR_HSM;
1617 active_ehi->action |= ATA_EH_SOFTRESET;
1618 ata_ehi_push_desc(active_ehi,
1619 "unknown FIS %08x %08x %08x %08x" ,
1620 unk[0], unk[1], unk[2], unk[3]);
1621 }
1622
1623 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1624 active_ehi->err_mask |= AC_ERR_HSM;
1625 active_ehi->action |= ATA_EH_SOFTRESET;
1626 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1627 }
1628
1629 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1630 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1631 host_ehi->action |= ATA_EH_SOFTRESET;
1632 ata_ehi_push_desc(host_ehi, "host bus error");
1633 }
1634
1635 if (irq_stat & PORT_IRQ_IF_ERR) {
1636 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1637 host_ehi->action |= ATA_EH_SOFTRESET;
1638 ata_ehi_push_desc(host_ehi, "interface fatal error");
1639 }
1640
1641 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1642 ata_ehi_hotplugged(host_ehi);
1643 ata_ehi_push_desc(host_ehi, "%s",
1644 irq_stat & PORT_IRQ_CONNECT ?
1645 "connection status changed" : "PHY RDY changed");
1646 }
1647
1648 /* okay, let's hand over to EH */
1649
1650 if (irq_stat & PORT_IRQ_FREEZE)
1651 ata_port_freeze(ap);
1652 else
1653 ata_port_abort(ap);
1654 }
1655
1656 static void ahci_port_intr(struct ata_port *ap)
1657 {
1658 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1659 struct ata_eh_info *ehi = &ap->link.eh_info;
1660 struct ahci_port_priv *pp = ap->private_data;
1661 struct ahci_host_priv *hpriv = ap->host->private_data;
1662 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1663 u32 status, qc_active;
1664 int rc;
1665
1666 status = readl(port_mmio + PORT_IRQ_STAT);
1667 writel(status, port_mmio + PORT_IRQ_STAT);
1668
1669 /* ignore BAD_PMP while resetting */
1670 if (unlikely(resetting))
1671 status &= ~PORT_IRQ_BAD_PMP;
1672
1673 /* If we are getting PhyRdy, this is
1674 * just a power state change, we should
1675 * clear out this, plus the PhyRdy/Comm
1676 * Wake bits from Serror
1677 */
1678 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1679 (status & PORT_IRQ_PHYRDY)) {
1680 status &= ~PORT_IRQ_PHYRDY;
1681 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1682 }
1683
1684 if (unlikely(status & PORT_IRQ_ERROR)) {
1685 ahci_error_intr(ap, status);
1686 return;
1687 }
1688
1689 if (status & PORT_IRQ_SDB_FIS) {
1690 /* If SNotification is available, leave notification
1691 * handling to sata_async_notification(). If not,
1692 * emulate it by snooping SDB FIS RX area.
1693 *
1694 * Snooping FIS RX area is probably cheaper than
1695 * poking SNotification but some constrollers which
1696 * implement SNotification, ICH9 for example, don't
1697 * store AN SDB FIS into receive area.
1698 */
1699 if (hpriv->cap & HOST_CAP_SNTF)
1700 sata_async_notification(ap);
1701 else {
1702 /* If the 'N' bit in word 0 of the FIS is set,
1703 * we just received asynchronous notification.
1704 * Tell libata about it.
1705 */
1706 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1707 u32 f0 = le32_to_cpu(f[0]);
1708
1709 if (f0 & (1 << 15))
1710 sata_async_notification(ap);
1711 }
1712 }
1713
1714 /* pp->active_link is valid iff any command is in flight */
1715 if (ap->qc_active && pp->active_link->sactive)
1716 qc_active = readl(port_mmio + PORT_SCR_ACT);
1717 else
1718 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1719
1720 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1721
1722 /* while resetting, invalid completions are expected */
1723 if (unlikely(rc < 0 && !resetting)) {
1724 ehi->err_mask |= AC_ERR_HSM;
1725 ehi->action |= ATA_EH_SOFTRESET;
1726 ata_port_freeze(ap);
1727 }
1728 }
1729
1730 static void ahci_irq_clear(struct ata_port *ap)
1731 {
1732 /* TODO */
1733 }
1734
1735 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1736 {
1737 struct ata_host *host = dev_instance;
1738 struct ahci_host_priv *hpriv;
1739 unsigned int i, handled = 0;
1740 void __iomem *mmio;
1741 u32 irq_stat, irq_ack = 0;
1742
1743 VPRINTK("ENTER\n");
1744
1745 hpriv = host->private_data;
1746 mmio = host->iomap[AHCI_PCI_BAR];
1747
1748 /* sigh. 0xffffffff is a valid return from h/w */
1749 irq_stat = readl(mmio + HOST_IRQ_STAT);
1750 irq_stat &= hpriv->port_map;
1751 if (!irq_stat)
1752 return IRQ_NONE;
1753
1754 spin_lock(&host->lock);
1755
1756 for (i = 0; i < host->n_ports; i++) {
1757 struct ata_port *ap;
1758
1759 if (!(irq_stat & (1 << i)))
1760 continue;
1761
1762 ap = host->ports[i];
1763 if (ap) {
1764 ahci_port_intr(ap);
1765 VPRINTK("port %u\n", i);
1766 } else {
1767 VPRINTK("port %u (no irq)\n", i);
1768 if (ata_ratelimit())
1769 dev_printk(KERN_WARNING, host->dev,
1770 "interrupt on disabled port %u\n", i);
1771 }
1772
1773 irq_ack |= (1 << i);
1774 }
1775
1776 if (irq_ack) {
1777 writel(irq_ack, mmio + HOST_IRQ_STAT);
1778 handled = 1;
1779 }
1780
1781 spin_unlock(&host->lock);
1782
1783 VPRINTK("EXIT\n");
1784
1785 return IRQ_RETVAL(handled);
1786 }
1787
1788 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1789 {
1790 struct ata_port *ap = qc->ap;
1791 void __iomem *port_mmio = ahci_port_base(ap);
1792 struct ahci_port_priv *pp = ap->private_data;
1793
1794 /* Keep track of the currently active link. It will be used
1795 * in completion path to determine whether NCQ phase is in
1796 * progress.
1797 */
1798 pp->active_link = qc->dev->link;
1799
1800 if (qc->tf.protocol == ATA_PROT_NCQ)
1801 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1802 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1803 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1804
1805 return 0;
1806 }
1807
1808 static void ahci_freeze(struct ata_port *ap)
1809 {
1810 void __iomem *port_mmio = ahci_port_base(ap);
1811
1812 /* turn IRQ off */
1813 writel(0, port_mmio + PORT_IRQ_MASK);
1814 }
1815
1816 static void ahci_thaw(struct ata_port *ap)
1817 {
1818 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1819 void __iomem *port_mmio = ahci_port_base(ap);
1820 u32 tmp;
1821 struct ahci_port_priv *pp = ap->private_data;
1822
1823 /* clear IRQ */
1824 tmp = readl(port_mmio + PORT_IRQ_STAT);
1825 writel(tmp, port_mmio + PORT_IRQ_STAT);
1826 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1827
1828 /* turn IRQ back on */
1829 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1830 }
1831
1832 static void ahci_error_handler(struct ata_port *ap)
1833 {
1834 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1835 /* restart engine */
1836 ahci_stop_engine(ap);
1837 ahci_start_engine(ap);
1838 }
1839
1840 /* perform recovery */
1841 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1842 ahci_hardreset, ahci_postreset,
1843 sata_pmp_std_prereset, ahci_pmp_softreset,
1844 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1845 }
1846
1847 static void ahci_vt8251_error_handler(struct ata_port *ap)
1848 {
1849 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1850 /* restart engine */
1851 ahci_stop_engine(ap);
1852 ahci_start_engine(ap);
1853 }
1854
1855 /* perform recovery */
1856 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1857 ahci_postreset);
1858 }
1859
1860 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1861 {
1862 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1863 /* restart engine */
1864 ahci_stop_engine(ap);
1865 ahci_start_engine(ap);
1866 }
1867
1868 /* perform recovery */
1869 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1870 ahci_postreset);
1871 }
1872
1873 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1874 {
1875 struct ata_port *ap = qc->ap;
1876
1877 /* make DMA engine forget about the failed command */
1878 if (qc->flags & ATA_QCFLAG_FAILED)
1879 ahci_kick_engine(ap, 1);
1880 }
1881
1882 static void ahci_pmp_attach(struct ata_port *ap)
1883 {
1884 void __iomem *port_mmio = ahci_port_base(ap);
1885 struct ahci_port_priv *pp = ap->private_data;
1886 u32 cmd;
1887
1888 cmd = readl(port_mmio + PORT_CMD);
1889 cmd |= PORT_CMD_PMP;
1890 writel(cmd, port_mmio + PORT_CMD);
1891
1892 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1893 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1894 }
1895
1896 static void ahci_pmp_detach(struct ata_port *ap)
1897 {
1898 void __iomem *port_mmio = ahci_port_base(ap);
1899 struct ahci_port_priv *pp = ap->private_data;
1900 u32 cmd;
1901
1902 cmd = readl(port_mmio + PORT_CMD);
1903 cmd &= ~PORT_CMD_PMP;
1904 writel(cmd, port_mmio + PORT_CMD);
1905
1906 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1907 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1908 }
1909
1910 static int ahci_port_resume(struct ata_port *ap)
1911 {
1912 ahci_power_up(ap);
1913 ahci_start_port(ap);
1914
1915 if (ap->nr_pmp_links)
1916 ahci_pmp_attach(ap);
1917 else
1918 ahci_pmp_detach(ap);
1919
1920 return 0;
1921 }
1922
1923 #ifdef CONFIG_PM
1924 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1925 {
1926 const char *emsg = NULL;
1927 int rc;
1928
1929 rc = ahci_deinit_port(ap, &emsg);
1930 if (rc == 0)
1931 ahci_power_down(ap);
1932 else {
1933 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1934 ahci_start_port(ap);
1935 }
1936
1937 return rc;
1938 }
1939
1940 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1941 {
1942 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1943 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1944 u32 ctl;
1945
1946 if (mesg.event & PM_EVENT_SLEEP) {
1947 /* AHCI spec rev1.1 section 8.3.3:
1948 * Software must disable interrupts prior to requesting a
1949 * transition of the HBA to D3 state.
1950 */
1951 ctl = readl(mmio + HOST_CTL);
1952 ctl &= ~HOST_IRQ_EN;
1953 writel(ctl, mmio + HOST_CTL);
1954 readl(mmio + HOST_CTL); /* flush */
1955 }
1956
1957 return ata_pci_device_suspend(pdev, mesg);
1958 }
1959
1960 static int ahci_pci_device_resume(struct pci_dev *pdev)
1961 {
1962 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1963 int rc;
1964
1965 rc = ata_pci_device_do_resume(pdev);
1966 if (rc)
1967 return rc;
1968
1969 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1970 rc = ahci_reset_controller(host);
1971 if (rc)
1972 return rc;
1973
1974 ahci_init_controller(host);
1975 }
1976
1977 ata_host_resume(host);
1978
1979 return 0;
1980 }
1981 #endif
1982
1983 static int ahci_port_start(struct ata_port *ap)
1984 {
1985 struct device *dev = ap->host->dev;
1986 struct ahci_port_priv *pp;
1987 void *mem;
1988 dma_addr_t mem_dma;
1989
1990 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1991 if (!pp)
1992 return -ENOMEM;
1993
1994 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1995 GFP_KERNEL);
1996 if (!mem)
1997 return -ENOMEM;
1998 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1999
2000 /*
2001 * First item in chunk of DMA memory: 32-slot command table,
2002 * 32 bytes each in size
2003 */
2004 pp->cmd_slot = mem;
2005 pp->cmd_slot_dma = mem_dma;
2006
2007 mem += AHCI_CMD_SLOT_SZ;
2008 mem_dma += AHCI_CMD_SLOT_SZ;
2009
2010 /*
2011 * Second item: Received-FIS area
2012 */
2013 pp->rx_fis = mem;
2014 pp->rx_fis_dma = mem_dma;
2015
2016 mem += AHCI_RX_FIS_SZ;
2017 mem_dma += AHCI_RX_FIS_SZ;
2018
2019 /*
2020 * Third item: data area for storing a single command
2021 * and its scatter-gather table
2022 */
2023 pp->cmd_tbl = mem;
2024 pp->cmd_tbl_dma = mem_dma;
2025
2026 /*
2027 * Save off initial list of interrupts to be enabled.
2028 * This could be changed later
2029 */
2030 pp->intr_mask = DEF_PORT_IRQ;
2031
2032 ap->private_data = pp;
2033
2034 /* engage engines, captain */
2035 return ahci_port_resume(ap);
2036 }
2037
2038 static void ahci_port_stop(struct ata_port *ap)
2039 {
2040 const char *emsg = NULL;
2041 int rc;
2042
2043 /* de-initialize port */
2044 rc = ahci_deinit_port(ap, &emsg);
2045 if (rc)
2046 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2047 }
2048
2049 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2050 {
2051 int rc;
2052
2053 if (using_dac &&
2054 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2055 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2056 if (rc) {
2057 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2058 if (rc) {
2059 dev_printk(KERN_ERR, &pdev->dev,
2060 "64-bit DMA enable failed\n");
2061 return rc;
2062 }
2063 }
2064 } else {
2065 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2066 if (rc) {
2067 dev_printk(KERN_ERR, &pdev->dev,
2068 "32-bit DMA enable failed\n");
2069 return rc;
2070 }
2071 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2072 if (rc) {
2073 dev_printk(KERN_ERR, &pdev->dev,
2074 "32-bit consistent DMA enable failed\n");
2075 return rc;
2076 }
2077 }
2078 return 0;
2079 }
2080
2081 static void ahci_print_info(struct ata_host *host)
2082 {
2083 struct ahci_host_priv *hpriv = host->private_data;
2084 struct pci_dev *pdev = to_pci_dev(host->dev);
2085 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2086 u32 vers, cap, impl, speed;
2087 const char *speed_s;
2088 u16 cc;
2089 const char *scc_s;
2090
2091 vers = readl(mmio + HOST_VERSION);
2092 cap = hpriv->cap;
2093 impl = hpriv->port_map;
2094
2095 speed = (cap >> 20) & 0xf;
2096 if (speed == 1)
2097 speed_s = "1.5";
2098 else if (speed == 2)
2099 speed_s = "3";
2100 else
2101 speed_s = "?";
2102
2103 pci_read_config_word(pdev, 0x0a, &cc);
2104 if (cc == PCI_CLASS_STORAGE_IDE)
2105 scc_s = "IDE";
2106 else if (cc == PCI_CLASS_STORAGE_SATA)
2107 scc_s = "SATA";
2108 else if (cc == PCI_CLASS_STORAGE_RAID)
2109 scc_s = "RAID";
2110 else
2111 scc_s = "unknown";
2112
2113 dev_printk(KERN_INFO, &pdev->dev,
2114 "AHCI %02x%02x.%02x%02x "
2115 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2116 ,
2117
2118 (vers >> 24) & 0xff,
2119 (vers >> 16) & 0xff,
2120 (vers >> 8) & 0xff,
2121 vers & 0xff,
2122
2123 ((cap >> 8) & 0x1f) + 1,
2124 (cap & 0x1f) + 1,
2125 speed_s,
2126 impl,
2127 scc_s);
2128
2129 dev_printk(KERN_INFO, &pdev->dev,
2130 "flags: "
2131 "%s%s%s%s%s%s%s"
2132 "%s%s%s%s%s%s%s\n"
2133 ,
2134
2135 cap & (1 << 31) ? "64bit " : "",
2136 cap & (1 << 30) ? "ncq " : "",
2137 cap & (1 << 29) ? "sntf " : "",
2138 cap & (1 << 28) ? "ilck " : "",
2139 cap & (1 << 27) ? "stag " : "",
2140 cap & (1 << 26) ? "pm " : "",
2141 cap & (1 << 25) ? "led " : "",
2142
2143 cap & (1 << 24) ? "clo " : "",
2144 cap & (1 << 19) ? "nz " : "",
2145 cap & (1 << 18) ? "only " : "",
2146 cap & (1 << 17) ? "pmp " : "",
2147 cap & (1 << 15) ? "pio " : "",
2148 cap & (1 << 14) ? "slum " : "",
2149 cap & (1 << 13) ? "part " : ""
2150 );
2151 }
2152
2153 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2154 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2155 * support PMP and the 4726 either directly exports the device
2156 * attached to the first downstream port or acts as a hardware storage
2157 * controller and emulate a single ATA device (can be RAID 0/1 or some
2158 * other configuration).
2159 *
2160 * When there's no device attached to the first downstream port of the
2161 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2162 * configure the 4726. However, ATA emulation of the device is very
2163 * lame. It doesn't send signature D2H Reg FIS after the initial
2164 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2165 *
2166 * The following function works around the problem by always using
2167 * hardreset on the port and not depending on receiving signature FIS
2168 * afterward. If signature FIS isn't received soon, ATA class is
2169 * assumed without follow-up softreset.
2170 */
2171 static void ahci_p5wdh_workaround(struct ata_host *host)
2172 {
2173 static struct dmi_system_id sysids[] = {
2174 {
2175 .ident = "P5W DH Deluxe",
2176 .matches = {
2177 DMI_MATCH(DMI_SYS_VENDOR,
2178 "ASUSTEK COMPUTER INC"),
2179 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2180 },
2181 },
2182 { }
2183 };
2184 struct pci_dev *pdev = to_pci_dev(host->dev);
2185
2186 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2187 dmi_check_system(sysids)) {
2188 struct ata_port *ap = host->ports[1];
2189
2190 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2191 "Deluxe on-board SIMG4726 workaround\n");
2192
2193 ap->ops = &ahci_p5wdh_ops;
2194 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2195 }
2196 }
2197
2198 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2199 {
2200 static int printed_version;
2201 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2202 const struct ata_port_info *ppi[] = { &pi, NULL };
2203 struct device *dev = &pdev->dev;
2204 struct ahci_host_priv *hpriv;
2205 struct ata_host *host;
2206 int n_ports, i, rc;
2207
2208 VPRINTK("ENTER\n");
2209
2210 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2211
2212 if (!printed_version++)
2213 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2214
2215 /* acquire resources */
2216 rc = pcim_enable_device(pdev);
2217 if (rc)
2218 return rc;
2219
2220 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2221 if (rc == -EBUSY)
2222 pcim_pin_device(pdev);
2223 if (rc)
2224 return rc;
2225
2226 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2227 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2228 u8 map;
2229
2230 /* ICH6s share the same PCI ID for both piix and ahci
2231 * modes. Enabling ahci mode while MAP indicates
2232 * combined mode is a bad idea. Yield to ata_piix.
2233 */
2234 pci_read_config_byte(pdev, ICH_MAP, &map);
2235 if (map & 0x3) {
2236 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2237 "combined mode, can't enable AHCI mode\n");
2238 return -ENODEV;
2239 }
2240 }
2241
2242 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2243 if (!hpriv)
2244 return -ENOMEM;
2245 hpriv->flags |= (unsigned long)pi.private_data;
2246
2247 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2248 pci_intx(pdev, 1);
2249
2250 /* save initial config */
2251 ahci_save_initial_config(pdev, hpriv);
2252
2253 /* prepare host */
2254 if (hpriv->cap & HOST_CAP_NCQ)
2255 pi.flags |= ATA_FLAG_NCQ;
2256
2257 if (hpriv->cap & HOST_CAP_PMP)
2258 pi.flags |= ATA_FLAG_PMP;
2259
2260 /* CAP.NP sometimes indicate the index of the last enabled
2261 * port, at other times, that of the last possible port, so
2262 * determining the maximum port number requires looking at
2263 * both CAP.NP and port_map.
2264 */
2265 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2266
2267 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2268 if (!host)
2269 return -ENOMEM;
2270 host->iomap = pcim_iomap_table(pdev);
2271 host->private_data = hpriv;
2272
2273 for (i = 0; i < host->n_ports; i++) {
2274 struct ata_port *ap = host->ports[i];
2275 void __iomem *port_mmio = ahci_port_base(ap);
2276
2277 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2278 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2279 0x100 + ap->port_no * 0x80, "port");
2280
2281 /* set initial link pm policy */
2282 ap->pm_policy = NOT_AVAILABLE;
2283
2284 /* standard SATA port setup */
2285 if (hpriv->port_map & (1 << i))
2286 ap->ioaddr.cmd_addr = port_mmio;
2287
2288 /* disabled/not-implemented port */
2289 else
2290 ap->ops = &ata_dummy_port_ops;
2291 }
2292
2293 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2294 ahci_p5wdh_workaround(host);
2295
2296 /* initialize adapter */
2297 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2298 if (rc)
2299 return rc;
2300
2301 rc = ahci_reset_controller(host);
2302 if (rc)
2303 return rc;
2304
2305 ahci_init_controller(host);
2306 ahci_print_info(host);
2307
2308 pci_set_master(pdev);
2309 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2310 &ahci_sht);
2311 }
2312
2313 static int __init ahci_init(void)
2314 {
2315 return pci_register_driver(&ahci_pci_driver);
2316 }
2317
2318 static void __exit ahci_exit(void)
2319 {
2320 pci_unregister_driver(&ahci_pci_driver);
2321 }
2322
2323
2324 MODULE_AUTHOR("Jeff Garzik");
2325 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2326 MODULE_LICENSE("GPL");
2327 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2328 MODULE_VERSION(DRV_VERSION);
2329
2330 module_init(ahci_init);
2331 module_exit(ahci_exit);
Support for the Chinese Samsung S3C2440 based development boards