2 * SGI Visual Workstation support and quirks, unmaintained.
4 * Split out from setup.c by davej@suse.de
6 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
8 * SGI Visual Workstation interrupt controller
10 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
11 * which serves as the main interrupt controller in the system. Non-legacy
12 * hardware in the system uses this controller directly. Legacy devices
13 * are connected to the PIIX4 which in turn has its 8259(s) connected to
14 * a of the Cobalt APIC entry.
16 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
18 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/smp.h>
25 #include <asm/visws/cobalt.h>
26 #include <asm/visws/piix4.h>
27 #include <asm/arch_hooks.h>
28 #include <asm/io_apic.h>
29 #include <asm/fixmap.h>
30 #include <asm/reboot.h>
31 #include <asm/setup.h>
36 #include <linux/kernel_stat.h>
38 #include <asm/i8259.h>
39 #include <asm/irq_vectors.h>
40 #include <asm/visws/lithium.h>
42 #include <linux/sched.h>
43 #include <linux/kernel.h>
44 #include <linux/pci.h>
45 #include <linux/pci_ids.h>
47 extern int no_broadcast
;
49 char visws_board_type
= -1;
50 char visws_board_rev
= -1;
52 int is_visws_box(void)
54 return visws_board_type
>= 0;
57 static int __init
visws_time_init(void)
59 printk(KERN_INFO
"Starting Cobalt Timer system clock\n");
61 /* Set the countdown value */
62 co_cpu_write(CO_CPU_TIMEVAL
, CO_TIME_HZ
/HZ
);
65 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) | CO_CTRL_TIMERUN
);
67 /* Enable (unmask) the timer interrupt */
68 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) & ~CO_CTRL_TIMEMASK
);
71 * Zero return means the generic timer setup code will set up
72 * the standard vector:
77 static int __init
visws_pre_intr_init(void)
79 init_VISWS_APIC_irqs();
82 * We dont want ISA irqs to be set up by the generic code:
87 /* Quirk for machine specific memory setup. */
89 #define MB (1024 * 1024)
91 unsigned long sgivwfb_mem_phys
;
92 unsigned long sgivwfb_mem_size
;
93 EXPORT_SYMBOL(sgivwfb_mem_phys
);
94 EXPORT_SYMBOL(sgivwfb_mem_size
);
96 long long mem_size __initdata
= 0;
98 static char * __init
visws_memory_setup(void)
100 long long gfx_mem_size
= 8 * MB
;
102 mem_size
= boot_params
.alt_mem_k
;
105 printk(KERN_WARNING
"Bootloader didn't set memory size, upgrade it !\n");
110 * this hardcodes the graphics memory to 8 MB
111 * it really should be sized dynamically (or at least
112 * set as a boot param)
114 if (!sgivwfb_mem_size
) {
115 printk(KERN_WARNING
"Defaulting to 8 MB framebuffer size\n");
116 sgivwfb_mem_size
= 8 * MB
;
122 sgivwfb_mem_size
&= ~((1 << 20) - 1);
123 sgivwfb_mem_phys
= mem_size
- gfx_mem_size
;
125 e820_add_region(0, LOWMEMSIZE(), E820_RAM
);
126 e820_add_region(HIGH_MEMORY
, mem_size
- sgivwfb_mem_size
- HIGH_MEMORY
, E820_RAM
);
127 e820_add_region(sgivwfb_mem_phys
, sgivwfb_mem_size
, E820_RESERVED
);
132 static void visws_machine_emergency_restart(void)
135 * Visual Workstations restart after this
136 * register is poked on the PIIX4
138 outb(PIIX4_RESET_VAL
, PIIX4_RESET_PORT
);
141 static void visws_machine_power_off(void)
143 unsigned short pm_status
;
144 /* extern unsigned int pci_bus0; */
146 while ((pm_status
= inw(PMSTS_PORT
)) & 0x100)
147 outw(pm_status
, PMSTS_PORT
);
149 outw(PM_SUSPEND_ENABLE
, PMCNTRL_PORT
);
153 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
154 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
156 /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
157 outl(PIIX_SPECIAL_STOP
, 0xCFC);
160 static int __init
visws_get_smp_config(unsigned int early
)
163 * Prevent MP-table parsing by the generic code:
169 * The Visual Workstation is Intel MP compliant in the hardware
170 * sense, but it doesn't have a BIOS(-configuration table).
171 * No problem for Linux.
174 static void __init
MP_processor_info(struct mpc_cpu
*m
)
176 int ver
, logical_apicid
;
177 physid_mask_t apic_cpus
;
179 if (!(m
->cpuflag
& CPU_ENABLED
))
182 logical_apicid
= m
->apicid
;
183 printk(KERN_INFO
"%sCPU #%d %u:%u APIC version %d\n",
184 m
->cpuflag
& CPU_BOOTPROCESSOR
? "Bootup " : "",
185 m
->apicid
, (m
->cpufeature
& CPU_FAMILY_MASK
) >> 8,
186 (m
->cpufeature
& CPU_MODEL_MASK
) >> 4, m
->apicver
);
188 if (m
->cpuflag
& CPU_BOOTPROCESSOR
)
189 boot_cpu_physical_apicid
= m
->apicid
;
192 if ((ver
>= 0x14 && m
->apicid
>= 0xff) || m
->apicid
>= 0xf) {
193 printk(KERN_ERR
"Processor #%d INVALID. (Max ID: %d).\n",
194 m
->apicid
, MAX_APICS
);
198 apic_cpus
= apic
->apicid_to_cpu_present(m
->apicid
);
199 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, apic_cpus
);
204 printk(KERN_ERR
"BIOS bug, APIC version is 0 for CPU#%d! "
205 "fixing up to 0x10. (tell your hw vendor)\n",
209 apic_version
[m
->apicid
] = ver
;
212 static int __init
visws_find_smp_config(unsigned int reserve
)
214 struct mpc_cpu
*mp
= phys_to_virt(CO_CPU_TAB_PHYS
);
215 unsigned short ncpus
= readw(phys_to_virt(CO_CPU_NUM_PHYS
));
217 if (ncpus
> CO_CPU_MAX
) {
218 printk(KERN_WARNING
"find_visws_smp: got cpu count of %d at %p\n",
224 if (ncpus
> setup_max_cpus
)
225 ncpus
= setup_max_cpus
;
227 #ifdef CONFIG_X86_LOCAL_APIC
228 smp_found_config
= 1;
231 MP_processor_info(mp
++);
233 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
238 static int visws_trap_init(void);
240 static struct x86_quirks visws_x86_quirks __initdata
= {
241 .arch_time_init
= visws_time_init
,
242 .arch_pre_intr_init
= visws_pre_intr_init
,
243 .arch_memory_setup
= visws_memory_setup
,
244 .arch_intr_init
= NULL
,
245 .arch_trap_init
= visws_trap_init
,
246 .mach_get_smp_config
= visws_get_smp_config
,
247 .mach_find_smp_config
= visws_find_smp_config
,
250 void __init
visws_early_detect(void)
254 visws_board_type
= (char)(inb_p(PIIX_GPI_BD_REG
) & PIIX_GPI_BD_REG
)
255 >> PIIX_GPI_BD_SHIFT
;
257 if (visws_board_type
< 0)
261 * Install special quirks for timer, interrupt and memory setup:
262 * Fall back to generic behavior for traps:
263 * Override generic MP-table parsing:
265 x86_quirks
= &visws_x86_quirks
;
268 * Install reboot quirks:
270 pm_power_off
= visws_machine_power_off
;
271 machine_ops
.emergency_restart
= visws_machine_emergency_restart
;
274 * Do not use broadcast IPIs:
278 #ifdef CONFIG_X86_IO_APIC
280 * Turn off IO-APIC detection and initialization:
282 skip_ioapic_setup
= 1;
287 * First, we have to initialize the 307 part to allow us access
288 * to the GPIO registers. Let's map them at 0x0fc0 which is right
289 * after the PIIX4 PM section.
291 outb_p(SIO_DEV_SEL
, SIO_INDEX
);
292 outb_p(SIO_GP_DEV
, SIO_DATA
); /* Talk to GPIO regs. */
294 outb_p(SIO_DEV_MSB
, SIO_INDEX
);
295 outb_p(SIO_GP_MSB
, SIO_DATA
); /* MSB of GPIO base address */
297 outb_p(SIO_DEV_LSB
, SIO_INDEX
);
298 outb_p(SIO_GP_LSB
, SIO_DATA
); /* LSB of GPIO base address */
300 outb_p(SIO_DEV_ENB
, SIO_INDEX
);
301 outb_p(1, SIO_DATA
); /* Enable GPIO registers. */
304 * Now, we have to map the power management section to write
305 * a bit which enables access to the GPIO registers.
306 * What lunatic came up with this shit?
308 outb_p(SIO_DEV_SEL
, SIO_INDEX
);
309 outb_p(SIO_PM_DEV
, SIO_DATA
); /* Talk to GPIO regs. */
311 outb_p(SIO_DEV_MSB
, SIO_INDEX
);
312 outb_p(SIO_PM_MSB
, SIO_DATA
); /* MSB of PM base address */
314 outb_p(SIO_DEV_LSB
, SIO_INDEX
);
315 outb_p(SIO_PM_LSB
, SIO_DATA
); /* LSB of PM base address */
317 outb_p(SIO_DEV_ENB
, SIO_INDEX
);
318 outb_p(1, SIO_DATA
); /* Enable PM registers. */
321 * Now, write the PM register which enables the GPIO registers.
323 outb_p(SIO_PM_FER2
, SIO_PM_INDEX
);
324 outb_p(SIO_PM_GP_EN
, SIO_PM_DATA
);
327 * Now, initialize the GPIO registers.
328 * We want them all to be inputs which is the
329 * power on default, so let's leave them alone.
330 * So, let's just read the board rev!
332 raw
= inb_p(SIO_GP_DATA1
);
333 raw
&= 0x7f; /* 7 bits of valid board revision ID. */
335 if (visws_board_type
== VISWS_320
) {
338 } else if (raw
< 0xc) {
343 } else if (visws_board_type
== VISWS_540
) {
346 visws_board_rev
= raw
;
349 printk(KERN_INFO
"Silicon Graphics Visual Workstation %s (rev %d) detected\n",
350 (visws_board_type
== VISWS_320
? "320" :
351 (visws_board_type
== VISWS_540
? "540" :
352 "unknown")), visws_board_rev
);
355 #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
356 #define BCD (LI_INTB | LI_INTC | LI_INTD)
357 #define ALLDEVS (A01234 | BCD)
359 static __init
void lithium_init(void)
361 set_fixmap(FIX_LI_PCIA
, LI_PCI_A_PHYS
);
362 set_fixmap(FIX_LI_PCIB
, LI_PCI_B_PHYS
);
364 if ((li_pcia_read16(PCI_VENDOR_ID
) != PCI_VENDOR_ID_SGI
) ||
365 (li_pcia_read16(PCI_DEVICE_ID
) != PCI_DEVICE_ID_SGI_LITHIUM
)) {
366 printk(KERN_EMERG
"Lithium hostbridge %c not found\n", 'A');
367 /* panic("This machine is not SGI Visual Workstation 320/540"); */
370 if ((li_pcib_read16(PCI_VENDOR_ID
) != PCI_VENDOR_ID_SGI
) ||
371 (li_pcib_read16(PCI_DEVICE_ID
) != PCI_DEVICE_ID_SGI_LITHIUM
)) {
372 printk(KERN_EMERG
"Lithium hostbridge %c not found\n", 'B');
373 /* panic("This machine is not SGI Visual Workstation 320/540"); */
376 li_pcia_write16(LI_PCI_INTEN
, ALLDEVS
);
377 li_pcib_write16(LI_PCI_INTEN
, ALLDEVS
);
380 static __init
void cobalt_init(void)
383 * On normal SMP PC this is used only with SMP, but we have to
384 * use it and set it up here to start the Cobalt clock
386 set_fixmap(FIX_APIC_BASE
, APIC_DEFAULT_PHYS_BASE
);
388 printk(KERN_INFO
"Local APIC Version %#x, ID %#x\n",
389 (unsigned int)apic_read(APIC_LVR
),
390 (unsigned int)apic_read(APIC_ID
));
392 set_fixmap(FIX_CO_CPU
, CO_CPU_PHYS
);
393 set_fixmap(FIX_CO_APIC
, CO_APIC_PHYS
);
394 printk(KERN_INFO
"Cobalt Revision %#lx, APIC ID %#lx\n",
395 co_cpu_read(CO_CPU_REV
), co_apic_read(CO_APIC_ID
));
397 /* Enable Cobalt APIC being careful to NOT change the ID! */
398 co_apic_write(CO_APIC_ID
, co_apic_read(CO_APIC_ID
) | CO_APIC_ENABLE
);
400 printk(KERN_INFO
"Cobalt APIC enabled: ID reg %#lx\n",
401 co_apic_read(CO_APIC_ID
));
404 static int __init
visws_trap_init(void)
413 * IRQ controller / APIC support:
416 static DEFINE_SPINLOCK(cobalt_lock
);
419 * Set the given Cobalt APIC Redirection Table entry to point
420 * to the given IDT vector/index.
422 static inline void co_apic_set(int entry
, int irq
)
424 co_apic_write(CO_APIC_LO(entry
), CO_APIC_LEVEL
| (irq
+ FIRST_EXTERNAL_VECTOR
));
425 co_apic_write(CO_APIC_HI(entry
), 0);
429 * Cobalt (IO)-APIC functions to handle PCI devices.
431 static inline int co_apic_ide0_hack(void)
433 extern char visws_board_type
;
434 extern char visws_board_rev
;
436 if (visws_board_type
== VISWS_320
&& visws_board_rev
== 5)
441 static int is_co_apic(unsigned int irq
)
447 case 0: return CO_APIC_CPU
;
448 case CO_IRQ_IDE0
: return co_apic_ide0_hack();
449 case CO_IRQ_IDE1
: return CO_APIC_IDE1
;
456 * This is the SGI Cobalt (IO-)APIC:
459 static void enable_cobalt_irq(unsigned int irq
)
461 co_apic_set(is_co_apic(irq
), irq
);
464 static void disable_cobalt_irq(unsigned int irq
)
466 int entry
= is_co_apic(irq
);
468 co_apic_write(CO_APIC_LO(entry
), CO_APIC_MASK
);
469 co_apic_read(CO_APIC_LO(entry
));
473 * "irq" really just serves to identify the device. Here is where we
474 * map this to the Cobalt APIC entry where it's physically wired.
475 * This is called via request_irq -> setup_irq -> irq_desc->startup()
477 static unsigned int startup_cobalt_irq(unsigned int irq
)
480 struct irq_desc
*desc
= irq_to_desc(irq
);
482 spin_lock_irqsave(&cobalt_lock
, flags
);
483 if ((desc
->status
& (IRQ_DISABLED
| IRQ_INPROGRESS
| IRQ_WAITING
)))
484 desc
->status
&= ~(IRQ_DISABLED
| IRQ_INPROGRESS
| IRQ_WAITING
);
485 enable_cobalt_irq(irq
);
486 spin_unlock_irqrestore(&cobalt_lock
, flags
);
490 static void ack_cobalt_irq(unsigned int irq
)
494 spin_lock_irqsave(&cobalt_lock
, flags
);
495 disable_cobalt_irq(irq
);
496 apic_write(APIC_EOI
, APIC_EIO_ACK
);
497 spin_unlock_irqrestore(&cobalt_lock
, flags
);
500 static void end_cobalt_irq(unsigned int irq
)
503 struct irq_desc
*desc
= irq_to_desc(irq
);
505 spin_lock_irqsave(&cobalt_lock
, flags
);
506 if (!(desc
->status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
507 enable_cobalt_irq(irq
);
508 spin_unlock_irqrestore(&cobalt_lock
, flags
);
511 static struct irq_chip cobalt_irq_type
= {
512 .typename
= "Cobalt-APIC",
513 .startup
= startup_cobalt_irq
,
514 .shutdown
= disable_cobalt_irq
,
515 .enable
= enable_cobalt_irq
,
516 .disable
= disable_cobalt_irq
,
517 .ack
= ack_cobalt_irq
,
518 .end
= end_cobalt_irq
,
523 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
524 * -- not the manner expected by the code in i8259.c.
526 * there is a 'master' physical interrupt source that gets sent to
527 * the CPU. But in the chipset there are various 'virtual' interrupts
528 * waiting to be handled. We represent this to Linux through a 'master'
529 * interrupt controller type, and through a special virtual interrupt-
530 * controller. Device drivers only see the virtual interrupt sources.
532 static unsigned int startup_piix4_master_irq(unsigned int irq
)
536 return startup_cobalt_irq(irq
);
539 static void end_piix4_master_irq(unsigned int irq
)
543 spin_lock_irqsave(&cobalt_lock
, flags
);
544 enable_cobalt_irq(irq
);
545 spin_unlock_irqrestore(&cobalt_lock
, flags
);
548 static struct irq_chip piix4_master_irq_type
= {
549 .typename
= "PIIX4-master",
550 .startup
= startup_piix4_master_irq
,
551 .ack
= ack_cobalt_irq
,
552 .end
= end_piix4_master_irq
,
556 static struct irq_chip piix4_virtual_irq_type
= {
557 .typename
= "PIIX4-virtual",
558 .shutdown
= disable_8259A_irq
,
559 .enable
= enable_8259A_irq
,
560 .disable
= disable_8259A_irq
,
565 * PIIX4-8259 master/virtual functions to handle interrupt requests
566 * from legacy devices: floppy, parallel, serial, rtc.
568 * None of these get Cobalt APIC entries, neither do they have IDT
569 * entries. These interrupts are purely virtual and distributed from
570 * the 'master' interrupt source: CO_IRQ_8259.
572 * When the 8259 interrupts its handler figures out which of these
573 * devices is interrupting and dispatches to its handler.
575 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
576 * enable_irq gets the right irq. This 'master' irq is never directly
577 * manipulated by any driver.
579 static irqreturn_t
piix4_master_intr(int irq
, void *dev_id
)
585 spin_lock_irqsave(&i8259A_lock
, flags
);
587 /* Find out what's interrupting in the PIIX4 master 8259 */
588 outb(0x0c, 0x20); /* OCW3 Poll command */
592 * Bit 7 == 0 means invalid/spurious
594 if (unlikely(!(realirq
& 0x80)))
599 if (unlikely(realirq
== 2)) {
603 if (unlikely(!(realirq
& 0x80)))
606 realirq
= (realirq
& 7) + 8;
609 /* mask and ack interrupt */
610 cached_irq_mask
|= 1 << realirq
;
611 if (unlikely(realirq
> 7)) {
613 outb(cached_slave_mask
, 0xa1);
614 outb(0x60 + (realirq
& 7), 0xa0);
615 outb(0x60 + 2, 0x20);
618 outb(cached_master_mask
, 0x21);
619 outb(0x60 + realirq
, 0x20);
622 spin_unlock_irqrestore(&i8259A_lock
, flags
);
624 desc
= irq_to_desc(realirq
);
627 * handle this 'virtual interrupt' as a Cobalt one now.
629 kstat_incr_irqs_this_cpu(realirq
, desc
);
631 if (likely(desc
->action
!= NULL
))
632 handle_IRQ_event(realirq
, desc
->action
);
634 if (!(desc
->status
& IRQ_DISABLED
))
635 enable_8259A_irq(realirq
);
640 spin_unlock_irqrestore(&i8259A_lock
, flags
);
644 static struct irqaction master_action
= {
645 .handler
= piix4_master_intr
,
646 .name
= "PIIX4-8259",
649 static struct irqaction cascade_action
= {
650 .handler
= no_action
,
655 void init_VISWS_APIC_irqs(void)
659 for (i
= 0; i
< CO_IRQ_APIC0
+ CO_APIC_LAST
+ 1; i
++) {
660 struct irq_desc
*desc
= irq_to_desc(i
);
662 desc
->status
= IRQ_DISABLED
;
667 desc
->chip
= &cobalt_irq_type
;
669 else if (i
== CO_IRQ_IDE0
) {
670 desc
->chip
= &cobalt_irq_type
;
672 else if (i
== CO_IRQ_IDE1
) {
673 desc
->chip
= &cobalt_irq_type
;
675 else if (i
== CO_IRQ_8259
) {
676 desc
->chip
= &piix4_master_irq_type
;
678 else if (i
< CO_IRQ_APIC0
) {
679 desc
->chip
= &piix4_virtual_irq_type
;
681 else if (IS_CO_APIC(i
)) {
682 desc
->chip
= &cobalt_irq_type
;
686 setup_irq(CO_IRQ_8259
, &master_action
);
687 setup_irq(2, &cascade_action
);