2 * at91-ssc.c -- ALSA SoC AT91 SSC Audio Layer Platform driver
4 * Author: Frank Mandarino <fmandarino@endrelia.com>
5 * Endrelia Technologies Inc.
7 * Based on pxa2xx Platform drivers by
8 * Liam Girdwood <liam.girdwood@wolfsonmicro.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/atmel_pdc.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
31 #include <mach/hardware.h>
32 #include <mach/at91_pmc.h>
33 #include <mach/at91_ssc.h>
39 #define DBG(x...) printk(KERN_DEBUG "at91-ssc:" x)
44 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
45 #define NUM_SSC_DEVICES 1
47 #define NUM_SSC_DEVICES 3
52 * SSC PDC registers required by the PCM DMA engine.
54 static struct at91_pdc_regs pdc_tx_reg
= {
57 .xnpr
= ATMEL_PDC_TNPR
,
58 .xncr
= ATMEL_PDC_TNCR
,
61 static struct at91_pdc_regs pdc_rx_reg
= {
64 .xnpr
= ATMEL_PDC_RNPR
,
65 .xncr
= ATMEL_PDC_RNCR
,
69 * SSC & PDC status bits for transmit and receive.
71 static struct at91_ssc_mask ssc_tx_mask
= {
72 .ssc_enable
= AT91_SSC_TXEN
,
73 .ssc_disable
= AT91_SSC_TXDIS
,
74 .ssc_endx
= AT91_SSC_ENDTX
,
75 .ssc_endbuf
= AT91_SSC_TXBUFE
,
76 .pdc_enable
= ATMEL_PDC_TXTEN
,
77 .pdc_disable
= ATMEL_PDC_TXTDIS
,
80 static struct at91_ssc_mask ssc_rx_mask
= {
81 .ssc_enable
= AT91_SSC_RXEN
,
82 .ssc_disable
= AT91_SSC_RXDIS
,
83 .ssc_endx
= AT91_SSC_ENDRX
,
84 .ssc_endbuf
= AT91_SSC_RXBUFF
,
85 .pdc_enable
= ATMEL_PDC_RXTEN
,
86 .pdc_disable
= ATMEL_PDC_RXTDIS
,
93 static struct at91_pcm_dma_params ssc_dma_params
[NUM_SSC_DEVICES
][2] = {
95 .name
= "SSC0 PCM out",
100 .name
= "SSC0 PCM in",
102 .mask
= &ssc_rx_mask
,
104 #if NUM_SSC_DEVICES == 3
106 .name
= "SSC1 PCM out",
108 .mask
= &ssc_tx_mask
,
111 .name
= "SSC1 PCM in",
113 .mask
= &ssc_rx_mask
,
116 .name
= "SSC2 PCM out",
118 .mask
= &ssc_tx_mask
,
121 .name
= "SSC2 PCM in",
123 .mask
= &ssc_rx_mask
,
128 struct at91_ssc_state
{
138 static struct at91_ssc_info
{
140 struct at91_ssc_periph ssc
;
141 spinlock_t lock
; /* lock for dir_mask */
142 unsigned short dir_mask
; /* 0=unused, 1=playback, 2=capture */
143 unsigned short initialized
; /* 1=SSC has been initialized */
144 unsigned short daifmt
;
145 unsigned short cmr_div
;
146 unsigned short tcmr_period
;
147 unsigned short rcmr_period
;
148 struct at91_pcm_dma_params
*dma_params
[2];
149 struct at91_ssc_state ssc_state
;
151 } ssc_info
[NUM_SSC_DEVICES
] = {
154 .lock
= __SPIN_LOCK_UNLOCKED(ssc_info
[0].lock
),
158 #if NUM_SSC_DEVICES == 3
161 .lock
= __SPIN_LOCK_UNLOCKED(ssc_info
[1].lock
),
167 .lock
= __SPIN_LOCK_UNLOCKED(ssc_info
[2].lock
),
174 static unsigned int at91_ssc_sysclk
;
177 * SSC interrupt handler. Passes PDC interrupts to the DMA
178 * interrupt handler in the PCM driver.
180 static irqreturn_t
at91_ssc_interrupt(int irq
, void *dev_id
)
182 struct at91_ssc_info
*ssc_p
= dev_id
;
183 struct at91_pcm_dma_params
*dma_params
;
187 ssc_sr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_SR
)
188 & at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_IMR
);
191 * Loop through the substreams attached to this SSC. If
192 * a DMA-related interrupt occurred on that substream, call
193 * the DMA interrupt handler function, if one has been
194 * registered in the dma_params structure by the PCM driver.
196 for (i
= 0; i
< ARRAY_SIZE(ssc_p
->dma_params
); i
++) {
197 dma_params
= ssc_p
->dma_params
[i
];
199 if (dma_params
!= NULL
&& dma_params
->dma_intr_handler
!= NULL
&&
201 (dma_params
->mask
->ssc_endx
| dma_params
->mask
->ssc_endbuf
)))
203 dma_params
->dma_intr_handler(ssc_sr
, dma_params
->substream
);
210 * Startup. Only that one substream allowed in each direction.
212 static int at91_ssc_startup(struct snd_pcm_substream
*substream
)
214 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
215 struct at91_ssc_info
*ssc_p
= &ssc_info
[rtd
->dai
->cpu_dai
->id
];
218 DBG("ssc_startup: SSC_SR=0x%08lx\n",
219 at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_SR
));
220 dir_mask
= substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
? 0x1 : 0x2;
222 spin_lock_irq(&ssc_p
->lock
);
223 if (ssc_p
->dir_mask
& dir_mask
) {
224 spin_unlock_irq(&ssc_p
->lock
);
227 ssc_p
->dir_mask
|= dir_mask
;
228 spin_unlock_irq(&ssc_p
->lock
);
234 * Shutdown. Clear DMA parameters and shutdown the SSC if there
235 * are no other substreams open.
237 static void at91_ssc_shutdown(struct snd_pcm_substream
*substream
)
239 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
240 struct at91_ssc_info
*ssc_p
= &ssc_info
[rtd
->dai
->cpu_dai
->id
];
241 struct at91_pcm_dma_params
*dma_params
;
244 dir
= substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
? 0 : 1;
245 dma_params
= ssc_p
->dma_params
[dir
];
247 if (dma_params
!= NULL
) {
248 at91_ssc_write(dma_params
->ssc_base
+ AT91_SSC_CR
,
249 dma_params
->mask
->ssc_disable
);
250 DBG("%s disabled SSC_SR=0x%08lx\n", (dir
? "receive" : "transmit"),
251 at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_SR
));
253 dma_params
->ssc_base
= NULL
;
254 dma_params
->substream
= NULL
;
255 ssc_p
->dma_params
[dir
] = NULL
;
260 spin_lock_irq(&ssc_p
->lock
);
261 ssc_p
->dir_mask
&= ~dir_mask
;
262 if (!ssc_p
->dir_mask
) {
263 /* Shutdown the SSC clock. */
264 DBG("Stopping pid %d clock\n", ssc_p
->ssc
.pid
);
265 at91_sys_write(AT91_PMC_PCDR
, 1<<ssc_p
->ssc
.pid
);
267 if (ssc_p
->initialized
) {
268 free_irq(ssc_p
->ssc
.pid
, ssc_p
);
269 ssc_p
->initialized
= 0;
273 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_CR
, AT91_SSC_SWRST
);
275 /* Clear the SSC dividers */
276 ssc_p
->cmr_div
= ssc_p
->tcmr_period
= ssc_p
->rcmr_period
= 0;
278 spin_unlock_irq(&ssc_p
->lock
);
282 * Record the SSC system clock rate.
284 static int at91_ssc_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
285 int clk_id
, unsigned int freq
, int dir
)
288 * The only clock supplied to the SSC is the AT91 master clock,
289 * which is only used if the SSC is generating BCLK and/or
293 case AT91_SYSCLK_MCK
:
294 at91_ssc_sysclk
= freq
;
304 * Record the DAI format for use in hw_params().
306 static int at91_ssc_set_dai_fmt(struct snd_soc_dai
*cpu_dai
,
309 struct at91_ssc_info
*ssc_p
= &ssc_info
[cpu_dai
->id
];
316 * Record SSC clock dividers for use in hw_params().
318 static int at91_ssc_set_dai_clkdiv(struct snd_soc_dai
*cpu_dai
,
321 struct at91_ssc_info
*ssc_p
= &ssc_info
[cpu_dai
->id
];
324 case AT91SSC_CMR_DIV
:
326 * The same master clock divider is used for both
327 * transmit and receive, so if a value has already
328 * been set, it must match this value.
330 if (ssc_p
->cmr_div
== 0)
331 ssc_p
->cmr_div
= div
;
333 if (div
!= ssc_p
->cmr_div
)
337 case AT91SSC_TCMR_PERIOD
:
338 ssc_p
->tcmr_period
= div
;
341 case AT91SSC_RCMR_PERIOD
:
342 ssc_p
->rcmr_period
= div
;
355 static int at91_ssc_hw_params(struct snd_pcm_substream
*substream
,
356 struct snd_pcm_hw_params
*params
)
358 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
359 int id
= rtd
->dai
->cpu_dai
->id
;
360 struct at91_ssc_info
*ssc_p
= &ssc_info
[id
];
361 struct at91_pcm_dma_params
*dma_params
;
362 int dir
, channels
, bits
;
363 u32 tfmr
, rfmr
, tcmr
, rcmr
;
368 * Currently, there is only one set of dma params for
369 * each direction. If more are added, this code will
370 * have to be changed to select the proper set.
372 dir
= substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
? 0 : 1;
374 dma_params
= &ssc_dma_params
[id
][dir
];
375 dma_params
->ssc_base
= ssc_p
->ssc
.base
;
376 dma_params
->substream
= substream
;
378 ssc_p
->dma_params
[dir
] = dma_params
;
381 * The cpu_dai->dma_data field is only used to communicate the
382 * appropriate DMA parameters to the pcm driver hw_params()
383 * function. It should not be used for other purposes
384 * as it is common to all substreams.
386 rtd
->dai
->cpu_dai
->dma_data
= dma_params
;
388 channels
= params_channels(params
);
391 * Determine sample size in bits and the PDC increment.
393 switch(params_format(params
)) {
394 case SNDRV_PCM_FORMAT_S8
:
396 dma_params
->pdc_xfer_size
= 1;
398 case SNDRV_PCM_FORMAT_S16_LE
:
400 dma_params
->pdc_xfer_size
= 2;
402 case SNDRV_PCM_FORMAT_S24_LE
:
404 dma_params
->pdc_xfer_size
= 4;
406 case SNDRV_PCM_FORMAT_S32_LE
:
408 dma_params
->pdc_xfer_size
= 4;
411 printk(KERN_WARNING
"at91-ssc: unsupported PCM format\n");
416 * The SSC only supports up to 16-bit samples in I2S format, due
417 * to the size of the Frame Mode Register FSLEN field.
419 if ((ssc_p
->daifmt
& SND_SOC_DAIFMT_FORMAT_MASK
) == SND_SOC_DAIFMT_I2S
422 "at91-ssc: sample size %d is too large for I2S\n", bits
);
427 * Compute SSC register settings.
429 switch (ssc_p
->daifmt
430 & (SND_SOC_DAIFMT_FORMAT_MASK
| SND_SOC_DAIFMT_MASTER_MASK
)) {
432 case SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_CBS_CFS
:
434 * I2S format, SSC provides BCLK and LRC clocks.
436 * The SSC transmit and receive clocks are generated from the
437 * MCK divider, and the BCLK signal is output on the SSC TK line.
439 rcmr
= (( ssc_p
->rcmr_period
<< 24) & AT91_SSC_PERIOD
)
440 | (( 1 << 16) & AT91_SSC_STTDLY
)
441 | (( AT91_SSC_START_FALLING_RF
) & AT91_SSC_START
)
442 | (( AT91_SSC_CK_RISING
) & AT91_SSC_CKI
)
443 | (( AT91_SSC_CKO_NONE
) & AT91_SSC_CKO
)
444 | (( AT91_SSC_CKS_DIV
) & AT91_SSC_CKS
);
446 rfmr
= (( AT91_SSC_FSEDGE_POSITIVE
) & AT91_SSC_FSEDGE
)
447 | (( AT91_SSC_FSOS_NEGATIVE
) & AT91_SSC_FSOS
)
448 | (((bits
- 1) << 16) & AT91_SSC_FSLEN
)
449 | (((channels
- 1) << 8) & AT91_SSC_DATNB
)
450 | (( 1 << 7) & AT91_SSC_MSBF
)
451 | (( 0 << 5) & AT91_SSC_LOOP
)
452 | (((bits
- 1) << 0) & AT91_SSC_DATALEN
);
454 tcmr
= (( ssc_p
->tcmr_period
<< 24) & AT91_SSC_PERIOD
)
455 | (( 1 << 16) & AT91_SSC_STTDLY
)
456 | (( AT91_SSC_START_FALLING_RF
) & AT91_SSC_START
)
457 | (( AT91_SSC_CKI_FALLING
) & AT91_SSC_CKI
)
458 | (( AT91_SSC_CKO_CONTINUOUS
) & AT91_SSC_CKO
)
459 | (( AT91_SSC_CKS_DIV
) & AT91_SSC_CKS
);
461 tfmr
= (( AT91_SSC_FSEDGE_POSITIVE
) & AT91_SSC_FSEDGE
)
462 | (( 0 << 23) & AT91_SSC_FSDEN
)
463 | (( AT91_SSC_FSOS_NEGATIVE
) & AT91_SSC_FSOS
)
464 | (((bits
- 1) << 16) & AT91_SSC_FSLEN
)
465 | (((channels
- 1) << 8) & AT91_SSC_DATNB
)
466 | (( 1 << 7) & AT91_SSC_MSBF
)
467 | (( 0 << 5) & AT91_SSC_DATDEF
)
468 | (((bits
- 1) << 0) & AT91_SSC_DATALEN
);
471 case SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_CBM_CFM
:
473 * I2S format, CODEC supplies BCLK and LRC clocks.
475 * The SSC transmit clock is obtained from the BCLK signal on
476 * on the TK line, and the SSC receive clock is generated from the
479 * For single channel data, one sample is transferred on the falling
480 * edge of the LRC clock. For two channel data, one sample is
481 * transferred on both edges of the LRC clock.
483 start_event
= channels
== 1
484 ? AT91_SSC_START_FALLING_RF
485 : AT91_SSC_START_EDGE_RF
;
487 rcmr
= (( 0 << 24) & AT91_SSC_PERIOD
)
488 | (( 1 << 16) & AT91_SSC_STTDLY
)
489 | (( start_event
) & AT91_SSC_START
)
490 | (( AT91_SSC_CK_RISING
) & AT91_SSC_CKI
)
491 | (( AT91_SSC_CKO_NONE
) & AT91_SSC_CKO
)
492 | (( AT91_SSC_CKS_CLOCK
) & AT91_SSC_CKS
);
494 rfmr
= (( AT91_SSC_FSEDGE_POSITIVE
) & AT91_SSC_FSEDGE
)
495 | (( AT91_SSC_FSOS_NONE
) & AT91_SSC_FSOS
)
496 | (( 0 << 16) & AT91_SSC_FSLEN
)
497 | (( 0 << 8) & AT91_SSC_DATNB
)
498 | (( 1 << 7) & AT91_SSC_MSBF
)
499 | (( 0 << 5) & AT91_SSC_LOOP
)
500 | (((bits
- 1) << 0) & AT91_SSC_DATALEN
);
502 tcmr
= (( 0 << 24) & AT91_SSC_PERIOD
)
503 | (( 1 << 16) & AT91_SSC_STTDLY
)
504 | (( start_event
) & AT91_SSC_START
)
505 | (( AT91_SSC_CKI_FALLING
) & AT91_SSC_CKI
)
506 | (( AT91_SSC_CKO_NONE
) & AT91_SSC_CKO
)
507 | (( AT91_SSC_CKS_PIN
) & AT91_SSC_CKS
);
509 tfmr
= (( AT91_SSC_FSEDGE_POSITIVE
) & AT91_SSC_FSEDGE
)
510 | (( 0 << 23) & AT91_SSC_FSDEN
)
511 | (( AT91_SSC_FSOS_NONE
) & AT91_SSC_FSOS
)
512 | (( 0 << 16) & AT91_SSC_FSLEN
)
513 | (( 0 << 8) & AT91_SSC_DATNB
)
514 | (( 1 << 7) & AT91_SSC_MSBF
)
515 | (( 0 << 5) & AT91_SSC_DATDEF
)
516 | (((bits
- 1) << 0) & AT91_SSC_DATALEN
);
519 case SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_CBS_CFS
:
521 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
523 * The SSC transmit and receive clocks are generated from the
524 * MCK divider, and the BCLK signal is output on the SSC TK line.
526 rcmr
= (( ssc_p
->rcmr_period
<< 24) & AT91_SSC_PERIOD
)
527 | (( 1 << 16) & AT91_SSC_STTDLY
)
528 | (( AT91_SSC_START_RISING_RF
) & AT91_SSC_START
)
529 | (( AT91_SSC_CK_RISING
) & AT91_SSC_CKI
)
530 | (( AT91_SSC_CKO_NONE
) & AT91_SSC_CKO
)
531 | (( AT91_SSC_CKS_DIV
) & AT91_SSC_CKS
);
533 rfmr
= (( AT91_SSC_FSEDGE_POSITIVE
) & AT91_SSC_FSEDGE
)
534 | (( AT91_SSC_FSOS_POSITIVE
) & AT91_SSC_FSOS
)
535 | (( 0 << 16) & AT91_SSC_FSLEN
)
536 | (((channels
- 1) << 8) & AT91_SSC_DATNB
)
537 | (( 1 << 7) & AT91_SSC_MSBF
)
538 | (( 0 << 5) & AT91_SSC_LOOP
)
539 | (((bits
- 1) << 0) & AT91_SSC_DATALEN
);
541 tcmr
= (( ssc_p
->tcmr_period
<< 24) & AT91_SSC_PERIOD
)
542 | (( 1 << 16) & AT91_SSC_STTDLY
)
543 | (( AT91_SSC_START_RISING_RF
) & AT91_SSC_START
)
544 | (( AT91_SSC_CK_RISING
) & AT91_SSC_CKI
)
545 | (( AT91_SSC_CKO_CONTINUOUS
) & AT91_SSC_CKO
)
546 | (( AT91_SSC_CKS_DIV
) & AT91_SSC_CKS
);
548 tfmr
= (( AT91_SSC_FSEDGE_POSITIVE
) & AT91_SSC_FSEDGE
)
549 | (( 0 << 23) & AT91_SSC_FSDEN
)
550 | (( AT91_SSC_FSOS_POSITIVE
) & AT91_SSC_FSOS
)
551 | (( 0 << 16) & AT91_SSC_FSLEN
)
552 | (((channels
- 1) << 8) & AT91_SSC_DATNB
)
553 | (( 1 << 7) & AT91_SSC_MSBF
)
554 | (( 0 << 5) & AT91_SSC_DATDEF
)
555 | (((bits
- 1) << 0) & AT91_SSC_DATALEN
);
561 case SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_CBM_CFM
:
563 printk(KERN_WARNING
"at91-ssc: unsupported DAI format 0x%x.\n",
568 DBG("RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", rcmr
, rfmr
, tcmr
, tfmr
);
570 if (!ssc_p
->initialized
) {
572 /* Enable PMC peripheral clock for this SSC */
573 DBG("Starting pid %d clock\n", ssc_p
->ssc
.pid
);
574 at91_sys_write(AT91_PMC_PCER
, 1<<ssc_p
->ssc
.pid
);
576 /* Reset the SSC and its PDC registers */
577 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_CR
, AT91_SSC_SWRST
);
579 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_RPR
, 0);
580 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_RCR
, 0);
581 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_RNPR
, 0);
582 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_RNCR
, 0);
583 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_TPR
, 0);
584 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_TCR
, 0);
585 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_TNPR
, 0);
586 at91_ssc_write(ssc_p
->ssc
.base
+ ATMEL_PDC_TNCR
, 0);
588 if ((ret
= request_irq(ssc_p
->ssc
.pid
, at91_ssc_interrupt
,
589 0, ssc_p
->name
, ssc_p
)) < 0) {
590 printk(KERN_WARNING
"at91-ssc: request_irq failure\n");
592 DBG("Stopping pid %d clock\n", ssc_p
->ssc
.pid
);
593 at91_sys_write(AT91_PMC_PCDR
, 1<<ssc_p
->ssc
.pid
);
597 ssc_p
->initialized
= 1;
600 /* set SSC clock mode register */
601 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_CMR
, ssc_p
->cmr_div
);
603 /* set receive clock mode and format */
604 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_RCMR
, rcmr
);
605 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_RFMR
, rfmr
);
607 /* set transmit clock mode and format */
608 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_TCMR
, tcmr
);
609 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_TFMR
, tfmr
);
611 DBG("hw_params: SSC initialized\n");
616 static int at91_ssc_prepare(struct snd_pcm_substream
*substream
)
618 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
619 struct at91_ssc_info
*ssc_p
= &ssc_info
[rtd
->dai
->cpu_dai
->id
];
620 struct at91_pcm_dma_params
*dma_params
;
623 dir
= substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
? 0 : 1;
624 dma_params
= ssc_p
->dma_params
[dir
];
626 at91_ssc_write(dma_params
->ssc_base
+ AT91_SSC_CR
,
627 dma_params
->mask
->ssc_enable
);
629 DBG("%s enabled SSC_SR=0x%08lx\n", dir
? "receive" : "transmit",
630 at91_ssc_read(dma_params
->ssc_base
+ AT91_SSC_SR
));
636 static int at91_ssc_suspend(struct platform_device
*pdev
,
637 struct snd_soc_dai
*cpu_dai
)
639 struct at91_ssc_info
*ssc_p
;
644 ssc_p
= &ssc_info
[cpu_dai
->id
];
646 /* Save the status register before disabling transmit and receive. */
647 ssc_p
->ssc_state
.ssc_sr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_SR
);
648 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_CR
,
649 AT91_SSC_TXDIS
| AT91_SSC_RXDIS
);
651 /* Save the current interrupt mask, then disable unmasked interrupts. */
652 ssc_p
->ssc_state
.ssc_imr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_IMR
);
653 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_IDR
, ssc_p
->ssc_state
.ssc_imr
);
655 ssc_p
->ssc_state
.ssc_cmr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_CMR
);
656 ssc_p
->ssc_state
.ssc_rcmr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_RCMR
);
657 ssc_p
->ssc_state
.ssc_rfmr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_RFMR
);
658 ssc_p
->ssc_state
.ssc_tcmr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_TCMR
);
659 ssc_p
->ssc_state
.ssc_tfmr
= at91_ssc_read(ssc_p
->ssc
.base
+ AT91_SSC_TFMR
);
664 static int at91_ssc_resume(struct platform_device
*pdev
,
665 struct snd_soc_dai
*cpu_dai
)
667 struct at91_ssc_info
*ssc_p
;
672 ssc_p
= &ssc_info
[cpu_dai
->id
];
674 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_TFMR
, ssc_p
->ssc_state
.ssc_tfmr
);
675 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_TCMR
, ssc_p
->ssc_state
.ssc_tcmr
);
676 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_RFMR
, ssc_p
->ssc_state
.ssc_rfmr
);
677 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_RCMR
, ssc_p
->ssc_state
.ssc_rcmr
);
678 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_CMR
, ssc_p
->ssc_state
.ssc_cmr
);
680 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_IER
, ssc_p
->ssc_state
.ssc_imr
);
682 at91_ssc_write(ssc_p
->ssc
.base
+ AT91_SSC_CR
,
683 ((ssc_p
->ssc_state
.ssc_sr
& AT91_SSC_RXENA
) ? AT91_SSC_RXEN
: 0) |
684 ((ssc_p
->ssc_state
.ssc_sr
& AT91_SSC_TXENA
) ? AT91_SSC_TXEN
: 0));
690 #define at91_ssc_suspend NULL
691 #define at91_ssc_resume NULL
694 #define AT91_SSC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
695 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
696 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
697 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
698 SNDRV_PCM_RATE_96000)
700 #define AT91_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
701 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
703 struct snd_soc_dai at91_ssc_dai
[NUM_SSC_DEVICES
] = {
704 { .name
= "at91-ssc0",
706 .type
= SND_SOC_DAI_PCM
,
707 .suspend
= at91_ssc_suspend
,
708 .resume
= at91_ssc_resume
,
712 .rates
= AT91_SSC_RATES
,
713 .formats
= AT91_SSC_FORMATS
,},
717 .rates
= AT91_SSC_RATES
,
718 .formats
= AT91_SSC_FORMATS
,},
720 .startup
= at91_ssc_startup
,
721 .shutdown
= at91_ssc_shutdown
,
722 .prepare
= at91_ssc_prepare
,
723 .hw_params
= at91_ssc_hw_params
,},
725 .set_sysclk
= at91_ssc_set_dai_sysclk
,
726 .set_fmt
= at91_ssc_set_dai_fmt
,
727 .set_clkdiv
= at91_ssc_set_dai_clkdiv
,},
728 .private_data
= &ssc_info
[0].ssc
,
730 #if NUM_SSC_DEVICES == 3
731 { .name
= "at91-ssc1",
733 .type
= SND_SOC_DAI_PCM
,
734 .suspend
= at91_ssc_suspend
,
735 .resume
= at91_ssc_resume
,
739 .rates
= AT91_SSC_RATES
,
740 .formats
= AT91_SSC_FORMATS
,},
744 .rates
= AT91_SSC_RATES
,
745 .formats
= AT91_SSC_FORMATS
,},
747 .startup
= at91_ssc_startup
,
748 .shutdown
= at91_ssc_shutdown
,
749 .prepare
= at91_ssc_prepare
,
750 .hw_params
= at91_ssc_hw_params
,},
752 .set_sysclk
= at91_ssc_set_dai_sysclk
,
753 .set_fmt
= at91_ssc_set_dai_fmt
,
754 .set_clkdiv
= at91_ssc_set_dai_clkdiv
,},
755 .private_data
= &ssc_info
[1].ssc
,
757 { .name
= "at91-ssc2",
759 .type
= SND_SOC_DAI_PCM
,
760 .suspend
= at91_ssc_suspend
,
761 .resume
= at91_ssc_resume
,
765 .rates
= AT91_SSC_RATES
,
766 .formats
= AT91_SSC_FORMATS
,},
770 .rates
= AT91_SSC_RATES
,
771 .formats
= AT91_SSC_FORMATS
,},
773 .startup
= at91_ssc_startup
,
774 .shutdown
= at91_ssc_shutdown
,
775 .prepare
= at91_ssc_prepare
,
776 .hw_params
= at91_ssc_hw_params
,},
778 .set_sysclk
= at91_ssc_set_dai_sysclk
,
779 .set_fmt
= at91_ssc_set_dai_fmt
,
780 .set_clkdiv
= at91_ssc_set_dai_clkdiv
,},
781 .private_data
= &ssc_info
[2].ssc
,
786 EXPORT_SYMBOL_GPL(at91_ssc_dai
);
788 /* Module information */
789 MODULE_AUTHOR("Frank Mandarino, fmandarino@endrelia.com, www.endrelia.com");
790 MODULE_DESCRIPTION("AT91 SSC ASoC Interface");
791 MODULE_LICENSE("GPL");