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[PATCH] PCI: disable msi mode in pci_disable_device
[linux-2.6/mini2440.git] / drivers / pci / hotplug / shpchp.h
blob7208b95c6ee779585ff056bcdaeb091140f44961
1 /*
2 * Standard Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29 #ifndef _SHPCHP_H
30 #define _SHPCHP_H
31
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/sched.h> /* signal_pending(), struct timer_list */
36 #include <linux/mutex.h>
37
38 #include "pci_hotplug.h"
39
40 #if !defined(MODULE)
41 #define MY_NAME "shpchp"
42 #else
43 #define MY_NAME THIS_MODULE->name
44 #endif
45
46 extern int shpchp_poll_mode;
47 extern int shpchp_poll_time;
48 extern int shpchp_debug;
49 extern struct workqueue_struct *shpchp_wq;
50
51 /*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
52 #define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
53 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
54 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
55 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
56
57 #define SLOT_NAME_SIZE 10
58 struct slot {
59 u8 bus;
60 u8 device;
61 u16 status;
62 u32 number;
63 u8 is_a_board;
64 u8 state;
65 u8 presence_save;
66 u8 pwr_save;
67 struct timer_list task_event;
68 u8 hp_slot;
69 struct controller *ctrl;
70 struct hpc_ops *hpc_ops;
71 struct hotplug_slot *hotplug_slot;
72 struct list_head slot_list;
73 char name[SLOT_NAME_SIZE];
74 struct work_struct work; /* work for button event */
75 struct mutex lock;
76 };
77
78 struct event_info {
79 u32 event_type;
80 struct slot *p_slot;
81 struct work_struct work;
82 };
83
84 struct controller {
85 struct mutex crit_sect; /* critical section mutex */
86 struct mutex cmd_lock; /* command lock */
87 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
88 int num_slots; /* Number of slots on ctlr */
89 int slot_num_inc; /* 1 or -1 */
90 struct pci_dev *pci_dev;
91 struct list_head slot_list;
92 struct hpc_ops *hpc_ops;
93 wait_queue_head_t queue; /* sleep & wake process */
94 u8 bus;
95 u8 device;
96 u8 function;
97 u8 slot_device_offset;
98 u8 add_support;
99 u32 pcix_misc2_reg; /* for amd pogo errata */
100 enum pci_bus_speed speed;
101 u32 first_slot; /* First physical slot number */
102 u8 slot_bus; /* Bus where the slots handled by this controller sit */
103 u32 cap_offset;
104 unsigned long mmio_base;
105 unsigned long mmio_size;
106 volatile int cmd_busy;
107 };
108
109
110 /* Define AMD SHPC ID */
111 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
112 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
113
114 /* AMD PCIX bridge registers */
115
116 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
117 #define PCIX_MISCII_OFFSET 0x48
118 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
119
120 /* AMD PCIX_MISCII masks and offsets */
121 #define PERRNONFATALENABLE_MASK 0x00040000
122 #define PERRFATALENABLE_MASK 0x00080000
123 #define PERRFLOODENABLE_MASK 0x00100000
124 #define SERRNONFATALENABLE_MASK 0x00200000
125 #define SERRFATALENABLE_MASK 0x00400000
126
127 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
128 #define PERR_OBSERVED_MASK 0x00000001
129
130 /* AMD PCIX_MEM_BASE_LIMIT masks */
131 #define RSE_MASK 0x40000000
132
133 #define INT_BUTTON_IGNORE 0
134 #define INT_PRESENCE_ON 1
135 #define INT_PRESENCE_OFF 2
136 #define INT_SWITCH_CLOSE 3
137 #define INT_SWITCH_OPEN 4
138 #define INT_POWER_FAULT 5
139 #define INT_POWER_FAULT_CLEAR 6
140 #define INT_BUTTON_PRESS 7
141 #define INT_BUTTON_RELEASE 8
142 #define INT_BUTTON_CANCEL 9
143
144 #define STATIC_STATE 0
145 #define BLINKINGON_STATE 1
146 #define BLINKINGOFF_STATE 2
147 #define POWERON_STATE 3
148 #define POWEROFF_STATE 4
149
150 #define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
151
152 /* Error messages */
153 #define INTERLOCK_OPEN 0x00000002
154 #define ADD_NOT_SUPPORTED 0x00000003
155 #define CARD_FUNCTIONING 0x00000005
156 #define ADAPTER_NOT_SAME 0x00000006
157 #define NO_ADAPTER_PRESENT 0x00000009
158 #define NOT_ENOUGH_RESOURCES 0x0000000B
159 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
160 #define WRONG_BUS_FREQUENCY 0x0000000D
161 #define POWER_FAILURE 0x0000000E
162
163 #define REMOVE_NOT_SUPPORTED 0x00000003
164
165 #define DISABLE_CARD 1
166
167 /*
168 * error Messages
169 */
170 #define msg_initialization_err "Initialization failure, error=%d\n"
171 #define msg_button_on "PCI slot #%s - powering on due to button press.\n"
172 #define msg_button_off "PCI slot #%s - powering off due to button press.\n"
173 #define msg_button_cancel "PCI slot #%s - action canceled due to button press.\n"
174
175 /* sysfs functions for the hotplug controller info */
176 extern void shpchp_create_ctrl_files (struct controller *ctrl);
177
178 extern int shpchp_sysfs_enable_slot(struct slot *slot);
179 extern int shpchp_sysfs_disable_slot(struct slot *slot);
180
181 extern u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
182 extern u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
183 extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
184 extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
185
186 /* pci functions */
187 extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
188 extern int shpchp_configure_device(struct slot *p_slot);
189 extern int shpchp_unconfigure_device(struct slot *p_slot);
190 extern void shpchp_remove_ctrl_files(struct controller *ctrl);
191 extern void cleanup_slots(struct controller *ctrl);
192 extern void queue_pushbutton_work(void *data);
193
194
195 #ifdef CONFIG_ACPI
196 static inline int get_hp_params_from_firmware(struct pci_dev *dev,
197 struct hotplug_params *hpp)
198 {
199 if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp)))
200 return -ENODEV;
201 return 0;
202 }
203 #define get_hp_hw_control_from_firmware(pdev) \
204 do { \
205 if (DEVICE_ACPI_HANDLE(&(pdev->dev))) \
206 acpi_run_oshp(DEVICE_ACPI_HANDLE(&(pdev->dev))); \
207 } while (0)
208 #else
209 #define get_hp_params_from_firmware(dev, hpp) (-ENODEV)
210 #define get_hp_hw_control_from_firmware(dev) do { } while (0)
211 #endif
212
213 struct ctrl_reg {
214 volatile u32 base_offset;
215 volatile u32 slot_avail1;
216 volatile u32 slot_avail2;
217 volatile u32 slot_config;
218 volatile u16 sec_bus_config;
219 volatile u8 msi_ctrl;
220 volatile u8 prog_interface;
221 volatile u16 cmd;
222 volatile u16 cmd_status;
223 volatile u32 intr_loc;
224 volatile u32 serr_loc;
225 volatile u32 serr_intr_enable;
226 volatile u32 slot1;
227 volatile u32 slot2;
228 volatile u32 slot3;
229 volatile u32 slot4;
230 volatile u32 slot5;
231 volatile u32 slot6;
232 volatile u32 slot7;
233 volatile u32 slot8;
234 volatile u32 slot9;
235 volatile u32 slot10;
236 volatile u32 slot11;
237 volatile u32 slot12;
238 } __attribute__ ((packed));
239
240 /* offsets to the controller registers based on the above structure layout */
241 enum ctrl_offsets {
242 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
243 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
244 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
245 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
246 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
247 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
248 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
249 CMD = offsetof(struct ctrl_reg, cmd),
250 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
251 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
252 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
253 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
254 SLOT1 = offsetof(struct ctrl_reg, slot1),
255 SLOT2 = offsetof(struct ctrl_reg, slot2),
256 SLOT3 = offsetof(struct ctrl_reg, slot3),
257 SLOT4 = offsetof(struct ctrl_reg, slot4),
258 SLOT5 = offsetof(struct ctrl_reg, slot5),
259 SLOT6 = offsetof(struct ctrl_reg, slot6),
260 SLOT7 = offsetof(struct ctrl_reg, slot7),
261 SLOT8 = offsetof(struct ctrl_reg, slot8),
262 SLOT9 = offsetof(struct ctrl_reg, slot9),
263 SLOT10 = offsetof(struct ctrl_reg, slot10),
264 SLOT11 = offsetof(struct ctrl_reg, slot11),
265 SLOT12 = offsetof(struct ctrl_reg, slot12),
266 };
267 typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
268 struct php_ctlr_state_s {
269 struct php_ctlr_state_s *pnext;
270 struct pci_dev *pci_dev;
271 unsigned int irq;
272 unsigned long flags; /* spinlock's */
273 u32 slot_device_offset;
274 u32 num_slots;
275 struct timer_list int_poll_timer; /* Added for poll event */
276 php_intr_callback_t attention_button_callback;
277 php_intr_callback_t switch_change_callback;
278 php_intr_callback_t presence_change_callback;
279 php_intr_callback_t power_fault_callback;
280 void *callback_instance_id;
281 void __iomem *creg; /* Ptr to controller register space */
282 };
283 /* Inline functions */
284
285
286 /* Inline functions to check the sanity of a pointer that is passed to us */
287 static inline int slot_paranoia_check (struct slot *slot, const char *function)
288 {
289 if (!slot) {
290 dbg("%s - slot == NULL", function);
291 return -1;
292 }
293 if (!slot->hotplug_slot) {
294 dbg("%s - slot->hotplug_slot == NULL!", function);
295 return -1;
296 }
297 return 0;
298 }
299
300 static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
301 {
302 struct slot *slot;
303
304 if (!hotplug_slot) {
305 dbg("%s - hotplug_slot == NULL\n", function);
306 return NULL;
307 }
308
309 slot = (struct slot *)hotplug_slot->private;
310 if (slot_paranoia_check (slot, function))
311 return NULL;
312 return slot;
313 }
314
315 static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
316 {
317 struct slot *slot;
318
319 if (!ctrl)
320 return NULL;
321
322 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
323 if (slot->device == device)
324 return slot;
325 }
326
327 err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
328
329 return NULL;
330 }
331
332 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
333 {
334 u32 pcix_misc2_temp;
335
336 /* save MiscII register */
337 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
338
339 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
340
341 /* clear SERR/PERR enable bits */
342 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
343 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
344 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
345 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
346 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
347 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
348 }
349
350 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
351 {
352 u32 pcix_misc2_temp;
353 u32 pcix_bridge_errors_reg;
354 u32 pcix_mem_base_reg;
355 u8 perr_set;
356 u8 rse_set;
357
358 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
359 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
360 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
361 if (perr_set) {
362 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
363
364 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
365 }
366
367 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
368 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
369 rse_set = pcix_mem_base_reg & RSE_MASK;
370 if (rse_set) {
371 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
372
373 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
374 }
375 /* restore MiscII register */
376 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
377
378 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
379 pcix_misc2_temp |= SERRFATALENABLE_MASK;
380 else
381 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
382
383 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
384 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
385 else
386 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
387
388 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
389 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
390 else
391 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
392
393 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
394 pcix_misc2_temp |= PERRFATALENABLE_MASK;
395 else
396 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
397
398 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
399 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
400 else
401 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
402 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
403 }
404
405 enum php_ctlr_type {
406 PCI,
407 ISA,
408 ACPI
409 };
410
411 int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
412
413 int shpc_get_ctlr_slot_config( struct controller *ctrl,
414 int *num_ctlr_slots,
415 int *first_device_num,
416 int *physical_slot_num,
417 int *updown,
418 int *flags);
419
420 struct hpc_ops {
421 int (*power_on_slot ) (struct slot *slot);
422 int (*slot_enable ) (struct slot *slot);
423 int (*slot_disable ) (struct slot *slot);
424 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed);
425 int (*get_power_status) (struct slot *slot, u8 *status);
426 int (*get_attention_status) (struct slot *slot, u8 *status);
427 int (*set_attention_status) (struct slot *slot, u8 status);
428 int (*get_latch_status) (struct slot *slot, u8 *status);
429 int (*get_adapter_status) (struct slot *slot, u8 *status);
430
431 int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
432 int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
433 int (*get_adapter_speed) (struct slot *slot, enum pci_bus_speed *speed);
434 int (*get_mode1_ECC_cap) (struct slot *slot, u8 *mode);
435 int (*get_prog_int) (struct slot *slot, u8 *prog_int);
436
437 int (*query_power_fault) (struct slot *slot);
438 void (*green_led_on) (struct slot *slot);
439 void (*green_led_off) (struct slot *slot);
440 void (*green_led_blink) (struct slot *slot);
441 void (*release_ctlr) (struct controller *ctrl);
442 int (*check_cmd_status) (struct controller *ctrl);
443 };
444
445 #endif /* _SHPCHP_H */
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