2 * arch/sh/kernel/cpu/sh4/probe.c
4 * CPU Subtype Probing for SH-4.
6 * Copyright (C) 2001 - 2007 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
18 int __init
detect_cpu_and_cache_system(void)
20 unsigned long pvr
, prr
, cvr
;
23 static unsigned long sizes
[16] = {
31 pvr
= (ctrl_inl(CCN_PVR
) >> 8) & 0xffffff;
32 prr
= (ctrl_inl(CCN_PRR
) >> 4) & 0xff;
33 cvr
= (ctrl_inl(CCN_CVR
));
36 * Setup some sane SH-4 defaults for the icache
38 boot_cpu_data
.icache
.way_incr
= (1 << 13);
39 boot_cpu_data
.icache
.entry_shift
= 5;
40 boot_cpu_data
.icache
.sets
= 256;
41 boot_cpu_data
.icache
.ways
= 1;
42 boot_cpu_data
.icache
.linesz
= L1_CACHE_BYTES
;
45 * And again for the dcache ..
47 boot_cpu_data
.dcache
.way_incr
= (1 << 14);
48 boot_cpu_data
.dcache
.entry_shift
= 5;
49 boot_cpu_data
.dcache
.sets
= 512;
50 boot_cpu_data
.dcache
.ways
= 1;
51 boot_cpu_data
.dcache
.linesz
= L1_CACHE_BYTES
;
53 /* We don't know the chip cut */
54 boot_cpu_data
.cut_major
= boot_cpu_data
.cut_minor
= -1;
57 * Setup some generic flags we can probe on SH-4A parts
59 if (((pvr
>> 16) & 0xff) == 0x10) {
60 if ((cvr
& 0x10000000) == 0)
61 boot_cpu_data
.flags
|= CPU_HAS_DSP
;
63 boot_cpu_data
.flags
|= CPU_HAS_LLSC
;
64 boot_cpu_data
.cut_major
= pvr
& 0x7f;
67 /* FPU detection works for everyone */
68 if ((cvr
& 0x20000000) == 1)
69 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
71 /* Mask off the upper chip ID */
75 * Probe the underlying processor version/revision and
76 * adjust cpu_data setup accordingly.
80 boot_cpu_data
.type
= CPU_SH7750
;
81 boot_cpu_data
.flags
|= CPU_HAS_P2_FLUSH_BUG
| CPU_HAS_FPU
|
85 boot_cpu_data
.type
= CPU_SH7750S
;
86 boot_cpu_data
.flags
|= CPU_HAS_P2_FLUSH_BUG
| CPU_HAS_FPU
|
90 boot_cpu_data
.type
= CPU_SH7751
;
91 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
95 boot_cpu_data
.type
= CPU_SH7770
;
96 boot_cpu_data
.icache
.ways
= 4;
97 boot_cpu_data
.dcache
.ways
= 4;
99 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_LLSC
;
104 boot_cpu_data
.type
= CPU_SH7781
;
105 else if (prr
== 0xa1)
106 boot_cpu_data
.type
= CPU_SH7763
;
108 boot_cpu_data
.type
= CPU_SH7780
;
110 boot_cpu_data
.icache
.ways
= 4;
111 boot_cpu_data
.dcache
.ways
= 4;
113 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_PERF_COUNTER
|
119 boot_cpu_data
.type
= CPU_SH7343
;
120 boot_cpu_data
.icache
.ways
= 4;
121 boot_cpu_data
.dcache
.ways
= 4;
122 boot_cpu_data
.flags
|= CPU_HAS_LLSC
;
126 boot_cpu_data
.type
= CPU_SH7785
;
127 boot_cpu_data
.icache
.ways
= 4;
128 boot_cpu_data
.dcache
.ways
= 4;
129 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_PERF_COUNTER
|
133 boot_cpu_data
.type
= CPU_SH7786
;
134 boot_cpu_data
.icache
.ways
= 4;
135 boot_cpu_data
.dcache
.ways
= 4;
136 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_PERF_COUNTER
|
137 CPU_HAS_LLSC
| CPU_HAS_PTEAEX
;
140 boot_cpu_data
.icache
.ways
= 4;
141 boot_cpu_data
.dcache
.ways
= 4;
142 boot_cpu_data
.flags
|= CPU_HAS_LLSC
;
147 boot_cpu_data
.type
= CPU_SH7723
;
148 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_L2_CACHE
;
151 boot_cpu_data
.type
= CPU_SH7366
;
155 boot_cpu_data
.type
= CPU_SH7722
;
160 boot_cpu_data
.type
= CPU_SH7724
;
161 boot_cpu_data
.icache
.ways
= 4;
162 boot_cpu_data
.dcache
.ways
= 4;
163 boot_cpu_data
.flags
|= CPU_HAS_LLSC
| CPU_HAS_FPU
| CPU_HAS_L2_CACHE
;
165 case 0x4000: /* 1st cut */
166 case 0x4001: /* 2nd cut */
167 boot_cpu_data
.type
= CPU_SHX3
;
168 boot_cpu_data
.icache
.ways
= 4;
169 boot_cpu_data
.dcache
.ways
= 4;
170 boot_cpu_data
.flags
|= CPU_HAS_FPU
| CPU_HAS_PERF_COUNTER
|
174 boot_cpu_data
.type
= CPU_SH4_501
;
175 boot_cpu_data
.icache
.ways
= 2;
176 boot_cpu_data
.dcache
.ways
= 2;
179 boot_cpu_data
.type
= CPU_SH4_202
;
180 boot_cpu_data
.icache
.ways
= 2;
181 boot_cpu_data
.dcache
.ways
= 2;
182 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
184 case 0x500 ... 0x501:
187 boot_cpu_data
.type
= CPU_SH7750R
;
190 boot_cpu_data
.type
= CPU_SH7751R
;
193 boot_cpu_data
.type
= CPU_SH7760
;
197 boot_cpu_data
.icache
.ways
= 2;
198 boot_cpu_data
.dcache
.ways
= 2;
200 boot_cpu_data
.flags
|= CPU_HAS_FPU
;
204 boot_cpu_data
.type
= CPU_SH_NONE
;
208 #ifdef CONFIG_CPU_HAS_PTEA
209 boot_cpu_data
.flags
|= CPU_HAS_PTEA
;
213 * On anything that's not a direct-mapped cache, look to the CVR
214 * for I/D-cache specifics.
216 if (boot_cpu_data
.icache
.ways
> 1) {
217 size
= sizes
[(cvr
>> 20) & 0xf];
218 boot_cpu_data
.icache
.way_incr
= (size
>> 1);
219 boot_cpu_data
.icache
.sets
= (size
>> 6);
223 /* And the rest of the D-cache */
224 if (boot_cpu_data
.dcache
.ways
> 1) {
225 size
= sizes
[(cvr
>> 16) & 0xf];
226 boot_cpu_data
.dcache
.way_incr
= (size
>> 1);
227 boot_cpu_data
.dcache
.sets
= (size
>> 6);
231 * Setup the L2 cache desc
233 * SH-4A's have an optional PIPT L2.
235 if (boot_cpu_data
.flags
& CPU_HAS_L2_CACHE
) {
236 /* Bug if we can't decode the L2 info */
237 BUG_ON(!(cvr
& 0xf));
239 /* Silicon and specifications have clearly never met.. */
243 * Size calculation is much more sensible
244 * than it is for the L1.
246 * Sizes are 128KB, 258KB, 512KB, and 1MB.
248 size
= (cvr
& 0xf) << 17;
252 boot_cpu_data
.scache
.way_incr
= (1 << 16);
253 boot_cpu_data
.scache
.entry_shift
= 5;
254 boot_cpu_data
.scache
.ways
= 4;
255 boot_cpu_data
.scache
.linesz
= L1_CACHE_BYTES
;
257 boot_cpu_data
.scache
.entry_mask
=
258 (boot_cpu_data
.scache
.way_incr
-
259 boot_cpu_data
.scache
.linesz
);
261 boot_cpu_data
.scache
.sets
= size
/
262 (boot_cpu_data
.scache
.linesz
*
263 boot_cpu_data
.scache
.ways
);
265 boot_cpu_data
.scache
.way_size
=
266 (boot_cpu_data
.scache
.sets
*
267 boot_cpu_data
.scache
.linesz
);