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virtio_blk: don't bounce highmem requests
[linux-2.6/mini2440.git] / sound / pci / hda / hda_intel.c
blob3128e1a6bc65ded0dfbf62c3d48e8b78ecd97b1b
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71 module_param_array(model, charp, NULL, 0444);
72 MODULE_PARM_DESC(model, "Use the given board model.");
73 module_param_array(position_fix, int, NULL, 0444);
74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
75 "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj, int, NULL, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
78 module_param_array(probe_mask, int, NULL, 0444);
79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only, bool, NULL, 0444);
81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
82 module_param(single_cmd, bool, 0444);
83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
85 module_param(enable_msi, int, 0444);
86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
87
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90 module_param(power_save, int, 0644);
91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
93
94 /* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
96 * wake up.
97 */
98 static int power_save_controller = 1;
99 module_param(power_save_controller, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101 #endif
102
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105 "{Intel, ICH6M},"
106 "{Intel, ICH7},"
107 "{Intel, ESB2},"
108 "{Intel, ICH8},"
109 "{Intel, ICH9},"
110 "{Intel, ICH10},"
111 "{Intel, PCH},"
112 "{Intel, SCH},"
113 "{ATI, SB450},"
114 "{ATI, SB600},"
115 "{ATI, RS600},"
116 "{ATI, RS690},"
117 "{ATI, RS780},"
118 "{ATI, R600},"
119 "{ATI, RV630},"
120 "{ATI, RV610},"
121 "{ATI, RV670},"
122 "{ATI, RV635},"
123 "{ATI, RV620},"
124 "{ATI, RV770},"
125 "{VIA, VT8251},"
126 "{VIA, VT8237A},"
127 "{SiS, SIS966},"
128 "{ULI, M5461}}");
129 MODULE_DESCRIPTION("Intel HDA driver");
130
131 #define SFX "hda-intel: "
132
133
134 /*
135 * registers
136 */
137 #define ICH6_REG_GCAP 0x00
138 #define ICH6_REG_VMIN 0x02
139 #define ICH6_REG_VMAJ 0x03
140 #define ICH6_REG_OUTPAY 0x04
141 #define ICH6_REG_INPAY 0x06
142 #define ICH6_REG_GCTL 0x08
143 #define ICH6_REG_WAKEEN 0x0c
144 #define ICH6_REG_STATESTS 0x0e
145 #define ICH6_REG_GSTS 0x10
146 #define ICH6_REG_INTCTL 0x20
147 #define ICH6_REG_INTSTS 0x24
148 #define ICH6_REG_WALCLK 0x30
149 #define ICH6_REG_SYNC 0x34
150 #define ICH6_REG_CORBLBASE 0x40
151 #define ICH6_REG_CORBUBASE 0x44
152 #define ICH6_REG_CORBWP 0x48
153 #define ICH6_REG_CORBRP 0x4A
154 #define ICH6_REG_CORBCTL 0x4c
155 #define ICH6_REG_CORBSTS 0x4d
156 #define ICH6_REG_CORBSIZE 0x4e
157
158 #define ICH6_REG_RIRBLBASE 0x50
159 #define ICH6_REG_RIRBUBASE 0x54
160 #define ICH6_REG_RIRBWP 0x58
161 #define ICH6_REG_RINTCNT 0x5a
162 #define ICH6_REG_RIRBCTL 0x5c
163 #define ICH6_REG_RIRBSTS 0x5d
164 #define ICH6_REG_RIRBSIZE 0x5e
165
166 #define ICH6_REG_IC 0x60
167 #define ICH6_REG_IR 0x64
168 #define ICH6_REG_IRS 0x68
169 #define ICH6_IRS_VALID (1<<1)
170 #define ICH6_IRS_BUSY (1<<0)
171
172 #define ICH6_REG_DPLBASE 0x70
173 #define ICH6_REG_DPUBASE 0x74
174 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
175
176 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
177 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
178
179 /* stream register offsets from stream base */
180 #define ICH6_REG_SD_CTL 0x00
181 #define ICH6_REG_SD_STS 0x03
182 #define ICH6_REG_SD_LPIB 0x04
183 #define ICH6_REG_SD_CBL 0x08
184 #define ICH6_REG_SD_LVI 0x0c
185 #define ICH6_REG_SD_FIFOW 0x0e
186 #define ICH6_REG_SD_FIFOSIZE 0x10
187 #define ICH6_REG_SD_FORMAT 0x12
188 #define ICH6_REG_SD_BDLPL 0x18
189 #define ICH6_REG_SD_BDLPU 0x1c
190
191 /* PCI space */
192 #define ICH6_PCIREG_TCSEL 0x44
193
194 /*
195 * other constants
196 */
197
198 /* max number of SDs */
199 /* ICH, ATI and VIA have 4 playback and 4 capture */
200 #define ICH6_NUM_CAPTURE 4
201 #define ICH6_NUM_PLAYBACK 4
202
203 /* ULI has 6 playback and 5 capture */
204 #define ULI_NUM_CAPTURE 5
205 #define ULI_NUM_PLAYBACK 6
206
207 /* ATI HDMI has 1 playback and 0 capture */
208 #define ATIHDMI_NUM_CAPTURE 0
209 #define ATIHDMI_NUM_PLAYBACK 1
210
211 /* TERA has 4 playback and 3 capture */
212 #define TERA_NUM_CAPTURE 3
213 #define TERA_NUM_PLAYBACK 4
214
215 /* this number is statically defined for simplicity */
216 #define MAX_AZX_DEV 16
217
218 /* max number of fragments - we may use more if allocating more pages for BDL */
219 #define BDL_SIZE 4096
220 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
221 #define AZX_MAX_FRAG 32
222 /* max buffer size - no h/w limit, you can increase as you like */
223 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
224 /* max number of PCM devics per card */
225 #define AZX_MAX_PCMS 8
226
227 /* RIRB int mask: overrun[2], response[0] */
228 #define RIRB_INT_RESPONSE 0x01
229 #define RIRB_INT_OVERRUN 0x04
230 #define RIRB_INT_MASK 0x05
231
232 /* STATESTS int mask: S3,SD2,SD1,SD0 */
233 #define AZX_MAX_CODECS 4
234 #define STATESTS_INT_MASK 0x0f
235
236 /* SD_CTL bits */
237 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
238 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
239 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
240 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
241 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
242 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
243 #define SD_CTL_STREAM_TAG_SHIFT 20
244
245 /* SD_CTL and SD_STS */
246 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
247 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
248 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
249 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
250 SD_INT_COMPLETE)
251
252 /* SD_STS */
253 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
254
255 /* INTCTL and INTSTS */
256 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
257 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
258 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
259
260 /* GCTL unsolicited response enable bit */
261 #define ICH6_GCTL_UREN (1<<8)
262
263 /* GCTL reset bit */
264 #define ICH6_GCTL_RESET (1<<0)
265
266 /* CORB/RIRB control, read/write pointer */
267 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
268 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
269 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
270 /* below are so far hardcoded - should read registers in future */
271 #define ICH6_MAX_CORB_ENTRIES 256
272 #define ICH6_MAX_RIRB_ENTRIES 256
273
274 /* position fix mode */
275 enum {
276 POS_FIX_AUTO,
277 POS_FIX_LPIB,
278 POS_FIX_POSBUF,
279 };
280
281 /* Defines for ATI HD Audio support in SB450 south bridge */
282 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
283 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
284
285 /* Defines for Nvidia HDA support */
286 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
287 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
288 #define NVIDIA_HDA_ISTRM_COH 0x4d
289 #define NVIDIA_HDA_OSTRM_COH 0x4c
290 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
291
292 /* Defines for Intel SCH HDA snoop control */
293 #define INTEL_SCH_HDA_DEVC 0x78
294 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
295
296 /* Define IN stream 0 FIFO size offset in VIA controller */
297 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
298 /* Define VIA HD Audio Device ID*/
299 #define VIA_HDAC_DEVICE_ID 0x3288
300
301 /* HD Audio class code */
302 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
303
304 /*
305 */
306
307 struct azx_dev {
308 struct snd_dma_buffer bdl; /* BDL buffer */
309 u32 *posbuf; /* position buffer pointer */
310
311 unsigned int bufsize; /* size of the play buffer in bytes */
312 unsigned int period_bytes; /* size of the period in bytes */
313 unsigned int frags; /* number for period in the play buffer */
314 unsigned int fifo_size; /* FIFO size */
315 unsigned long start_jiffies; /* start + minimum jiffies */
316 unsigned long min_jiffies; /* minimum jiffies before position is valid */
317
318 void __iomem *sd_addr; /* stream descriptor pointer */
319
320 u32 sd_int_sta_mask; /* stream int status mask */
321
322 /* pcm support */
323 struct snd_pcm_substream *substream; /* assigned substream,
324 * set in PCM open
325 */
326 unsigned int format_val; /* format value to be set in the
327 * controller and the codec
328 */
329 unsigned char stream_tag; /* assigned stream */
330 unsigned char index; /* stream index */
331
332 unsigned int opened :1;
333 unsigned int running :1;
334 unsigned int irq_pending :1;
335 unsigned int start_flag: 1; /* stream full start flag */
336 /*
337 * For VIA:
338 * A flag to ensure DMA position is 0
339 * when link position is not greater than FIFO size
340 */
341 unsigned int insufficient :1;
342 };
343
344 /* CORB/RIRB */
345 struct azx_rb {
346 u32 *buf; /* CORB/RIRB buffer
347 * Each CORB entry is 4byte, RIRB is 8byte
348 */
349 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
350 /* for RIRB */
351 unsigned short rp, wp; /* read/write pointers */
352 int cmds; /* number of pending requests */
353 u32 res; /* last read value */
354 };
355
356 struct azx {
357 struct snd_card *card;
358 struct pci_dev *pci;
359 int dev_index;
360
361 /* chip type specific */
362 int driver_type;
363 int playback_streams;
364 int playback_index_offset;
365 int capture_streams;
366 int capture_index_offset;
367 int num_streams;
368
369 /* pci resources */
370 unsigned long addr;
371 void __iomem *remap_addr;
372 int irq;
373
374 /* locks */
375 spinlock_t reg_lock;
376 struct mutex open_mutex;
377
378 /* streams (x num_streams) */
379 struct azx_dev *azx_dev;
380
381 /* PCM */
382 struct snd_pcm *pcm[AZX_MAX_PCMS];
383
384 /* HD codec */
385 unsigned short codec_mask;
386 int codec_probe_mask; /* copied from probe_mask option */
387 struct hda_bus *bus;
388
389 /* CORB/RIRB */
390 struct azx_rb corb;
391 struct azx_rb rirb;
392
393 /* CORB/RIRB and position buffers */
394 struct snd_dma_buffer rb;
395 struct snd_dma_buffer posbuf;
396
397 /* flags */
398 int position_fix;
399 unsigned int running :1;
400 unsigned int initialized :1;
401 unsigned int single_cmd :1;
402 unsigned int polling_mode :1;
403 unsigned int msi :1;
404 unsigned int irq_pending_warned :1;
405 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
406 unsigned int probing :1; /* codec probing phase */
407
408 /* for debugging */
409 unsigned int last_cmd; /* last issued command (to sync) */
410
411 /* for pending irqs */
412 struct work_struct irq_pending_work;
413
414 /* reboot notifier (for mysterious hangup problem at power-down) */
415 struct notifier_block reboot_notifier;
416 };
417
418 /* driver types */
419 enum {
420 AZX_DRIVER_ICH,
421 AZX_DRIVER_SCH,
422 AZX_DRIVER_ATI,
423 AZX_DRIVER_ATIHDMI,
424 AZX_DRIVER_VIA,
425 AZX_DRIVER_SIS,
426 AZX_DRIVER_ULI,
427 AZX_DRIVER_NVIDIA,
428 AZX_DRIVER_TERA,
429 AZX_DRIVER_GENERIC,
430 AZX_NUM_DRIVERS, /* keep this as last entry */
431 };
432
433 static char *driver_short_names[] __devinitdata = {
434 [AZX_DRIVER_ICH] = "HDA Intel",
435 [AZX_DRIVER_SCH] = "HDA Intel MID",
436 [AZX_DRIVER_ATI] = "HDA ATI SB",
437 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
438 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
439 [AZX_DRIVER_SIS] = "HDA SIS966",
440 [AZX_DRIVER_ULI] = "HDA ULI M5461",
441 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
442 [AZX_DRIVER_TERA] = "HDA Teradici",
443 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
444 };
445
446 /*
447 * macros for easy use
448 */
449 #define azx_writel(chip,reg,value) \
450 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
451 #define azx_readl(chip,reg) \
452 readl((chip)->remap_addr + ICH6_REG_##reg)
453 #define azx_writew(chip,reg,value) \
454 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
455 #define azx_readw(chip,reg) \
456 readw((chip)->remap_addr + ICH6_REG_##reg)
457 #define azx_writeb(chip,reg,value) \
458 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
459 #define azx_readb(chip,reg) \
460 readb((chip)->remap_addr + ICH6_REG_##reg)
461
462 #define azx_sd_writel(dev,reg,value) \
463 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
464 #define azx_sd_readl(dev,reg) \
465 readl((dev)->sd_addr + ICH6_REG_##reg)
466 #define azx_sd_writew(dev,reg,value) \
467 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
468 #define azx_sd_readw(dev,reg) \
469 readw((dev)->sd_addr + ICH6_REG_##reg)
470 #define azx_sd_writeb(dev,reg,value) \
471 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
472 #define azx_sd_readb(dev,reg) \
473 readb((dev)->sd_addr + ICH6_REG_##reg)
474
475 /* for pcm support */
476 #define get_azx_dev(substream) (substream->runtime->private_data)
477
478 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
479
480 /*
481 * Interface for HD codec
482 */
483
484 /*
485 * CORB / RIRB interface
486 */
487 static int azx_alloc_cmd_io(struct azx *chip)
488 {
489 int err;
490
491 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
492 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
493 snd_dma_pci_data(chip->pci),
494 PAGE_SIZE, &chip->rb);
495 if (err < 0) {
496 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
497 return err;
498 }
499 return 0;
500 }
501
502 static void azx_init_cmd_io(struct azx *chip)
503 {
504 /* CORB set up */
505 chip->corb.addr = chip->rb.addr;
506 chip->corb.buf = (u32 *)chip->rb.area;
507 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
508 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
509
510 /* set the corb size to 256 entries (ULI requires explicitly) */
511 azx_writeb(chip, CORBSIZE, 0x02);
512 /* set the corb write pointer to 0 */
513 azx_writew(chip, CORBWP, 0);
514 /* reset the corb hw read pointer */
515 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
516 /* enable corb dma */
517 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
518
519 /* RIRB set up */
520 chip->rirb.addr = chip->rb.addr + 2048;
521 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
522 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
523 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
524
525 /* set the rirb size to 256 entries (ULI requires explicitly) */
526 azx_writeb(chip, RIRBSIZE, 0x02);
527 /* reset the rirb hw write pointer */
528 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
529 /* set N=1, get RIRB response interrupt for new entry */
530 azx_writew(chip, RINTCNT, 1);
531 /* enable rirb dma and response irq */
532 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
533 chip->rirb.rp = chip->rirb.cmds = 0;
534 }
535
536 static void azx_free_cmd_io(struct azx *chip)
537 {
538 /* disable ringbuffer DMAs */
539 azx_writeb(chip, RIRBCTL, 0);
540 azx_writeb(chip, CORBCTL, 0);
541 }
542
543 /* send a command */
544 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
545 {
546 struct azx *chip = bus->private_data;
547 unsigned int wp;
548
549 /* add command to corb */
550 wp = azx_readb(chip, CORBWP);
551 wp++;
552 wp %= ICH6_MAX_CORB_ENTRIES;
553
554 spin_lock_irq(&chip->reg_lock);
555 chip->rirb.cmds++;
556 chip->corb.buf[wp] = cpu_to_le32(val);
557 azx_writel(chip, CORBWP, wp);
558 spin_unlock_irq(&chip->reg_lock);
559
560 return 0;
561 }
562
563 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
564
565 /* retrieve RIRB entry - called from interrupt handler */
566 static void azx_update_rirb(struct azx *chip)
567 {
568 unsigned int rp, wp;
569 u32 res, res_ex;
570
571 wp = azx_readb(chip, RIRBWP);
572 if (wp == chip->rirb.wp)
573 return;
574 chip->rirb.wp = wp;
575
576 while (chip->rirb.rp != wp) {
577 chip->rirb.rp++;
578 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
579
580 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
581 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
582 res = le32_to_cpu(chip->rirb.buf[rp]);
583 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
584 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
585 else if (chip->rirb.cmds) {
586 chip->rirb.res = res;
587 smp_wmb();
588 chip->rirb.cmds--;
589 }
590 }
591 }
592
593 /* receive a response */
594 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
595 {
596 struct azx *chip = bus->private_data;
597 unsigned long timeout;
598
599 again:
600 timeout = jiffies + msecs_to_jiffies(1000);
601 for (;;) {
602 if (chip->polling_mode) {
603 spin_lock_irq(&chip->reg_lock);
604 azx_update_rirb(chip);
605 spin_unlock_irq(&chip->reg_lock);
606 }
607 if (!chip->rirb.cmds) {
608 smp_rmb();
609 return chip->rirb.res; /* the last value */
610 }
611 if (time_after(jiffies, timeout))
612 break;
613 if (bus->needs_damn_long_delay)
614 msleep(2); /* temporary workaround */
615 else {
616 udelay(10);
617 cond_resched();
618 }
619 }
620
621 if (chip->msi) {
622 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
623 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
624 free_irq(chip->irq, chip);
625 chip->irq = -1;
626 pci_disable_msi(chip->pci);
627 chip->msi = 0;
628 if (azx_acquire_irq(chip, 1) < 0)
629 return -1;
630 goto again;
631 }
632
633 if (!chip->polling_mode) {
634 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
635 "switching to polling mode: last cmd=0x%08x\n",
636 chip->last_cmd);
637 chip->polling_mode = 1;
638 goto again;
639 }
640
641 if (chip->probing) {
642 /* If this critical timeout happens during the codec probing
643 * phase, this is likely an access to a non-existing codec
644 * slot. Better to return an error and reset the system.
645 */
646 return -1;
647 }
648
649 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
650 "switching to single_cmd mode: last cmd=0x%08x\n",
651 chip->last_cmd);
652 chip->rirb.rp = azx_readb(chip, RIRBWP);
653 chip->rirb.cmds = 0;
654 /* switch to single_cmd mode */
655 chip->single_cmd = 1;
656 azx_free_cmd_io(chip);
657 return -1;
658 }
659
660 /*
661 * Use the single immediate command instead of CORB/RIRB for simplicity
662 *
663 * Note: according to Intel, this is not preferred use. The command was
664 * intended for the BIOS only, and may get confused with unsolicited
665 * responses. So, we shouldn't use it for normal operation from the
666 * driver.
667 * I left the codes, however, for debugging/testing purposes.
668 */
669
670 /* send a command */
671 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
672 {
673 struct azx *chip = bus->private_data;
674 int timeout = 50;
675
676 while (timeout--) {
677 /* check ICB busy bit */
678 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
679 /* Clear IRV valid bit */
680 azx_writew(chip, IRS, azx_readw(chip, IRS) |
681 ICH6_IRS_VALID);
682 azx_writel(chip, IC, val);
683 azx_writew(chip, IRS, azx_readw(chip, IRS) |
684 ICH6_IRS_BUSY);
685 return 0;
686 }
687 udelay(1);
688 }
689 if (printk_ratelimit())
690 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
691 azx_readw(chip, IRS), val);
692 return -EIO;
693 }
694
695 /* receive a response */
696 static unsigned int azx_single_get_response(struct hda_bus *bus)
697 {
698 struct azx *chip = bus->private_data;
699 int timeout = 50;
700
701 while (timeout--) {
702 /* check IRV busy bit */
703 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
704 return azx_readl(chip, IR);
705 udelay(1);
706 }
707 if (printk_ratelimit())
708 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
709 azx_readw(chip, IRS));
710 return (unsigned int)-1;
711 }
712
713 /*
714 * The below are the main callbacks from hda_codec.
715 *
716 * They are just the skeleton to call sub-callbacks according to the
717 * current setting of chip->single_cmd.
718 */
719
720 /* send a command */
721 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
722 {
723 struct azx *chip = bus->private_data;
724
725 chip->last_cmd = val;
726 if (chip->single_cmd)
727 return azx_single_send_cmd(bus, val);
728 else
729 return azx_corb_send_cmd(bus, val);
730 }
731
732 /* get a response */
733 static unsigned int azx_get_response(struct hda_bus *bus)
734 {
735 struct azx *chip = bus->private_data;
736 if (chip->single_cmd)
737 return azx_single_get_response(bus);
738 else
739 return azx_rirb_get_response(bus);
740 }
741
742 #ifdef CONFIG_SND_HDA_POWER_SAVE
743 static void azx_power_notify(struct hda_bus *bus);
744 #endif
745
746 /* reset codec link */
747 static int azx_reset(struct azx *chip)
748 {
749 int count;
750
751 /* clear STATESTS */
752 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
753
754 /* reset controller */
755 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
756
757 count = 50;
758 while (azx_readb(chip, GCTL) && --count)
759 msleep(1);
760
761 /* delay for >= 100us for codec PLL to settle per spec
762 * Rev 0.9 section 5.5.1
763 */
764 msleep(1);
765
766 /* Bring controller out of reset */
767 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
768
769 count = 50;
770 while (!azx_readb(chip, GCTL) && --count)
771 msleep(1);
772
773 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
774 msleep(1);
775
776 /* check to see if controller is ready */
777 if (!azx_readb(chip, GCTL)) {
778 snd_printd("azx_reset: controller not ready!\n");
779 return -EBUSY;
780 }
781
782 /* Accept unsolicited responses */
783 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
784
785 /* detect codecs */
786 if (!chip->codec_mask) {
787 chip->codec_mask = azx_readw(chip, STATESTS);
788 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
789 }
790
791 return 0;
792 }
793
794
795 /*
796 * Lowlevel interface
797 */
798
799 /* enable interrupts */
800 static void azx_int_enable(struct azx *chip)
801 {
802 /* enable controller CIE and GIE */
803 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
804 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
805 }
806
807 /* disable interrupts */
808 static void azx_int_disable(struct azx *chip)
809 {
810 int i;
811
812 /* disable interrupts in stream descriptor */
813 for (i = 0; i < chip->num_streams; i++) {
814 struct azx_dev *azx_dev = &chip->azx_dev[i];
815 azx_sd_writeb(azx_dev, SD_CTL,
816 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
817 }
818
819 /* disable SIE for all streams */
820 azx_writeb(chip, INTCTL, 0);
821
822 /* disable controller CIE and GIE */
823 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
824 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
825 }
826
827 /* clear interrupts */
828 static void azx_int_clear(struct azx *chip)
829 {
830 int i;
831
832 /* clear stream status */
833 for (i = 0; i < chip->num_streams; i++) {
834 struct azx_dev *azx_dev = &chip->azx_dev[i];
835 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
836 }
837
838 /* clear STATESTS */
839 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
840
841 /* clear rirb status */
842 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
843
844 /* clear int status */
845 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
846 }
847
848 /* start a stream */
849 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
850 {
851 /*
852 * Before stream start, initialize parameter
853 */
854 azx_dev->insufficient = 1;
855
856 /* enable SIE */
857 azx_writeb(chip, INTCTL,
858 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
859 /* set DMA start and interrupt mask */
860 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
861 SD_CTL_DMA_START | SD_INT_MASK);
862 }
863
864 /* stop DMA */
865 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
866 {
867 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
868 ~(SD_CTL_DMA_START | SD_INT_MASK));
869 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
870 }
871
872 /* stop a stream */
873 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
874 {
875 azx_stream_clear(chip, azx_dev);
876 /* disable SIE */
877 azx_writeb(chip, INTCTL,
878 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
879 }
880
881
882 /*
883 * reset and start the controller registers
884 */
885 static void azx_init_chip(struct azx *chip)
886 {
887 if (chip->initialized)
888 return;
889
890 /* reset controller */
891 azx_reset(chip);
892
893 /* initialize interrupts */
894 azx_int_clear(chip);
895 azx_int_enable(chip);
896
897 /* initialize the codec command I/O */
898 if (!chip->single_cmd)
899 azx_init_cmd_io(chip);
900
901 /* program the position buffer */
902 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
903 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
904
905 chip->initialized = 1;
906 }
907
908 /*
909 * initialize the PCI registers
910 */
911 /* update bits in a PCI register byte */
912 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
913 unsigned char mask, unsigned char val)
914 {
915 unsigned char data;
916
917 pci_read_config_byte(pci, reg, &data);
918 data &= ~mask;
919 data |= (val & mask);
920 pci_write_config_byte(pci, reg, data);
921 }
922
923 static void azx_init_pci(struct azx *chip)
924 {
925 unsigned short snoop;
926
927 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
928 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
929 * Ensuring these bits are 0 clears playback static on some HD Audio
930 * codecs
931 */
932 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
933
934 switch (chip->driver_type) {
935 case AZX_DRIVER_ATI:
936 /* For ATI SB450 azalia HD audio, we need to enable snoop */
937 update_pci_byte(chip->pci,
938 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
939 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
940 break;
941 case AZX_DRIVER_NVIDIA:
942 /* For NVIDIA HDA, enable snoop */
943 update_pci_byte(chip->pci,
944 NVIDIA_HDA_TRANSREG_ADDR,
945 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
946 update_pci_byte(chip->pci,
947 NVIDIA_HDA_ISTRM_COH,
948 0x01, NVIDIA_HDA_ENABLE_COHBIT);
949 update_pci_byte(chip->pci,
950 NVIDIA_HDA_OSTRM_COH,
951 0x01, NVIDIA_HDA_ENABLE_COHBIT);
952 break;
953 case AZX_DRIVER_SCH:
954 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
955 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
956 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
957 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
958 pci_read_config_word(chip->pci,
959 INTEL_SCH_HDA_DEVC, &snoop);
960 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
961 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
962 ? "Failed" : "OK");
963 }
964 break;
965
966 }
967 }
968
969
970 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
971
972 /*
973 * interrupt handler
974 */
975 static irqreturn_t azx_interrupt(int irq, void *dev_id)
976 {
977 struct azx *chip = dev_id;
978 struct azx_dev *azx_dev;
979 u32 status;
980 int i, ok;
981
982 spin_lock(&chip->reg_lock);
983
984 status = azx_readl(chip, INTSTS);
985 if (status == 0) {
986 spin_unlock(&chip->reg_lock);
987 return IRQ_NONE;
988 }
989
990 for (i = 0; i < chip->num_streams; i++) {
991 azx_dev = &chip->azx_dev[i];
992 if (status & azx_dev->sd_int_sta_mask) {
993 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
994 if (!azx_dev->substream || !azx_dev->running)
995 continue;
996 /* check whether this IRQ is really acceptable */
997 ok = azx_position_ok(chip, azx_dev);
998 if (ok == 1) {
999 azx_dev->irq_pending = 0;
1000 spin_unlock(&chip->reg_lock);
1001 snd_pcm_period_elapsed(azx_dev->substream);
1002 spin_lock(&chip->reg_lock);
1003 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1004 /* bogus IRQ, process it later */
1005 azx_dev->irq_pending = 1;
1006 queue_work(chip->bus->workq,
1007 &chip->irq_pending_work);
1008 }
1009 }
1010 }
1011
1012 /* clear rirb int */
1013 status = azx_readb(chip, RIRBSTS);
1014 if (status & RIRB_INT_MASK) {
1015 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1016 azx_update_rirb(chip);
1017 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1018 }
1019
1020 #if 0
1021 /* clear state status int */
1022 if (azx_readb(chip, STATESTS) & 0x04)
1023 azx_writeb(chip, STATESTS, 0x04);
1024 #endif
1025 spin_unlock(&chip->reg_lock);
1026
1027 return IRQ_HANDLED;
1028 }
1029
1030
1031 /*
1032 * set up a BDL entry
1033 */
1034 static int setup_bdle(struct snd_pcm_substream *substream,
1035 struct azx_dev *azx_dev, u32 **bdlp,
1036 int ofs, int size, int with_ioc)
1037 {
1038 u32 *bdl = *bdlp;
1039
1040 while (size > 0) {
1041 dma_addr_t addr;
1042 int chunk;
1043
1044 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1045 return -EINVAL;
1046
1047 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1048 /* program the address field of the BDL entry */
1049 bdl[0] = cpu_to_le32((u32)addr);
1050 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1051 /* program the size field of the BDL entry */
1052 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1053 bdl[2] = cpu_to_le32(chunk);
1054 /* program the IOC to enable interrupt
1055 * only when the whole fragment is processed
1056 */
1057 size -= chunk;
1058 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1059 bdl += 4;
1060 azx_dev->frags++;
1061 ofs += chunk;
1062 }
1063 *bdlp = bdl;
1064 return ofs;
1065 }
1066
1067 /*
1068 * set up BDL entries
1069 */
1070 static int azx_setup_periods(struct azx *chip,
1071 struct snd_pcm_substream *substream,
1072 struct azx_dev *azx_dev)
1073 {
1074 u32 *bdl;
1075 int i, ofs, periods, period_bytes;
1076 int pos_adj;
1077
1078 /* reset BDL address */
1079 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1080 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1081
1082 period_bytes = azx_dev->period_bytes;
1083 periods = azx_dev->bufsize / period_bytes;
1084
1085 /* program the initial BDL entries */
1086 bdl = (u32 *)azx_dev->bdl.area;
1087 ofs = 0;
1088 azx_dev->frags = 0;
1089 pos_adj = bdl_pos_adj[chip->dev_index];
1090 if (pos_adj > 0) {
1091 struct snd_pcm_runtime *runtime = substream->runtime;
1092 int pos_align = pos_adj;
1093 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1094 if (!pos_adj)
1095 pos_adj = pos_align;
1096 else
1097 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1098 pos_align;
1099 pos_adj = frames_to_bytes(runtime, pos_adj);
1100 if (pos_adj >= period_bytes) {
1101 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1102 bdl_pos_adj[chip->dev_index]);
1103 pos_adj = 0;
1104 } else {
1105 ofs = setup_bdle(substream, azx_dev,
1106 &bdl, ofs, pos_adj, 1);
1107 if (ofs < 0)
1108 goto error;
1109 }
1110 } else
1111 pos_adj = 0;
1112 for (i = 0; i < periods; i++) {
1113 if (i == periods - 1 && pos_adj)
1114 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1115 period_bytes - pos_adj, 0);
1116 else
1117 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1118 period_bytes, 1);
1119 if (ofs < 0)
1120 goto error;
1121 }
1122 return 0;
1123
1124 error:
1125 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1126 azx_dev->bufsize, period_bytes);
1127 return -EINVAL;
1128 }
1129
1130 /* reset stream */
1131 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1132 {
1133 unsigned char val;
1134 int timeout;
1135
1136 azx_stream_clear(chip, azx_dev);
1137
1138 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1139 SD_CTL_STREAM_RESET);
1140 udelay(3);
1141 timeout = 300;
1142 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1143 --timeout)
1144 ;
1145 val &= ~SD_CTL_STREAM_RESET;
1146 azx_sd_writeb(azx_dev, SD_CTL, val);
1147 udelay(3);
1148
1149 timeout = 300;
1150 /* waiting for hardware to report that the stream is out of reset */
1151 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1152 --timeout)
1153 ;
1154
1155 /* reset first position - may not be synced with hw at this time */
1156 *azx_dev->posbuf = 0;
1157 }
1158
1159 /*
1160 * set up the SD for streaming
1161 */
1162 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1163 {
1164 /* make sure the run bit is zero for SD */
1165 azx_stream_clear(chip, azx_dev);
1166 /* program the stream_tag */
1167 azx_sd_writel(azx_dev, SD_CTL,
1168 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1169 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1170
1171 /* program the length of samples in cyclic buffer */
1172 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1173
1174 /* program the stream format */
1175 /* this value needs to be the same as the one programmed */
1176 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1177
1178 /* program the stream LVI (last valid index) of the BDL */
1179 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1180
1181 /* program the BDL address */
1182 /* lower BDL address */
1183 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1184 /* upper BDL address */
1185 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1186
1187 /* enable the position buffer */
1188 if (chip->position_fix == POS_FIX_POSBUF ||
1189 chip->position_fix == POS_FIX_AUTO ||
1190 chip->via_dmapos_patch) {
1191 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1192 azx_writel(chip, DPLBASE,
1193 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1194 }
1195
1196 /* set the interrupt enable bits in the descriptor control register */
1197 azx_sd_writel(azx_dev, SD_CTL,
1198 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1199
1200 return 0;
1201 }
1202
1203 /*
1204 * Probe the given codec address
1205 */
1206 static int probe_codec(struct azx *chip, int addr)
1207 {
1208 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1209 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1210 unsigned int res;
1211
1212 chip->probing = 1;
1213 azx_send_cmd(chip->bus, cmd);
1214 res = azx_get_response(chip->bus);
1215 chip->probing = 0;
1216 if (res == -1)
1217 return -EIO;
1218 snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1219 return 0;
1220 }
1221
1222 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1223 struct hda_pcm *cpcm);
1224 static void azx_stop_chip(struct azx *chip);
1225
1226 /*
1227 * Codec initialization
1228 */
1229
1230 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1231 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1232 [AZX_DRIVER_TERA] = 1,
1233 };
1234
1235 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1236 int no_init)
1237 {
1238 struct hda_bus_template bus_temp;
1239 int c, codecs, err;
1240 int max_slots;
1241
1242 memset(&bus_temp, 0, sizeof(bus_temp));
1243 bus_temp.private_data = chip;
1244 bus_temp.modelname = model;
1245 bus_temp.pci = chip->pci;
1246 bus_temp.ops.command = azx_send_cmd;
1247 bus_temp.ops.get_response = azx_get_response;
1248 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1249 #ifdef CONFIG_SND_HDA_POWER_SAVE
1250 bus_temp.power_save = &power_save;
1251 bus_temp.ops.pm_notify = azx_power_notify;
1252 #endif
1253
1254 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1255 if (err < 0)
1256 return err;
1257
1258 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1259 chip->bus->needs_damn_long_delay = 1;
1260
1261 codecs = 0;
1262 max_slots = azx_max_codecs[chip->driver_type];
1263 if (!max_slots)
1264 max_slots = AZX_MAX_CODECS;
1265
1266 /* First try to probe all given codec slots */
1267 for (c = 0; c < max_slots; c++) {
1268 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1269 if (probe_codec(chip, c) < 0) {
1270 /* Some BIOSen give you wrong codec addresses
1271 * that don't exist
1272 */
1273 snd_printk(KERN_WARNING
1274 "hda_intel: Codec #%d probe error; "
1275 "disabling it...\n", c);
1276 chip->codec_mask &= ~(1 << c);
1277 /* More badly, accessing to a non-existing
1278 * codec often screws up the controller chip,
1279 * and distrubs the further communications.
1280 * Thus if an error occurs during probing,
1281 * better to reset the controller chip to
1282 * get back to the sanity state.
1283 */
1284 azx_stop_chip(chip);
1285 azx_init_chip(chip);
1286 }
1287 }
1288 }
1289
1290 /* Then create codec instances */
1291 for (c = 0; c < max_slots; c++) {
1292 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1293 struct hda_codec *codec;
1294 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1295 if (err < 0)
1296 continue;
1297 codecs++;
1298 }
1299 }
1300 if (!codecs) {
1301 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1302 return -ENXIO;
1303 }
1304
1305 return 0;
1306 }
1307
1308
1309 /*
1310 * PCM support
1311 */
1312
1313 /* assign a stream for the PCM */
1314 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1315 {
1316 int dev, i, nums;
1317 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1318 dev = chip->playback_index_offset;
1319 nums = chip->playback_streams;
1320 } else {
1321 dev = chip->capture_index_offset;
1322 nums = chip->capture_streams;
1323 }
1324 for (i = 0; i < nums; i++, dev++)
1325 if (!chip->azx_dev[dev].opened) {
1326 chip->azx_dev[dev].opened = 1;
1327 return &chip->azx_dev[dev];
1328 }
1329 return NULL;
1330 }
1331
1332 /* release the assigned stream */
1333 static inline void azx_release_device(struct azx_dev *azx_dev)
1334 {
1335 azx_dev->opened = 0;
1336 }
1337
1338 static struct snd_pcm_hardware azx_pcm_hw = {
1339 .info = (SNDRV_PCM_INFO_MMAP |
1340 SNDRV_PCM_INFO_INTERLEAVED |
1341 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1342 SNDRV_PCM_INFO_MMAP_VALID |
1343 /* No full-resume yet implemented */
1344 /* SNDRV_PCM_INFO_RESUME |*/
1345 SNDRV_PCM_INFO_PAUSE |
1346 SNDRV_PCM_INFO_SYNC_START),
1347 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1348 .rates = SNDRV_PCM_RATE_48000,
1349 .rate_min = 48000,
1350 .rate_max = 48000,
1351 .channels_min = 2,
1352 .channels_max = 2,
1353 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1354 .period_bytes_min = 128,
1355 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1356 .periods_min = 2,
1357 .periods_max = AZX_MAX_FRAG,
1358 .fifo_size = 0,
1359 };
1360
1361 struct azx_pcm {
1362 struct azx *chip;
1363 struct hda_codec *codec;
1364 struct hda_pcm_stream *hinfo[2];
1365 };
1366
1367 static int azx_pcm_open(struct snd_pcm_substream *substream)
1368 {
1369 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1370 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1371 struct azx *chip = apcm->chip;
1372 struct azx_dev *azx_dev;
1373 struct snd_pcm_runtime *runtime = substream->runtime;
1374 unsigned long flags;
1375 int err;
1376
1377 mutex_lock(&chip->open_mutex);
1378 azx_dev = azx_assign_device(chip, substream->stream);
1379 if (azx_dev == NULL) {
1380 mutex_unlock(&chip->open_mutex);
1381 return -EBUSY;
1382 }
1383 runtime->hw = azx_pcm_hw;
1384 runtime->hw.channels_min = hinfo->channels_min;
1385 runtime->hw.channels_max = hinfo->channels_max;
1386 runtime->hw.formats = hinfo->formats;
1387 runtime->hw.rates = hinfo->rates;
1388 snd_pcm_limit_hw_rates(runtime);
1389 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1390 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1391 128);
1392 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1393 128);
1394 snd_hda_power_up(apcm->codec);
1395 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1396 if (err < 0) {
1397 azx_release_device(azx_dev);
1398 snd_hda_power_down(apcm->codec);
1399 mutex_unlock(&chip->open_mutex);
1400 return err;
1401 }
1402 spin_lock_irqsave(&chip->reg_lock, flags);
1403 azx_dev->substream = substream;
1404 azx_dev->running = 0;
1405 spin_unlock_irqrestore(&chip->reg_lock, flags);
1406
1407 runtime->private_data = azx_dev;
1408 snd_pcm_set_sync(substream);
1409 mutex_unlock(&chip->open_mutex);
1410
1411 return 0;
1412 }
1413
1414 static int azx_pcm_close(struct snd_pcm_substream *substream)
1415 {
1416 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1417 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1418 struct azx *chip = apcm->chip;
1419 struct azx_dev *azx_dev = get_azx_dev(substream);
1420 unsigned long flags;
1421
1422 mutex_lock(&chip->open_mutex);
1423 spin_lock_irqsave(&chip->reg_lock, flags);
1424 azx_dev->substream = NULL;
1425 azx_dev->running = 0;
1426 spin_unlock_irqrestore(&chip->reg_lock, flags);
1427 azx_release_device(azx_dev);
1428 hinfo->ops.close(hinfo, apcm->codec, substream);
1429 snd_hda_power_down(apcm->codec);
1430 mutex_unlock(&chip->open_mutex);
1431 return 0;
1432 }
1433
1434 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1435 struct snd_pcm_hw_params *hw_params)
1436 {
1437 struct azx_dev *azx_dev = get_azx_dev(substream);
1438
1439 azx_dev->bufsize = 0;
1440 azx_dev->period_bytes = 0;
1441 azx_dev->format_val = 0;
1442 return snd_pcm_lib_malloc_pages(substream,
1443 params_buffer_bytes(hw_params));
1444 }
1445
1446 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1447 {
1448 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1449 struct azx_dev *azx_dev = get_azx_dev(substream);
1450 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1451
1452 /* reset BDL address */
1453 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1454 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1455 azx_sd_writel(azx_dev, SD_CTL, 0);
1456 azx_dev->bufsize = 0;
1457 azx_dev->period_bytes = 0;
1458 azx_dev->format_val = 0;
1459
1460 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1461
1462 return snd_pcm_lib_free_pages(substream);
1463 }
1464
1465 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1466 {
1467 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1468 struct azx *chip = apcm->chip;
1469 struct azx_dev *azx_dev = get_azx_dev(substream);
1470 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1471 struct snd_pcm_runtime *runtime = substream->runtime;
1472 unsigned int bufsize, period_bytes, format_val;
1473 int err;
1474
1475 azx_stream_reset(chip, azx_dev);
1476 format_val = snd_hda_calc_stream_format(runtime->rate,
1477 runtime->channels,
1478 runtime->format,
1479 hinfo->maxbps);
1480 if (!format_val) {
1481 snd_printk(KERN_ERR SFX
1482 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1483 runtime->rate, runtime->channels, runtime->format);
1484 return -EINVAL;
1485 }
1486
1487 bufsize = snd_pcm_lib_buffer_bytes(substream);
1488 period_bytes = snd_pcm_lib_period_bytes(substream);
1489
1490 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1491 bufsize, format_val);
1492
1493 if (bufsize != azx_dev->bufsize ||
1494 period_bytes != azx_dev->period_bytes ||
1495 format_val != azx_dev->format_val) {
1496 azx_dev->bufsize = bufsize;
1497 azx_dev->period_bytes = period_bytes;
1498 azx_dev->format_val = format_val;
1499 err = azx_setup_periods(chip, substream, azx_dev);
1500 if (err < 0)
1501 return err;
1502 }
1503
1504 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1505 (runtime->rate * 2);
1506 azx_setup_controller(chip, azx_dev);
1507 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1508 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1509 else
1510 azx_dev->fifo_size = 0;
1511
1512 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1513 azx_dev->format_val, substream);
1514 }
1515
1516 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1517 {
1518 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1519 struct azx *chip = apcm->chip;
1520 struct azx_dev *azx_dev;
1521 struct snd_pcm_substream *s;
1522 int rstart = 0, start, nsync = 0, sbits = 0;
1523 int nwait, timeout;
1524
1525 switch (cmd) {
1526 case SNDRV_PCM_TRIGGER_START:
1527 rstart = 1;
1528 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1529 case SNDRV_PCM_TRIGGER_RESUME:
1530 start = 1;
1531 break;
1532 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1533 case SNDRV_PCM_TRIGGER_SUSPEND:
1534 case SNDRV_PCM_TRIGGER_STOP:
1535 start = 0;
1536 break;
1537 default:
1538 return -EINVAL;
1539 }
1540
1541 snd_pcm_group_for_each_entry(s, substream) {
1542 if (s->pcm->card != substream->pcm->card)
1543 continue;
1544 azx_dev = get_azx_dev(s);
1545 sbits |= 1 << azx_dev->index;
1546 nsync++;
1547 snd_pcm_trigger_done(s, substream);
1548 }
1549
1550 spin_lock(&chip->reg_lock);
1551 if (nsync > 1) {
1552 /* first, set SYNC bits of corresponding streams */
1553 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1554 }
1555 snd_pcm_group_for_each_entry(s, substream) {
1556 if (s->pcm->card != substream->pcm->card)
1557 continue;
1558 azx_dev = get_azx_dev(s);
1559 if (rstart) {
1560 azx_dev->start_flag = 1;
1561 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1562 }
1563 if (start)
1564 azx_stream_start(chip, azx_dev);
1565 else
1566 azx_stream_stop(chip, azx_dev);
1567 azx_dev->running = start;
1568 }
1569 spin_unlock(&chip->reg_lock);
1570 if (start) {
1571 if (nsync == 1)
1572 return 0;
1573 /* wait until all FIFOs get ready */
1574 for (timeout = 5000; timeout; timeout--) {
1575 nwait = 0;
1576 snd_pcm_group_for_each_entry(s, substream) {
1577 if (s->pcm->card != substream->pcm->card)
1578 continue;
1579 azx_dev = get_azx_dev(s);
1580 if (!(azx_sd_readb(azx_dev, SD_STS) &
1581 SD_STS_FIFO_READY))
1582 nwait++;
1583 }
1584 if (!nwait)
1585 break;
1586 cpu_relax();
1587 }
1588 } else {
1589 /* wait until all RUN bits are cleared */
1590 for (timeout = 5000; timeout; timeout--) {
1591 nwait = 0;
1592 snd_pcm_group_for_each_entry(s, substream) {
1593 if (s->pcm->card != substream->pcm->card)
1594 continue;
1595 azx_dev = get_azx_dev(s);
1596 if (azx_sd_readb(azx_dev, SD_CTL) &
1597 SD_CTL_DMA_START)
1598 nwait++;
1599 }
1600 if (!nwait)
1601 break;
1602 cpu_relax();
1603 }
1604 }
1605 if (nsync > 1) {
1606 spin_lock(&chip->reg_lock);
1607 /* reset SYNC bits */
1608 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1609 spin_unlock(&chip->reg_lock);
1610 }
1611 return 0;
1612 }
1613
1614 /* get the current DMA position with correction on VIA chips */
1615 static unsigned int azx_via_get_position(struct azx *chip,
1616 struct azx_dev *azx_dev)
1617 {
1618 unsigned int link_pos, mini_pos, bound_pos;
1619 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1620 unsigned int fifo_size;
1621
1622 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1623 if (azx_dev->index >= 4) {
1624 /* Playback, no problem using link position */
1625 return link_pos;
1626 }
1627
1628 /* Capture */
1629 /* For new chipset,
1630 * use mod to get the DMA position just like old chipset
1631 */
1632 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1633 mod_dma_pos %= azx_dev->period_bytes;
1634
1635 /* azx_dev->fifo_size can't get FIFO size of in stream.
1636 * Get from base address + offset.
1637 */
1638 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1639
1640 if (azx_dev->insufficient) {
1641 /* Link position never gather than FIFO size */
1642 if (link_pos <= fifo_size)
1643 return 0;
1644
1645 azx_dev->insufficient = 0;
1646 }
1647
1648 if (link_pos <= fifo_size)
1649 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1650 else
1651 mini_pos = link_pos - fifo_size;
1652
1653 /* Find nearest previous boudary */
1654 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1655 mod_link_pos = link_pos % azx_dev->period_bytes;
1656 if (mod_link_pos >= fifo_size)
1657 bound_pos = link_pos - mod_link_pos;
1658 else if (mod_dma_pos >= mod_mini_pos)
1659 bound_pos = mini_pos - mod_mini_pos;
1660 else {
1661 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1662 if (bound_pos >= azx_dev->bufsize)
1663 bound_pos = 0;
1664 }
1665
1666 /* Calculate real DMA position we want */
1667 return bound_pos + mod_dma_pos;
1668 }
1669
1670 static unsigned int azx_get_position(struct azx *chip,
1671 struct azx_dev *azx_dev)
1672 {
1673 unsigned int pos;
1674
1675 if (chip->via_dmapos_patch)
1676 pos = azx_via_get_position(chip, azx_dev);
1677 else if (chip->position_fix == POS_FIX_POSBUF ||
1678 chip->position_fix == POS_FIX_AUTO) {
1679 /* use the position buffer */
1680 pos = le32_to_cpu(*azx_dev->posbuf);
1681 } else {
1682 /* read LPIB */
1683 pos = azx_sd_readl(azx_dev, SD_LPIB);
1684 }
1685 if (pos >= azx_dev->bufsize)
1686 pos = 0;
1687 return pos;
1688 }
1689
1690 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1691 {
1692 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1693 struct azx *chip = apcm->chip;
1694 struct azx_dev *azx_dev = get_azx_dev(substream);
1695 return bytes_to_frames(substream->runtime,
1696 azx_get_position(chip, azx_dev));
1697 }
1698
1699 /*
1700 * Check whether the current DMA position is acceptable for updating
1701 * periods. Returns non-zero if it's OK.
1702 *
1703 * Many HD-audio controllers appear pretty inaccurate about
1704 * the update-IRQ timing. The IRQ is issued before actually the
1705 * data is processed. So, we need to process it afterwords in a
1706 * workqueue.
1707 */
1708 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1709 {
1710 unsigned int pos;
1711
1712 if (azx_dev->start_flag &&
1713 time_before_eq(jiffies, azx_dev->start_jiffies))
1714 return -1; /* bogus (too early) interrupt */
1715 azx_dev->start_flag = 0;
1716
1717 pos = azx_get_position(chip, azx_dev);
1718 if (chip->position_fix == POS_FIX_AUTO) {
1719 if (!pos) {
1720 printk(KERN_WARNING
1721 "hda-intel: Invalid position buffer, "
1722 "using LPIB read method instead.\n");
1723 chip->position_fix = POS_FIX_LPIB;
1724 pos = azx_get_position(chip, azx_dev);
1725 } else
1726 chip->position_fix = POS_FIX_POSBUF;
1727 }
1728
1729 if (!bdl_pos_adj[chip->dev_index])
1730 return 1; /* no delayed ack */
1731 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1732 return 0; /* NG - it's below the period boundary */
1733 return 1; /* OK, it's fine */
1734 }
1735
1736 /*
1737 * The work for pending PCM period updates.
1738 */
1739 static void azx_irq_pending_work(struct work_struct *work)
1740 {
1741 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1742 int i, pending;
1743
1744 if (!chip->irq_pending_warned) {
1745 printk(KERN_WARNING
1746 "hda-intel: IRQ timing workaround is activated "
1747 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1748 chip->card->number);
1749 chip->irq_pending_warned = 1;
1750 }
1751
1752 for (;;) {
1753 pending = 0;
1754 spin_lock_irq(&chip->reg_lock);
1755 for (i = 0; i < chip->num_streams; i++) {
1756 struct azx_dev *azx_dev = &chip->azx_dev[i];
1757 if (!azx_dev->irq_pending ||
1758 !azx_dev->substream ||
1759 !azx_dev->running)
1760 continue;
1761 if (azx_position_ok(chip, azx_dev)) {
1762 azx_dev->irq_pending = 0;
1763 spin_unlock(&chip->reg_lock);
1764 snd_pcm_period_elapsed(azx_dev->substream);
1765 spin_lock(&chip->reg_lock);
1766 } else
1767 pending++;
1768 }
1769 spin_unlock_irq(&chip->reg_lock);
1770 if (!pending)
1771 return;
1772 cond_resched();
1773 }
1774 }
1775
1776 /* clear irq_pending flags and assure no on-going workq */
1777 static void azx_clear_irq_pending(struct azx *chip)
1778 {
1779 int i;
1780
1781 spin_lock_irq(&chip->reg_lock);
1782 for (i = 0; i < chip->num_streams; i++)
1783 chip->azx_dev[i].irq_pending = 0;
1784 spin_unlock_irq(&chip->reg_lock);
1785 }
1786
1787 static struct snd_pcm_ops azx_pcm_ops = {
1788 .open = azx_pcm_open,
1789 .close = azx_pcm_close,
1790 .ioctl = snd_pcm_lib_ioctl,
1791 .hw_params = azx_pcm_hw_params,
1792 .hw_free = azx_pcm_hw_free,
1793 .prepare = azx_pcm_prepare,
1794 .trigger = azx_pcm_trigger,
1795 .pointer = azx_pcm_pointer,
1796 .page = snd_pcm_sgbuf_ops_page,
1797 };
1798
1799 static void azx_pcm_free(struct snd_pcm *pcm)
1800 {
1801 struct azx_pcm *apcm = pcm->private_data;
1802 if (apcm) {
1803 apcm->chip->pcm[pcm->device] = NULL;
1804 kfree(apcm);
1805 }
1806 }
1807
1808 static int
1809 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1810 struct hda_pcm *cpcm)
1811 {
1812 struct azx *chip = bus->private_data;
1813 struct snd_pcm *pcm;
1814 struct azx_pcm *apcm;
1815 int pcm_dev = cpcm->device;
1816 int s, err;
1817
1818 if (pcm_dev >= AZX_MAX_PCMS) {
1819 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1820 pcm_dev);
1821 return -EINVAL;
1822 }
1823 if (chip->pcm[pcm_dev]) {
1824 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1825 return -EBUSY;
1826 }
1827 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1828 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1829 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1830 &pcm);
1831 if (err < 0)
1832 return err;
1833 strcpy(pcm->name, cpcm->name);
1834 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1835 if (apcm == NULL)
1836 return -ENOMEM;
1837 apcm->chip = chip;
1838 apcm->codec = codec;
1839 pcm->private_data = apcm;
1840 pcm->private_free = azx_pcm_free;
1841 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1842 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1843 chip->pcm[pcm_dev] = pcm;
1844 cpcm->pcm = pcm;
1845 for (s = 0; s < 2; s++) {
1846 apcm->hinfo[s] = &cpcm->stream[s];
1847 if (cpcm->stream[s].substreams)
1848 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1849 }
1850 /* buffer pre-allocation */
1851 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1852 snd_dma_pci_data(chip->pci),
1853 1024 * 64, 32 * 1024 * 1024);
1854 return 0;
1855 }
1856
1857 /*
1858 * mixer creation - all stuff is implemented in hda module
1859 */
1860 static int __devinit azx_mixer_create(struct azx *chip)
1861 {
1862 return snd_hda_build_controls(chip->bus);
1863 }
1864
1865
1866 /*
1867 * initialize SD streams
1868 */
1869 static int __devinit azx_init_stream(struct azx *chip)
1870 {
1871 int i;
1872
1873 /* initialize each stream (aka device)
1874 * assign the starting bdl address to each stream (device)
1875 * and initialize
1876 */
1877 for (i = 0; i < chip->num_streams; i++) {
1878 struct azx_dev *azx_dev = &chip->azx_dev[i];
1879 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1880 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1881 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1882 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1883 azx_dev->sd_int_sta_mask = 1 << i;
1884 /* stream tag: must be non-zero and unique */
1885 azx_dev->index = i;
1886 azx_dev->stream_tag = i + 1;
1887 }
1888
1889 return 0;
1890 }
1891
1892 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1893 {
1894 if (request_irq(chip->pci->irq, azx_interrupt,
1895 chip->msi ? 0 : IRQF_SHARED,
1896 "HDA Intel", chip)) {
1897 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1898 "disabling device\n", chip->pci->irq);
1899 if (do_disconnect)
1900 snd_card_disconnect(chip->card);
1901 return -1;
1902 }
1903 chip->irq = chip->pci->irq;
1904 pci_intx(chip->pci, !chip->msi);
1905 return 0;
1906 }
1907
1908
1909 static void azx_stop_chip(struct azx *chip)
1910 {
1911 if (!chip->initialized)
1912 return;
1913
1914 /* disable interrupts */
1915 azx_int_disable(chip);
1916 azx_int_clear(chip);
1917
1918 /* disable CORB/RIRB */
1919 azx_free_cmd_io(chip);
1920
1921 /* disable position buffer */
1922 azx_writel(chip, DPLBASE, 0);
1923 azx_writel(chip, DPUBASE, 0);
1924
1925 chip->initialized = 0;
1926 }
1927
1928 #ifdef CONFIG_SND_HDA_POWER_SAVE
1929 /* power-up/down the controller */
1930 static void azx_power_notify(struct hda_bus *bus)
1931 {
1932 struct azx *chip = bus->private_data;
1933 struct hda_codec *c;
1934 int power_on = 0;
1935
1936 list_for_each_entry(c, &bus->codec_list, list) {
1937 if (c->power_on) {
1938 power_on = 1;
1939 break;
1940 }
1941 }
1942 if (power_on)
1943 azx_init_chip(chip);
1944 else if (chip->running && power_save_controller)
1945 azx_stop_chip(chip);
1946 }
1947 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1948
1949 #ifdef CONFIG_PM
1950 /*
1951 * power management
1952 */
1953
1954 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1955 {
1956 struct hda_codec *codec;
1957
1958 list_for_each_entry(codec, &bus->codec_list, list) {
1959 if (snd_hda_codec_needs_resume(codec))
1960 return 1;
1961 }
1962 return 0;
1963 }
1964
1965 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1966 {
1967 struct snd_card *card = pci_get_drvdata(pci);
1968 struct azx *chip = card->private_data;
1969 int i;
1970
1971 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1972 azx_clear_irq_pending(chip);
1973 for (i = 0; i < AZX_MAX_PCMS; i++)
1974 snd_pcm_suspend_all(chip->pcm[i]);
1975 if (chip->initialized)
1976 snd_hda_suspend(chip->bus, state);
1977 azx_stop_chip(chip);
1978 if (chip->irq >= 0) {
1979 free_irq(chip->irq, chip);
1980 chip->irq = -1;
1981 }
1982 if (chip->msi)
1983 pci_disable_msi(chip->pci);
1984 pci_disable_device(pci);
1985 pci_save_state(pci);
1986 pci_set_power_state(pci, pci_choose_state(pci, state));
1987 return 0;
1988 }
1989
1990 static int azx_resume(struct pci_dev *pci)
1991 {
1992 struct snd_card *card = pci_get_drvdata(pci);
1993 struct azx *chip = card->private_data;
1994
1995 pci_set_power_state(pci, PCI_D0);
1996 pci_restore_state(pci);
1997 if (pci_enable_device(pci) < 0) {
1998 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1999 "disabling device\n");
2000 snd_card_disconnect(card);
2001 return -EIO;
2002 }
2003 pci_set_master(pci);
2004 if (chip->msi)
2005 if (pci_enable_msi(pci) < 0)
2006 chip->msi = 0;
2007 if (azx_acquire_irq(chip, 1) < 0)
2008 return -EIO;
2009 azx_init_pci(chip);
2010
2011 if (snd_hda_codecs_inuse(chip->bus))
2012 azx_init_chip(chip);
2013
2014 snd_hda_resume(chip->bus);
2015 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2016 return 0;
2017 }
2018 #endif /* CONFIG_PM */
2019
2020
2021 /*
2022 * reboot notifier for hang-up problem at power-down
2023 */
2024 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2025 {
2026 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2027 azx_stop_chip(chip);
2028 return NOTIFY_OK;
2029 }
2030
2031 static void azx_notifier_register(struct azx *chip)
2032 {
2033 chip->reboot_notifier.notifier_call = azx_halt;
2034 register_reboot_notifier(&chip->reboot_notifier);
2035 }
2036
2037 static void azx_notifier_unregister(struct azx *chip)
2038 {
2039 if (chip->reboot_notifier.notifier_call)
2040 unregister_reboot_notifier(&chip->reboot_notifier);
2041 }
2042
2043 /*
2044 * destructor
2045 */
2046 static int azx_free(struct azx *chip)
2047 {
2048 int i;
2049
2050 azx_notifier_unregister(chip);
2051
2052 if (chip->initialized) {
2053 azx_clear_irq_pending(chip);
2054 for (i = 0; i < chip->num_streams; i++)
2055 azx_stream_stop(chip, &chip->azx_dev[i]);
2056 azx_stop_chip(chip);
2057 }
2058
2059 if (chip->irq >= 0)
2060 free_irq(chip->irq, (void*)chip);
2061 if (chip->msi)
2062 pci_disable_msi(chip->pci);
2063 if (chip->remap_addr)
2064 iounmap(chip->remap_addr);
2065
2066 if (chip->azx_dev) {
2067 for (i = 0; i < chip->num_streams; i++)
2068 if (chip->azx_dev[i].bdl.area)
2069 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2070 }
2071 if (chip->rb.area)
2072 snd_dma_free_pages(&chip->rb);
2073 if (chip->posbuf.area)
2074 snd_dma_free_pages(&chip->posbuf);
2075 pci_release_regions(chip->pci);
2076 pci_disable_device(chip->pci);
2077 kfree(chip->azx_dev);
2078 kfree(chip);
2079
2080 return 0;
2081 }
2082
2083 static int azx_dev_free(struct snd_device *device)
2084 {
2085 return azx_free(device->device_data);
2086 }
2087
2088 /*
2089 * white/black-listing for position_fix
2090 */
2091 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2092 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2093 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2094 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2095 {}
2096 };
2097
2098 static int __devinit check_position_fix(struct azx *chip, int fix)
2099 {
2100 const struct snd_pci_quirk *q;
2101
2102 switch (fix) {
2103 case POS_FIX_LPIB:
2104 case POS_FIX_POSBUF:
2105 return fix;
2106 }
2107
2108 /* Check VIA/ATI HD Audio Controller exist */
2109 switch (chip->driver_type) {
2110 case AZX_DRIVER_VIA:
2111 case AZX_DRIVER_ATI:
2112 chip->via_dmapos_patch = 1;
2113 /* Use link position directly, avoid any transfer problem. */
2114 return POS_FIX_LPIB;
2115 }
2116 chip->via_dmapos_patch = 0;
2117
2118 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2119 if (q) {
2120 printk(KERN_INFO
2121 "hda_intel: position_fix set to %d "
2122 "for device %04x:%04x\n",
2123 q->value, q->subvendor, q->subdevice);
2124 return q->value;
2125 }
2126 return POS_FIX_AUTO;
2127 }
2128
2129 /*
2130 * black-lists for probe_mask
2131 */
2132 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2133 /* Thinkpad often breaks the controller communication when accessing
2134 * to the non-working (or non-existing) modem codec slot.
2135 */
2136 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2137 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2138 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2139 /* broken BIOS */
2140 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2141 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2142 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2143 /* forced codec slots */
2144 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2145 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2146 {}
2147 };
2148
2149 #define AZX_FORCE_CODEC_MASK 0x100
2150
2151 static void __devinit check_probe_mask(struct azx *chip, int dev)
2152 {
2153 const struct snd_pci_quirk *q;
2154
2155 chip->codec_probe_mask = probe_mask[dev];
2156 if (chip->codec_probe_mask == -1) {
2157 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2158 if (q) {
2159 printk(KERN_INFO
2160 "hda_intel: probe_mask set to 0x%x "
2161 "for device %04x:%04x\n",
2162 q->value, q->subvendor, q->subdevice);
2163 chip->codec_probe_mask = q->value;
2164 }
2165 }
2166
2167 /* check forced option */
2168 if (chip->codec_probe_mask != -1 &&
2169 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2170 chip->codec_mask = chip->codec_probe_mask & 0xff;
2171 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2172 chip->codec_mask);
2173 }
2174 }
2175
2176
2177 /*
2178 * constructor
2179 */
2180 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2181 int dev, int driver_type,
2182 struct azx **rchip)
2183 {
2184 struct azx *chip;
2185 int i, err;
2186 unsigned short gcap;
2187 static struct snd_device_ops ops = {
2188 .dev_free = azx_dev_free,
2189 };
2190
2191 *rchip = NULL;
2192
2193 err = pci_enable_device(pci);
2194 if (err < 0)
2195 return err;
2196
2197 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2198 if (!chip) {
2199 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2200 pci_disable_device(pci);
2201 return -ENOMEM;
2202 }
2203
2204 spin_lock_init(&chip->reg_lock);
2205 mutex_init(&chip->open_mutex);
2206 chip->card = card;
2207 chip->pci = pci;
2208 chip->irq = -1;
2209 chip->driver_type = driver_type;
2210 chip->msi = enable_msi;
2211 chip->dev_index = dev;
2212 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2213
2214 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2215 check_probe_mask(chip, dev);
2216
2217 chip->single_cmd = single_cmd;
2218
2219 if (bdl_pos_adj[dev] < 0) {
2220 switch (chip->driver_type) {
2221 case AZX_DRIVER_ICH:
2222 bdl_pos_adj[dev] = 1;
2223 break;
2224 default:
2225 bdl_pos_adj[dev] = 32;
2226 break;
2227 }
2228 }
2229
2230 #if BITS_PER_LONG != 64
2231 /* Fix up base address on ULI M5461 */
2232 if (chip->driver_type == AZX_DRIVER_ULI) {
2233 u16 tmp3;
2234 pci_read_config_word(pci, 0x40, &tmp3);
2235 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2236 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2237 }
2238 #endif
2239
2240 err = pci_request_regions(pci, "ICH HD audio");
2241 if (err < 0) {
2242 kfree(chip);
2243 pci_disable_device(pci);
2244 return err;
2245 }
2246
2247 chip->addr = pci_resource_start(pci, 0);
2248 chip->remap_addr = pci_ioremap_bar(pci, 0);
2249 if (chip->remap_addr == NULL) {
2250 snd_printk(KERN_ERR SFX "ioremap error\n");
2251 err = -ENXIO;
2252 goto errout;
2253 }
2254
2255 if (chip->msi)
2256 if (pci_enable_msi(pci) < 0)
2257 chip->msi = 0;
2258
2259 if (azx_acquire_irq(chip, 0) < 0) {
2260 err = -EBUSY;
2261 goto errout;
2262 }
2263
2264 pci_set_master(pci);
2265 synchronize_irq(chip->irq);
2266
2267 gcap = azx_readw(chip, GCAP);
2268 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2269
2270 /* ATI chips seems buggy about 64bit DMA addresses */
2271 if (chip->driver_type == AZX_DRIVER_ATI)
2272 gcap &= ~0x01;
2273
2274 /* allow 64bit DMA address if supported by H/W */
2275 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2276 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2277 else {
2278 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2279 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2280 }
2281
2282 /* read number of streams from GCAP register instead of using
2283 * hardcoded value
2284 */
2285 chip->capture_streams = (gcap >> 8) & 0x0f;
2286 chip->playback_streams = (gcap >> 12) & 0x0f;
2287 if (!chip->playback_streams && !chip->capture_streams) {
2288 /* gcap didn't give any info, switching to old method */
2289
2290 switch (chip->driver_type) {
2291 case AZX_DRIVER_ULI:
2292 chip->playback_streams = ULI_NUM_PLAYBACK;
2293 chip->capture_streams = ULI_NUM_CAPTURE;
2294 break;
2295 case AZX_DRIVER_ATIHDMI:
2296 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2297 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2298 break;
2299 case AZX_DRIVER_GENERIC:
2300 default:
2301 chip->playback_streams = ICH6_NUM_PLAYBACK;
2302 chip->capture_streams = ICH6_NUM_CAPTURE;
2303 break;
2304 }
2305 }
2306 chip->capture_index_offset = 0;
2307 chip->playback_index_offset = chip->capture_streams;
2308 chip->num_streams = chip->playback_streams + chip->capture_streams;
2309 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2310 GFP_KERNEL);
2311 if (!chip->azx_dev) {
2312 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2313 goto errout;
2314 }
2315
2316 for (i = 0; i < chip->num_streams; i++) {
2317 /* allocate memory for the BDL for each stream */
2318 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2319 snd_dma_pci_data(chip->pci),
2320 BDL_SIZE, &chip->azx_dev[i].bdl);
2321 if (err < 0) {
2322 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2323 goto errout;
2324 }
2325 }
2326 /* allocate memory for the position buffer */
2327 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2328 snd_dma_pci_data(chip->pci),
2329 chip->num_streams * 8, &chip->posbuf);
2330 if (err < 0) {
2331 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2332 goto errout;
2333 }
2334 /* allocate CORB/RIRB */
2335 if (!chip->single_cmd) {
2336 err = azx_alloc_cmd_io(chip);
2337 if (err < 0)
2338 goto errout;
2339 }
2340
2341 /* initialize streams */
2342 azx_init_stream(chip);
2343
2344 /* initialize chip */
2345 azx_init_pci(chip);
2346 azx_init_chip(chip);
2347
2348 /* codec detection */
2349 if (!chip->codec_mask) {
2350 snd_printk(KERN_ERR SFX "no codecs found!\n");
2351 err = -ENODEV;
2352 goto errout;
2353 }
2354
2355 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2356 if (err <0) {
2357 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2358 goto errout;
2359 }
2360
2361 strcpy(card->driver, "HDA-Intel");
2362 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2363 sprintf(card->longname, "%s at 0x%lx irq %i",
2364 card->shortname, chip->addr, chip->irq);
2365
2366 *rchip = chip;
2367 return 0;
2368
2369 errout:
2370 azx_free(chip);
2371 return err;
2372 }
2373
2374 static void power_down_all_codecs(struct azx *chip)
2375 {
2376 #ifdef CONFIG_SND_HDA_POWER_SAVE
2377 /* The codecs were powered up in snd_hda_codec_new().
2378 * Now all initialization done, so turn them down if possible
2379 */
2380 struct hda_codec *codec;
2381 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2382 snd_hda_power_down(codec);
2383 }
2384 #endif
2385 }
2386
2387 static int __devinit azx_probe(struct pci_dev *pci,
2388 const struct pci_device_id *pci_id)
2389 {
2390 static int dev;
2391 struct snd_card *card;
2392 struct azx *chip;
2393 int err;
2394
2395 if (dev >= SNDRV_CARDS)
2396 return -ENODEV;
2397 if (!enable[dev]) {
2398 dev++;
2399 return -ENOENT;
2400 }
2401
2402 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2403 if (err < 0) {
2404 snd_printk(KERN_ERR SFX "Error creating card!\n");
2405 return err;
2406 }
2407
2408 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2409 if (err < 0)
2410 goto out_free;
2411 card->private_data = chip;
2412
2413 /* create codec instances */
2414 err = azx_codec_create(chip, model[dev], probe_only[dev]);
2415 if (err < 0)
2416 goto out_free;
2417
2418 /* create PCM streams */
2419 err = snd_hda_build_pcms(chip->bus);
2420 if (err < 0)
2421 goto out_free;
2422
2423 /* create mixer controls */
2424 err = azx_mixer_create(chip);
2425 if (err < 0)
2426 goto out_free;
2427
2428 snd_card_set_dev(card, &pci->dev);
2429
2430 err = snd_card_register(card);
2431 if (err < 0)
2432 goto out_free;
2433
2434 pci_set_drvdata(pci, card);
2435 chip->running = 1;
2436 power_down_all_codecs(chip);
2437 azx_notifier_register(chip);
2438
2439 dev++;
2440 return err;
2441 out_free:
2442 snd_card_free(card);
2443 return err;
2444 }
2445
2446 static void __devexit azx_remove(struct pci_dev *pci)
2447 {
2448 snd_card_free(pci_get_drvdata(pci));
2449 pci_set_drvdata(pci, NULL);
2450 }
2451
2452 /* PCI IDs */
2453 static struct pci_device_id azx_ids[] = {
2454 /* ICH 6..10 */
2455 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2456 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2457 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2458 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2459 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2460 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2461 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2462 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2463 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2464 /* PCH */
2465 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2466 /* SCH */
2467 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2468 /* ATI SB 450/600 */
2469 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2470 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2471 /* ATI HDMI */
2472 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2473 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2474 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2475 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2476 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2477 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2478 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2479 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2480 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2481 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2482 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2483 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2484 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2485 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2486 /* VIA VT8251/VT8237A */
2487 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2488 /* SIS966 */
2489 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2490 /* ULI M5461 */
2491 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2492 /* NVIDIA MCP */
2493 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2494 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2495 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2496 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2497 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2498 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2499 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2500 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2501 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2502 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2503 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2504 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2505 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2506 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2507 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2508 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2509 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2510 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2511 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2512 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2513 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2514 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2515 /* Teradici */
2516 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2517 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2518 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2519 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2520 .class_mask = 0xffffff,
2521 .driver_data = AZX_DRIVER_GENERIC },
2522 { 0, }
2523 };
2524 MODULE_DEVICE_TABLE(pci, azx_ids);
2525
2526 /* pci_driver definition */
2527 static struct pci_driver driver = {
2528 .name = "HDA Intel",
2529 .id_table = azx_ids,
2530 .probe = azx_probe,
2531 .remove = __devexit_p(azx_remove),
2532 #ifdef CONFIG_PM
2533 .suspend = azx_suspend,
2534 .resume = azx_resume,
2535 #endif
2536 };
2537
2538 static int __init alsa_card_azx_init(void)
2539 {
2540 return pci_register_driver(&driver);
2541 }
2542
2543 static void __exit alsa_card_azx_exit(void)
2544 {
2545 pci_unregister_driver(&driver);
2546 }
2547
2548 module_init(alsa_card_azx_init)
2549 module_exit(alsa_card_azx_exit)
Support for the Chinese Samsung S3C2440 based development boards