arch/powerpc/sysdev/qe_lib/qe_ic.c

   1 /*
   2  * arch/powerpc/sysdev/qe_lib/qe_ic.c
   3  *
   4  * Copyright (C) 2006 Freescale Semicondutor, Inc.  All rights reserved.
   5  *
   6  * Author: Li Yang <leoli@freescale.com>
   7  * Based on code from Shlomi Gridish <gridish@freescale.com>
   8  *
   9  * QUICC ENGINE Interrupt Controller
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/reboot.h>
  21 #include <linux/slab.h>
  22 #include <linux/stddef.h>
  23 #include <linux/sched.h>
  24 #include <linux/signal.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/device.h>
  27 #include <linux/bootmem.h>
  28 #include <linux/spinlock.h>
  29 #include <asm/irq.h>
  30 #include <asm/io.h>
  31 #include <asm/prom.h>
  32 #include <asm/qe_ic.h>
  33
  34 #include "qe_ic.h"
  35
  36 static DEFINE_SPINLOCK(qe_ic_lock);
  37
  38 static struct qe_ic_info qe_ic_info[] = {
  39         [1] = {
  40                .mask = 0x00008000,
  41                .mask_reg = QEIC_CIMR,
  42                .pri_code = 0,
  43                .pri_reg = QEIC_CIPWCC,
  44                },
  45         [2] = {
  46                .mask = 0x00004000,
  47                .mask_reg = QEIC_CIMR,
  48                .pri_code = 1,
  49                .pri_reg = QEIC_CIPWCC,
  50                },
  51         [3] = {
  52                .mask = 0x00002000,
  53                .mask_reg = QEIC_CIMR,
  54                .pri_code = 2,
  55                .pri_reg = QEIC_CIPWCC,
  56                },
  57         [10] = {
  58                 .mask = 0x00000040,
  59                 .mask_reg = QEIC_CIMR,
  60                 .pri_code = 1,
  61                 .pri_reg = QEIC_CIPZCC,
  62                 },
  63         [11] = {
  64                 .mask = 0x00000020,
  65                 .mask_reg = QEIC_CIMR,
  66                 .pri_code = 2,
  67                 .pri_reg = QEIC_CIPZCC,
  68                 },
  69         [12] = {
  70                 .mask = 0x00000010,
  71                 .mask_reg = QEIC_CIMR,
  72                 .pri_code = 3,
  73                 .pri_reg = QEIC_CIPZCC,
  74                 },
  75         [13] = {
  76                 .mask = 0x00000008,
  77                 .mask_reg = QEIC_CIMR,
  78                 .pri_code = 4,
  79                 .pri_reg = QEIC_CIPZCC,
  80                 },
  81         [14] = {
  82                 .mask = 0x00000004,
  83                 .mask_reg = QEIC_CIMR,
  84                 .pri_code = 5,
  85                 .pri_reg = QEIC_CIPZCC,
  86                 },
  87         [15] = {
  88                 .mask = 0x00000002,
  89                 .mask_reg = QEIC_CIMR,
  90                 .pri_code = 6,
  91                 .pri_reg = QEIC_CIPZCC,
  92                 },
  93         [20] = {
  94                 .mask = 0x10000000,
  95                 .mask_reg = QEIC_CRIMR,
  96                 .pri_code = 3,
  97                 .pri_reg = QEIC_CIPRTA,
  98                 },
  99         [25] = {
 100                 .mask = 0x00800000,
 101                 .mask_reg = QEIC_CRIMR,
 102                 .pri_code = 0,
 103                 .pri_reg = QEIC_CIPRTB,
 104                 },
 105         [26] = {
 106                 .mask = 0x00400000,
 107                 .mask_reg = QEIC_CRIMR,
 108                 .pri_code = 1,
 109                 .pri_reg = QEIC_CIPRTB,
 110                 },
 111         [27] = {
 112                 .mask = 0x00200000,
 113                 .mask_reg = QEIC_CRIMR,
 114                 .pri_code = 2,
 115                 .pri_reg = QEIC_CIPRTB,
 116                 },
 117         [28] = {
 118                 .mask = 0x00100000,
 119                 .mask_reg = QEIC_CRIMR,
 120                 .pri_code = 3,
 121                 .pri_reg = QEIC_CIPRTB,
 122                 },
 123         [32] = {
 124                 .mask = 0x80000000,
 125                 .mask_reg = QEIC_CIMR,
 126                 .pri_code = 0,
 127                 .pri_reg = QEIC_CIPXCC,
 128                 },
 129         [33] = {
 130                 .mask = 0x40000000,
 131                 .mask_reg = QEIC_CIMR,
 132                 .pri_code = 1,
 133                 .pri_reg = QEIC_CIPXCC,
 134                 },
 135         [34] = {
 136                 .mask = 0x20000000,
 137                 .mask_reg = QEIC_CIMR,
 138                 .pri_code = 2,
 139                 .pri_reg = QEIC_CIPXCC,
 140                 },
 141         [35] = {
 142                 .mask = 0x10000000,
 143                 .mask_reg = QEIC_CIMR,
 144                 .pri_code = 3,
 145                 .pri_reg = QEIC_CIPXCC,
 146                 },
 147         [36] = {
 148                 .mask = 0x08000000,
 149                 .mask_reg = QEIC_CIMR,
 150                 .pri_code = 4,
 151                 .pri_reg = QEIC_CIPXCC,
 152                 },
 153         [40] = {
 154                 .mask = 0x00800000,
 155                 .mask_reg = QEIC_CIMR,
 156                 .pri_code = 0,
 157                 .pri_reg = QEIC_CIPYCC,
 158                 },
 159         [41] = {
 160                 .mask = 0x00400000,
 161                 .mask_reg = QEIC_CIMR,
 162                 .pri_code = 1,
 163                 .pri_reg = QEIC_CIPYCC,
 164                 },
 165         [42] = {
 166                 .mask = 0x00200000,
 167                 .mask_reg = QEIC_CIMR,
 168                 .pri_code = 2,
 169                 .pri_reg = QEIC_CIPYCC,
 170                 },
 171         [43] = {
 172                 .mask = 0x00100000,
 173                 .mask_reg = QEIC_CIMR,
 174                 .pri_code = 3,
 175                 .pri_reg = QEIC_CIPYCC,
 176                 },
 177 };
 178
 179 static inline u32 qe_ic_read(volatile __be32  __iomem * base, unsigned int reg)
 180 {
 181         return in_be32(base + (reg >> 2));
 182 }
 183
 184 static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg,
 185                                u32 value)
 186 {
 187         out_be32(base + (reg >> 2), value);
 188 }
 189
 190 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
 191 {
 192         return irq_desc[virq].chip_data;
 193 }
 194
 195 #define virq_to_hw(virq)        ((unsigned int)irq_map[virq].hwirq)
 196
 197 static void qe_ic_unmask_irq(unsigned int virq)
 198 {
 199         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 200         unsigned int src = virq_to_hw(virq);
 201         unsigned long flags;
 202         u32 temp;
 203
 204         spin_lock_irqsave(&qe_ic_lock, flags);
 205
 206         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
 207         qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
 208                     temp | qe_ic_info[src].mask);
 209
 210         spin_unlock_irqrestore(&qe_ic_lock, flags);
 211 }
 212
 213 static void qe_ic_mask_irq(unsigned int virq)
 214 {
 215         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 216         unsigned int src = virq_to_hw(virq);
 217         unsigned long flags;
 218         u32 temp;
 219
 220         spin_lock_irqsave(&qe_ic_lock, flags);
 221
 222         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
 223         qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
 224                     temp & ~qe_ic_info[src].mask);
 225
 226         spin_unlock_irqrestore(&qe_ic_lock, flags);
 227 }
 228
 229 static void qe_ic_mask_irq_and_ack(unsigned int virq)
 230 {
 231         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 232         unsigned int src = virq_to_hw(virq);
 233         unsigned long flags;
 234         u32 temp;
 235
 236         spin_lock_irqsave(&qe_ic_lock, flags);
 237
 238         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
 239         qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
 240                     temp & ~qe_ic_info[src].mask);
 241
 242         /* There is nothing to do for ack here, ack is handled in ISR */
 243
 244         spin_unlock_irqrestore(&qe_ic_lock, flags);
 245 }
 246
 247 static struct irq_chip qe_ic_irq_chip = {
 248         .typename = " QEIC  ",
 249         .unmask = qe_ic_unmask_irq,
 250         .mask = qe_ic_mask_irq,
 251         .mask_ack = qe_ic_mask_irq_and_ack,
 252 };
 253
 254 static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
 255 {
 256         struct qe_ic *qe_ic = h->host_data;
 257
 258         /* Exact match, unless qe_ic node is NULL */
 259         return qe_ic->of_node == NULL || qe_ic->of_node == node;
 260 }
 261
 262 static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
 263                           irq_hw_number_t hw)
 264 {
 265         struct qe_ic *qe_ic = h->host_data;
 266         struct irq_chip *chip;
 267
 268         if (qe_ic_info[hw].mask == 0) {
 269                 printk(KERN_ERR "Can't map reserved IRQ \n");
 270                 return -EINVAL;
 271         }
 272         /* Default chip */
 273         chip = &qe_ic->hc_irq;
 274
 275         set_irq_chip_data(virq, qe_ic);
 276         get_irq_desc(virq)->status |= IRQ_LEVEL;
 277
 278         set_irq_chip_and_handler(virq, chip, handle_level_irq);
 279
 280         return 0;
 281 }
 282
 283 static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
 284                             u32 * intspec, unsigned int intsize,
 285                             irq_hw_number_t * out_hwirq,
 286                             unsigned int *out_flags)
 287 {
 288         *out_hwirq = intspec[0];
 289         if (intsize > 1)
 290                 *out_flags = intspec[1];
 291         else
 292                 *out_flags = IRQ_TYPE_NONE;
 293         return 0;
 294 }
 295
 296 static struct irq_host_ops qe_ic_host_ops = {
 297         .match = qe_ic_host_match,
 298         .map = qe_ic_host_map,
 299         .xlate = qe_ic_host_xlate,
 300 };
 301
 302 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 303 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic, struct pt_regs *regs)
 304 {
 305         int irq;
 306
 307         BUG_ON(qe_ic == NULL);
 308
 309         /* get the interrupt source vector. */
 310         irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
 311
 312         if (irq == 0)
 313                 return NO_IRQ;
 314
 315         return irq_linear_revmap(qe_ic->irqhost, irq);
 316 }
 317
 318 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 319 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic, struct pt_regs *regs)
 320 {
 321         int irq;
 322
 323         BUG_ON(qe_ic == NULL);
 324
 325         /* get the interrupt source vector. */
 326         irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
 327
 328         if (irq == 0)
 329                 return NO_IRQ;
 330
 331         return irq_linear_revmap(qe_ic->irqhost, irq);
 332 }
 333
 334 /* FIXME: We mask all the QE Low interrupts while handling.  We should
 335  * let other interrupt come in, but BAD interrupts are generated */
 336 void fastcall qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc,
 337                                 struct pt_regs *regs)
 338 {
 339         struct qe_ic *qe_ic = desc->handler_data;
 340         struct irq_chip *chip = irq_desc[irq].chip;
 341
 342         unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic, regs);
 343
 344         chip->mask_ack(irq);
 345         if (cascade_irq != NO_IRQ)
 346                 generic_handle_irq(cascade_irq, regs);
 347         chip->unmask(irq);
 348 }
 349
 350 /* FIXME: We mask all the QE High interrupts while handling.  We should
 351  * let other interrupt come in, but BAD interrupts are generated */
 352 void fastcall qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc,
 353                                  struct pt_regs *regs)
 354 {
 355         struct qe_ic *qe_ic = desc->handler_data;
 356         struct irq_chip *chip = irq_desc[irq].chip;
 357
 358         unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic, regs);
 359
 360         chip->mask_ack(irq);
 361         if (cascade_irq != NO_IRQ)
 362                 generic_handle_irq(cascade_irq, regs);
 363         chip->unmask(irq);
 364 }
 365
 366 void __init qe_ic_init(struct device_node *node, unsigned int flags)
 367 {
 368         struct qe_ic *qe_ic;
 369         struct resource res;
 370         u32 temp = 0, ret, high_active = 0;
 371
 372         qe_ic = alloc_bootmem(sizeof(struct qe_ic));
 373         if (qe_ic == NULL)
 374                 return;
 375
 376         memset(qe_ic, 0, sizeof(struct qe_ic));
 377         qe_ic->of_node = node ? of_node_get(node) : NULL;
 378
 379         qe_ic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
 380                                         NR_QE_IC_INTS, &qe_ic_host_ops, 0);
 381         if (qe_ic->irqhost == NULL) {
 382                 of_node_put(node);
 383                 return;
 384         }
 385
 386         ret = of_address_to_resource(node, 0, &res);
 387         if (ret)
 388                 return;
 389
 390         qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
 391
 392         qe_ic->irqhost->host_data = qe_ic;
 393         qe_ic->hc_irq = qe_ic_irq_chip;
 394
 395         qe_ic->virq_high = irq_of_parse_and_map(node, 0);
 396         qe_ic->virq_low = irq_of_parse_and_map(node, 1);
 397
 398         if (qe_ic->virq_low == NO_IRQ) {
 399                 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
 400                 return;
 401         }
 402
 403         /* default priority scheme is grouped. If spread mode is    */
 404         /* required, configure cicr accordingly.                    */
 405         if (flags & QE_IC_SPREADMODE_GRP_W)
 406                 temp |= CICR_GWCC;
 407         if (flags & QE_IC_SPREADMODE_GRP_X)
 408                 temp |= CICR_GXCC;
 409         if (flags & QE_IC_SPREADMODE_GRP_Y)
 410                 temp |= CICR_GYCC;
 411         if (flags & QE_IC_SPREADMODE_GRP_Z)
 412                 temp |= CICR_GZCC;
 413         if (flags & QE_IC_SPREADMODE_GRP_RISCA)
 414                 temp |= CICR_GRTA;
 415         if (flags & QE_IC_SPREADMODE_GRP_RISCB)
 416                 temp |= CICR_GRTB;
 417
 418         /* choose destination signal for highest priority interrupt */
 419         if (flags & QE_IC_HIGH_SIGNAL) {
 420                 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
 421                 high_active = 1;
 422         }
 423
 424         qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 425
 426         set_irq_data(qe_ic->virq_low, qe_ic);
 427         set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
 428
 429         if (qe_ic->virq_high != NO_IRQ) {
 430                 set_irq_data(qe_ic->virq_high, qe_ic);
 431                 set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
 432         }
 433
 434         printk("QEIC (%d IRQ sources) at %p\n", NR_QE_IC_INTS, qe_ic->regs);
 435 }
 436
 437 void qe_ic_set_highest_priority(unsigned int virq, int high)
 438 {
 439         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 440         unsigned int src = virq_to_hw(virq);
 441         u32 temp = 0;
 442
 443         temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
 444
 445         temp &= ~CICR_HP_MASK;
 446         temp |= src << CICR_HP_SHIFT;
 447
 448         temp &= ~CICR_HPIT_MASK;
 449         temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
 450
 451         qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 452 }
 453
 454 /* Set Priority level within its group, from 1 to 8 */
 455 int qe_ic_set_priority(unsigned int virq, unsigned int priority)
 456 {
 457         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 458         unsigned int src = virq_to_hw(virq);
 459         u32 temp;
 460
 461         if (priority > 8 || priority == 0)
 462                 return -EINVAL;
 463         if (src > 127)
 464                 return -EINVAL;
 465         if (qe_ic_info[src].pri_reg == 0)
 466                 return -EINVAL;
 467
 468         temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
 469
 470         if (priority < 4) {
 471                 temp &= ~(0x7 << (32 - priority * 3));
 472                 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
 473         } else {
 474                 temp &= ~(0x7 << (24 - priority * 3));
 475                 temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
 476         }
 477
 478         qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
 479
 480         return 0;
 481 }
 482
 483 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */
 484 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
 485 {
 486         struct qe_ic *qe_ic = qe_ic_from_irq(virq);
 487         unsigned int src = virq_to_hw(virq);
 488         u32 temp, control_reg = QEIC_CICNR, shift = 0;
 489
 490         if (priority > 2 || priority == 0)
 491                 return -EINVAL;
 492
 493         switch (qe_ic_info[src].pri_reg) {
 494         case QEIC_CIPZCC:
 495                 shift = CICNR_ZCC1T_SHIFT;
 496                 break;
 497         case QEIC_CIPWCC:
 498                 shift = CICNR_WCC1T_SHIFT;
 499                 break;
 500         case QEIC_CIPYCC:
 501                 shift = CICNR_YCC1T_SHIFT;
 502                 break;
 503         case QEIC_CIPXCC:
 504                 shift = CICNR_XCC1T_SHIFT;
 505                 break;
 506         case QEIC_CIPRTA:
 507                 shift = CRICR_RTA1T_SHIFT;
 508                 control_reg = QEIC_CRICR;
 509                 break;
 510         case QEIC_CIPRTB:
 511                 shift = CRICR_RTB1T_SHIFT;
 512                 control_reg = QEIC_CRICR;
 513                 break;
 514         default:
 515                 return -EINVAL;
 516         }
 517
 518         shift += (2 - priority) * 2;
 519         temp = qe_ic_read(qe_ic->regs, control_reg);
 520         temp &= ~(SIGNAL_MASK << shift);
 521         temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
 522         qe_ic_write(qe_ic->regs, control_reg, temp);
 523
 524         return 0;
 525 }
 526
 527 static struct sysdev_class qe_ic_sysclass = {
 528         set_kset_name("qe_ic"),
 529 };
 530
 531 static struct sys_device device_qe_ic = {
 532         .id = 0,
 533         .cls = &qe_ic_sysclass,
 534 };
 535
 536 static int __init init_qe_ic_sysfs(void)
 537 {
 538         int rc;
 539
 540         printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
 541
 542         rc = sysdev_class_register(&qe_ic_sysclass);
 543         if (rc) {
 544                 printk(KERN_ERR "Failed registering qe_ic sys class\n");
 545                 return -ENODEV;
 546         }
 547         rc = sysdev_register(&device_qe_ic);
 548         if (rc) {
 549                 printk(KERN_ERR "Failed registering qe_ic sys device\n");
 550                 return -ENODEV;
 551         }
 552         return 0;
 553 }
 554
 555 subsys_initcall(init_qe_ic_sysfs);