2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/gpio.h>
24 #include <mach/hardware.h>
25 #include <mach/irqs.h>
26 #include <mach/imx-uart.h>
30 static struct resource uart0
[] = {
32 .start
= UART1_BASE_ADDR
,
33 .end
= UART1_BASE_ADDR
+ 0x0B5,
34 .flags
= IORESOURCE_MEM
,
36 .start
= MXC_INT_UART1
,
38 .flags
= IORESOURCE_IRQ
,
42 struct platform_device mxc_uart_device0
= {
46 .num_resources
= ARRAY_SIZE(uart0
),
49 static struct resource uart1
[] = {
51 .start
= UART2_BASE_ADDR
,
52 .end
= UART2_BASE_ADDR
+ 0x0B5,
53 .flags
= IORESOURCE_MEM
,
55 .start
= MXC_INT_UART2
,
57 .flags
= IORESOURCE_IRQ
,
61 struct platform_device mxc_uart_device1
= {
65 .num_resources
= ARRAY_SIZE(uart1
),
68 static struct resource uart2
[] = {
70 .start
= UART3_BASE_ADDR
,
71 .end
= UART3_BASE_ADDR
+ 0x0B5,
72 .flags
= IORESOURCE_MEM
,
74 .start
= MXC_INT_UART3
,
76 .flags
= IORESOURCE_IRQ
,
80 struct platform_device mxc_uart_device2
= {
84 .num_resources
= ARRAY_SIZE(uart2
),
87 #ifdef CONFIG_ARCH_MX31
88 static struct resource uart3
[] = {
90 .start
= UART4_BASE_ADDR
,
91 .end
= UART4_BASE_ADDR
+ 0x0B5,
92 .flags
= IORESOURCE_MEM
,
94 .start
= MXC_INT_UART4
,
96 .flags
= IORESOURCE_IRQ
,
100 struct platform_device mxc_uart_device3
= {
104 .num_resources
= ARRAY_SIZE(uart3
),
107 static struct resource uart4
[] = {
109 .start
= UART5_BASE_ADDR
,
110 .end
= UART5_BASE_ADDR
+ 0x0B5,
111 .flags
= IORESOURCE_MEM
,
113 .start
= MXC_INT_UART5
,
114 .end
= MXC_INT_UART5
,
115 .flags
= IORESOURCE_IRQ
,
119 struct platform_device mxc_uart_device4
= {
123 .num_resources
= ARRAY_SIZE(uart4
),
125 #endif /* CONFIG_ARCH_MX31 */
127 /* GPIO port description */
128 static struct mxc_gpio_port imx_gpio_ports
[] = {
130 .chip
.label
= "gpio-0",
131 .base
= IO_ADDRESS(GPIO1_BASE_ADDR
),
132 .irq
= MXC_INT_GPIO1
,
133 .virtual_irq_start
= MXC_GPIO_IRQ_START
,
136 .chip
.label
= "gpio-1",
137 .base
= IO_ADDRESS(GPIO2_BASE_ADDR
),
138 .irq
= MXC_INT_GPIO2
,
139 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 32,
142 .chip
.label
= "gpio-2",
143 .base
= IO_ADDRESS(GPIO3_BASE_ADDR
),
144 .irq
= MXC_INT_GPIO3
,
145 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 64,
149 int __init
mxc_register_gpios(void)
151 return mxc_gpio_init(imx_gpio_ports
, ARRAY_SIZE(imx_gpio_ports
));
154 static struct resource mxc_w1_master_resources
[] = {
156 .start
= OWIRE_BASE_ADDR
,
157 .end
= OWIRE_BASE_ADDR
+ SZ_4K
- 1,
158 .flags
= IORESOURCE_MEM
,
162 struct platform_device mxc_w1_master_device
= {
165 .num_resources
= ARRAY_SIZE(mxc_w1_master_resources
),
166 .resource
= mxc_w1_master_resources
,
169 static struct resource mxc_nand_resources
[] = {
171 .start
= 0, /* runtime dependent */
173 .flags
= IORESOURCE_MEM
175 .start
= MXC_INT_NANDFC
,
176 .end
= MXC_INT_NANDFC
,
177 .flags
= IORESOURCE_IRQ
181 struct platform_device mxc_nand_device
= {
184 .num_resources
= ARRAY_SIZE(mxc_nand_resources
),
185 .resource
= mxc_nand_resources
,
188 static struct resource mxc_i2c0_resources
[] = {
190 .start
= I2C_BASE_ADDR
,
191 .end
= I2C_BASE_ADDR
+ SZ_4K
- 1,
192 .flags
= IORESOURCE_MEM
,
195 .start
= MXC_INT_I2C
,
197 .flags
= IORESOURCE_IRQ
,
201 struct platform_device mxc_i2c_device0
= {
204 .num_resources
= ARRAY_SIZE(mxc_i2c0_resources
),
205 .resource
= mxc_i2c0_resources
,
208 static struct resource mxc_i2c1_resources
[] = {
210 .start
= I2C2_BASE_ADDR
,
211 .end
= I2C2_BASE_ADDR
+ SZ_4K
- 1,
212 .flags
= IORESOURCE_MEM
,
215 .start
= MXC_INT_I2C2
,
217 .flags
= IORESOURCE_IRQ
,
221 struct platform_device mxc_i2c_device1
= {
224 .num_resources
= ARRAY_SIZE(mxc_i2c1_resources
),
225 .resource
= mxc_i2c1_resources
,
228 static struct resource mxc_i2c2_resources
[] = {
230 .start
= I2C3_BASE_ADDR
,
231 .end
= I2C3_BASE_ADDR
+ SZ_4K
- 1,
232 .flags
= IORESOURCE_MEM
,
235 .start
= MXC_INT_I2C3
,
237 .flags
= IORESOURCE_IRQ
,
241 struct platform_device mxc_i2c_device2
= {
244 .num_resources
= ARRAY_SIZE(mxc_i2c2_resources
),
245 .resource
= mxc_i2c2_resources
,
248 #ifdef CONFIG_ARCH_MX31
249 static struct resource mxcsdhc0_resources
[] = {
251 .start
= MMC_SDHC1_BASE_ADDR
,
252 .end
= MMC_SDHC1_BASE_ADDR
+ SZ_16K
- 1,
253 .flags
= IORESOURCE_MEM
,
255 .start
= MXC_INT_MMC_SDHC1
,
256 .end
= MXC_INT_MMC_SDHC1
,
257 .flags
= IORESOURCE_IRQ
,
261 static struct resource mxcsdhc1_resources
[] = {
263 .start
= MMC_SDHC2_BASE_ADDR
,
264 .end
= MMC_SDHC2_BASE_ADDR
+ SZ_16K
- 1,
265 .flags
= IORESOURCE_MEM
,
267 .start
= MXC_INT_MMC_SDHC2
,
268 .end
= MXC_INT_MMC_SDHC2
,
269 .flags
= IORESOURCE_IRQ
,
273 struct platform_device mxcsdhc_device0
= {
276 .num_resources
= ARRAY_SIZE(mxcsdhc0_resources
),
277 .resource
= mxcsdhc0_resources
,
280 struct platform_device mxcsdhc_device1
= {
283 .num_resources
= ARRAY_SIZE(mxcsdhc1_resources
),
284 .resource
= mxcsdhc1_resources
,
286 #endif /* CONFIG_ARCH_MX31 */
288 /* i.MX31 Image Processing Unit */
290 /* The resource order is important! */
291 static struct resource mx3_ipu_rsrc
[] = {
293 .start
= IPU_CTRL_BASE_ADDR
,
294 .end
= IPU_CTRL_BASE_ADDR
+ 0x5F,
295 .flags
= IORESOURCE_MEM
,
297 .start
= IPU_CTRL_BASE_ADDR
+ 0x88,
298 .end
= IPU_CTRL_BASE_ADDR
+ 0xB3,
299 .flags
= IORESOURCE_MEM
,
301 .start
= MXC_INT_IPU_SYN
,
302 .end
= MXC_INT_IPU_SYN
,
303 .flags
= IORESOURCE_IRQ
,
305 .start
= MXC_INT_IPU_ERR
,
306 .end
= MXC_INT_IPU_ERR
,
307 .flags
= IORESOURCE_IRQ
,
311 struct platform_device mx3_ipu
= {
314 .num_resources
= ARRAY_SIZE(mx3_ipu_rsrc
),
315 .resource
= mx3_ipu_rsrc
,
318 static struct resource fb_resources
[] = {
320 .start
= IPU_CTRL_BASE_ADDR
+ 0xB4,
321 .end
= IPU_CTRL_BASE_ADDR
+ 0x1BF,
322 .flags
= IORESOURCE_MEM
,
326 struct platform_device mx3_fb
= {
327 .name
= "mx3_sdc_fb",
329 .num_resources
= ARRAY_SIZE(fb_resources
),
330 .resource
= fb_resources
,
332 .coherent_dma_mask
= 0xffffffff,
336 #ifdef CONFIG_ARCH_MX35
337 static struct resource mxc_fec_resources
[] = {
339 .start
= MXC_FEC_BASE_ADDR
,
340 .end
= MXC_FEC_BASE_ADDR
+ 0xfff,
341 .flags
= IORESOURCE_MEM
343 .start
= MXC_INT_FEC
,
345 .flags
= IORESOURCE_IRQ
349 struct platform_device mxc_fec_device
= {
352 .num_resources
= ARRAY_SIZE(mxc_fec_resources
),
353 .resource
= mxc_fec_resources
,
357 static int mx3_devices_init(void)
360 mxc_nand_resources
[0].start
= MX31_NFC_BASE_ADDR
;
361 mxc_nand_resources
[0].end
= MX31_NFC_BASE_ADDR
+ 0xfff;
364 mxc_nand_resources
[0].start
= MX35_NFC_BASE_ADDR
;
365 mxc_nand_resources
[0].end
= MX35_NFC_BASE_ADDR
+ 0xfff;
371 subsys_initcall(mx3_devices_init
);