?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
e1000e: Add support for BM PHYs on ICH9
[linux-2.6/mini2440.git] / drivers / net / e1000e / phy.c
blobb133dcf0e950e9d8067df175ba75e4b461bef250
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/delay.h>
30
31 #include "e1000.h"
32
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40
41 /* Cable length tables */
42 static const u16 e1000_m88_cable_length_table[] =
43 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
44
45 static const u16 e1000_igp_2_cable_length_table[] =
46 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
47 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
48 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
49 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
50 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
51 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
52 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
53 124};
54 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
55 ARRAY_SIZE(e1000_igp_2_cable_length_table)
56
57 /**
58 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
59 * @hw: pointer to the HW structure
60 *
61 * Read the PHY management control register and check whether a PHY reset
62 * is blocked. If a reset is not blocked return 0, otherwise
63 * return E1000_BLK_PHY_RESET (12).
64 **/
65 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
66 {
67 u32 manc;
68
69 manc = er32(MANC);
70
71 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
72 E1000_BLK_PHY_RESET : 0;
73 }
74
75 /**
76 * e1000e_get_phy_id - Retrieve the PHY ID and revision
77 * @hw: pointer to the HW structure
78 *
79 * Reads the PHY registers and stores the PHY ID and possibly the PHY
80 * revision in the hardware structure.
81 **/
82 s32 e1000e_get_phy_id(struct e1000_hw *hw)
83 {
84 struct e1000_phy_info *phy = &hw->phy;
85 s32 ret_val;
86 u16 phy_id;
87
88 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
89 if (ret_val)
90 return ret_val;
91
92 phy->id = (u32)(phy_id << 16);
93 udelay(20);
94 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
95 if (ret_val)
96 return ret_val;
97
98 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
99 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
100
101 return 0;
102 }
103
104 /**
105 * e1000e_phy_reset_dsp - Reset PHY DSP
106 * @hw: pointer to the HW structure
107 *
108 * Reset the digital signal processor.
109 **/
110 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
111 {
112 s32 ret_val;
113
114 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
115 if (ret_val)
116 return ret_val;
117
118 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
119 }
120
121 /**
122 * e1000e_read_phy_reg_mdic - Read MDI control register
123 * @hw: pointer to the HW structure
124 * @offset: register offset to be read
125 * @data: pointer to the read data
126 *
127 * Reads the MDI control register in the PHY at offset and stores the
128 * information read to data.
129 **/
130 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
131 {
132 struct e1000_phy_info *phy = &hw->phy;
133 u32 i, mdic = 0;
134
135 if (offset > MAX_PHY_REG_ADDRESS) {
136 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
137 return -E1000_ERR_PARAM;
138 }
139
140 /*
141 * Set up Op-code, Phy Address, and register offset in the MDI
142 * Control register. The MAC will take care of interfacing with the
143 * PHY to retrieve the desired data.
144 */
145 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
146 (phy->addr << E1000_MDIC_PHY_SHIFT) |
147 (E1000_MDIC_OP_READ));
148
149 ew32(MDIC, mdic);
150
151 /*
152 * Poll the ready bit to see if the MDI read completed
153 * Increasing the time out as testing showed failures with
154 * the lower time out
155 */
156 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
157 udelay(50);
158 mdic = er32(MDIC);
159 if (mdic & E1000_MDIC_READY)
160 break;
161 }
162 if (!(mdic & E1000_MDIC_READY)) {
163 hw_dbg(hw, "MDI Read did not complete\n");
164 return -E1000_ERR_PHY;
165 }
166 if (mdic & E1000_MDIC_ERROR) {
167 hw_dbg(hw, "MDI Error\n");
168 return -E1000_ERR_PHY;
169 }
170 *data = (u16) mdic;
171
172 return 0;
173 }
174
175 /**
176 * e1000e_write_phy_reg_mdic - Write MDI control register
177 * @hw: pointer to the HW structure
178 * @offset: register offset to write to
179 * @data: data to write to register at offset
180 *
181 * Writes data to MDI control register in the PHY at offset.
182 **/
183 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
184 {
185 struct e1000_phy_info *phy = &hw->phy;
186 u32 i, mdic = 0;
187
188 if (offset > MAX_PHY_REG_ADDRESS) {
189 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
190 return -E1000_ERR_PARAM;
191 }
192
193 /*
194 * Set up Op-code, Phy Address, and register offset in the MDI
195 * Control register. The MAC will take care of interfacing with the
196 * PHY to retrieve the desired data.
197 */
198 mdic = (((u32)data) |
199 (offset << E1000_MDIC_REG_SHIFT) |
200 (phy->addr << E1000_MDIC_PHY_SHIFT) |
201 (E1000_MDIC_OP_WRITE));
202
203 ew32(MDIC, mdic);
204
205 /*
206 * Poll the ready bit to see if the MDI read completed
207 * Increasing the time out as testing showed failures with
208 * the lower time out
209 */
210 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
211 udelay(50);
212 mdic = er32(MDIC);
213 if (mdic & E1000_MDIC_READY)
214 break;
215 }
216 if (!(mdic & E1000_MDIC_READY)) {
217 hw_dbg(hw, "MDI Write did not complete\n");
218 return -E1000_ERR_PHY;
219 }
220 if (mdic & E1000_MDIC_ERROR) {
221 hw_dbg(hw, "MDI Error\n");
222 return -E1000_ERR_PHY;
223 }
224
225 return 0;
226 }
227
228 /**
229 * e1000e_read_phy_reg_m88 - Read m88 PHY register
230 * @hw: pointer to the HW structure
231 * @offset: register offset to be read
232 * @data: pointer to the read data
233 *
234 * Acquires semaphore, if necessary, then reads the PHY register at offset
235 * and storing the retrieved information in data. Release any acquired
236 * semaphores before exiting.
237 **/
238 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
239 {
240 s32 ret_val;
241
242 ret_val = hw->phy.ops.acquire_phy(hw);
243 if (ret_val)
244 return ret_val;
245
246 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
247 data);
248
249 hw->phy.ops.release_phy(hw);
250
251 return ret_val;
252 }
253
254 /**
255 * e1000e_write_phy_reg_m88 - Write m88 PHY register
256 * @hw: pointer to the HW structure
257 * @offset: register offset to write to
258 * @data: data to write at register offset
259 *
260 * Acquires semaphore, if necessary, then writes the data to PHY register
261 * at the offset. Release any acquired semaphores before exiting.
262 **/
263 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
264 {
265 s32 ret_val;
266
267 ret_val = hw->phy.ops.acquire_phy(hw);
268 if (ret_val)
269 return ret_val;
270
271 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
272 data);
273
274 hw->phy.ops.release_phy(hw);
275
276 return ret_val;
277 }
278
279 /**
280 * e1000e_read_phy_reg_igp - Read igp PHY register
281 * @hw: pointer to the HW structure
282 * @offset: register offset to be read
283 * @data: pointer to the read data
284 *
285 * Acquires semaphore, if necessary, then reads the PHY register at offset
286 * and storing the retrieved information in data. Release any acquired
287 * semaphores before exiting.
288 **/
289 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
290 {
291 s32 ret_val;
292
293 ret_val = hw->phy.ops.acquire_phy(hw);
294 if (ret_val)
295 return ret_val;
296
297 if (offset > MAX_PHY_MULTI_PAGE_REG) {
298 ret_val = e1000e_write_phy_reg_mdic(hw,
299 IGP01E1000_PHY_PAGE_SELECT,
300 (u16)offset);
301 if (ret_val) {
302 hw->phy.ops.release_phy(hw);
303 return ret_val;
304 }
305 }
306
307 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
308 data);
309
310 hw->phy.ops.release_phy(hw);
311
312 return ret_val;
313 }
314
315 /**
316 * e1000e_write_phy_reg_igp - Write igp PHY register
317 * @hw: pointer to the HW structure
318 * @offset: register offset to write to
319 * @data: data to write at register offset
320 *
321 * Acquires semaphore, if necessary, then writes the data to PHY register
322 * at the offset. Release any acquired semaphores before exiting.
323 **/
324 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
325 {
326 s32 ret_val;
327
328 ret_val = hw->phy.ops.acquire_phy(hw);
329 if (ret_val)
330 return ret_val;
331
332 if (offset > MAX_PHY_MULTI_PAGE_REG) {
333 ret_val = e1000e_write_phy_reg_mdic(hw,
334 IGP01E1000_PHY_PAGE_SELECT,
335 (u16)offset);
336 if (ret_val) {
337 hw->phy.ops.release_phy(hw);
338 return ret_val;
339 }
340 }
341
342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
343 data);
344
345 hw->phy.ops.release_phy(hw);
346
347 return ret_val;
348 }
349
350 /**
351 * e1000e_read_kmrn_reg - Read kumeran register
352 * @hw: pointer to the HW structure
353 * @offset: register offset to be read
354 * @data: pointer to the read data
355 *
356 * Acquires semaphore, if necessary. Then reads the PHY register at offset
357 * using the kumeran interface. The information retrieved is stored in data.
358 * Release any acquired semaphores before exiting.
359 **/
360 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
361 {
362 u32 kmrnctrlsta;
363 s32 ret_val;
364
365 ret_val = hw->phy.ops.acquire_phy(hw);
366 if (ret_val)
367 return ret_val;
368
369 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
370 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
371 ew32(KMRNCTRLSTA, kmrnctrlsta);
372
373 udelay(2);
374
375 kmrnctrlsta = er32(KMRNCTRLSTA);
376 *data = (u16)kmrnctrlsta;
377
378 hw->phy.ops.release_phy(hw);
379
380 return ret_val;
381 }
382
383 /**
384 * e1000e_write_kmrn_reg - Write kumeran register
385 * @hw: pointer to the HW structure
386 * @offset: register offset to write to
387 * @data: data to write at register offset
388 *
389 * Acquires semaphore, if necessary. Then write the data to PHY register
390 * at the offset using the kumeran interface. Release any acquired semaphores
391 * before exiting.
392 **/
393 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
394 {
395 u32 kmrnctrlsta;
396 s32 ret_val;
397
398 ret_val = hw->phy.ops.acquire_phy(hw);
399 if (ret_val)
400 return ret_val;
401
402 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
403 E1000_KMRNCTRLSTA_OFFSET) | data;
404 ew32(KMRNCTRLSTA, kmrnctrlsta);
405
406 udelay(2);
407 hw->phy.ops.release_phy(hw);
408
409 return ret_val;
410 }
411
412 /**
413 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
414 * @hw: pointer to the HW structure
415 *
416 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
417 * and downshift values are set also.
418 **/
419 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
420 {
421 struct e1000_phy_info *phy = &hw->phy;
422 s32 ret_val;
423 u16 phy_data;
424
425 /* Enable CRS on Tx. This must be set for half-duplex operation. */
426 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
427 if (ret_val)
428 return ret_val;
429
430 /* For newer PHYs this bit is downshift enable */
431 if (phy->type == e1000_phy_m88)
432 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
433
434 /*
435 * Options:
436 * MDI/MDI-X = 0 (default)
437 * 0 - Auto for all speeds
438 * 1 - MDI mode
439 * 2 - MDI-X mode
440 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
441 */
442 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
443
444 switch (phy->mdix) {
445 case 1:
446 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
447 break;
448 case 2:
449 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
450 break;
451 case 3:
452 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
453 break;
454 case 0:
455 default:
456 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
457 break;
458 }
459
460 /*
461 * Options:
462 * disable_polarity_correction = 0 (default)
463 * Automatic Correction for Reversed Cable Polarity
464 * 0 - Disabled
465 * 1 - Enabled
466 */
467 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
468 if (phy->disable_polarity_correction == 1)
469 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
470
471 /* Enable downshift on BM (disabled by default) */
472 if (phy->type == e1000_phy_bm)
473 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
474
475 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
476 if (ret_val)
477 return ret_val;
478
479 if ((phy->type == e1000_phy_m88) && (phy->revision < 4)) {
480 /*
481 * Force TX_CLK in the Extended PHY Specific Control Register
482 * to 25MHz clock.
483 */
484 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
485 if (ret_val)
486 return ret_val;
487
488 phy_data |= M88E1000_EPSCR_TX_CLK_25;
489
490 if ((phy->revision == 2) &&
491 (phy->id == M88E1111_I_PHY_ID)) {
492 /* 82573L PHY - set the downshift counter to 5x. */
493 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
494 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
495 } else {
496 /* Configure Master and Slave downshift values */
497 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
498 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
499 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
500 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
501 }
502 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
503 if (ret_val)
504 return ret_val;
505 }
506
507 /* Commit the changes. */
508 ret_val = e1000e_commit_phy(hw);
509 if (ret_val)
510 hw_dbg(hw, "Error committing the PHY changes\n");
511
512 return ret_val;
513 }
514
515 /**
516 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
517 * @hw: pointer to the HW structure
518 *
519 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
520 * igp PHY's.
521 **/
522 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
523 {
524 struct e1000_phy_info *phy = &hw->phy;
525 s32 ret_val;
526 u16 data;
527
528 ret_val = e1000_phy_hw_reset(hw);
529 if (ret_val) {
530 hw_dbg(hw, "Error resetting the PHY.\n");
531 return ret_val;
532 }
533
534 /*
535 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
536 * timeout issues when LFS is enabled.
537 */
538 msleep(100);
539
540 /* disable lplu d0 during driver init */
541 ret_val = e1000_set_d0_lplu_state(hw, 0);
542 if (ret_val) {
543 hw_dbg(hw, "Error Disabling LPLU D0\n");
544 return ret_val;
545 }
546 /* Configure mdi-mdix settings */
547 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
548 if (ret_val)
549 return ret_val;
550
551 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
552
553 switch (phy->mdix) {
554 case 1:
555 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
556 break;
557 case 2:
558 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
559 break;
560 case 0:
561 default:
562 data |= IGP01E1000_PSCR_AUTO_MDIX;
563 break;
564 }
565 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
566 if (ret_val)
567 return ret_val;
568
569 /* set auto-master slave resolution settings */
570 if (hw->mac.autoneg) {
571 /*
572 * when autonegotiation advertisement is only 1000Mbps then we
573 * should disable SmartSpeed and enable Auto MasterSlave
574 * resolution as hardware default.
575 */
576 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
577 /* Disable SmartSpeed */
578 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
579 &data);
580 if (ret_val)
581 return ret_val;
582
583 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
584 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
585 data);
586 if (ret_val)
587 return ret_val;
588
589 /* Set auto Master/Slave resolution process */
590 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
591 if (ret_val)
592 return ret_val;
593
594 data &= ~CR_1000T_MS_ENABLE;
595 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
596 if (ret_val)
597 return ret_val;
598 }
599
600 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
601 if (ret_val)
602 return ret_val;
603
604 /* load defaults for future use */
605 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
606 ((data & CR_1000T_MS_VALUE) ?
607 e1000_ms_force_master :
608 e1000_ms_force_slave) :
609 e1000_ms_auto;
610
611 switch (phy->ms_type) {
612 case e1000_ms_force_master:
613 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
614 break;
615 case e1000_ms_force_slave:
616 data |= CR_1000T_MS_ENABLE;
617 data &= ~(CR_1000T_MS_VALUE);
618 break;
619 case e1000_ms_auto:
620 data &= ~CR_1000T_MS_ENABLE;
621 default:
622 break;
623 }
624 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
625 }
626
627 return ret_val;
628 }
629
630 /**
631 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
632 * @hw: pointer to the HW structure
633 *
634 * Reads the MII auto-neg advertisement register and/or the 1000T control
635 * register and if the PHY is already setup for auto-negotiation, then
636 * return successful. Otherwise, setup advertisement and flow control to
637 * the appropriate values for the wanted auto-negotiation.
638 **/
639 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
640 {
641 struct e1000_phy_info *phy = &hw->phy;
642 s32 ret_val;
643 u16 mii_autoneg_adv_reg;
644 u16 mii_1000t_ctrl_reg = 0;
645
646 phy->autoneg_advertised &= phy->autoneg_mask;
647
648 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
649 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
650 if (ret_val)
651 return ret_val;
652
653 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
654 /* Read the MII 1000Base-T Control Register (Address 9). */
655 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
656 if (ret_val)
657 return ret_val;
658 }
659
660 /*
661 * Need to parse both autoneg_advertised and fc and set up
662 * the appropriate PHY registers. First we will parse for
663 * autoneg_advertised software override. Since we can advertise
664 * a plethora of combinations, we need to check each bit
665 * individually.
666 */
667
668 /*
669 * First we clear all the 10/100 mb speed bits in the Auto-Neg
670 * Advertisement Register (Address 4) and the 1000 mb speed bits in
671 * the 1000Base-T Control Register (Address 9).
672 */
673 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
674 NWAY_AR_100TX_HD_CAPS |
675 NWAY_AR_10T_FD_CAPS |
676 NWAY_AR_10T_HD_CAPS);
677 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
678
679 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
680
681 /* Do we want to advertise 10 Mb Half Duplex? */
682 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
683 hw_dbg(hw, "Advertise 10mb Half duplex\n");
684 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
685 }
686
687 /* Do we want to advertise 10 Mb Full Duplex? */
688 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
689 hw_dbg(hw, "Advertise 10mb Full duplex\n");
690 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
691 }
692
693 /* Do we want to advertise 100 Mb Half Duplex? */
694 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
695 hw_dbg(hw, "Advertise 100mb Half duplex\n");
696 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
697 }
698
699 /* Do we want to advertise 100 Mb Full Duplex? */
700 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
701 hw_dbg(hw, "Advertise 100mb Full duplex\n");
702 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
703 }
704
705 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
706 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
707 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
708
709 /* Do we want to advertise 1000 Mb Full Duplex? */
710 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
711 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
712 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
713 }
714
715 /*
716 * Check for a software override of the flow control settings, and
717 * setup the PHY advertisement registers accordingly. If
718 * auto-negotiation is enabled, then software will have to set the
719 * "PAUSE" bits to the correct value in the Auto-Negotiation
720 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
721 * negotiation.
722 *
723 * The possible values of the "fc" parameter are:
724 * 0: Flow control is completely disabled
725 * 1: Rx flow control is enabled (we can receive pause frames
726 * but not send pause frames).
727 * 2: Tx flow control is enabled (we can send pause frames
728 * but we do not support receiving pause frames).
729 * 3: Both Rx and Tx flow control (symmetric) are enabled.
730 * other: No software override. The flow control configuration
731 * in the EEPROM is used.
732 */
733 switch (hw->fc.type) {
734 case e1000_fc_none:
735 /*
736 * Flow control (Rx & Tx) is completely disabled by a
737 * software over-ride.
738 */
739 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
740 break;
741 case e1000_fc_rx_pause:
742 /*
743 * Rx Flow control is enabled, and Tx Flow control is
744 * disabled, by a software over-ride.
745 *
746 * Since there really isn't a way to advertise that we are
747 * capable of Rx Pause ONLY, we will advertise that we
748 * support both symmetric and asymmetric Rx PAUSE. Later
749 * (in e1000e_config_fc_after_link_up) we will disable the
750 * hw's ability to send PAUSE frames.
751 */
752 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
753 break;
754 case e1000_fc_tx_pause:
755 /*
756 * Tx Flow control is enabled, and Rx Flow control is
757 * disabled, by a software over-ride.
758 */
759 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
760 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
761 break;
762 case e1000_fc_full:
763 /*
764 * Flow control (both Rx and Tx) is enabled by a software
765 * over-ride.
766 */
767 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
768 break;
769 default:
770 hw_dbg(hw, "Flow control param set incorrectly\n");
771 ret_val = -E1000_ERR_CONFIG;
772 return ret_val;
773 }
774
775 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
776 if (ret_val)
777 return ret_val;
778
779 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
780
781 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
782 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
783 }
784
785 return ret_val;
786 }
787
788 /**
789 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
790 * @hw: pointer to the HW structure
791 *
792 * Performs initial bounds checking on autoneg advertisement parameter, then
793 * configure to advertise the full capability. Setup the PHY to autoneg
794 * and restart the negotiation process between the link partner. If
795 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
796 **/
797 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
798 {
799 struct e1000_phy_info *phy = &hw->phy;
800 s32 ret_val;
801 u16 phy_ctrl;
802
803 /*
804 * Perform some bounds checking on the autoneg advertisement
805 * parameter.
806 */
807 phy->autoneg_advertised &= phy->autoneg_mask;
808
809 /*
810 * If autoneg_advertised is zero, we assume it was not defaulted
811 * by the calling code so we set to advertise full capability.
812 */
813 if (phy->autoneg_advertised == 0)
814 phy->autoneg_advertised = phy->autoneg_mask;
815
816 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
817 ret_val = e1000_phy_setup_autoneg(hw);
818 if (ret_val) {
819 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
820 return ret_val;
821 }
822 hw_dbg(hw, "Restarting Auto-Neg\n");
823
824 /*
825 * Restart auto-negotiation by setting the Auto Neg Enable bit and
826 * the Auto Neg Restart bit in the PHY control register.
827 */
828 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
829 if (ret_val)
830 return ret_val;
831
832 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
833 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
834 if (ret_val)
835 return ret_val;
836
837 /*
838 * Does the user want to wait for Auto-Neg to complete here, or
839 * check at a later time (for example, callback routine).
840 */
841 if (phy->autoneg_wait_to_complete) {
842 ret_val = e1000_wait_autoneg(hw);
843 if (ret_val) {
844 hw_dbg(hw, "Error while waiting for "
845 "autoneg to complete\n");
846 return ret_val;
847 }
848 }
849
850 hw->mac.get_link_status = 1;
851
852 return ret_val;
853 }
854
855 /**
856 * e1000e_setup_copper_link - Configure copper link settings
857 * @hw: pointer to the HW structure
858 *
859 * Calls the appropriate function to configure the link for auto-neg or forced
860 * speed and duplex. Then we check for link, once link is established calls
861 * to configure collision distance and flow control are called. If link is
862 * not established, we return -E1000_ERR_PHY (-2).
863 **/
864 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
865 {
866 s32 ret_val;
867 bool link;
868
869 if (hw->mac.autoneg) {
870 /*
871 * Setup autoneg and flow control advertisement and perform
872 * autonegotiation.
873 */
874 ret_val = e1000_copper_link_autoneg(hw);
875 if (ret_val)
876 return ret_val;
877 } else {
878 /*
879 * PHY will be set to 10H, 10F, 100H or 100F
880 * depending on user settings.
881 */
882 hw_dbg(hw, "Forcing Speed and Duplex\n");
883 ret_val = e1000_phy_force_speed_duplex(hw);
884 if (ret_val) {
885 hw_dbg(hw, "Error Forcing Speed and Duplex\n");
886 return ret_val;
887 }
888 }
889
890 /*
891 * Check link status. Wait up to 100 microseconds for link to become
892 * valid.
893 */
894 ret_val = e1000e_phy_has_link_generic(hw,
895 COPPER_LINK_UP_LIMIT,
896 10,
897 &link);
898 if (ret_val)
899 return ret_val;
900
901 if (link) {
902 hw_dbg(hw, "Valid link established!!!\n");
903 e1000e_config_collision_dist(hw);
904 ret_val = e1000e_config_fc_after_link_up(hw);
905 } else {
906 hw_dbg(hw, "Unable to establish link!!!\n");
907 }
908
909 return ret_val;
910 }
911
912 /**
913 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
914 * @hw: pointer to the HW structure
915 *
916 * Calls the PHY setup function to force speed and duplex. Clears the
917 * auto-crossover to force MDI manually. Waits for link and returns
918 * successful if link up is successful, else -E1000_ERR_PHY (-2).
919 **/
920 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
921 {
922 struct e1000_phy_info *phy = &hw->phy;
923 s32 ret_val;
924 u16 phy_data;
925 bool link;
926
927 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
928 if (ret_val)
929 return ret_val;
930
931 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
932
933 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
934 if (ret_val)
935 return ret_val;
936
937 /*
938 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
939 * forced whenever speed and duplex are forced.
940 */
941 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
942 if (ret_val)
943 return ret_val;
944
945 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
946 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
947
948 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
949 if (ret_val)
950 return ret_val;
951
952 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
953
954 udelay(1);
955
956 if (phy->autoneg_wait_to_complete) {
957 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
958
959 ret_val = e1000e_phy_has_link_generic(hw,
960 PHY_FORCE_LIMIT,
961 100000,
962 &link);
963 if (ret_val)
964 return ret_val;
965
966 if (!link)
967 hw_dbg(hw, "Link taking longer than expected.\n");
968
969 /* Try once more */
970 ret_val = e1000e_phy_has_link_generic(hw,
971 PHY_FORCE_LIMIT,
972 100000,
973 &link);
974 if (ret_val)
975 return ret_val;
976 }
977
978 return ret_val;
979 }
980
981 /**
982 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
983 * @hw: pointer to the HW structure
984 *
985 * Calls the PHY setup function to force speed and duplex. Clears the
986 * auto-crossover to force MDI manually. Resets the PHY to commit the
987 * changes. If time expires while waiting for link up, we reset the DSP.
988 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
989 * successful completion, else return corresponding error code.
990 **/
991 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
992 {
993 struct e1000_phy_info *phy = &hw->phy;
994 s32 ret_val;
995 u16 phy_data;
996 bool link;
997
998 /*
999 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1000 * forced whenever speed and duplex are forced.
1001 */
1002 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1003 if (ret_val)
1004 return ret_val;
1005
1006 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1007 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1008 if (ret_val)
1009 return ret_val;
1010
1011 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
1012
1013 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1014 if (ret_val)
1015 return ret_val;
1016
1017 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1018
1019 /* Reset the phy to commit changes. */
1020 phy_data |= MII_CR_RESET;
1021
1022 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1023 if (ret_val)
1024 return ret_val;
1025
1026 udelay(1);
1027
1028 if (phy->autoneg_wait_to_complete) {
1029 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
1030
1031 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1032 100000, &link);
1033 if (ret_val)
1034 return ret_val;
1035
1036 if (!link) {
1037 /*
1038 * We didn't get link.
1039 * Reset the DSP and cross our fingers.
1040 */
1041 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1042 0x001d);
1043 if (ret_val)
1044 return ret_val;
1045 ret_val = e1000e_phy_reset_dsp(hw);
1046 if (ret_val)
1047 return ret_val;
1048 }
1049
1050 /* Try once more */
1051 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1052 100000, &link);
1053 if (ret_val)
1054 return ret_val;
1055 }
1056
1057 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1058 if (ret_val)
1059 return ret_val;
1060
1061 /*
1062 * Resetting the phy means we need to re-force TX_CLK in the
1063 * Extended PHY Specific Control Register to 25MHz clock from
1064 * the reset value of 2.5MHz.
1065 */
1066 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1067 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1068 if (ret_val)
1069 return ret_val;
1070
1071 /*
1072 * In addition, we must re-enable CRS on Tx for both half and full
1073 * duplex.
1074 */
1075 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1076 if (ret_val)
1077 return ret_val;
1078
1079 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1080 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1081
1082 return ret_val;
1083 }
1084
1085 /**
1086 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1087 * @hw: pointer to the HW structure
1088 * @phy_ctrl: pointer to current value of PHY_CONTROL
1089 *
1090 * Forces speed and duplex on the PHY by doing the following: disable flow
1091 * control, force speed/duplex on the MAC, disable auto speed detection,
1092 * disable auto-negotiation, configure duplex, configure speed, configure
1093 * the collision distance, write configuration to CTRL register. The
1094 * caller must write to the PHY_CONTROL register for these settings to
1095 * take affect.
1096 **/
1097 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1098 {
1099 struct e1000_mac_info *mac = &hw->mac;
1100 u32 ctrl;
1101
1102 /* Turn off flow control when forcing speed/duplex */
1103 hw->fc.type = e1000_fc_none;
1104
1105 /* Force speed/duplex on the mac */
1106 ctrl = er32(CTRL);
1107 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1108 ctrl &= ~E1000_CTRL_SPD_SEL;
1109
1110 /* Disable Auto Speed Detection */
1111 ctrl &= ~E1000_CTRL_ASDE;
1112
1113 /* Disable autoneg on the phy */
1114 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1115
1116 /* Forcing Full or Half Duplex? */
1117 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1118 ctrl &= ~E1000_CTRL_FD;
1119 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1120 hw_dbg(hw, "Half Duplex\n");
1121 } else {
1122 ctrl |= E1000_CTRL_FD;
1123 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1124 hw_dbg(hw, "Full Duplex\n");
1125 }
1126
1127 /* Forcing 10mb or 100mb? */
1128 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1129 ctrl |= E1000_CTRL_SPD_100;
1130 *phy_ctrl |= MII_CR_SPEED_100;
1131 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1132 hw_dbg(hw, "Forcing 100mb\n");
1133 } else {
1134 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1135 *phy_ctrl |= MII_CR_SPEED_10;
1136 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1137 hw_dbg(hw, "Forcing 10mb\n");
1138 }
1139
1140 e1000e_config_collision_dist(hw);
1141
1142 ew32(CTRL, ctrl);
1143 }
1144
1145 /**
1146 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1147 * @hw: pointer to the HW structure
1148 * @active: boolean used to enable/disable lplu
1149 *
1150 * Success returns 0, Failure returns 1
1151 *
1152 * The low power link up (lplu) state is set to the power management level D3
1153 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1154 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1155 * is used during Dx states where the power conservation is most important.
1156 * During driver activity, SmartSpeed should be enabled so performance is
1157 * maintained.
1158 **/
1159 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1160 {
1161 struct e1000_phy_info *phy = &hw->phy;
1162 s32 ret_val;
1163 u16 data;
1164
1165 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1166 if (ret_val)
1167 return ret_val;
1168
1169 if (!active) {
1170 data &= ~IGP02E1000_PM_D3_LPLU;
1171 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1172 if (ret_val)
1173 return ret_val;
1174 /*
1175 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1176 * during Dx states where the power conservation is most
1177 * important. During driver activity we should enable
1178 * SmartSpeed, so performance is maintained.
1179 */
1180 if (phy->smart_speed == e1000_smart_speed_on) {
1181 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1182 &data);
1183 if (ret_val)
1184 return ret_val;
1185
1186 data |= IGP01E1000_PSCFR_SMART_SPEED;
1187 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1188 data);
1189 if (ret_val)
1190 return ret_val;
1191 } else if (phy->smart_speed == e1000_smart_speed_off) {
1192 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1193 &data);
1194 if (ret_val)
1195 return ret_val;
1196
1197 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1198 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1199 data);
1200 if (ret_val)
1201 return ret_val;
1202 }
1203 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1204 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1205 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1206 data |= IGP02E1000_PM_D3_LPLU;
1207 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1208 if (ret_val)
1209 return ret_val;
1210
1211 /* When LPLU is enabled, we should disable SmartSpeed */
1212 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1213 if (ret_val)
1214 return ret_val;
1215
1216 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1217 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1218 }
1219
1220 return ret_val;
1221 }
1222
1223 /**
1224 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1225 * @hw: pointer to the HW structure
1226 *
1227 * Success returns 0, Failure returns 1
1228 *
1229 * A downshift is detected by querying the PHY link health.
1230 **/
1231 s32 e1000e_check_downshift(struct e1000_hw *hw)
1232 {
1233 struct e1000_phy_info *phy = &hw->phy;
1234 s32 ret_val;
1235 u16 phy_data, offset, mask;
1236
1237 switch (phy->type) {
1238 case e1000_phy_m88:
1239 case e1000_phy_gg82563:
1240 offset = M88E1000_PHY_SPEC_STATUS;
1241 mask = M88E1000_PSSR_DOWNSHIFT;
1242 break;
1243 case e1000_phy_igp_2:
1244 case e1000_phy_igp_3:
1245 offset = IGP01E1000_PHY_LINK_HEALTH;
1246 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1247 break;
1248 default:
1249 /* speed downshift not supported */
1250 phy->speed_downgraded = 0;
1251 return 0;
1252 }
1253
1254 ret_val = e1e_rphy(hw, offset, &phy_data);
1255
1256 if (!ret_val)
1257 phy->speed_downgraded = (phy_data & mask);
1258
1259 return ret_val;
1260 }
1261
1262 /**
1263 * e1000_check_polarity_m88 - Checks the polarity.
1264 * @hw: pointer to the HW structure
1265 *
1266 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1267 *
1268 * Polarity is determined based on the PHY specific status register.
1269 **/
1270 static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1271 {
1272 struct e1000_phy_info *phy = &hw->phy;
1273 s32 ret_val;
1274 u16 data;
1275
1276 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1277
1278 if (!ret_val)
1279 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1280 ? e1000_rev_polarity_reversed
1281 : e1000_rev_polarity_normal;
1282
1283 return ret_val;
1284 }
1285
1286 /**
1287 * e1000_check_polarity_igp - Checks the polarity.
1288 * @hw: pointer to the HW structure
1289 *
1290 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1291 *
1292 * Polarity is determined based on the PHY port status register, and the
1293 * current speed (since there is no polarity at 100Mbps).
1294 **/
1295 static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1296 {
1297 struct e1000_phy_info *phy = &hw->phy;
1298 s32 ret_val;
1299 u16 data, offset, mask;
1300
1301 /*
1302 * Polarity is determined based on the speed of
1303 * our connection.
1304 */
1305 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1306 if (ret_val)
1307 return ret_val;
1308
1309 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1310 IGP01E1000_PSSR_SPEED_1000MBPS) {
1311 offset = IGP01E1000_PHY_PCS_INIT_REG;
1312 mask = IGP01E1000_PHY_POLARITY_MASK;
1313 } else {
1314 /*
1315 * This really only applies to 10Mbps since
1316 * there is no polarity for 100Mbps (always 0).
1317 */
1318 offset = IGP01E1000_PHY_PORT_STATUS;
1319 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1320 }
1321
1322 ret_val = e1e_rphy(hw, offset, &data);
1323
1324 if (!ret_val)
1325 phy->cable_polarity = (data & mask)
1326 ? e1000_rev_polarity_reversed
1327 : e1000_rev_polarity_normal;
1328
1329 return ret_val;
1330 }
1331
1332 /**
1333 * e1000_wait_autoneg - Wait for auto-neg completion
1334 * @hw: pointer to the HW structure
1335 *
1336 * Waits for auto-negotiation to complete or for the auto-negotiation time
1337 * limit to expire, which ever happens first.
1338 **/
1339 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1340 {
1341 s32 ret_val = 0;
1342 u16 i, phy_status;
1343
1344 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1345 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1346 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1347 if (ret_val)
1348 break;
1349 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1350 if (ret_val)
1351 break;
1352 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1353 break;
1354 msleep(100);
1355 }
1356
1357 /*
1358 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1359 * has completed.
1360 */
1361 return ret_val;
1362 }
1363
1364 /**
1365 * e1000e_phy_has_link_generic - Polls PHY for link
1366 * @hw: pointer to the HW structure
1367 * @iterations: number of times to poll for link
1368 * @usec_interval: delay between polling attempts
1369 * @success: pointer to whether polling was successful or not
1370 *
1371 * Polls the PHY status register for link, 'iterations' number of times.
1372 **/
1373 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1374 u32 usec_interval, bool *success)
1375 {
1376 s32 ret_val = 0;
1377 u16 i, phy_status;
1378
1379 for (i = 0; i < iterations; i++) {
1380 /*
1381 * Some PHYs require the PHY_STATUS register to be read
1382 * twice due to the link bit being sticky. No harm doing
1383 * it across the board.
1384 */
1385 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1386 if (ret_val)
1387 break;
1388 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1389 if (ret_val)
1390 break;
1391 if (phy_status & MII_SR_LINK_STATUS)
1392 break;
1393 if (usec_interval >= 1000)
1394 mdelay(usec_interval/1000);
1395 else
1396 udelay(usec_interval);
1397 }
1398
1399 *success = (i < iterations);
1400
1401 return ret_val;
1402 }
1403
1404 /**
1405 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1406 * @hw: pointer to the HW structure
1407 *
1408 * Reads the PHY specific status register to retrieve the cable length
1409 * information. The cable length is determined by averaging the minimum and
1410 * maximum values to get the "average" cable length. The m88 PHY has four
1411 * possible cable length values, which are:
1412 * Register Value Cable Length
1413 * 0 < 50 meters
1414 * 1 50 - 80 meters
1415 * 2 80 - 110 meters
1416 * 3 110 - 140 meters
1417 * 4 > 140 meters
1418 **/
1419 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1420 {
1421 struct e1000_phy_info *phy = &hw->phy;
1422 s32 ret_val;
1423 u16 phy_data, index;
1424
1425 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1426 if (ret_val)
1427 return ret_val;
1428
1429 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1430 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1431 phy->min_cable_length = e1000_m88_cable_length_table[index];
1432 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1433
1434 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1435
1436 return ret_val;
1437 }
1438
1439 /**
1440 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1441 * @hw: pointer to the HW structure
1442 *
1443 * The automatic gain control (agc) normalizes the amplitude of the
1444 * received signal, adjusting for the attenuation produced by the
1445 * cable. By reading the AGC registers, which represent the
1446 * combination of course and fine gain value, the value can be put
1447 * into a lookup table to obtain the approximate cable length
1448 * for each channel.
1449 **/
1450 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1451 {
1452 struct e1000_phy_info *phy = &hw->phy;
1453 s32 ret_val;
1454 u16 phy_data, i, agc_value = 0;
1455 u16 cur_agc_index, max_agc_index = 0;
1456 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1457 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1458 {IGP02E1000_PHY_AGC_A,
1459 IGP02E1000_PHY_AGC_B,
1460 IGP02E1000_PHY_AGC_C,
1461 IGP02E1000_PHY_AGC_D};
1462
1463 /* Read the AGC registers for all channels */
1464 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1465 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1466 if (ret_val)
1467 return ret_val;
1468
1469 /*
1470 * Getting bits 15:9, which represent the combination of
1471 * course and fine gain values. The result is a number
1472 * that can be put into the lookup table to obtain the
1473 * approximate cable length.
1474 */
1475 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1476 IGP02E1000_AGC_LENGTH_MASK;
1477
1478 /* Array index bound check. */
1479 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1480 (cur_agc_index == 0))
1481 return -E1000_ERR_PHY;
1482
1483 /* Remove min & max AGC values from calculation. */
1484 if (e1000_igp_2_cable_length_table[min_agc_index] >
1485 e1000_igp_2_cable_length_table[cur_agc_index])
1486 min_agc_index = cur_agc_index;
1487 if (e1000_igp_2_cable_length_table[max_agc_index] <
1488 e1000_igp_2_cable_length_table[cur_agc_index])
1489 max_agc_index = cur_agc_index;
1490
1491 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1492 }
1493
1494 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1495 e1000_igp_2_cable_length_table[max_agc_index]);
1496 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1497
1498 /* Calculate cable length with the error range of +/- 10 meters. */
1499 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1500 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1501 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1502
1503 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1504
1505 return ret_val;
1506 }
1507
1508 /**
1509 * e1000e_get_phy_info_m88 - Retrieve PHY information
1510 * @hw: pointer to the HW structure
1511 *
1512 * Valid for only copper links. Read the PHY status register (sticky read)
1513 * to verify that link is up. Read the PHY special control register to
1514 * determine the polarity and 10base-T extended distance. Read the PHY
1515 * special status register to determine MDI/MDIx and current speed. If
1516 * speed is 1000, then determine cable length, local and remote receiver.
1517 **/
1518 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1519 {
1520 struct e1000_phy_info *phy = &hw->phy;
1521 s32 ret_val;
1522 u16 phy_data;
1523 bool link;
1524
1525 if (hw->phy.media_type != e1000_media_type_copper) {
1526 hw_dbg(hw, "Phy info is only valid for copper media\n");
1527 return -E1000_ERR_CONFIG;
1528 }
1529
1530 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1531 if (ret_val)
1532 return ret_val;
1533
1534 if (!link) {
1535 hw_dbg(hw, "Phy info is only valid if link is up\n");
1536 return -E1000_ERR_CONFIG;
1537 }
1538
1539 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1540 if (ret_val)
1541 return ret_val;
1542
1543 phy->polarity_correction = (phy_data &
1544 M88E1000_PSCR_POLARITY_REVERSAL);
1545
1546 ret_val = e1000_check_polarity_m88(hw);
1547 if (ret_val)
1548 return ret_val;
1549
1550 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1551 if (ret_val)
1552 return ret_val;
1553
1554 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1555
1556 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1557 ret_val = e1000_get_cable_length(hw);
1558 if (ret_val)
1559 return ret_val;
1560
1561 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1562 if (ret_val)
1563 return ret_val;
1564
1565 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1566 ? e1000_1000t_rx_status_ok
1567 : e1000_1000t_rx_status_not_ok;
1568
1569 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1570 ? e1000_1000t_rx_status_ok
1571 : e1000_1000t_rx_status_not_ok;
1572 } else {
1573 /* Set values to "undefined" */
1574 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1575 phy->local_rx = e1000_1000t_rx_status_undefined;
1576 phy->remote_rx = e1000_1000t_rx_status_undefined;
1577 }
1578
1579 return ret_val;
1580 }
1581
1582 /**
1583 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1584 * @hw: pointer to the HW structure
1585 *
1586 * Read PHY status to determine if link is up. If link is up, then
1587 * set/determine 10base-T extended distance and polarity correction. Read
1588 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1589 * determine on the cable length, local and remote receiver.
1590 **/
1591 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1592 {
1593 struct e1000_phy_info *phy = &hw->phy;
1594 s32 ret_val;
1595 u16 data;
1596 bool link;
1597
1598 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1599 if (ret_val)
1600 return ret_val;
1601
1602 if (!link) {
1603 hw_dbg(hw, "Phy info is only valid if link is up\n");
1604 return -E1000_ERR_CONFIG;
1605 }
1606
1607 phy->polarity_correction = 1;
1608
1609 ret_val = e1000_check_polarity_igp(hw);
1610 if (ret_val)
1611 return ret_val;
1612
1613 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1614 if (ret_val)
1615 return ret_val;
1616
1617 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
1618
1619 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1620 IGP01E1000_PSSR_SPEED_1000MBPS) {
1621 ret_val = e1000_get_cable_length(hw);
1622 if (ret_val)
1623 return ret_val;
1624
1625 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
1626 if (ret_val)
1627 return ret_val;
1628
1629 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1630 ? e1000_1000t_rx_status_ok
1631 : e1000_1000t_rx_status_not_ok;
1632
1633 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1634 ? e1000_1000t_rx_status_ok
1635 : e1000_1000t_rx_status_not_ok;
1636 } else {
1637 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1638 phy->local_rx = e1000_1000t_rx_status_undefined;
1639 phy->remote_rx = e1000_1000t_rx_status_undefined;
1640 }
1641
1642 return ret_val;
1643 }
1644
1645 /**
1646 * e1000e_phy_sw_reset - PHY software reset
1647 * @hw: pointer to the HW structure
1648 *
1649 * Does a software reset of the PHY by reading the PHY control register and
1650 * setting/write the control register reset bit to the PHY.
1651 **/
1652 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
1653 {
1654 s32 ret_val;
1655 u16 phy_ctrl;
1656
1657 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1658 if (ret_val)
1659 return ret_val;
1660
1661 phy_ctrl |= MII_CR_RESET;
1662 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1663 if (ret_val)
1664 return ret_val;
1665
1666 udelay(1);
1667
1668 return ret_val;
1669 }
1670
1671 /**
1672 * e1000e_phy_hw_reset_generic - PHY hardware reset
1673 * @hw: pointer to the HW structure
1674 *
1675 * Verify the reset block is not blocking us from resetting. Acquire
1676 * semaphore (if necessary) and read/set/write the device control reset
1677 * bit in the PHY. Wait the appropriate delay time for the device to
1678 * reset and release the semaphore (if necessary).
1679 **/
1680 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1681 {
1682 struct e1000_phy_info *phy = &hw->phy;
1683 s32 ret_val;
1684 u32 ctrl;
1685
1686 ret_val = e1000_check_reset_block(hw);
1687 if (ret_val)
1688 return 0;
1689
1690 ret_val = phy->ops.acquire_phy(hw);
1691 if (ret_val)
1692 return ret_val;
1693
1694 ctrl = er32(CTRL);
1695 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
1696 e1e_flush();
1697
1698 udelay(phy->reset_delay_us);
1699
1700 ew32(CTRL, ctrl);
1701 e1e_flush();
1702
1703 udelay(150);
1704
1705 phy->ops.release_phy(hw);
1706
1707 return e1000_get_phy_cfg_done(hw);
1708 }
1709
1710 /**
1711 * e1000e_get_cfg_done - Generic configuration done
1712 * @hw: pointer to the HW structure
1713 *
1714 * Generic function to wait 10 milli-seconds for configuration to complete
1715 * and return success.
1716 **/
1717 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
1718 {
1719 mdelay(10);
1720 return 0;
1721 }
1722
1723 /* Internal function pointers */
1724
1725 /**
1726 * e1000_get_phy_cfg_done - Generic PHY configuration done
1727 * @hw: pointer to the HW structure
1728 *
1729 * Return success if silicon family did not implement a family specific
1730 * get_cfg_done function.
1731 **/
1732 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1733 {
1734 if (hw->phy.ops.get_cfg_done)
1735 return hw->phy.ops.get_cfg_done(hw);
1736
1737 return 0;
1738 }
1739
1740 /**
1741 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1742 * @hw: pointer to the HW structure
1743 *
1744 * When the silicon family has not implemented a forced speed/duplex
1745 * function for the PHY, simply return 0.
1746 **/
1747 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1748 {
1749 if (hw->phy.ops.force_speed_duplex)
1750 return hw->phy.ops.force_speed_duplex(hw);
1751
1752 return 0;
1753 }
1754
1755 /**
1756 * e1000e_get_phy_type_from_id - Get PHY type from id
1757 * @phy_id: phy_id read from the phy
1758 *
1759 * Returns the phy type from the id.
1760 **/
1761 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1762 {
1763 enum e1000_phy_type phy_type = e1000_phy_unknown;
1764
1765 switch (phy_id) {
1766 case M88E1000_I_PHY_ID:
1767 case M88E1000_E_PHY_ID:
1768 case M88E1111_I_PHY_ID:
1769 case M88E1011_I_PHY_ID:
1770 phy_type = e1000_phy_m88;
1771 break;
1772 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
1773 phy_type = e1000_phy_igp_2;
1774 break;
1775 case GG82563_E_PHY_ID:
1776 phy_type = e1000_phy_gg82563;
1777 break;
1778 case IGP03E1000_E_PHY_ID:
1779 phy_type = e1000_phy_igp_3;
1780 break;
1781 case IFE_E_PHY_ID:
1782 case IFE_PLUS_E_PHY_ID:
1783 case IFE_C_E_PHY_ID:
1784 phy_type = e1000_phy_ife;
1785 break;
1786 case BME1000_E_PHY_ID:
1787 case BME1000_E_PHY_ID_R2:
1788 phy_type = e1000_phy_bm;
1789 break;
1790 default:
1791 phy_type = e1000_phy_unknown;
1792 break;
1793 }
1794 return phy_type;
1795 }
1796
1797 /**
1798 * e1000e_determine_phy_address - Determines PHY address.
1799 * @hw: pointer to the HW structure
1800 *
1801 * This uses a trial and error method to loop through possible PHY
1802 * addresses. It tests each by reading the PHY ID registers and
1803 * checking for a match.
1804 **/
1805 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
1806 {
1807 s32 ret_val = -E1000_ERR_PHY_TYPE;
1808 u32 phy_addr= 0;
1809 u32 i = 0;
1810 enum e1000_phy_type phy_type = e1000_phy_unknown;
1811
1812 do {
1813 for (phy_addr = 0; phy_addr < 4; phy_addr++) {
1814 hw->phy.addr = phy_addr;
1815 e1000e_get_phy_id(hw);
1816 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
1817
1818 /*
1819 * If phy_type is valid, break - we found our
1820 * PHY address
1821 */
1822 if (phy_type != e1000_phy_unknown) {
1823 ret_val = 0;
1824 break;
1825 }
1826 }
1827 i++;
1828 } while ((ret_val != 0) && (i < 100));
1829
1830 return ret_val;
1831 }
1832
1833 /**
1834 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
1835 * @page: page to access
1836 *
1837 * Returns the phy address for the page requested.
1838 **/
1839 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
1840 {
1841 u32 phy_addr = 2;
1842
1843 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
1844 phy_addr = 1;
1845
1846 return phy_addr;
1847 }
1848
1849 /**
1850 * e1000e_write_phy_reg_bm - Write BM PHY register
1851 * @hw: pointer to the HW structure
1852 * @offset: register offset to write to
1853 * @data: data to write at register offset
1854 *
1855 * Acquires semaphore, if necessary, then writes the data to PHY register
1856 * at the offset. Release any acquired semaphores before exiting.
1857 **/
1858 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
1859 {
1860 s32 ret_val;
1861 u32 page_select = 0;
1862 u32 page = offset >> IGP_PAGE_SHIFT;
1863 u32 page_shift = 0;
1864
1865 /* Page 800 works differently than the rest so it has its own func */
1866 if (page == BM_WUC_PAGE) {
1867 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
1868 false);
1869 goto out;
1870 }
1871
1872 ret_val = hw->phy.ops.acquire_phy(hw);
1873 if (ret_val)
1874 goto out;
1875
1876 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
1877
1878 if (offset > MAX_PHY_MULTI_PAGE_REG) {
1879 /*
1880 * Page select is register 31 for phy address 1 and 22 for
1881 * phy address 2 and 3. Page select is shifted only for
1882 * phy address 1.
1883 */
1884 if (hw->phy.addr == 1) {
1885 page_shift = IGP_PAGE_SHIFT;
1886 page_select = IGP01E1000_PHY_PAGE_SELECT;
1887 } else {
1888 page_shift = 0;
1889 page_select = BM_PHY_PAGE_SELECT;
1890 }
1891
1892 /* Page is shifted left, PHY expects (page x 32) */
1893 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
1894 (page << page_shift));
1895 if (ret_val) {
1896 hw->phy.ops.release_phy(hw);
1897 goto out;
1898 }
1899 }
1900
1901 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
1902 data);
1903
1904 hw->phy.ops.release_phy(hw);
1905
1906 out:
1907 return ret_val;
1908 }
1909
1910 /**
1911 * e1000e_read_phy_reg_bm - Read BM PHY register
1912 * @hw: pointer to the HW structure
1913 * @offset: register offset to be read
1914 * @data: pointer to the read data
1915 *
1916 * Acquires semaphore, if necessary, then reads the PHY register at offset
1917 * and storing the retrieved information in data. Release any acquired
1918 * semaphores before exiting.
1919 **/
1920 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
1921 {
1922 s32 ret_val;
1923 u32 page_select = 0;
1924 u32 page = offset >> IGP_PAGE_SHIFT;
1925 u32 page_shift = 0;
1926
1927 /* Page 800 works differently than the rest so it has its own func */
1928 if (page == BM_WUC_PAGE) {
1929 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
1930 true);
1931 goto out;
1932 }
1933
1934 ret_val = hw->phy.ops.acquire_phy(hw);
1935 if (ret_val)
1936 goto out;
1937
1938 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
1939
1940 if (offset > MAX_PHY_MULTI_PAGE_REG) {
1941 /*
1942 * Page select is register 31 for phy address 1 and 22 for
1943 * phy address 2 and 3. Page select is shifted only for
1944 * phy address 1.
1945 */
1946 if (hw->phy.addr == 1) {
1947 page_shift = IGP_PAGE_SHIFT;
1948 page_select = IGP01E1000_PHY_PAGE_SELECT;
1949 } else {
1950 page_shift = 0;
1951 page_select = BM_PHY_PAGE_SELECT;
1952 }
1953
1954 /* Page is shifted left, PHY expects (page x 32) */
1955 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
1956 (page << page_shift));
1957 if (ret_val) {
1958 hw->phy.ops.release_phy(hw);
1959 goto out;
1960 }
1961 }
1962
1963 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
1964 data);
1965 hw->phy.ops.release_phy(hw);
1966
1967 out:
1968 return ret_val;
1969 }
1970
1971 /**
1972 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
1973 * @hw: pointer to the HW structure
1974 * @offset: register offset to be read or written
1975 * @data: pointer to the data to read or write
1976 * @read: determines if operation is read or write
1977 *
1978 * Acquires semaphore, if necessary, then reads the PHY register at offset
1979 * and storing the retrieved information in data. Release any acquired
1980 * semaphores before exiting. Note that procedure to read the wakeup
1981 * registers are different. It works as such:
1982 * 1) Set page 769, register 17, bit 2 = 1
1983 * 2) Set page to 800 for host (801 if we were manageability)
1984 * 3) Write the address using the address opcode (0x11)
1985 * 4) Read or write the data using the data opcode (0x12)
1986 * 5) Restore 769_17.2 to its original value
1987 **/
1988 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
1989 u16 *data, bool read)
1990 {
1991 s32 ret_val;
1992 u16 reg = ((u16)offset) & PHY_REG_MASK;
1993 u16 phy_reg = 0;
1994 u8 phy_acquired = 1;
1995
1996
1997 ret_val = hw->phy.ops.acquire_phy(hw);
1998 if (ret_val) {
1999 phy_acquired = 0;
2000 goto out;
2001 }
2002
2003 /* All operations in this function are phy address 1 */
2004 hw->phy.addr = 1;
2005
2006 /* Set page 769 */
2007 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2008 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2009
2010 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2011 if (ret_val)
2012 goto out;
2013
2014 /* First clear bit 4 to avoid a power state change */
2015 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2016 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2017 if (ret_val)
2018 goto out;
2019
2020 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2021 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2022 phy_reg | BM_WUC_ENABLE_BIT);
2023 if (ret_val)
2024 goto out;
2025
2026 /* Select page 800 */
2027 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2028 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2029
2030 /* Write the page 800 offset value using opcode 0x11 */
2031 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2032 if (ret_val)
2033 goto out;
2034
2035 if (read) {
2036 /* Read the page 800 value using opcode 0x12 */
2037 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2038 data);
2039 } else {
2040 /* Read the page 800 value using opcode 0x12 */
2041 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2042 *data);
2043 }
2044
2045 if (ret_val)
2046 goto out;
2047
2048 /*
2049 * Restore 769_17.2 to its original value
2050 * Set page 769
2051 */
2052 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2053 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2054
2055 /* Clear 769_17.2 */
2056 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2057
2058 out:
2059 if (phy_acquired == 1)
2060 hw->phy.ops.release_phy(hw);
2061 return ret_val;
2062 }
2063
2064 /**
2065 * e1000e_commit_phy - Soft PHY reset
2066 * @hw: pointer to the HW structure
2067 *
2068 * Performs a soft PHY reset on those that apply. This is a function pointer
2069 * entry point called by drivers.
2070 **/
2071 s32 e1000e_commit_phy(struct e1000_hw *hw)
2072 {
2073 if (hw->phy.ops.commit_phy)
2074 return hw->phy.ops.commit_phy(hw);
2075
2076 return 0;
2077 }
2078
2079 /**
2080 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2081 * @hw: pointer to the HW structure
2082 * @active: boolean used to enable/disable lplu
2083 *
2084 * Success returns 0, Failure returns 1
2085 *
2086 * The low power link up (lplu) state is set to the power management level D0
2087 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2088 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2089 * is used during Dx states where the power conservation is most important.
2090 * During driver activity, SmartSpeed should be enabled so performance is
2091 * maintained. This is a function pointer entry point called by drivers.
2092 **/
2093 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2094 {
2095 if (hw->phy.ops.set_d0_lplu_state)
2096 return hw->phy.ops.set_d0_lplu_state(hw, active);
2097
2098 return 0;
2099 }
Support for the Chinese Samsung S3C2440 based development boards