3 * Purpose: Generic MCA handling layer
5 * Copyright (C) 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Copyright (C) 2002 Dell Inc.
9 * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
11 * Copyright (C) 2002 Intel
12 * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
14 * Copyright (C) 2001 Intel
15 * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
17 * Copyright (C) 2000 Intel
18 * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
20 * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
21 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
23 * Copyright (C) 2006 FUJITSU LIMITED
24 * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
26 * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
27 * Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
28 * added min save state dump, added INIT handler.
30 * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
31 * Added setup of CMCI and CPEI IRQs, logging of corrected platform
32 * errors, completed code for logging of corrected & uncorrected
33 * machine check errors, and updated for conformance with Nov. 2000
34 * revision of the SAL 3.0 spec.
36 * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
37 * Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
38 * set SAL default return values, changed error record structure to
39 * linked list, added init call to sal_get_state_info_size().
41 * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
44 * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
45 * Added INIT backtrace support.
47 * 2003-12-08 Keith Owens <kaos@sgi.com>
48 * smp_call_function() must not be called from interrupt context
49 * (can deadlock on tasklist_lock).
50 * Use keventd to call smp_call_function().
52 * 2004-02-01 Keith Owens <kaos@sgi.com>
53 * Avoid deadlock when using printk() for MCA and INIT records.
54 * Delete all record printing code, moved to salinfo_decode in user
55 * space. Mark variables and functions static where possible.
56 * Delete dead variables and functions. Reorder to remove the need
57 * for forward declarations and to consolidate related code.
59 * 2005-08-12 Keith Owens <kaos@sgi.com>
60 * Convert MCA/INIT handlers to use per event stacks and SAL/OS
63 * 2005-10-07 Keith Owens <kaos@sgi.com>
64 * Add notify_die() hooks.
66 * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
67 * Add printing support for MCA/INIT.
69 * 2007-04-27 Russ Anderson <rja@sgi.com>
70 * Support multiple cpus going through OS_MCA in the same event.
72 #include <linux/types.h>
73 #include <linux/init.h>
74 #include <linux/sched.h>
75 #include <linux/interrupt.h>
76 #include <linux/irq.h>
77 #include <linux/bootmem.h>
78 #include <linux/acpi.h>
79 #include <linux/timer.h>
80 #include <linux/module.h>
81 #include <linux/kernel.h>
82 #include <linux/smp.h>
83 #include <linux/workqueue.h>
84 #include <linux/cpumask.h>
85 #include <linux/kdebug.h>
86 #include <linux/cpu.h>
88 #include <asm/delay.h>
89 #include <asm/machvec.h>
90 #include <asm/meminit.h>
92 #include <asm/ptrace.h>
93 #include <asm/system.h>
96 #include <asm/kexec.h>
99 #include <asm/hw_irq.h>
105 #if defined(IA64_MCA_DEBUG_INFO)
106 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
108 # define IA64_MCA_DEBUG(fmt...)
111 /* Used by mca_asm.S */
112 DEFINE_PER_CPU(u64
, ia64_mca_data
); /* == __per_cpu_mca[smp_processor_id()] */
113 DEFINE_PER_CPU(u64
, ia64_mca_per_cpu_pte
); /* PTE to map per-CPU area */
114 DEFINE_PER_CPU(u64
, ia64_mca_pal_pte
); /* PTE to map PAL code */
115 DEFINE_PER_CPU(u64
, ia64_mca_pal_base
); /* vaddr PAL code granule */
116 DEFINE_PER_CPU(u64
, ia64_mca_tr_reload
); /* Flag for TR reload */
118 unsigned long __per_cpu_mca
[NR_CPUS
];
121 extern void ia64_os_init_dispatch_monarch (void);
122 extern void ia64_os_init_dispatch_slave (void);
124 static int monarch_cpu
= -1;
126 static ia64_mc_info_t ia64_mc_info
;
128 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
129 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
130 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
131 #define CPE_HISTORY_LENGTH 5
132 #define CMC_HISTORY_LENGTH 5
135 static struct timer_list cpe_poll_timer
;
137 static struct timer_list cmc_poll_timer
;
139 * This variable tells whether we are currently in polling mode.
140 * Start with this in the wrong state so we won't play w/ timers
141 * before the system is ready.
143 static int cmc_polling_enabled
= 1;
146 * Clearing this variable prevents CPE polling from getting activated
147 * in mca_late_init. Use it if your system doesn't provide a CPEI,
148 * but encounters problems retrieving CPE logs. This should only be
149 * necessary for debugging.
151 static int cpe_poll_enabled
= 1;
153 extern void salinfo_log_wakeup(int type
, u8
*buffer
, u64 size
, int irqsafe
);
155 static int mca_init __initdata
;
158 * limited & delayed printing support for MCA/INIT handler
161 #define mprintk(fmt...) ia64_mca_printk(fmt)
163 #define MLOGBUF_SIZE (512+256*NR_CPUS)
164 #define MLOGBUF_MSGMAX 256
165 static char mlogbuf
[MLOGBUF_SIZE
];
166 static DEFINE_SPINLOCK(mlogbuf_wlock
); /* mca context only */
167 static DEFINE_SPINLOCK(mlogbuf_rlock
); /* normal context only */
168 static unsigned long mlogbuf_start
;
169 static unsigned long mlogbuf_end
;
170 static unsigned int mlogbuf_finished
= 0;
171 static unsigned long mlogbuf_timestamp
= 0;
173 static int loglevel_save
= -1;
174 #define BREAK_LOGLEVEL(__console_loglevel) \
175 oops_in_progress = 1; \
176 if (loglevel_save < 0) \
177 loglevel_save = __console_loglevel; \
178 __console_loglevel = 15;
180 #define RESTORE_LOGLEVEL(__console_loglevel) \
181 if (loglevel_save >= 0) { \
182 __console_loglevel = loglevel_save; \
183 loglevel_save = -1; \
185 mlogbuf_finished = 0; \
186 oops_in_progress = 0;
189 * Push messages into buffer, print them later if not urgent.
191 void ia64_mca_printk(const char *fmt
, ...)
195 char temp_buf
[MLOGBUF_MSGMAX
];
199 printed_len
= vscnprintf(temp_buf
, sizeof(temp_buf
), fmt
, args
);
202 /* Copy the output into mlogbuf */
203 if (oops_in_progress
) {
204 /* mlogbuf was abandoned, use printk directly instead. */
207 spin_lock(&mlogbuf_wlock
);
208 for (p
= temp_buf
; *p
; p
++) {
209 unsigned long next
= (mlogbuf_end
+ 1) % MLOGBUF_SIZE
;
210 if (next
!= mlogbuf_start
) {
211 mlogbuf
[mlogbuf_end
] = *p
;
218 mlogbuf
[mlogbuf_end
] = '\0';
219 spin_unlock(&mlogbuf_wlock
);
222 EXPORT_SYMBOL(ia64_mca_printk
);
225 * Print buffered messages.
226 * NOTE: call this after returning normal context. (ex. from salinfod)
228 void ia64_mlogbuf_dump(void)
230 char temp_buf
[MLOGBUF_MSGMAX
];
234 unsigned int printed_len
;
236 /* Get output from mlogbuf */
237 while (mlogbuf_start
!= mlogbuf_end
) {
242 spin_lock_irqsave(&mlogbuf_rlock
, flags
);
244 index
= mlogbuf_start
;
245 while (index
!= mlogbuf_end
) {
247 index
= (index
+ 1) % MLOGBUF_SIZE
;
251 if (++printed_len
>= MLOGBUF_MSGMAX
- 1)
257 mlogbuf_start
= index
;
259 mlogbuf_timestamp
= 0;
260 spin_unlock_irqrestore(&mlogbuf_rlock
, flags
);
263 EXPORT_SYMBOL(ia64_mlogbuf_dump
);
266 * Call this if system is going to down or if immediate flushing messages to
267 * console is required. (ex. recovery was failed, crash dump is going to be
268 * invoked, long-wait rendezvous etc.)
269 * NOTE: this should be called from monarch.
271 static void ia64_mlogbuf_finish(int wait
)
273 BREAK_LOGLEVEL(console_loglevel
);
275 spin_lock_init(&mlogbuf_rlock
);
277 printk(KERN_EMERG
"mlogbuf_finish: printing switched to urgent mode, "
278 "MCA/INIT might be dodgy or fail.\n");
283 /* wait for console */
284 printk("Delaying for 5 seconds...\n");
287 mlogbuf_finished
= 1;
291 * Print buffered messages from INIT context.
293 static void ia64_mlogbuf_dump_from_init(void)
295 if (mlogbuf_finished
)
298 if (mlogbuf_timestamp
&& (mlogbuf_timestamp
+ 30*HZ
> jiffies
)) {
299 printk(KERN_ERR
"INIT: mlogbuf_dump is interrupted by INIT "
300 " and the system seems to be messed up.\n");
301 ia64_mlogbuf_finish(0);
305 if (!spin_trylock(&mlogbuf_rlock
)) {
306 printk(KERN_ERR
"INIT: mlogbuf_dump is interrupted by INIT. "
307 "Generated messages other than stack dump will be "
308 "buffered to mlogbuf and will be printed later.\n");
309 printk(KERN_ERR
"INIT: If messages would not printed after "
310 "this INIT, wait 30sec and assert INIT again.\n");
311 if (!mlogbuf_timestamp
)
312 mlogbuf_timestamp
= jiffies
;
315 spin_unlock(&mlogbuf_rlock
);
320 ia64_mca_spin(const char *func
)
322 if (monarch_cpu
== smp_processor_id())
323 ia64_mlogbuf_finish(0);
324 mprintk(KERN_EMERG
"%s: spinning here, not returning to SAL\n", func
);
329 * IA64_MCA log support
331 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
332 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
334 typedef struct ia64_state_log_s
338 unsigned long isl_count
;
339 ia64_err_rec_t
*isl_log
[IA64_MAX_LOGS
]; /* need space to store header + error log */
342 static ia64_state_log_t ia64_state_log
[IA64_MAX_LOG_TYPES
];
344 #define IA64_LOG_ALLOCATE(it, size) \
345 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
346 (ia64_err_rec_t *)alloc_bootmem(size); \
347 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
348 (ia64_err_rec_t *)alloc_bootmem(size);}
349 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
350 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
351 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
352 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
353 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
354 #define IA64_LOG_INDEX_INC(it) \
355 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
356 ia64_state_log[it].isl_count++;}
357 #define IA64_LOG_INDEX_DEC(it) \
358 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
359 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
360 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
361 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
365 * Reset the OS ia64 log buffer
366 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
370 ia64_log_init(int sal_info_type
)
374 IA64_LOG_NEXT_INDEX(sal_info_type
) = 0;
375 IA64_LOG_LOCK_INIT(sal_info_type
);
377 // SAL will tell us the maximum size of any error record of this type
378 max_size
= ia64_sal_get_state_info_size(sal_info_type
);
380 /* alloc_bootmem() doesn't like zero-sized allocations! */
383 // set up OS data structures to hold error info
384 IA64_LOG_ALLOCATE(sal_info_type
, max_size
);
385 memset(IA64_LOG_CURR_BUFFER(sal_info_type
), 0, max_size
);
386 memset(IA64_LOG_NEXT_BUFFER(sal_info_type
), 0, max_size
);
392 * Get the current MCA log from SAL and copy it into the OS log buffer.
394 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
395 * irq_safe whether you can use printk at this point
396 * Outputs : size (total record length)
397 * *buffer (ptr to error record)
401 ia64_log_get(int sal_info_type
, u8
**buffer
, int irq_safe
)
403 sal_log_record_header_t
*log_buffer
;
407 IA64_LOG_LOCK(sal_info_type
);
409 /* Get the process state information */
410 log_buffer
= IA64_LOG_NEXT_BUFFER(sal_info_type
);
412 total_len
= ia64_sal_get_state_info(sal_info_type
, (u64
*)log_buffer
);
415 IA64_LOG_INDEX_INC(sal_info_type
);
416 IA64_LOG_UNLOCK(sal_info_type
);
418 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
419 __func__
, sal_info_type
, total_len
);
421 *buffer
= (u8
*) log_buffer
;
424 IA64_LOG_UNLOCK(sal_info_type
);
430 * ia64_mca_log_sal_error_record
432 * This function retrieves a specified error record type from SAL
433 * and wakes up any processes waiting for error records.
435 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
436 * FIXME: remove MCA and irq_safe.
439 ia64_mca_log_sal_error_record(int sal_info_type
)
442 sal_log_record_header_t
*rh
;
444 int irq_safe
= sal_info_type
!= SAL_INFO_TYPE_MCA
;
445 #ifdef IA64_MCA_DEBUG_INFO
446 static const char * const rec_name
[] = { "MCA", "INIT", "CMC", "CPE" };
449 size
= ia64_log_get(sal_info_type
, &buffer
, irq_safe
);
453 salinfo_log_wakeup(sal_info_type
, buffer
, size
, irq_safe
);
456 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
458 sal_info_type
< ARRAY_SIZE(rec_name
) ? rec_name
[sal_info_type
] : "UNKNOWN");
460 /* Clear logs from corrected errors in case there's no user-level logger */
461 rh
= (sal_log_record_header_t
*)buffer
;
462 if (rh
->severity
== sal_log_severity_corrected
)
463 ia64_sal_clear_state_info(sal_info_type
);
468 * See if the MCA surfaced in an instruction range
469 * that has been tagged as recoverable.
472 * first First address range to check
473 * last Last address range to check
474 * ip Instruction pointer, address we are looking for
477 * 1 on Success (in the table)/ 0 on Failure (not in the table)
480 search_mca_table (const struct mca_table_entry
*first
,
481 const struct mca_table_entry
*last
,
484 const struct mca_table_entry
*curr
;
485 u64 curr_start
, curr_end
;
488 while (curr
<= last
) {
489 curr_start
= (u64
) &curr
->start_addr
+ curr
->start_addr
;
490 curr_end
= (u64
) &curr
->end_addr
+ curr
->end_addr
;
492 if ((ip
>= curr_start
) && (ip
<= curr_end
)) {
500 /* Given an address, look for it in the mca tables. */
501 int mca_recover_range(unsigned long addr
)
503 extern struct mca_table_entry __start___mca_table
[];
504 extern struct mca_table_entry __stop___mca_table
[];
506 return search_mca_table(__start___mca_table
, __stop___mca_table
-1, addr
);
508 EXPORT_SYMBOL_GPL(mca_recover_range
);
513 int ia64_cpe_irq
= -1;
516 ia64_mca_cpe_int_handler (int cpe_irq
, void *arg
)
518 static unsigned long cpe_history
[CPE_HISTORY_LENGTH
];
520 static DEFINE_SPINLOCK(cpe_history_lock
);
522 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
523 __func__
, cpe_irq
, smp_processor_id());
525 /* SAL spec states this should run w/ interrupts enabled */
528 spin_lock(&cpe_history_lock
);
529 if (!cpe_poll_enabled
&& cpe_vector
>= 0) {
531 int i
, count
= 1; /* we know 1 happened now */
532 unsigned long now
= jiffies
;
534 for (i
= 0; i
< CPE_HISTORY_LENGTH
; i
++) {
535 if (now
- cpe_history
[i
] <= HZ
)
539 IA64_MCA_DEBUG(KERN_INFO
"CPE threshold %d/%d\n", count
, CPE_HISTORY_LENGTH
);
540 if (count
>= CPE_HISTORY_LENGTH
) {
542 cpe_poll_enabled
= 1;
543 spin_unlock(&cpe_history_lock
);
544 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR
));
547 * Corrected errors will still be corrected, but
548 * make sure there's a log somewhere that indicates
549 * something is generating more than we can handle.
551 printk(KERN_WARNING
"WARNING: Switching to polling CPE handler; error records may be lost\n");
553 mod_timer(&cpe_poll_timer
, jiffies
+ MIN_CPE_POLL_INTERVAL
);
555 /* lock already released, get out now */
558 cpe_history
[index
++] = now
;
559 if (index
== CPE_HISTORY_LENGTH
)
563 spin_unlock(&cpe_history_lock
);
565 /* Get the CPE error record and log it */
566 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE
);
571 #endif /* CONFIG_ACPI */
575 * ia64_mca_register_cpev
577 * Register the corrected platform error vector with SAL.
580 * cpev Corrected Platform Error Vector number
586 ia64_mca_register_cpev (int cpev
)
588 /* Register the CPE interrupt vector with SAL */
589 struct ia64_sal_retval isrv
;
591 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT
, SAL_MC_PARAM_MECHANISM_INT
, cpev
, 0, 0);
593 printk(KERN_ERR
"Failed to register Corrected Platform "
594 "Error interrupt vector with SAL (status %ld)\n", isrv
.status
);
598 IA64_MCA_DEBUG("%s: corrected platform error "
599 "vector %#x registered\n", __func__
, cpev
);
601 #endif /* CONFIG_ACPI */
604 * ia64_mca_cmc_vector_setup
606 * Setup the corrected machine check vector register in the processor.
607 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
608 * This function is invoked on a per-processor basis.
617 ia64_mca_cmc_vector_setup (void)
621 cmcv
.cmcv_regval
= 0;
622 cmcv
.cmcv_mask
= 1; /* Mask/disable interrupt at first */
623 cmcv
.cmcv_vector
= IA64_CMC_VECTOR
;
624 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
626 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
627 __func__
, smp_processor_id(), IA64_CMC_VECTOR
);
629 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
630 __func__
, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV
));
634 * ia64_mca_cmc_vector_disable
636 * Mask the corrected machine check vector register in the processor.
637 * This function is invoked on a per-processor basis.
646 ia64_mca_cmc_vector_disable (void *dummy
)
650 cmcv
.cmcv_regval
= ia64_getreg(_IA64_REG_CR_CMCV
);
652 cmcv
.cmcv_mask
= 1; /* Mask/disable interrupt */
653 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
655 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
656 __func__
, smp_processor_id(), cmcv
.cmcv_vector
);
660 * ia64_mca_cmc_vector_enable
662 * Unmask the corrected machine check vector register in the processor.
663 * This function is invoked on a per-processor basis.
672 ia64_mca_cmc_vector_enable (void *dummy
)
676 cmcv
.cmcv_regval
= ia64_getreg(_IA64_REG_CR_CMCV
);
678 cmcv
.cmcv_mask
= 0; /* Unmask/enable interrupt */
679 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
681 IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
682 __func__
, smp_processor_id(), cmcv
.cmcv_vector
);
686 * ia64_mca_cmc_vector_disable_keventd
688 * Called via keventd (smp_call_function() is not safe in interrupt context) to
689 * disable the cmc interrupt vector.
692 ia64_mca_cmc_vector_disable_keventd(struct work_struct
*unused
)
694 on_each_cpu(ia64_mca_cmc_vector_disable
, NULL
, 1, 0);
698 * ia64_mca_cmc_vector_enable_keventd
700 * Called via keventd (smp_call_function() is not safe in interrupt context) to
701 * enable the cmc interrupt vector.
704 ia64_mca_cmc_vector_enable_keventd(struct work_struct
*unused
)
706 on_each_cpu(ia64_mca_cmc_vector_enable
, NULL
, 1, 0);
712 * Send an inter-cpu interrupt to wake-up a particular cpu.
718 ia64_mca_wakeup(int cpu
)
720 platform_send_ipi(cpu
, IA64_MCA_WAKEUP_VECTOR
, IA64_IPI_DM_INT
, 0);
724 * ia64_mca_wakeup_all
726 * Wakeup all the slave cpus which have rendez'ed previously.
732 ia64_mca_wakeup_all(void)
736 /* Clear the Rendez checkin flag for all cpus */
737 for_each_online_cpu(cpu
) {
738 if (ia64_mc_info
.imi_rendez_checkin
[cpu
] == IA64_MCA_RENDEZ_CHECKIN_DONE
)
739 ia64_mca_wakeup(cpu
);
745 * ia64_mca_rendez_interrupt_handler
747 * This is handler used to put slave processors into spinloop
748 * while the monarch processor does the mca handling and later
749 * wake each slave up once the monarch is done. The state
750 * IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
751 * in SAL. The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
752 * the cpu has come out of OS rendezvous.
758 ia64_mca_rendez_int_handler(int rendez_irq
, void *arg
)
761 int cpu
= smp_processor_id();
762 struct ia64_mca_notify_die nd
=
763 { .sos
= NULL
, .monarch_cpu
= &monarch_cpu
};
765 /* Mask all interrupts */
766 local_irq_save(flags
);
767 if (notify_die(DIE_MCA_RENDZVOUS_ENTER
, "MCA", get_irq_regs(),
768 (long)&nd
, 0, 0) == NOTIFY_STOP
)
769 ia64_mca_spin(__func__
);
771 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_DONE
;
772 /* Register with the SAL monarch that the slave has
775 ia64_sal_mc_rendez();
777 if (notify_die(DIE_MCA_RENDZVOUS_PROCESS
, "MCA", get_irq_regs(),
778 (long)&nd
, 0, 0) == NOTIFY_STOP
)
779 ia64_mca_spin(__func__
);
781 /* Wait for the monarch cpu to exit. */
782 while (monarch_cpu
!= -1)
783 cpu_relax(); /* spin until monarch leaves */
785 if (notify_die(DIE_MCA_RENDZVOUS_LEAVE
, "MCA", get_irq_regs(),
786 (long)&nd
, 0, 0) == NOTIFY_STOP
)
787 ia64_mca_spin(__func__
);
789 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
790 /* Enable all interrupts */
791 local_irq_restore(flags
);
796 * ia64_mca_wakeup_int_handler
798 * The interrupt handler for processing the inter-cpu interrupt to the
799 * slave cpu which was spinning in the rendez loop.
800 * Since this spinning is done by turning off the interrupts and
801 * polling on the wakeup-interrupt bit in the IRR, there is
802 * nothing useful to be done in the handler.
804 * Inputs : wakeup_irq (Wakeup-interrupt bit)
805 * arg (Interrupt handler specific argument)
810 ia64_mca_wakeup_int_handler(int wakeup_irq
, void *arg
)
815 /* Function pointer for extra MCA recovery */
816 int (*ia64_mca_ucmc_extension
)
817 (void*,struct ia64_sal_os_state
*)
821 ia64_reg_MCA_extension(int (*fn
)(void *, struct ia64_sal_os_state
*))
823 if (ia64_mca_ucmc_extension
)
826 ia64_mca_ucmc_extension
= fn
;
831 ia64_unreg_MCA_extension(void)
833 if (ia64_mca_ucmc_extension
)
834 ia64_mca_ucmc_extension
= NULL
;
837 EXPORT_SYMBOL(ia64_reg_MCA_extension
);
838 EXPORT_SYMBOL(ia64_unreg_MCA_extension
);
842 copy_reg(const u64
*fr
, u64 fnat
, u64
*tr
, u64
*tnat
)
844 u64 fslot
, tslot
, nat
;
846 fslot
= ((unsigned long)fr
>> 3) & 63;
847 tslot
= ((unsigned long)tr
>> 3) & 63;
848 *tnat
&= ~(1UL << tslot
);
849 nat
= (fnat
>> fslot
) & 1;
850 *tnat
|= (nat
<< tslot
);
853 /* Change the comm field on the MCA/INT task to include the pid that
854 * was interrupted, it makes for easier debugging. If that pid was 0
855 * (swapper or nested MCA/INIT) then use the start of the previous comm
856 * field suffixed with its cpu.
860 ia64_mca_modify_comm(const struct task_struct
*previous_current
)
862 char *p
, comm
[sizeof(current
->comm
)];
863 if (previous_current
->pid
)
864 snprintf(comm
, sizeof(comm
), "%s %d",
865 current
->comm
, previous_current
->pid
);
868 if ((p
= strchr(previous_current
->comm
, ' ')))
869 l
= p
- previous_current
->comm
;
871 l
= strlen(previous_current
->comm
);
872 snprintf(comm
, sizeof(comm
), "%s %*s %d",
873 current
->comm
, l
, previous_current
->comm
,
874 task_thread_info(previous_current
)->cpu
);
876 memcpy(current
->comm
, comm
, sizeof(current
->comm
));
879 /* On entry to this routine, we are running on the per cpu stack, see
880 * mca_asm.h. The original stack has not been touched by this event. Some of
881 * the original stack's registers will be in the RBS on this stack. This stack
882 * also contains a partial pt_regs and switch_stack, the rest of the data is in
885 * The first thing to do is modify the original stack to look like a blocked
886 * task so we can run backtrace on the original task. Also mark the per cpu
887 * stack as current to ensure that we use the correct task state, it also means
888 * that we can do backtrace on the MCA/INIT handler code itself.
891 static struct task_struct
*
892 ia64_mca_modify_original_stack(struct pt_regs
*regs
,
893 const struct switch_stack
*sw
,
894 struct ia64_sal_os_state
*sos
,
899 extern char ia64_leave_kernel
[]; /* Need asm address, not function descriptor */
900 const pal_min_state_area_t
*ms
= sos
->pal_min_state
;
901 struct task_struct
*previous_current
;
902 struct pt_regs
*old_regs
;
903 struct switch_stack
*old_sw
;
904 unsigned size
= sizeof(struct pt_regs
) +
905 sizeof(struct switch_stack
) + 16;
906 u64
*old_bspstore
, *old_bsp
;
907 u64
*new_bspstore
, *new_bsp
;
908 u64 old_unat
, old_rnat
, new_rnat
, nat
;
909 u64 slots
, loadrs
= regs
->loadrs
;
910 u64 r12
= ms
->pmsa_gr
[12-1], r13
= ms
->pmsa_gr
[13-1];
911 u64 ar_bspstore
= regs
->ar_bspstore
;
912 u64 ar_bsp
= regs
->ar_bspstore
+ (loadrs
>> 16);
915 int cpu
= smp_processor_id();
917 previous_current
= curr_task(cpu
);
918 set_curr_task(cpu
, current
);
919 if ((p
= strchr(current
->comm
, ' ')))
922 /* Best effort attempt to cope with MCA/INIT delivered while in
925 regs
->cr_ipsr
= ms
->pmsa_ipsr
;
926 if (ia64_psr(regs
)->dt
== 0) {
938 if (ia64_psr(regs
)->rt
== 0) {
951 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
952 * have been copied to the old stack, the old stack may fail the
953 * validation tests below. So ia64_old_stack() must restore the dirty
954 * registers from the new stack. The old and new bspstore probably
955 * have different alignments, so loadrs calculated on the old bsp
956 * cannot be used to restore from the new bsp. Calculate a suitable
957 * loadrs for the new stack and save it in the new pt_regs, where
958 * ia64_old_stack() can get it.
960 old_bspstore
= (u64
*)ar_bspstore
;
961 old_bsp
= (u64
*)ar_bsp
;
962 slots
= ia64_rse_num_regs(old_bspstore
, old_bsp
);
963 new_bspstore
= (u64
*)((u64
)current
+ IA64_RBS_OFFSET
);
964 new_bsp
= ia64_rse_skip_regs(new_bspstore
, slots
);
965 regs
->loadrs
= (new_bsp
- new_bspstore
) * 8 << 16;
967 /* Verify the previous stack state before we change it */
968 if (user_mode(regs
)) {
969 msg
= "occurred in user space";
970 /* previous_current is guaranteed to be valid when the task was
971 * in user space, so ...
973 ia64_mca_modify_comm(previous_current
);
977 if (r13
!= sos
->prev_IA64_KR_CURRENT
) {
978 msg
= "inconsistent previous current and r13";
982 if (!mca_recover_range(ms
->pmsa_iip
)) {
983 if ((r12
- r13
) >= KERNEL_STACK_SIZE
) {
984 msg
= "inconsistent r12 and r13";
987 if ((ar_bspstore
- r13
) >= KERNEL_STACK_SIZE
) {
988 msg
= "inconsistent ar.bspstore and r13";
993 msg
= "old_bspstore is in the wrong region";
996 if ((ar_bsp
- r13
) >= KERNEL_STACK_SIZE
) {
997 msg
= "inconsistent ar.bsp and r13";
1000 size
+= (ia64_rse_skip_regs(old_bspstore
, slots
) - old_bspstore
) * 8;
1001 if (ar_bspstore
+ size
> r12
) {
1002 msg
= "no room for blocked state";
1007 ia64_mca_modify_comm(previous_current
);
1009 /* Make the original task look blocked. First stack a struct pt_regs,
1010 * describing the state at the time of interrupt. mca_asm.S built a
1011 * partial pt_regs, copy it and fill in the blanks using minstate.
1013 p
= (char *)r12
- sizeof(*regs
);
1014 old_regs
= (struct pt_regs
*)p
;
1015 memcpy(old_regs
, regs
, sizeof(*regs
));
1016 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
1017 * pmsa_{xip,xpsr,xfs}
1019 if (ia64_psr(regs
)->ic
) {
1020 old_regs
->cr_iip
= ms
->pmsa_iip
;
1021 old_regs
->cr_ipsr
= ms
->pmsa_ipsr
;
1022 old_regs
->cr_ifs
= ms
->pmsa_ifs
;
1024 old_regs
->cr_iip
= ms
->pmsa_xip
;
1025 old_regs
->cr_ipsr
= ms
->pmsa_xpsr
;
1026 old_regs
->cr_ifs
= ms
->pmsa_xfs
;
1028 old_regs
->pr
= ms
->pmsa_pr
;
1029 old_regs
->b0
= ms
->pmsa_br0
;
1030 old_regs
->loadrs
= loadrs
;
1031 old_regs
->ar_rsc
= ms
->pmsa_rsc
;
1032 old_unat
= old_regs
->ar_unat
;
1033 copy_reg(&ms
->pmsa_gr
[1-1], ms
->pmsa_nat_bits
, &old_regs
->r1
, &old_unat
);
1034 copy_reg(&ms
->pmsa_gr
[2-1], ms
->pmsa_nat_bits
, &old_regs
->r2
, &old_unat
);
1035 copy_reg(&ms
->pmsa_gr
[3-1], ms
->pmsa_nat_bits
, &old_regs
->r3
, &old_unat
);
1036 copy_reg(&ms
->pmsa_gr
[8-1], ms
->pmsa_nat_bits
, &old_regs
->r8
, &old_unat
);
1037 copy_reg(&ms
->pmsa_gr
[9-1], ms
->pmsa_nat_bits
, &old_regs
->r9
, &old_unat
);
1038 copy_reg(&ms
->pmsa_gr
[10-1], ms
->pmsa_nat_bits
, &old_regs
->r10
, &old_unat
);
1039 copy_reg(&ms
->pmsa_gr
[11-1], ms
->pmsa_nat_bits
, &old_regs
->r11
, &old_unat
);
1040 copy_reg(&ms
->pmsa_gr
[12-1], ms
->pmsa_nat_bits
, &old_regs
->r12
, &old_unat
);
1041 copy_reg(&ms
->pmsa_gr
[13-1], ms
->pmsa_nat_bits
, &old_regs
->r13
, &old_unat
);
1042 copy_reg(&ms
->pmsa_gr
[14-1], ms
->pmsa_nat_bits
, &old_regs
->r14
, &old_unat
);
1043 copy_reg(&ms
->pmsa_gr
[15-1], ms
->pmsa_nat_bits
, &old_regs
->r15
, &old_unat
);
1044 if (ia64_psr(old_regs
)->bn
)
1045 bank
= ms
->pmsa_bank1_gr
;
1047 bank
= ms
->pmsa_bank0_gr
;
1048 copy_reg(&bank
[16-16], ms
->pmsa_nat_bits
, &old_regs
->r16
, &old_unat
);
1049 copy_reg(&bank
[17-16], ms
->pmsa_nat_bits
, &old_regs
->r17
, &old_unat
);
1050 copy_reg(&bank
[18-16], ms
->pmsa_nat_bits
, &old_regs
->r18
, &old_unat
);
1051 copy_reg(&bank
[19-16], ms
->pmsa_nat_bits
, &old_regs
->r19
, &old_unat
);
1052 copy_reg(&bank
[20-16], ms
->pmsa_nat_bits
, &old_regs
->r20
, &old_unat
);
1053 copy_reg(&bank
[21-16], ms
->pmsa_nat_bits
, &old_regs
->r21
, &old_unat
);
1054 copy_reg(&bank
[22-16], ms
->pmsa_nat_bits
, &old_regs
->r22
, &old_unat
);
1055 copy_reg(&bank
[23-16], ms
->pmsa_nat_bits
, &old_regs
->r23
, &old_unat
);
1056 copy_reg(&bank
[24-16], ms
->pmsa_nat_bits
, &old_regs
->r24
, &old_unat
);
1057 copy_reg(&bank
[25-16], ms
->pmsa_nat_bits
, &old_regs
->r25
, &old_unat
);
1058 copy_reg(&bank
[26-16], ms
->pmsa_nat_bits
, &old_regs
->r26
, &old_unat
);
1059 copy_reg(&bank
[27-16], ms
->pmsa_nat_bits
, &old_regs
->r27
, &old_unat
);
1060 copy_reg(&bank
[28-16], ms
->pmsa_nat_bits
, &old_regs
->r28
, &old_unat
);
1061 copy_reg(&bank
[29-16], ms
->pmsa_nat_bits
, &old_regs
->r29
, &old_unat
);
1062 copy_reg(&bank
[30-16], ms
->pmsa_nat_bits
, &old_regs
->r30
, &old_unat
);
1063 copy_reg(&bank
[31-16], ms
->pmsa_nat_bits
, &old_regs
->r31
, &old_unat
);
1065 /* Next stack a struct switch_stack. mca_asm.S built a partial
1066 * switch_stack, copy it and fill in the blanks using pt_regs and
1069 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
1070 * ar.pfs is set to 0.
1072 * unwind.c::unw_unwind() does special processing for interrupt frames.
1073 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
1074 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
1075 * that this is documented, of course. Set PRED_NON_SYSCALL in the
1076 * switch_stack on the original stack so it will unwind correctly when
1077 * unwind.c reads pt_regs.
1079 * thread.ksp is updated to point to the synthesized switch_stack.
1081 p
-= sizeof(struct switch_stack
);
1082 old_sw
= (struct switch_stack
*)p
;
1083 memcpy(old_sw
, sw
, sizeof(*sw
));
1084 old_sw
->caller_unat
= old_unat
;
1085 old_sw
->ar_fpsr
= old_regs
->ar_fpsr
;
1086 copy_reg(&ms
->pmsa_gr
[4-1], ms
->pmsa_nat_bits
, &old_sw
->r4
, &old_unat
);
1087 copy_reg(&ms
->pmsa_gr
[5-1], ms
->pmsa_nat_bits
, &old_sw
->r5
, &old_unat
);
1088 copy_reg(&ms
->pmsa_gr
[6-1], ms
->pmsa_nat_bits
, &old_sw
->r6
, &old_unat
);
1089 copy_reg(&ms
->pmsa_gr
[7-1], ms
->pmsa_nat_bits
, &old_sw
->r7
, &old_unat
);
1090 old_sw
->b0
= (u64
)ia64_leave_kernel
;
1091 old_sw
->b1
= ms
->pmsa_br1
;
1093 old_sw
->ar_unat
= old_unat
;
1094 old_sw
->pr
= old_regs
->pr
| (1UL << PRED_NON_SYSCALL
);
1095 previous_current
->thread
.ksp
= (u64
)p
- 16;
1097 /* Finally copy the original stack's registers back to its RBS.
1098 * Registers from ar.bspstore through ar.bsp at the time of the event
1099 * are in the current RBS, copy them back to the original stack. The
1100 * copy must be done register by register because the original bspstore
1101 * and the current one have different alignments, so the saved RNAT
1102 * data occurs at different places.
1104 * mca_asm does cover, so the old_bsp already includes all registers at
1105 * the time of MCA/INIT. It also does flushrs, so all registers before
1106 * this function have been written to backing store on the MCA/INIT
1109 new_rnat
= ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore
));
1110 old_rnat
= regs
->ar_rnat
;
1112 if (ia64_rse_is_rnat_slot(new_bspstore
)) {
1113 new_rnat
= ia64_get_rnat(new_bspstore
++);
1115 if (ia64_rse_is_rnat_slot(old_bspstore
)) {
1116 *old_bspstore
++ = old_rnat
;
1119 nat
= (new_rnat
>> ia64_rse_slot_num(new_bspstore
)) & 1UL;
1120 old_rnat
&= ~(1UL << ia64_rse_slot_num(old_bspstore
));
1121 old_rnat
|= (nat
<< ia64_rse_slot_num(old_bspstore
));
1122 *old_bspstore
++ = *new_bspstore
++;
1124 old_sw
->ar_bspstore
= (unsigned long)old_bspstore
;
1125 old_sw
->ar_rnat
= old_rnat
;
1127 sos
->prev_task
= previous_current
;
1128 return previous_current
;
1131 printk(KERN_INFO
"cpu %d, %s %s, original stack not modified\n",
1132 smp_processor_id(), type
, msg
);
1133 return previous_current
;
1136 /* The monarch/slave interaction is based on monarch_cpu and requires that all
1137 * slaves have entered rendezvous before the monarch leaves. If any cpu has
1138 * not entered rendezvous yet then wait a bit. The assumption is that any
1139 * slave that has not rendezvoused after a reasonable time is never going to do
1140 * so. In this context, slave includes cpus that respond to the MCA rendezvous
1141 * interrupt, as well as cpus that receive the INIT slave event.
1145 ia64_wait_for_slaves(int monarch
, const char *type
)
1150 * wait 5 seconds total for slaves (arbitrary)
1152 for (i
= 0; i
< 5000; i
++) {
1154 for_each_online_cpu(c
) {
1157 if (ia64_mc_info
.imi_rendez_checkin
[c
]
1158 == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
) {
1159 udelay(1000); /* short wait */
1169 * Maybe slave(s) dead. Print buffered messages immediately.
1171 ia64_mlogbuf_finish(0);
1172 mprintk(KERN_INFO
"OS %s slave did not rendezvous on cpu", type
);
1173 for_each_online_cpu(c
) {
1176 if (ia64_mc_info
.imi_rendez_checkin
[c
] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
)
1183 mprintk(KERN_INFO
"All OS %s slaves have reached rendezvous\n", type
);
1189 * Switch rid when TR reload and needed!
1190 * iord: 1: itr, 2: itr;
1193 static void mca_insert_tr(u64 iord
)
1198 struct ia64_tr_entry
*p
;
1200 int cpu
= smp_processor_id();
1202 psr
= ia64_clear_ic();
1203 for (i
= IA64_TR_ALLOC_BASE
; i
< IA64_TR_ALLOC_MAX
; i
++) {
1204 p
= &__per_cpu_idtrs
[cpu
][iord
-1][i
];
1206 old_rr
= ia64_get_rr(p
->ifa
);
1207 if (old_rr
!= p
->rr
) {
1208 ia64_set_rr(p
->ifa
, p
->rr
);
1211 ia64_ptr(iord
, p
->ifa
, p
->itir
>> 2);
1214 ia64_itr(0x1, i
, p
->ifa
, p
->pte
, p
->itir
>> 2);
1218 ia64_itr(0x2, i
, p
->ifa
, p
->pte
, p
->itir
>> 2);
1221 if (old_rr
!= p
->rr
) {
1222 ia64_set_rr(p
->ifa
, old_rr
);
1233 * This is uncorrectable machine check handler called from OS_MCA
1234 * dispatch code which is in turn called from SAL_CHECK().
1235 * This is the place where the core of OS MCA handling is done.
1236 * Right now the logs are extracted and displayed in a well-defined
1237 * format. This handler code is supposed to be run only on the
1238 * monarch processor. Once the monarch is done with MCA handling
1239 * further MCA logging is enabled by clearing logs.
1240 * Monarch also has the duty of sending wakeup-IPIs to pull the
1241 * slave processors out of rendezvous spinloop.
1243 * If multiple processors call into OS_MCA, the first will become
1244 * the monarch. Subsequent cpus will be recorded in the mca_cpu
1245 * bitmask. After the first monarch has processed its MCA, it
1246 * will wake up the next cpu in the mca_cpu bitmask and then go
1247 * into the rendezvous loop. When all processors have serviced
1248 * their MCA, the last monarch frees up the rest of the processors.
1251 ia64_mca_handler(struct pt_regs
*regs
, struct switch_stack
*sw
,
1252 struct ia64_sal_os_state
*sos
)
1254 int recover
, cpu
= smp_processor_id();
1255 struct task_struct
*previous_current
;
1256 struct ia64_mca_notify_die nd
=
1257 { .sos
= sos
, .monarch_cpu
= &monarch_cpu
};
1258 static atomic_t mca_count
;
1259 static cpumask_t mca_cpu
;
1261 if (atomic_add_return(1, &mca_count
) == 1) {
1265 cpu_set(cpu
, mca_cpu
);
1268 mprintk(KERN_INFO
"Entered OS MCA handler. PSP=%lx cpu=%d "
1269 "monarch=%ld\n", sos
->proc_state_param
, cpu
, sos
->monarch
);
1271 previous_current
= ia64_mca_modify_original_stack(regs
, sw
, sos
, "MCA");
1273 if (notify_die(DIE_MCA_MONARCH_ENTER
, "MCA", regs
, (long)&nd
, 0, 0)
1275 ia64_mca_spin(__func__
);
1277 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA
;
1279 ia64_wait_for_slaves(cpu
, "MCA");
1281 /* Wakeup all the processors which are spinning in the
1282 * rendezvous loop. They will leave SAL, then spin in the OS
1283 * with interrupts disabled until this monarch cpu leaves the
1284 * MCA handler. That gets control back to the OS so we can
1285 * backtrace the other cpus, backtrace when spinning in SAL
1288 ia64_mca_wakeup_all();
1289 if (notify_die(DIE_MCA_MONARCH_PROCESS
, "MCA", regs
, (long)&nd
, 0, 0)
1291 ia64_mca_spin(__func__
);
1293 while (cpu_isset(cpu
, mca_cpu
))
1294 cpu_relax(); /* spin until monarch wakes us */
1297 /* Get the MCA error record and log it */
1298 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA
);
1300 /* MCA error recovery */
1301 recover
= (ia64_mca_ucmc_extension
1302 && ia64_mca_ucmc_extension(
1303 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA
),
1307 sal_log_record_header_t
*rh
= IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA
);
1308 rh
->severity
= sal_log_severity_corrected
;
1309 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA
);
1310 sos
->os_status
= IA64_MCA_CORRECTED
;
1312 /* Dump buffered message to console */
1313 ia64_mlogbuf_finish(1);
1315 atomic_set(&kdump_in_progress
, 1);
1319 if (__get_cpu_var(ia64_mca_tr_reload
)) {
1320 mca_insert_tr(0x1); /*Reload dynamic itrs*/
1321 mca_insert_tr(0x2); /*Reload dynamic itrs*/
1323 if (notify_die(DIE_MCA_MONARCH_LEAVE
, "MCA", regs
, (long)&nd
, 0, recover
)
1325 ia64_mca_spin(__func__
);
1328 if (atomic_dec_return(&mca_count
) > 0) {
1331 /* wake up the next monarch cpu,
1332 * and put this cpu in the rendez loop.
1334 for_each_online_cpu(i
) {
1335 if (cpu_isset(i
, mca_cpu
)) {
1337 cpu_clear(i
, mca_cpu
); /* wake next cpu */
1338 while (monarch_cpu
!= -1)
1339 cpu_relax(); /* spin until last cpu leaves */
1340 set_curr_task(cpu
, previous_current
);
1341 ia64_mc_info
.imi_rendez_checkin
[cpu
]
1342 = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1347 set_curr_task(cpu
, previous_current
);
1348 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1349 monarch_cpu
= -1; /* This frees the slaves and previous monarchs */
1352 static DECLARE_WORK(cmc_disable_work
, ia64_mca_cmc_vector_disable_keventd
);
1353 static DECLARE_WORK(cmc_enable_work
, ia64_mca_cmc_vector_enable_keventd
);
1356 * ia64_mca_cmc_int_handler
1358 * This is corrected machine check interrupt handler.
1359 * Right now the logs are extracted and displayed in a well-defined
1364 * client data arg ptr
1370 ia64_mca_cmc_int_handler(int cmc_irq
, void *arg
)
1372 static unsigned long cmc_history
[CMC_HISTORY_LENGTH
];
1374 static DEFINE_SPINLOCK(cmc_history_lock
);
1376 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1377 __func__
, cmc_irq
, smp_processor_id());
1379 /* SAL spec states this should run w/ interrupts enabled */
1382 spin_lock(&cmc_history_lock
);
1383 if (!cmc_polling_enabled
) {
1384 int i
, count
= 1; /* we know 1 happened now */
1385 unsigned long now
= jiffies
;
1387 for (i
= 0; i
< CMC_HISTORY_LENGTH
; i
++) {
1388 if (now
- cmc_history
[i
] <= HZ
)
1392 IA64_MCA_DEBUG(KERN_INFO
"CMC threshold %d/%d\n", count
, CMC_HISTORY_LENGTH
);
1393 if (count
>= CMC_HISTORY_LENGTH
) {
1395 cmc_polling_enabled
= 1;
1396 spin_unlock(&cmc_history_lock
);
1397 /* If we're being hit with CMC interrupts, we won't
1398 * ever execute the schedule_work() below. Need to
1399 * disable CMC interrupts on this processor now.
1401 ia64_mca_cmc_vector_disable(NULL
);
1402 schedule_work(&cmc_disable_work
);
1405 * Corrected errors will still be corrected, but
1406 * make sure there's a log somewhere that indicates
1407 * something is generating more than we can handle.
1409 printk(KERN_WARNING
"WARNING: Switching to polling CMC handler; error records may be lost\n");
1411 mod_timer(&cmc_poll_timer
, jiffies
+ CMC_POLL_INTERVAL
);
1413 /* lock already released, get out now */
1416 cmc_history
[index
++] = now
;
1417 if (index
== CMC_HISTORY_LENGTH
)
1421 spin_unlock(&cmc_history_lock
);
1423 /* Get the CMC error record and log it */
1424 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC
);
1430 * ia64_mca_cmc_int_caller
1432 * Triggered by sw interrupt from CMC polling routine. Calls
1433 * real interrupt handler and either triggers a sw interrupt
1434 * on the next cpu or does cleanup at the end.
1438 * client data arg ptr
1443 ia64_mca_cmc_int_caller(int cmc_irq
, void *arg
)
1445 static int start_count
= -1;
1448 cpuid
= smp_processor_id();
1450 /* If first cpu, update count */
1451 if (start_count
== -1)
1452 start_count
= IA64_LOG_COUNT(SAL_INFO_TYPE_CMC
);
1454 ia64_mca_cmc_int_handler(cmc_irq
, arg
);
1456 for (++cpuid
; cpuid
< NR_CPUS
&& !cpu_online(cpuid
) ; cpuid
++);
1458 if (cpuid
< NR_CPUS
) {
1459 platform_send_ipi(cpuid
, IA64_CMCP_VECTOR
, IA64_IPI_DM_INT
, 0);
1461 /* If no log record, switch out of polling mode */
1462 if (start_count
== IA64_LOG_COUNT(SAL_INFO_TYPE_CMC
)) {
1464 printk(KERN_WARNING
"Returning to interrupt driven CMC handler\n");
1465 schedule_work(&cmc_enable_work
);
1466 cmc_polling_enabled
= 0;
1470 mod_timer(&cmc_poll_timer
, jiffies
+ CMC_POLL_INTERVAL
);
1482 * Poll for Corrected Machine Checks (CMCs)
1484 * Inputs : dummy(unused)
1489 ia64_mca_cmc_poll (unsigned long dummy
)
1491 /* Trigger a CMC interrupt cascade */
1492 platform_send_ipi(first_cpu(cpu_online_map
), IA64_CMCP_VECTOR
, IA64_IPI_DM_INT
, 0);
1496 * ia64_mca_cpe_int_caller
1498 * Triggered by sw interrupt from CPE polling routine. Calls
1499 * real interrupt handler and either triggers a sw interrupt
1500 * on the next cpu or does cleanup at the end.
1504 * client data arg ptr
1511 ia64_mca_cpe_int_caller(int cpe_irq
, void *arg
)
1513 static int start_count
= -1;
1514 static int poll_time
= MIN_CPE_POLL_INTERVAL
;
1517 cpuid
= smp_processor_id();
1519 /* If first cpu, update count */
1520 if (start_count
== -1)
1521 start_count
= IA64_LOG_COUNT(SAL_INFO_TYPE_CPE
);
1523 ia64_mca_cpe_int_handler(cpe_irq
, arg
);
1525 for (++cpuid
; cpuid
< NR_CPUS
&& !cpu_online(cpuid
) ; cpuid
++);
1527 if (cpuid
< NR_CPUS
) {
1528 platform_send_ipi(cpuid
, IA64_CPEP_VECTOR
, IA64_IPI_DM_INT
, 0);
1531 * If a log was recorded, increase our polling frequency,
1532 * otherwise, backoff or return to interrupt mode.
1534 if (start_count
!= IA64_LOG_COUNT(SAL_INFO_TYPE_CPE
)) {
1535 poll_time
= max(MIN_CPE_POLL_INTERVAL
, poll_time
/ 2);
1536 } else if (cpe_vector
< 0) {
1537 poll_time
= min(MAX_CPE_POLL_INTERVAL
, poll_time
* 2);
1539 poll_time
= MIN_CPE_POLL_INTERVAL
;
1541 printk(KERN_WARNING
"Returning to interrupt driven CPE handler\n");
1542 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR
));
1543 cpe_poll_enabled
= 0;
1546 if (cpe_poll_enabled
)
1547 mod_timer(&cpe_poll_timer
, jiffies
+ poll_time
);
1557 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1558 * on first cpu, from there it will trickle through all the cpus.
1560 * Inputs : dummy(unused)
1565 ia64_mca_cpe_poll (unsigned long dummy
)
1567 /* Trigger a CPE interrupt cascade */
1568 platform_send_ipi(first_cpu(cpu_online_map
), IA64_CPEP_VECTOR
, IA64_IPI_DM_INT
, 0);
1571 #endif /* CONFIG_ACPI */
1574 default_monarch_init_process(struct notifier_block
*self
, unsigned long val
, void *data
)
1577 struct task_struct
*g
, *t
;
1578 if (val
!= DIE_INIT_MONARCH_PROCESS
)
1581 if (atomic_read(&kdump_in_progress
))
1586 * FIXME: mlogbuf will brim over with INIT stack dumps.
1587 * To enable show_stack from INIT, we use oops_in_progress which should
1588 * be used in real oops. This would cause something wrong after INIT.
1590 BREAK_LOGLEVEL(console_loglevel
);
1591 ia64_mlogbuf_dump_from_init();
1593 printk(KERN_ERR
"Processes interrupted by INIT -");
1594 for_each_online_cpu(c
) {
1595 struct ia64_sal_os_state
*s
;
1596 t
= __va(__per_cpu_mca
[c
] + IA64_MCA_CPU_INIT_STACK_OFFSET
);
1597 s
= (struct ia64_sal_os_state
*)((char *)t
+ MCA_SOS_OFFSET
);
1601 printk(" %d", g
->pid
);
1603 printk(" %d (cpu %d task 0x%p)", g
->pid
, task_cpu(g
), g
);
1607 if (read_trylock(&tasklist_lock
)) {
1608 do_each_thread (g
, t
) {
1609 printk("\nBacktrace of pid %d (%s)\n", t
->pid
, t
->comm
);
1610 show_stack(t
, NULL
);
1611 } while_each_thread (g
, t
);
1612 read_unlock(&tasklist_lock
);
1614 /* FIXME: This will not restore zapped printk locks. */
1615 RESTORE_LOGLEVEL(console_loglevel
);
1620 * C portion of the OS INIT handler
1622 * Called from ia64_os_init_dispatch
1624 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
1625 * this event. This code is used for both monarch and slave INIT events, see
1628 * All INIT events switch to the INIT stack and change the previous process to
1629 * blocked status. If one of the INIT events is the monarch then we are
1630 * probably processing the nmi button/command. Use the monarch cpu to dump all
1631 * the processes. The slave INIT events all spin until the monarch cpu
1632 * returns. We can also get INIT slave events for MCA, in which case the MCA
1633 * process is the monarch.
1637 ia64_init_handler(struct pt_regs
*regs
, struct switch_stack
*sw
,
1638 struct ia64_sal_os_state
*sos
)
1640 static atomic_t slaves
;
1641 static atomic_t monarchs
;
1642 struct task_struct
*previous_current
;
1643 int cpu
= smp_processor_id();
1644 struct ia64_mca_notify_die nd
=
1645 { .sos
= sos
, .monarch_cpu
= &monarch_cpu
};
1647 (void) notify_die(DIE_INIT_ENTER
, "INIT", regs
, (long)&nd
, 0, 0);
1649 mprintk(KERN_INFO
"Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1650 sos
->proc_state_param
, cpu
, sos
->monarch
);
1651 salinfo_log_wakeup(SAL_INFO_TYPE_INIT
, NULL
, 0, 0);
1653 previous_current
= ia64_mca_modify_original_stack(regs
, sw
, sos
, "INIT");
1654 sos
->os_status
= IA64_INIT_RESUME
;
1656 /* FIXME: Workaround for broken proms that drive all INIT events as
1657 * slaves. The last slave that enters is promoted to be a monarch.
1658 * Remove this code in September 2006, that gives platforms a year to
1659 * fix their proms and get their customers updated.
1661 if (!sos
->monarch
&& atomic_add_return(1, &slaves
) == num_online_cpus()) {
1662 mprintk(KERN_WARNING
"%s: Promoting cpu %d to monarch.\n",
1664 atomic_dec(&slaves
);
1668 /* FIXME: Workaround for broken proms that drive all INIT events as
1669 * monarchs. Second and subsequent monarchs are demoted to slaves.
1670 * Remove this code in September 2006, that gives platforms a year to
1671 * fix their proms and get their customers updated.
1673 if (sos
->monarch
&& atomic_add_return(1, &monarchs
) > 1) {
1674 mprintk(KERN_WARNING
"%s: Demoting cpu %d to slave.\n",
1676 atomic_dec(&monarchs
);
1680 if (!sos
->monarch
) {
1681 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_INIT
;
1682 while (monarch_cpu
== -1)
1683 cpu_relax(); /* spin until monarch enters */
1684 if (notify_die(DIE_INIT_SLAVE_ENTER
, "INIT", regs
, (long)&nd
, 0, 0)
1686 ia64_mca_spin(__func__
);
1687 if (notify_die(DIE_INIT_SLAVE_PROCESS
, "INIT", regs
, (long)&nd
, 0, 0)
1689 ia64_mca_spin(__func__
);
1690 while (monarch_cpu
!= -1)
1691 cpu_relax(); /* spin until monarch leaves */
1692 if (notify_die(DIE_INIT_SLAVE_LEAVE
, "INIT", regs
, (long)&nd
, 0, 0)
1694 ia64_mca_spin(__func__
);
1695 mprintk("Slave on cpu %d returning to normal service.\n", cpu
);
1696 set_curr_task(cpu
, previous_current
);
1697 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1698 atomic_dec(&slaves
);
1703 if (notify_die(DIE_INIT_MONARCH_ENTER
, "INIT", regs
, (long)&nd
, 0, 0)
1705 ia64_mca_spin(__func__
);
1708 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1709 * generated via the BMC's command-line interface, but since the console is on the
1710 * same serial line, the user will need some time to switch out of the BMC before
1713 mprintk("Delaying for 5 seconds...\n");
1715 ia64_wait_for_slaves(cpu
, "INIT");
1716 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1717 * to default_monarch_init_process() above and just print all the
1720 if (notify_die(DIE_INIT_MONARCH_PROCESS
, "INIT", regs
, (long)&nd
, 0, 0)
1722 ia64_mca_spin(__func__
);
1723 if (notify_die(DIE_INIT_MONARCH_LEAVE
, "INIT", regs
, (long)&nd
, 0, 0)
1725 ia64_mca_spin(__func__
);
1726 mprintk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu
);
1727 atomic_dec(&monarchs
);
1728 set_curr_task(cpu
, previous_current
);
1734 ia64_mca_disable_cpe_polling(char *str
)
1736 cpe_poll_enabled
= 0;
1740 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling
);
1742 static struct irqaction cmci_irqaction
= {
1743 .handler
= ia64_mca_cmc_int_handler
,
1744 .flags
= IRQF_DISABLED
,
1748 static struct irqaction cmcp_irqaction
= {
1749 .handler
= ia64_mca_cmc_int_caller
,
1750 .flags
= IRQF_DISABLED
,
1754 static struct irqaction mca_rdzv_irqaction
= {
1755 .handler
= ia64_mca_rendez_int_handler
,
1756 .flags
= IRQF_DISABLED
,
1760 static struct irqaction mca_wkup_irqaction
= {
1761 .handler
= ia64_mca_wakeup_int_handler
,
1762 .flags
= IRQF_DISABLED
,
1767 static struct irqaction mca_cpe_irqaction
= {
1768 .handler
= ia64_mca_cpe_int_handler
,
1769 .flags
= IRQF_DISABLED
,
1773 static struct irqaction mca_cpep_irqaction
= {
1774 .handler
= ia64_mca_cpe_int_caller
,
1775 .flags
= IRQF_DISABLED
,
1778 #endif /* CONFIG_ACPI */
1780 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
1781 * these stacks can never sleep, they cannot return from the kernel to user
1782 * space, they do not appear in a normal ps listing. So there is no need to
1783 * format most of the fields.
1786 static void __cpuinit
1787 format_mca_init_stack(void *mca_data
, unsigned long offset
,
1788 const char *type
, int cpu
)
1790 struct task_struct
*p
= (struct task_struct
*)((char *)mca_data
+ offset
);
1791 struct thread_info
*ti
;
1792 memset(p
, 0, KERNEL_STACK_SIZE
);
1793 ti
= task_thread_info(p
);
1794 ti
->flags
= _TIF_MCA_INIT
;
1795 ti
->preempt_count
= 1;
1799 p
->state
= TASK_UNINTERRUPTIBLE
;
1800 cpu_set(cpu
, p
->cpus_allowed
);
1801 INIT_LIST_HEAD(&p
->tasks
);
1802 p
->parent
= p
->real_parent
= p
->group_leader
= p
;
1803 INIT_LIST_HEAD(&p
->children
);
1804 INIT_LIST_HEAD(&p
->sibling
);
1805 strncpy(p
->comm
, type
, sizeof(p
->comm
)-1);
1808 /* Caller prevents this from being called after init */
1809 static void * __init_refok
mca_bootmem(void)
1811 return __alloc_bootmem(sizeof(struct ia64_mca_cpu
),
1812 KERNEL_STACK_SIZE
, 0);
1815 /* Do per-CPU MCA-related initialization. */
1817 ia64_mca_cpu_init(void *cpu_data
)
1821 long sz
= sizeof(struct ia64_mca_cpu
);
1822 int cpu
= smp_processor_id();
1823 static int first_time
= 1;
1826 * Structure will already be allocated if cpu has been online,
1829 if (__per_cpu_mca
[cpu
]) {
1830 data
= __va(__per_cpu_mca
[cpu
]);
1833 data
= mca_bootmem();
1836 data
= page_address(alloc_pages_node(numa_node_id(),
1837 GFP_KERNEL
, get_order(sz
)));
1839 panic("Could not allocate MCA memory for cpu %d\n",
1842 format_mca_init_stack(data
, offsetof(struct ia64_mca_cpu
, mca_stack
),
1844 format_mca_init_stack(data
, offsetof(struct ia64_mca_cpu
, init_stack
),
1846 __get_cpu_var(ia64_mca_data
) = __per_cpu_mca
[cpu
] = __pa(data
);
1849 * Stash away a copy of the PTE needed to map the per-CPU page.
1850 * We may need it during MCA recovery.
1852 __get_cpu_var(ia64_mca_per_cpu_pte
) =
1853 pte_val(mk_pte_phys(__pa(cpu_data
), PAGE_KERNEL
));
1856 * Also, stash away a copy of the PAL address and the PTE
1859 pal_vaddr
= efi_get_pal_addr();
1862 __get_cpu_var(ia64_mca_pal_base
) =
1863 GRANULEROUNDDOWN((unsigned long) pal_vaddr
);
1864 __get_cpu_var(ia64_mca_pal_pte
) = pte_val(mk_pte_phys(__pa(pal_vaddr
),
1868 static void __cpuinit
ia64_mca_cmc_vector_adjust(void *dummy
)
1870 unsigned long flags
;
1872 local_irq_save(flags
);
1873 if (!cmc_polling_enabled
)
1874 ia64_mca_cmc_vector_enable(NULL
);
1875 local_irq_restore(flags
);
1878 static int __cpuinit
mca_cpu_callback(struct notifier_block
*nfb
,
1879 unsigned long action
,
1882 int hotcpu
= (unsigned long) hcpu
;
1886 case CPU_ONLINE_FROZEN
:
1887 smp_call_function_single(hotcpu
, ia64_mca_cmc_vector_adjust
,
1894 static struct notifier_block mca_cpu_notifier __cpuinitdata
= {
1895 .notifier_call
= mca_cpu_callback
1901 * Do all the system level mca specific initialization.
1903 * 1. Register spinloop and wakeup request interrupt vectors
1905 * 2. Register OS_MCA handler entry point
1907 * 3. Register OS_INIT handler entry point
1909 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1911 * Note that this initialization is done very early before some kernel
1912 * services are available.
1921 ia64_fptr_t
*init_hldlr_ptr_monarch
= (ia64_fptr_t
*)ia64_os_init_dispatch_monarch
;
1922 ia64_fptr_t
*init_hldlr_ptr_slave
= (ia64_fptr_t
*)ia64_os_init_dispatch_slave
;
1923 ia64_fptr_t
*mca_hldlr_ptr
= (ia64_fptr_t
*)ia64_os_mca_dispatch
;
1926 struct ia64_sal_retval isrv
;
1927 u64 timeout
= IA64_MCA_RENDEZ_TIMEOUT
; /* platform specific */
1928 static struct notifier_block default_init_monarch_nb
= {
1929 .notifier_call
= default_monarch_init_process
,
1930 .priority
= 0/* we need to notified last */
1933 IA64_MCA_DEBUG("%s: begin\n", __func__
);
1935 /* Clear the Rendez checkin flag for all cpus */
1936 for(i
= 0 ; i
< NR_CPUS
; i
++)
1937 ia64_mc_info
.imi_rendez_checkin
[i
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1940 * Register the rendezvous spinloop and wakeup mechanism with SAL
1943 /* Register the rendezvous interrupt vector with SAL */
1945 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT
,
1946 SAL_MC_PARAM_MECHANISM_INT
,
1947 IA64_MCA_RENDEZ_VECTOR
,
1949 SAL_MC_PARAM_RZ_ALWAYS
);
1954 printk(KERN_INFO
"Increasing MCA rendezvous timeout from "
1955 "%ld to %ld milliseconds\n", timeout
, isrv
.v0
);
1957 (void) notify_die(DIE_MCA_NEW_TIMEOUT
, "MCA", NULL
, timeout
, 0, 0);
1960 printk(KERN_ERR
"Failed to register rendezvous interrupt "
1961 "with SAL (status %ld)\n", rc
);
1965 /* Register the wakeup interrupt vector with SAL */
1966 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP
,
1967 SAL_MC_PARAM_MECHANISM_INT
,
1968 IA64_MCA_WAKEUP_VECTOR
,
1972 printk(KERN_ERR
"Failed to register wakeup interrupt with SAL "
1973 "(status %ld)\n", rc
);
1977 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__
);
1979 ia64_mc_info
.imi_mca_handler
= ia64_tpa(mca_hldlr_ptr
->fp
);
1981 * XXX - disable SAL checksum by setting size to 0; should be
1982 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1984 ia64_mc_info
.imi_mca_handler_size
= 0;
1986 /* Register the os mca handler with SAL */
1987 if ((rc
= ia64_sal_set_vectors(SAL_VECTOR_OS_MCA
,
1988 ia64_mc_info
.imi_mca_handler
,
1989 ia64_tpa(mca_hldlr_ptr
->gp
),
1990 ia64_mc_info
.imi_mca_handler_size
,
1993 printk(KERN_ERR
"Failed to register OS MCA handler with SAL "
1994 "(status %ld)\n", rc
);
1998 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__
,
1999 ia64_mc_info
.imi_mca_handler
, ia64_tpa(mca_hldlr_ptr
->gp
));
2002 * XXX - disable SAL checksum by setting size to 0, should be
2003 * size of the actual init handler in mca_asm.S.
2005 ia64_mc_info
.imi_monarch_init_handler
= ia64_tpa(init_hldlr_ptr_monarch
->fp
);
2006 ia64_mc_info
.imi_monarch_init_handler_size
= 0;
2007 ia64_mc_info
.imi_slave_init_handler
= ia64_tpa(init_hldlr_ptr_slave
->fp
);
2008 ia64_mc_info
.imi_slave_init_handler_size
= 0;
2010 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__
,
2011 ia64_mc_info
.imi_monarch_init_handler
);
2013 /* Register the os init handler with SAL */
2014 if ((rc
= ia64_sal_set_vectors(SAL_VECTOR_OS_INIT
,
2015 ia64_mc_info
.imi_monarch_init_handler
,
2016 ia64_tpa(ia64_getreg(_IA64_REG_GP
)),
2017 ia64_mc_info
.imi_monarch_init_handler_size
,
2018 ia64_mc_info
.imi_slave_init_handler
,
2019 ia64_tpa(ia64_getreg(_IA64_REG_GP
)),
2020 ia64_mc_info
.imi_slave_init_handler_size
)))
2022 printk(KERN_ERR
"Failed to register m/s INIT handlers with SAL "
2023 "(status %ld)\n", rc
);
2026 if (register_die_notifier(&default_init_monarch_nb
)) {
2027 printk(KERN_ERR
"Failed to register default monarch INIT process\n");
2031 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__
);
2034 * Configure the CMCI/P vector and handler. Interrupts for CMC are
2035 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
2037 register_percpu_irq(IA64_CMC_VECTOR
, &cmci_irqaction
);
2038 register_percpu_irq(IA64_CMCP_VECTOR
, &cmcp_irqaction
);
2039 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
2041 /* Setup the MCA rendezvous interrupt vector */
2042 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR
, &mca_rdzv_irqaction
);
2044 /* Setup the MCA wakeup interrupt vector */
2045 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR
, &mca_wkup_irqaction
);
2048 /* Setup the CPEI/P handler */
2049 register_percpu_irq(IA64_CPEP_VECTOR
, &mca_cpep_irqaction
);
2052 /* Initialize the areas set aside by the OS to buffer the
2053 * platform/processor error states for MCA/INIT/CMC
2056 ia64_log_init(SAL_INFO_TYPE_MCA
);
2057 ia64_log_init(SAL_INFO_TYPE_INIT
);
2058 ia64_log_init(SAL_INFO_TYPE_CMC
);
2059 ia64_log_init(SAL_INFO_TYPE_CPE
);
2062 printk(KERN_INFO
"MCA related initialization done\n");
2066 * ia64_mca_late_init
2068 * Opportunity to setup things that require initialization later
2069 * than ia64_mca_init. Setup a timer to poll for CPEs if the
2070 * platform doesn't support an interrupt driven mechanism.
2076 ia64_mca_late_init(void)
2081 register_hotcpu_notifier(&mca_cpu_notifier
);
2083 /* Setup the CMCI/P vector and handler */
2084 init_timer(&cmc_poll_timer
);
2085 cmc_poll_timer
.function
= ia64_mca_cmc_poll
;
2087 /* Unmask/enable the vector */
2088 cmc_polling_enabled
= 0;
2089 schedule_work(&cmc_enable_work
);
2091 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__
);
2094 /* Setup the CPEI/P vector and handler */
2095 cpe_vector
= acpi_request_vector(ACPI_INTERRUPT_CPEI
);
2096 init_timer(&cpe_poll_timer
);
2097 cpe_poll_timer
.function
= ia64_mca_cpe_poll
;
2103 if (cpe_vector
>= 0) {
2104 /* If platform supports CPEI, enable the irq. */
2105 irq
= local_vector_to_irq(cpe_vector
);
2107 cpe_poll_enabled
= 0;
2108 desc
= irq_desc
+ irq
;
2109 desc
->status
|= IRQ_PER_CPU
;
2110 setup_irq(irq
, &mca_cpe_irqaction
);
2112 ia64_mca_register_cpev(cpe_vector
);
2113 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
2117 printk(KERN_ERR
"%s: Failed to find irq for CPE "
2118 "interrupt handler, vector %d\n",
2119 __func__
, cpe_vector
);
2121 /* If platform doesn't support CPEI, get the timer going. */
2122 if (cpe_poll_enabled
) {
2123 ia64_mca_cpe_poll(0UL);
2124 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__
);
2132 device_initcall(ia64_mca_late_init
);