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[AGPGART] intel_agp: use table for device probe
[linux-2.6/mini2440.git] / drivers / char / agp / intel-agp.c
blobdcb6d4f73348979104382e714e1a62cc8aab14f0
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
17 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
18 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
19 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
20 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
21 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
22 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
23
24 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
25 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
26 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
27 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
28 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB)
29
30
31 extern int agp_memory_reserved;
32
33
34 /* Intel 815 register */
35 #define INTEL_815_APCONT 0x51
36 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
37
38 /* Intel i820 registers */
39 #define INTEL_I820_RDCR 0x51
40 #define INTEL_I820_ERRSTS 0xc8
41
42 /* Intel i840 registers */
43 #define INTEL_I840_MCHCFG 0x50
44 #define INTEL_I840_ERRSTS 0xc8
45
46 /* Intel i850 registers */
47 #define INTEL_I850_MCHCFG 0x50
48 #define INTEL_I850_ERRSTS 0xc8
49
50 /* intel 915G registers */
51 #define I915_GMADDR 0x18
52 #define I915_MMADDR 0x10
53 #define I915_PTEADDR 0x1C
54 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
55 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
56
57 /* Intel 965G registers */
58 #define I965_MSAC 0x62
59
60 /* Intel 7505 registers */
61 #define INTEL_I7505_APSIZE 0x74
62 #define INTEL_I7505_NCAPID 0x60
63 #define INTEL_I7505_NISTAT 0x6c
64 #define INTEL_I7505_ATTBASE 0x78
65 #define INTEL_I7505_ERRSTS 0x42
66 #define INTEL_I7505_AGPCTRL 0x70
67 #define INTEL_I7505_MCHCFG 0x50
68
69 static const struct aper_size_info_fixed intel_i810_sizes[] =
70 {
71 {64, 16384, 4},
72 /* The 32M mode still requires a 64k gatt */
73 {32, 8192, 4}
74 };
75
76 #define AGP_DCACHE_MEMORY 1
77 #define AGP_PHYS_MEMORY 2
78 #define INTEL_AGP_CACHED_MEMORY 3
79
80 static struct gatt_mask intel_i810_masks[] =
81 {
82 {.mask = I810_PTE_VALID, .type = 0},
83 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
84 {.mask = I810_PTE_VALID, .type = 0},
85 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
86 .type = INTEL_AGP_CACHED_MEMORY}
87 };
88
89 static struct _intel_private {
90 struct pci_dev *pcidev; /* device one */
91 u8 __iomem *registers;
92 u32 __iomem *gtt; /* I915G */
93 int num_dcache_entries;
94 /* gtt_entries is the number of gtt entries that are already mapped
95 * to stolen memory. Stolen memory is larger than the memory mapped
96 * through gtt_entries, as it includes some reserved space for the BIOS
97 * popup and for the GTT.
98 */
99 int gtt_entries; /* i830+ */
100 } intel_private;
101
102 static int intel_i810_fetch_size(void)
103 {
104 u32 smram_miscc;
105 struct aper_size_info_fixed *values;
106
107 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
108 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
109
110 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
111 printk(KERN_WARNING PFX "i810 is disabled\n");
112 return 0;
113 }
114 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
115 agp_bridge->previous_size =
116 agp_bridge->current_size = (void *) (values + 1);
117 agp_bridge->aperture_size_idx = 1;
118 return values[1].size;
119 } else {
120 agp_bridge->previous_size =
121 agp_bridge->current_size = (void *) (values);
122 agp_bridge->aperture_size_idx = 0;
123 return values[0].size;
124 }
125
126 return 0;
127 }
128
129 static int intel_i810_configure(void)
130 {
131 struct aper_size_info_fixed *current_size;
132 u32 temp;
133 int i;
134
135 current_size = A_SIZE_FIX(agp_bridge->current_size);
136
137 if (!intel_private.registers) {
138 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
139 temp &= 0xfff80000;
140
141 intel_private.registers = ioremap(temp, 128 * 4096);
142 if (!intel_private.registers) {
143 printk(KERN_ERR PFX "Unable to remap memory.\n");
144 return -ENOMEM;
145 }
146 }
147
148 if ((readl(intel_private.registers+I810_DRAM_CTL)
149 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
150 /* This will need to be dynamically assigned */
151 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
152 intel_private.num_dcache_entries = 1024;
153 }
154 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
155 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
156 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
157 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
158
159 if (agp_bridge->driver->needs_scratch_page) {
160 for (i = 0; i < current_size->num_entries; i++) {
161 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
162 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
163 }
164 }
165 global_cache_flush();
166 return 0;
167 }
168
169 static void intel_i810_cleanup(void)
170 {
171 writel(0, intel_private.registers+I810_PGETBL_CTL);
172 readl(intel_private.registers); /* PCI Posting. */
173 iounmap(intel_private.registers);
174 }
175
176 static void intel_i810_tlbflush(struct agp_memory *mem)
177 {
178 return;
179 }
180
181 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
182 {
183 return;
184 }
185
186 /* Exists to support ARGB cursors */
187 static void *i8xx_alloc_pages(void)
188 {
189 struct page * page;
190
191 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
192 if (page == NULL)
193 return NULL;
194
195 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
196 change_page_attr(page, 4, PAGE_KERNEL);
197 global_flush_tlb();
198 __free_pages(page, 2);
199 return NULL;
200 }
201 global_flush_tlb();
202 get_page(page);
203 SetPageLocked(page);
204 atomic_inc(&agp_bridge->current_memory_agp);
205 return page_address(page);
206 }
207
208 static void i8xx_destroy_pages(void *addr)
209 {
210 struct page *page;
211
212 if (addr == NULL)
213 return;
214
215 page = virt_to_page(addr);
216 change_page_attr(page, 4, PAGE_KERNEL);
217 global_flush_tlb();
218 put_page(page);
219 unlock_page(page);
220 __free_pages(page, 2);
221 atomic_dec(&agp_bridge->current_memory_agp);
222 }
223
224 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
225 int type)
226 {
227 if (type < AGP_USER_TYPES)
228 return type;
229 else if (type == AGP_USER_CACHED_MEMORY)
230 return INTEL_AGP_CACHED_MEMORY;
231 else
232 return 0;
233 }
234
235 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
236 int type)
237 {
238 int i, j, num_entries;
239 void *temp;
240 int ret = -EINVAL;
241 int mask_type;
242
243 if (mem->page_count == 0)
244 goto out;
245
246 temp = agp_bridge->current_size;
247 num_entries = A_SIZE_FIX(temp)->num_entries;
248
249 if ((pg_start + mem->page_count) > num_entries)
250 goto out_err;
251
252
253 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
254 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
255 ret = -EBUSY;
256 goto out_err;
257 }
258 }
259
260 if (type != mem->type)
261 goto out_err;
262
263 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
264
265 switch (mask_type) {
266 case AGP_DCACHE_MEMORY:
267 if (!mem->is_flushed)
268 global_cache_flush();
269 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
270 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
271 intel_private.registers+I810_PTE_BASE+(i*4));
272 }
273 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
274 break;
275 case AGP_PHYS_MEMORY:
276 case AGP_NORMAL_MEMORY:
277 if (!mem->is_flushed)
278 global_cache_flush();
279 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
280 writel(agp_bridge->driver->mask_memory(agp_bridge,
281 mem->memory[i],
282 mask_type),
283 intel_private.registers+I810_PTE_BASE+(j*4));
284 }
285 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
286 break;
287 default:
288 goto out_err;
289 }
290
291 agp_bridge->driver->tlb_flush(mem);
292 out:
293 ret = 0;
294 out_err:
295 mem->is_flushed = 1;
296 return ret;
297 }
298
299 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
300 int type)
301 {
302 int i;
303
304 if (mem->page_count == 0)
305 return 0;
306
307 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
308 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
309 }
310 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
311
312 agp_bridge->driver->tlb_flush(mem);
313 return 0;
314 }
315
316 /*
317 * The i810/i830 requires a physical address to program its mouse
318 * pointer into hardware.
319 * However the Xserver still writes to it through the agp aperture.
320 */
321 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
322 {
323 struct agp_memory *new;
324 void *addr;
325
326 switch (pg_count) {
327 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
328 global_flush_tlb();
329 break;
330 case 4:
331 /* kludge to get 4 physical pages for ARGB cursor */
332 addr = i8xx_alloc_pages();
333 break;
334 default:
335 return NULL;
336 }
337
338 if (addr == NULL)
339 return NULL;
340
341 new = agp_create_memory(pg_count);
342 if (new == NULL)
343 return NULL;
344
345 new->memory[0] = virt_to_gart(addr);
346 if (pg_count == 4) {
347 /* kludge to get 4 physical pages for ARGB cursor */
348 new->memory[1] = new->memory[0] + PAGE_SIZE;
349 new->memory[2] = new->memory[1] + PAGE_SIZE;
350 new->memory[3] = new->memory[2] + PAGE_SIZE;
351 }
352 new->page_count = pg_count;
353 new->num_scratch_pages = pg_count;
354 new->type = AGP_PHYS_MEMORY;
355 new->physical = new->memory[0];
356 return new;
357 }
358
359 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
360 {
361 struct agp_memory *new;
362
363 if (type == AGP_DCACHE_MEMORY) {
364 if (pg_count != intel_private.num_dcache_entries)
365 return NULL;
366
367 new = agp_create_memory(1);
368 if (new == NULL)
369 return NULL;
370
371 new->type = AGP_DCACHE_MEMORY;
372 new->page_count = pg_count;
373 new->num_scratch_pages = 0;
374 agp_free_page_array(new);
375 return new;
376 }
377 if (type == AGP_PHYS_MEMORY)
378 return alloc_agpphysmem_i8xx(pg_count, type);
379 return NULL;
380 }
381
382 static void intel_i810_free_by_type(struct agp_memory *curr)
383 {
384 agp_free_key(curr->key);
385 if (curr->type == AGP_PHYS_MEMORY) {
386 if (curr->page_count == 4)
387 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
388 else {
389 agp_bridge->driver->agp_destroy_page(
390 gart_to_virt(curr->memory[0]));
391 global_flush_tlb();
392 }
393 agp_free_page_array(curr);
394 }
395 kfree(curr);
396 }
397
398 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
399 unsigned long addr, int type)
400 {
401 /* Type checking must be done elsewhere */
402 return addr | bridge->driver->masks[type].mask;
403 }
404
405 static struct aper_size_info_fixed intel_i830_sizes[] =
406 {
407 {128, 32768, 5},
408 /* The 64M mode still requires a 128k gatt */
409 {64, 16384, 5},
410 {256, 65536, 6},
411 {512, 131072, 7},
412 };
413
414 static void intel_i830_init_gtt_entries(void)
415 {
416 u16 gmch_ctrl;
417 int gtt_entries;
418 u8 rdct;
419 int local = 0;
420 static const int ddt[4] = { 0, 16, 32, 64 };
421 int size; /* reserved space (in kb) at the top of stolen memory */
422
423 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
424
425 if (IS_I965) {
426 u32 pgetbl_ctl;
427 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
428
429 /* The 965 has a field telling us the size of the GTT,
430 * which may be larger than what is necessary to map the
431 * aperture.
432 */
433 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
434 case I965_PGETBL_SIZE_128KB:
435 size = 128;
436 break;
437 case I965_PGETBL_SIZE_256KB:
438 size = 256;
439 break;
440 case I965_PGETBL_SIZE_512KB:
441 size = 512;
442 break;
443 default:
444 printk(KERN_INFO PFX "Unknown page table size, "
445 "assuming 512KB\n");
446 size = 512;
447 }
448 size += 4; /* add in BIOS popup space */
449 } else {
450 /* On previous hardware, the GTT size was just what was
451 * required to map the aperture.
452 */
453 size = agp_bridge->driver->fetch_size() + 4;
454 }
455
456 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
457 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
458 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
459 case I830_GMCH_GMS_STOLEN_512:
460 gtt_entries = KB(512) - KB(size);
461 break;
462 case I830_GMCH_GMS_STOLEN_1024:
463 gtt_entries = MB(1) - KB(size);
464 break;
465 case I830_GMCH_GMS_STOLEN_8192:
466 gtt_entries = MB(8) - KB(size);
467 break;
468 case I830_GMCH_GMS_LOCAL:
469 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
470 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
471 MB(ddt[I830_RDRAM_DDT(rdct)]);
472 local = 1;
473 break;
474 default:
475 gtt_entries = 0;
476 break;
477 }
478 } else {
479 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
480 case I855_GMCH_GMS_STOLEN_1M:
481 gtt_entries = MB(1) - KB(size);
482 break;
483 case I855_GMCH_GMS_STOLEN_4M:
484 gtt_entries = MB(4) - KB(size);
485 break;
486 case I855_GMCH_GMS_STOLEN_8M:
487 gtt_entries = MB(8) - KB(size);
488 break;
489 case I855_GMCH_GMS_STOLEN_16M:
490 gtt_entries = MB(16) - KB(size);
491 break;
492 case I855_GMCH_GMS_STOLEN_32M:
493 gtt_entries = MB(32) - KB(size);
494 break;
495 case I915_GMCH_GMS_STOLEN_48M:
496 /* Check it's really I915G */
497 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
498 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
499 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
500 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 )
501 gtt_entries = MB(48) - KB(size);
502 else
503 gtt_entries = 0;
504 break;
505 case I915_GMCH_GMS_STOLEN_64M:
506 /* Check it's really I915G */
507 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
508 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
509 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
510 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965)
511 gtt_entries = MB(64) - KB(size);
512 else
513 gtt_entries = 0;
514 default:
515 gtt_entries = 0;
516 break;
517 }
518 }
519 if (gtt_entries > 0)
520 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
521 gtt_entries / KB(1), local ? "local" : "stolen");
522 else
523 printk(KERN_INFO PFX
524 "No pre-allocated video memory detected.\n");
525 gtt_entries /= KB(4);
526
527 intel_private.gtt_entries = gtt_entries;
528 }
529
530 /* The intel i830 automatically initializes the agp aperture during POST.
531 * Use the memory already set aside for in the GTT.
532 */
533 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
534 {
535 int page_order;
536 struct aper_size_info_fixed *size;
537 int num_entries;
538 u32 temp;
539
540 size = agp_bridge->current_size;
541 page_order = size->page_order;
542 num_entries = size->num_entries;
543 agp_bridge->gatt_table_real = NULL;
544
545 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
546 temp &= 0xfff80000;
547
548 intel_private.registers = ioremap(temp,128 * 4096);
549 if (!intel_private.registers)
550 return -ENOMEM;
551
552 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
553 global_cache_flush(); /* FIXME: ?? */
554
555 /* we have to call this as early as possible after the MMIO base address is known */
556 intel_i830_init_gtt_entries();
557
558 agp_bridge->gatt_table = NULL;
559
560 agp_bridge->gatt_bus_addr = temp;
561
562 return 0;
563 }
564
565 /* Return the gatt table to a sane state. Use the top of stolen
566 * memory for the GTT.
567 */
568 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
569 {
570 return 0;
571 }
572
573 static int intel_i830_fetch_size(void)
574 {
575 u16 gmch_ctrl;
576 struct aper_size_info_fixed *values;
577
578 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
579
580 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
581 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
582 /* 855GM/852GM/865G has 128MB aperture size */
583 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
584 agp_bridge->aperture_size_idx = 0;
585 return values[0].size;
586 }
587
588 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
589
590 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
591 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
592 agp_bridge->aperture_size_idx = 0;
593 return values[0].size;
594 } else {
595 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
596 agp_bridge->aperture_size_idx = 1;
597 return values[1].size;
598 }
599
600 return 0;
601 }
602
603 static int intel_i830_configure(void)
604 {
605 struct aper_size_info_fixed *current_size;
606 u32 temp;
607 u16 gmch_ctrl;
608 int i;
609
610 current_size = A_SIZE_FIX(agp_bridge->current_size);
611
612 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
613 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
614
615 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
616 gmch_ctrl |= I830_GMCH_ENABLED;
617 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
618
619 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
620 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
621
622 if (agp_bridge->driver->needs_scratch_page) {
623 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
624 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
625 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
626 }
627 }
628
629 global_cache_flush();
630 return 0;
631 }
632
633 static void intel_i830_cleanup(void)
634 {
635 iounmap(intel_private.registers);
636 }
637
638 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
639 {
640 int i,j,num_entries;
641 void *temp;
642 int ret = -EINVAL;
643 int mask_type;
644
645 if (mem->page_count == 0)
646 goto out;
647
648 temp = agp_bridge->current_size;
649 num_entries = A_SIZE_FIX(temp)->num_entries;
650
651 if (pg_start < intel_private.gtt_entries) {
652 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
653 pg_start,intel_private.gtt_entries);
654
655 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
656 goto out_err;
657 }
658
659 if ((pg_start + mem->page_count) > num_entries)
660 goto out_err;
661
662 /* The i830 can't check the GTT for entries since its read only,
663 * depend on the caller to make the correct offset decisions.
664 */
665
666 if (type != mem->type)
667 goto out_err;
668
669 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
670
671 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
672 mask_type != INTEL_AGP_CACHED_MEMORY)
673 goto out_err;
674
675 if (!mem->is_flushed)
676 global_cache_flush();
677
678 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
679 writel(agp_bridge->driver->mask_memory(agp_bridge,
680 mem->memory[i], mask_type),
681 intel_private.registers+I810_PTE_BASE+(j*4));
682 }
683 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
684 agp_bridge->driver->tlb_flush(mem);
685
686 out:
687 ret = 0;
688 out_err:
689 mem->is_flushed = 1;
690 return ret;
691 }
692
693 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
694 int type)
695 {
696 int i;
697
698 if (mem->page_count == 0)
699 return 0;
700
701 if (pg_start < intel_private.gtt_entries) {
702 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
703 return -EINVAL;
704 }
705
706 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
707 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
708 }
709 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
710
711 agp_bridge->driver->tlb_flush(mem);
712 return 0;
713 }
714
715 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
716 {
717 if (type == AGP_PHYS_MEMORY)
718 return alloc_agpphysmem_i8xx(pg_count, type);
719 /* always return NULL for other allocation types for now */
720 return NULL;
721 }
722
723 static int intel_i915_configure(void)
724 {
725 struct aper_size_info_fixed *current_size;
726 u32 temp;
727 u16 gmch_ctrl;
728 int i;
729
730 current_size = A_SIZE_FIX(agp_bridge->current_size);
731
732 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
733
734 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
735
736 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
737 gmch_ctrl |= I830_GMCH_ENABLED;
738 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
739
740 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
741 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
742
743 if (agp_bridge->driver->needs_scratch_page) {
744 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
745 writel(agp_bridge->scratch_page, intel_private.gtt+i);
746 readl(intel_private.gtt+i); /* PCI Posting. */
747 }
748 }
749
750 global_cache_flush();
751 return 0;
752 }
753
754 static void intel_i915_cleanup(void)
755 {
756 iounmap(intel_private.gtt);
757 iounmap(intel_private.registers);
758 }
759
760 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
761 int type)
762 {
763 int i,j,num_entries;
764 void *temp;
765 int ret = -EINVAL;
766 int mask_type;
767
768 if (mem->page_count == 0)
769 goto out;
770
771 temp = agp_bridge->current_size;
772 num_entries = A_SIZE_FIX(temp)->num_entries;
773
774 if (pg_start < intel_private.gtt_entries) {
775 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
776 pg_start,intel_private.gtt_entries);
777
778 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
779 goto out_err;
780 }
781
782 if ((pg_start + mem->page_count) > num_entries)
783 goto out_err;
784
785 /* The i915 can't check the GTT for entries since its read only,
786 * depend on the caller to make the correct offset decisions.
787 */
788
789 if (type != mem->type)
790 goto out_err;
791
792 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
793
794 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
795 mask_type != INTEL_AGP_CACHED_MEMORY)
796 goto out_err;
797
798 if (!mem->is_flushed)
799 global_cache_flush();
800
801 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
802 writel(agp_bridge->driver->mask_memory(agp_bridge,
803 mem->memory[i], mask_type), intel_private.gtt+j);
804 }
805
806 readl(intel_private.gtt+j-1);
807 agp_bridge->driver->tlb_flush(mem);
808
809 out:
810 ret = 0;
811 out_err:
812 mem->is_flushed = 1;
813 return ret;
814 }
815
816 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
817 int type)
818 {
819 int i;
820
821 if (mem->page_count == 0)
822 return 0;
823
824 if (pg_start < intel_private.gtt_entries) {
825 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
826 return -EINVAL;
827 }
828
829 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
830 writel(agp_bridge->scratch_page, intel_private.gtt+i);
831 }
832 readl(intel_private.gtt+i-1);
833
834 agp_bridge->driver->tlb_flush(mem);
835 return 0;
836 }
837
838 /* Return the aperture size by just checking the resource length. The effect
839 * described in the spec of the MSAC registers is just changing of the
840 * resource size.
841 */
842 static int intel_i9xx_fetch_size(void)
843 {
844 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
845 int aper_size; /* size in megabytes */
846 int i;
847
848 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
849
850 for (i = 0; i < num_sizes; i++) {
851 if (aper_size == intel_i830_sizes[i].size) {
852 agp_bridge->current_size = intel_i830_sizes + i;
853 agp_bridge->previous_size = agp_bridge->current_size;
854 return aper_size;
855 }
856 }
857
858 return 0;
859 }
860
861 /* The intel i915 automatically initializes the agp aperture during POST.
862 * Use the memory already set aside for in the GTT.
863 */
864 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
865 {
866 int page_order;
867 struct aper_size_info_fixed *size;
868 int num_entries;
869 u32 temp, temp2;
870
871 size = agp_bridge->current_size;
872 page_order = size->page_order;
873 num_entries = size->num_entries;
874 agp_bridge->gatt_table_real = NULL;
875
876 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
877 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
878
879 intel_private.gtt = ioremap(temp2, 256 * 1024);
880 if (!intel_private.gtt)
881 return -ENOMEM;
882
883 temp &= 0xfff80000;
884
885 intel_private.registers = ioremap(temp,128 * 4096);
886 if (!intel_private.registers)
887 return -ENOMEM;
888
889 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
890 global_cache_flush(); /* FIXME: ? */
891
892 /* we have to call this as early as possible after the MMIO base address is known */
893 intel_i830_init_gtt_entries();
894
895 agp_bridge->gatt_table = NULL;
896
897 agp_bridge->gatt_bus_addr = temp;
898
899 return 0;
900 }
901
902 /*
903 * The i965 supports 36-bit physical addresses, but to keep
904 * the format of the GTT the same, the bits that don't fit
905 * in a 32-bit word are shifted down to bits 4..7.
906 *
907 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
908 * is always zero on 32-bit architectures, so no need to make
909 * this conditional.
910 */
911 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
912 unsigned long addr, int type)
913 {
914 /* Shift high bits down */
915 addr |= (addr >> 28) & 0xf0;
916
917 /* Type checking must be done elsewhere */
918 return addr | bridge->driver->masks[type].mask;
919 }
920
921 /* The intel i965 automatically initializes the agp aperture during POST.
922 * Use the memory already set aside for in the GTT.
923 */
924 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
925 {
926 int page_order;
927 struct aper_size_info_fixed *size;
928 int num_entries;
929 u32 temp;
930
931 size = agp_bridge->current_size;
932 page_order = size->page_order;
933 num_entries = size->num_entries;
934 agp_bridge->gatt_table_real = NULL;
935
936 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
937
938 temp &= 0xfff00000;
939 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
940
941 if (!intel_private.gtt)
942 return -ENOMEM;
943
944
945 intel_private.registers = ioremap(temp,128 * 4096);
946 if (!intel_private.registers)
947 return -ENOMEM;
948
949 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
950 global_cache_flush(); /* FIXME: ? */
951
952 /* we have to call this as early as possible after the MMIO base address is known */
953 intel_i830_init_gtt_entries();
954
955 agp_bridge->gatt_table = NULL;
956
957 agp_bridge->gatt_bus_addr = temp;
958
959 return 0;
960 }
961
962
963 static int intel_fetch_size(void)
964 {
965 int i;
966 u16 temp;
967 struct aper_size_info_16 *values;
968
969 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
970 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
971
972 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
973 if (temp == values[i].size_value) {
974 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
975 agp_bridge->aperture_size_idx = i;
976 return values[i].size;
977 }
978 }
979
980 return 0;
981 }
982
983 static int __intel_8xx_fetch_size(u8 temp)
984 {
985 int i;
986 struct aper_size_info_8 *values;
987
988 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
989
990 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
991 if (temp == values[i].size_value) {
992 agp_bridge->previous_size =
993 agp_bridge->current_size = (void *) (values + i);
994 agp_bridge->aperture_size_idx = i;
995 return values[i].size;
996 }
997 }
998 return 0;
999 }
1000
1001 static int intel_8xx_fetch_size(void)
1002 {
1003 u8 temp;
1004
1005 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1006 return __intel_8xx_fetch_size(temp);
1007 }
1008
1009 static int intel_815_fetch_size(void)
1010 {
1011 u8 temp;
1012
1013 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1014 * one non-reserved bit, so mask the others out ... */
1015 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1016 temp &= (1 << 3);
1017
1018 return __intel_8xx_fetch_size(temp);
1019 }
1020
1021 static void intel_tlbflush(struct agp_memory *mem)
1022 {
1023 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1024 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1025 }
1026
1027
1028 static void intel_8xx_tlbflush(struct agp_memory *mem)
1029 {
1030 u32 temp;
1031 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1032 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1033 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1034 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1035 }
1036
1037
1038 static void intel_cleanup(void)
1039 {
1040 u16 temp;
1041 struct aper_size_info_16 *previous_size;
1042
1043 previous_size = A_SIZE_16(agp_bridge->previous_size);
1044 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1045 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1046 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1047 }
1048
1049
1050 static void intel_8xx_cleanup(void)
1051 {
1052 u16 temp;
1053 struct aper_size_info_8 *previous_size;
1054
1055 previous_size = A_SIZE_8(agp_bridge->previous_size);
1056 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1057 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1058 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1059 }
1060
1061
1062 static int intel_configure(void)
1063 {
1064 u32 temp;
1065 u16 temp2;
1066 struct aper_size_info_16 *current_size;
1067
1068 current_size = A_SIZE_16(agp_bridge->current_size);
1069
1070 /* aperture size */
1071 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1072
1073 /* address to map to */
1074 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1075 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1076
1077 /* attbase - aperture base */
1078 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1079
1080 /* agpctrl */
1081 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1082
1083 /* paccfg/nbxcfg */
1084 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1085 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1086 (temp2 & ~(1 << 10)) | (1 << 9));
1087 /* clear any possible error conditions */
1088 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1089 return 0;
1090 }
1091
1092 static int intel_815_configure(void)
1093 {
1094 u32 temp, addr;
1095 u8 temp2;
1096 struct aper_size_info_8 *current_size;
1097
1098 /* attbase - aperture base */
1099 /* the Intel 815 chipset spec. says that bits 29-31 in the
1100 * ATTBASE register are reserved -> try not to write them */
1101 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1102 printk (KERN_EMERG PFX "gatt bus addr too high");
1103 return -EINVAL;
1104 }
1105
1106 current_size = A_SIZE_8(agp_bridge->current_size);
1107
1108 /* aperture size */
1109 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1110 current_size->size_value);
1111
1112 /* address to map to */
1113 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1114 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1115
1116 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1117 addr &= INTEL_815_ATTBASE_MASK;
1118 addr |= agp_bridge->gatt_bus_addr;
1119 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1120
1121 /* agpctrl */
1122 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1123
1124 /* apcont */
1125 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1126 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1127
1128 /* clear any possible error conditions */
1129 /* Oddness : this chipset seems to have no ERRSTS register ! */
1130 return 0;
1131 }
1132
1133 static void intel_820_tlbflush(struct agp_memory *mem)
1134 {
1135 return;
1136 }
1137
1138 static void intel_820_cleanup(void)
1139 {
1140 u8 temp;
1141 struct aper_size_info_8 *previous_size;
1142
1143 previous_size = A_SIZE_8(agp_bridge->previous_size);
1144 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1145 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1146 temp & ~(1 << 1));
1147 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1148 previous_size->size_value);
1149 }
1150
1151
1152 static int intel_820_configure(void)
1153 {
1154 u32 temp;
1155 u8 temp2;
1156 struct aper_size_info_8 *current_size;
1157
1158 current_size = A_SIZE_8(agp_bridge->current_size);
1159
1160 /* aperture size */
1161 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1162
1163 /* address to map to */
1164 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1165 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1166
1167 /* attbase - aperture base */
1168 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1169
1170 /* agpctrl */
1171 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1172
1173 /* global enable aperture access */
1174 /* This flag is not accessed through MCHCFG register as in */
1175 /* i850 chipset. */
1176 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1177 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1178 /* clear any possible AGP-related error conditions */
1179 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1180 return 0;
1181 }
1182
1183 static int intel_840_configure(void)
1184 {
1185 u32 temp;
1186 u16 temp2;
1187 struct aper_size_info_8 *current_size;
1188
1189 current_size = A_SIZE_8(agp_bridge->current_size);
1190
1191 /* aperture size */
1192 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1193
1194 /* address to map to */
1195 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1196 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1197
1198 /* attbase - aperture base */
1199 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1200
1201 /* agpctrl */
1202 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1203
1204 /* mcgcfg */
1205 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1206 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1207 /* clear any possible error conditions */
1208 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1209 return 0;
1210 }
1211
1212 static int intel_845_configure(void)
1213 {
1214 u32 temp;
1215 u8 temp2;
1216 struct aper_size_info_8 *current_size;
1217
1218 current_size = A_SIZE_8(agp_bridge->current_size);
1219
1220 /* aperture size */
1221 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1222
1223 if (agp_bridge->apbase_config != 0) {
1224 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1225 agp_bridge->apbase_config);
1226 } else {
1227 /* address to map to */
1228 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1229 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1230 agp_bridge->apbase_config = temp;
1231 }
1232
1233 /* attbase - aperture base */
1234 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1235
1236 /* agpctrl */
1237 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1238
1239 /* agpm */
1240 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1241 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1242 /* clear any possible error conditions */
1243 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1244 return 0;
1245 }
1246
1247 static int intel_850_configure(void)
1248 {
1249 u32 temp;
1250 u16 temp2;
1251 struct aper_size_info_8 *current_size;
1252
1253 current_size = A_SIZE_8(agp_bridge->current_size);
1254
1255 /* aperture size */
1256 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1257
1258 /* address to map to */
1259 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1260 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1261
1262 /* attbase - aperture base */
1263 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1264
1265 /* agpctrl */
1266 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1267
1268 /* mcgcfg */
1269 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1270 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1271 /* clear any possible AGP-related error conditions */
1272 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1273 return 0;
1274 }
1275
1276 static int intel_860_configure(void)
1277 {
1278 u32 temp;
1279 u16 temp2;
1280 struct aper_size_info_8 *current_size;
1281
1282 current_size = A_SIZE_8(agp_bridge->current_size);
1283
1284 /* aperture size */
1285 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1286
1287 /* address to map to */
1288 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1289 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1290
1291 /* attbase - aperture base */
1292 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1293
1294 /* agpctrl */
1295 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1296
1297 /* mcgcfg */
1298 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1299 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1300 /* clear any possible AGP-related error conditions */
1301 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1302 return 0;
1303 }
1304
1305 static int intel_830mp_configure(void)
1306 {
1307 u32 temp;
1308 u16 temp2;
1309 struct aper_size_info_8 *current_size;
1310
1311 current_size = A_SIZE_8(agp_bridge->current_size);
1312
1313 /* aperture size */
1314 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1315
1316 /* address to map to */
1317 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1318 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1319
1320 /* attbase - aperture base */
1321 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1322
1323 /* agpctrl */
1324 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1325
1326 /* gmch */
1327 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1328 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1329 /* clear any possible AGP-related error conditions */
1330 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1331 return 0;
1332 }
1333
1334 static int intel_7505_configure(void)
1335 {
1336 u32 temp;
1337 u16 temp2;
1338 struct aper_size_info_8 *current_size;
1339
1340 current_size = A_SIZE_8(agp_bridge->current_size);
1341
1342 /* aperture size */
1343 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1344
1345 /* address to map to */
1346 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1347 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1348
1349 /* attbase - aperture base */
1350 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1351
1352 /* agpctrl */
1353 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1354
1355 /* mchcfg */
1356 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1357 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1358
1359 return 0;
1360 }
1361
1362 /* Setup function */
1363 static const struct gatt_mask intel_generic_masks[] =
1364 {
1365 {.mask = 0x00000017, .type = 0}
1366 };
1367
1368 static const struct aper_size_info_8 intel_815_sizes[2] =
1369 {
1370 {64, 16384, 4, 0},
1371 {32, 8192, 3, 8},
1372 };
1373
1374 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1375 {
1376 {256, 65536, 6, 0},
1377 {128, 32768, 5, 32},
1378 {64, 16384, 4, 48},
1379 {32, 8192, 3, 56},
1380 {16, 4096, 2, 60},
1381 {8, 2048, 1, 62},
1382 {4, 1024, 0, 63}
1383 };
1384
1385 static const struct aper_size_info_16 intel_generic_sizes[7] =
1386 {
1387 {256, 65536, 6, 0},
1388 {128, 32768, 5, 32},
1389 {64, 16384, 4, 48},
1390 {32, 8192, 3, 56},
1391 {16, 4096, 2, 60},
1392 {8, 2048, 1, 62},
1393 {4, 1024, 0, 63}
1394 };
1395
1396 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1397 {
1398 {256, 65536, 6, 0},
1399 {128, 32768, 5, 32},
1400 {64, 16384, 4, 48},
1401 {32, 8192, 3, 56}
1402 };
1403
1404 static const struct agp_bridge_driver intel_generic_driver = {
1405 .owner = THIS_MODULE,
1406 .aperture_sizes = intel_generic_sizes,
1407 .size_type = U16_APER_SIZE,
1408 .num_aperture_sizes = 7,
1409 .configure = intel_configure,
1410 .fetch_size = intel_fetch_size,
1411 .cleanup = intel_cleanup,
1412 .tlb_flush = intel_tlbflush,
1413 .mask_memory = agp_generic_mask_memory,
1414 .masks = intel_generic_masks,
1415 .agp_enable = agp_generic_enable,
1416 .cache_flush = global_cache_flush,
1417 .create_gatt_table = agp_generic_create_gatt_table,
1418 .free_gatt_table = agp_generic_free_gatt_table,
1419 .insert_memory = agp_generic_insert_memory,
1420 .remove_memory = agp_generic_remove_memory,
1421 .alloc_by_type = agp_generic_alloc_by_type,
1422 .free_by_type = agp_generic_free_by_type,
1423 .agp_alloc_page = agp_generic_alloc_page,
1424 .agp_destroy_page = agp_generic_destroy_page,
1425 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1426 };
1427
1428 static const struct agp_bridge_driver intel_810_driver = {
1429 .owner = THIS_MODULE,
1430 .aperture_sizes = intel_i810_sizes,
1431 .size_type = FIXED_APER_SIZE,
1432 .num_aperture_sizes = 2,
1433 .needs_scratch_page = TRUE,
1434 .configure = intel_i810_configure,
1435 .fetch_size = intel_i810_fetch_size,
1436 .cleanup = intel_i810_cleanup,
1437 .tlb_flush = intel_i810_tlbflush,
1438 .mask_memory = intel_i810_mask_memory,
1439 .masks = intel_i810_masks,
1440 .agp_enable = intel_i810_agp_enable,
1441 .cache_flush = global_cache_flush,
1442 .create_gatt_table = agp_generic_create_gatt_table,
1443 .free_gatt_table = agp_generic_free_gatt_table,
1444 .insert_memory = intel_i810_insert_entries,
1445 .remove_memory = intel_i810_remove_entries,
1446 .alloc_by_type = intel_i810_alloc_by_type,
1447 .free_by_type = intel_i810_free_by_type,
1448 .agp_alloc_page = agp_generic_alloc_page,
1449 .agp_destroy_page = agp_generic_destroy_page,
1450 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1451 };
1452
1453 static const struct agp_bridge_driver intel_815_driver = {
1454 .owner = THIS_MODULE,
1455 .aperture_sizes = intel_815_sizes,
1456 .size_type = U8_APER_SIZE,
1457 .num_aperture_sizes = 2,
1458 .configure = intel_815_configure,
1459 .fetch_size = intel_815_fetch_size,
1460 .cleanup = intel_8xx_cleanup,
1461 .tlb_flush = intel_8xx_tlbflush,
1462 .mask_memory = agp_generic_mask_memory,
1463 .masks = intel_generic_masks,
1464 .agp_enable = agp_generic_enable,
1465 .cache_flush = global_cache_flush,
1466 .create_gatt_table = agp_generic_create_gatt_table,
1467 .free_gatt_table = agp_generic_free_gatt_table,
1468 .insert_memory = agp_generic_insert_memory,
1469 .remove_memory = agp_generic_remove_memory,
1470 .alloc_by_type = agp_generic_alloc_by_type,
1471 .free_by_type = agp_generic_free_by_type,
1472 .agp_alloc_page = agp_generic_alloc_page,
1473 .agp_destroy_page = agp_generic_destroy_page,
1474 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1475 };
1476
1477 static const struct agp_bridge_driver intel_830_driver = {
1478 .owner = THIS_MODULE,
1479 .aperture_sizes = intel_i830_sizes,
1480 .size_type = FIXED_APER_SIZE,
1481 .num_aperture_sizes = 4,
1482 .needs_scratch_page = TRUE,
1483 .configure = intel_i830_configure,
1484 .fetch_size = intel_i830_fetch_size,
1485 .cleanup = intel_i830_cleanup,
1486 .tlb_flush = intel_i810_tlbflush,
1487 .mask_memory = intel_i810_mask_memory,
1488 .masks = intel_i810_masks,
1489 .agp_enable = intel_i810_agp_enable,
1490 .cache_flush = global_cache_flush,
1491 .create_gatt_table = intel_i830_create_gatt_table,
1492 .free_gatt_table = intel_i830_free_gatt_table,
1493 .insert_memory = intel_i830_insert_entries,
1494 .remove_memory = intel_i830_remove_entries,
1495 .alloc_by_type = intel_i830_alloc_by_type,
1496 .free_by_type = intel_i810_free_by_type,
1497 .agp_alloc_page = agp_generic_alloc_page,
1498 .agp_destroy_page = agp_generic_destroy_page,
1499 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1500 };
1501
1502 static const struct agp_bridge_driver intel_820_driver = {
1503 .owner = THIS_MODULE,
1504 .aperture_sizes = intel_8xx_sizes,
1505 .size_type = U8_APER_SIZE,
1506 .num_aperture_sizes = 7,
1507 .configure = intel_820_configure,
1508 .fetch_size = intel_8xx_fetch_size,
1509 .cleanup = intel_820_cleanup,
1510 .tlb_flush = intel_820_tlbflush,
1511 .mask_memory = agp_generic_mask_memory,
1512 .masks = intel_generic_masks,
1513 .agp_enable = agp_generic_enable,
1514 .cache_flush = global_cache_flush,
1515 .create_gatt_table = agp_generic_create_gatt_table,
1516 .free_gatt_table = agp_generic_free_gatt_table,
1517 .insert_memory = agp_generic_insert_memory,
1518 .remove_memory = agp_generic_remove_memory,
1519 .alloc_by_type = agp_generic_alloc_by_type,
1520 .free_by_type = agp_generic_free_by_type,
1521 .agp_alloc_page = agp_generic_alloc_page,
1522 .agp_destroy_page = agp_generic_destroy_page,
1523 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1524 };
1525
1526 static const struct agp_bridge_driver intel_830mp_driver = {
1527 .owner = THIS_MODULE,
1528 .aperture_sizes = intel_830mp_sizes,
1529 .size_type = U8_APER_SIZE,
1530 .num_aperture_sizes = 4,
1531 .configure = intel_830mp_configure,
1532 .fetch_size = intel_8xx_fetch_size,
1533 .cleanup = intel_8xx_cleanup,
1534 .tlb_flush = intel_8xx_tlbflush,
1535 .mask_memory = agp_generic_mask_memory,
1536 .masks = intel_generic_masks,
1537 .agp_enable = agp_generic_enable,
1538 .cache_flush = global_cache_flush,
1539 .create_gatt_table = agp_generic_create_gatt_table,
1540 .free_gatt_table = agp_generic_free_gatt_table,
1541 .insert_memory = agp_generic_insert_memory,
1542 .remove_memory = agp_generic_remove_memory,
1543 .alloc_by_type = agp_generic_alloc_by_type,
1544 .free_by_type = agp_generic_free_by_type,
1545 .agp_alloc_page = agp_generic_alloc_page,
1546 .agp_destroy_page = agp_generic_destroy_page,
1547 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1548 };
1549
1550 static const struct agp_bridge_driver intel_840_driver = {
1551 .owner = THIS_MODULE,
1552 .aperture_sizes = intel_8xx_sizes,
1553 .size_type = U8_APER_SIZE,
1554 .num_aperture_sizes = 7,
1555 .configure = intel_840_configure,
1556 .fetch_size = intel_8xx_fetch_size,
1557 .cleanup = intel_8xx_cleanup,
1558 .tlb_flush = intel_8xx_tlbflush,
1559 .mask_memory = agp_generic_mask_memory,
1560 .masks = intel_generic_masks,
1561 .agp_enable = agp_generic_enable,
1562 .cache_flush = global_cache_flush,
1563 .create_gatt_table = agp_generic_create_gatt_table,
1564 .free_gatt_table = agp_generic_free_gatt_table,
1565 .insert_memory = agp_generic_insert_memory,
1566 .remove_memory = agp_generic_remove_memory,
1567 .alloc_by_type = agp_generic_alloc_by_type,
1568 .free_by_type = agp_generic_free_by_type,
1569 .agp_alloc_page = agp_generic_alloc_page,
1570 .agp_destroy_page = agp_generic_destroy_page,
1571 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1572 };
1573
1574 static const struct agp_bridge_driver intel_845_driver = {
1575 .owner = THIS_MODULE,
1576 .aperture_sizes = intel_8xx_sizes,
1577 .size_type = U8_APER_SIZE,
1578 .num_aperture_sizes = 7,
1579 .configure = intel_845_configure,
1580 .fetch_size = intel_8xx_fetch_size,
1581 .cleanup = intel_8xx_cleanup,
1582 .tlb_flush = intel_8xx_tlbflush,
1583 .mask_memory = agp_generic_mask_memory,
1584 .masks = intel_generic_masks,
1585 .agp_enable = agp_generic_enable,
1586 .cache_flush = global_cache_flush,
1587 .create_gatt_table = agp_generic_create_gatt_table,
1588 .free_gatt_table = agp_generic_free_gatt_table,
1589 .insert_memory = agp_generic_insert_memory,
1590 .remove_memory = agp_generic_remove_memory,
1591 .alloc_by_type = agp_generic_alloc_by_type,
1592 .free_by_type = agp_generic_free_by_type,
1593 .agp_alloc_page = agp_generic_alloc_page,
1594 .agp_destroy_page = agp_generic_destroy_page,
1595 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1596 };
1597
1598 static const struct agp_bridge_driver intel_850_driver = {
1599 .owner = THIS_MODULE,
1600 .aperture_sizes = intel_8xx_sizes,
1601 .size_type = U8_APER_SIZE,
1602 .num_aperture_sizes = 7,
1603 .configure = intel_850_configure,
1604 .fetch_size = intel_8xx_fetch_size,
1605 .cleanup = intel_8xx_cleanup,
1606 .tlb_flush = intel_8xx_tlbflush,
1607 .mask_memory = agp_generic_mask_memory,
1608 .masks = intel_generic_masks,
1609 .agp_enable = agp_generic_enable,
1610 .cache_flush = global_cache_flush,
1611 .create_gatt_table = agp_generic_create_gatt_table,
1612 .free_gatt_table = agp_generic_free_gatt_table,
1613 .insert_memory = agp_generic_insert_memory,
1614 .remove_memory = agp_generic_remove_memory,
1615 .alloc_by_type = agp_generic_alloc_by_type,
1616 .free_by_type = agp_generic_free_by_type,
1617 .agp_alloc_page = agp_generic_alloc_page,
1618 .agp_destroy_page = agp_generic_destroy_page,
1619 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1620 };
1621
1622 static const struct agp_bridge_driver intel_860_driver = {
1623 .owner = THIS_MODULE,
1624 .aperture_sizes = intel_8xx_sizes,
1625 .size_type = U8_APER_SIZE,
1626 .num_aperture_sizes = 7,
1627 .configure = intel_860_configure,
1628 .fetch_size = intel_8xx_fetch_size,
1629 .cleanup = intel_8xx_cleanup,
1630 .tlb_flush = intel_8xx_tlbflush,
1631 .mask_memory = agp_generic_mask_memory,
1632 .masks = intel_generic_masks,
1633 .agp_enable = agp_generic_enable,
1634 .cache_flush = global_cache_flush,
1635 .create_gatt_table = agp_generic_create_gatt_table,
1636 .free_gatt_table = agp_generic_free_gatt_table,
1637 .insert_memory = agp_generic_insert_memory,
1638 .remove_memory = agp_generic_remove_memory,
1639 .alloc_by_type = agp_generic_alloc_by_type,
1640 .free_by_type = agp_generic_free_by_type,
1641 .agp_alloc_page = agp_generic_alloc_page,
1642 .agp_destroy_page = agp_generic_destroy_page,
1643 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1644 };
1645
1646 static const struct agp_bridge_driver intel_915_driver = {
1647 .owner = THIS_MODULE,
1648 .aperture_sizes = intel_i830_sizes,
1649 .size_type = FIXED_APER_SIZE,
1650 .num_aperture_sizes = 4,
1651 .needs_scratch_page = TRUE,
1652 .configure = intel_i915_configure,
1653 .fetch_size = intel_i9xx_fetch_size,
1654 .cleanup = intel_i915_cleanup,
1655 .tlb_flush = intel_i810_tlbflush,
1656 .mask_memory = intel_i810_mask_memory,
1657 .masks = intel_i810_masks,
1658 .agp_enable = intel_i810_agp_enable,
1659 .cache_flush = global_cache_flush,
1660 .create_gatt_table = intel_i915_create_gatt_table,
1661 .free_gatt_table = intel_i830_free_gatt_table,
1662 .insert_memory = intel_i915_insert_entries,
1663 .remove_memory = intel_i915_remove_entries,
1664 .alloc_by_type = intel_i830_alloc_by_type,
1665 .free_by_type = intel_i810_free_by_type,
1666 .agp_alloc_page = agp_generic_alloc_page,
1667 .agp_destroy_page = agp_generic_destroy_page,
1668 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1669 };
1670
1671 static const struct agp_bridge_driver intel_i965_driver = {
1672 .owner = THIS_MODULE,
1673 .aperture_sizes = intel_i830_sizes,
1674 .size_type = FIXED_APER_SIZE,
1675 .num_aperture_sizes = 4,
1676 .needs_scratch_page = TRUE,
1677 .configure = intel_i915_configure,
1678 .fetch_size = intel_i9xx_fetch_size,
1679 .cleanup = intel_i915_cleanup,
1680 .tlb_flush = intel_i810_tlbflush,
1681 .mask_memory = intel_i965_mask_memory,
1682 .masks = intel_i810_masks,
1683 .agp_enable = intel_i810_agp_enable,
1684 .cache_flush = global_cache_flush,
1685 .create_gatt_table = intel_i965_create_gatt_table,
1686 .free_gatt_table = intel_i830_free_gatt_table,
1687 .insert_memory = intel_i915_insert_entries,
1688 .remove_memory = intel_i915_remove_entries,
1689 .alloc_by_type = intel_i830_alloc_by_type,
1690 .free_by_type = intel_i810_free_by_type,
1691 .agp_alloc_page = agp_generic_alloc_page,
1692 .agp_destroy_page = agp_generic_destroy_page,
1693 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1694 };
1695
1696 static const struct agp_bridge_driver intel_7505_driver = {
1697 .owner = THIS_MODULE,
1698 .aperture_sizes = intel_8xx_sizes,
1699 .size_type = U8_APER_SIZE,
1700 .num_aperture_sizes = 7,
1701 .configure = intel_7505_configure,
1702 .fetch_size = intel_8xx_fetch_size,
1703 .cleanup = intel_8xx_cleanup,
1704 .tlb_flush = intel_8xx_tlbflush,
1705 .mask_memory = agp_generic_mask_memory,
1706 .masks = intel_generic_masks,
1707 .agp_enable = agp_generic_enable,
1708 .cache_flush = global_cache_flush,
1709 .create_gatt_table = agp_generic_create_gatt_table,
1710 .free_gatt_table = agp_generic_free_gatt_table,
1711 .insert_memory = agp_generic_insert_memory,
1712 .remove_memory = agp_generic_remove_memory,
1713 .alloc_by_type = agp_generic_alloc_by_type,
1714 .free_by_type = agp_generic_free_by_type,
1715 .agp_alloc_page = agp_generic_alloc_page,
1716 .agp_destroy_page = agp_generic_destroy_page,
1717 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1718 };
1719
1720
1721 static int find_gmch(u16 device)
1722 {
1723 struct pci_dev *gmch_device;
1724
1725 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1726 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1727 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1728 device, gmch_device);
1729 }
1730
1731 if (!gmch_device)
1732 return 0;
1733
1734 intel_private.pcidev = gmch_device;
1735 return 1;
1736 }
1737
1738 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1739 * driver and gmch_driver must be non-null, and find_gmch will determine
1740 * which one should be used if a gmch_chip_id is present.
1741 */
1742 static const struct intel_driver_description {
1743 unsigned int chip_id;
1744 unsigned int gmch_chip_id;
1745 char *name;
1746 const struct agp_bridge_driver *driver;
1747 const struct agp_bridge_driver *gmch_driver;
1748 } intel_agp_chipsets[] = {
1749 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL },
1750 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL },
1751 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL },
1752 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1753 NULL, &intel_810_driver },
1754 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1755 NULL, &intel_810_driver },
1756 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1757 NULL, &intel_810_driver },
1758 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1759 &intel_810_driver, &intel_815_driver },
1760 { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL },
1761 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL },
1762 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1763 &intel_830mp_driver, &intel_830_driver },
1764 { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL },
1765 { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL },
1766 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1767 &intel_845_driver, &intel_830_driver },
1768 { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL },
1769 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
1770 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1771 &intel_845_driver, &intel_830_driver },
1772 { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
1773 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
1774 &intel_845_driver, &intel_830_driver },
1775 { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
1776 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1777 &intel_845_driver, &intel_915_driver },
1778 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1779 &intel_845_driver, &intel_915_driver },
1780 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1781 &intel_845_driver, &intel_915_driver },
1782 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1783 &intel_845_driver, &intel_915_driver },
1784 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1785 &intel_845_driver, &intel_i965_driver },
1786 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, "965G",
1787 &intel_845_driver, &intel_i965_driver },
1788 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1789 &intel_845_driver, &intel_i965_driver },
1790 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1791 &intel_845_driver, &intel_i965_driver },
1792 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1793 &intel_845_driver, &intel_i965_driver },
1794 { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
1795 { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
1796 { 0, 0, NULL, NULL, NULL }
1797 };
1798
1799 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1800 const struct pci_device_id *ent)
1801 {
1802 struct agp_bridge_data *bridge;
1803 u8 cap_ptr = 0;
1804 struct resource *r;
1805 int i;
1806
1807 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1808
1809 bridge = agp_alloc_bridge();
1810 if (!bridge)
1811 return -ENOMEM;
1812
1813 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1814 /* In case that multiple models of gfx chip may
1815 stand on same host bridge type, this can be
1816 sure we detect the right IGD. */
1817 if ((pdev->device == intel_agp_chipsets[i].chip_id) &&
1818 ((intel_agp_chipsets[i].gmch_chip_id == 0) ||
1819 find_gmch(intel_agp_chipsets[i].gmch_chip_id)))
1820 break;
1821 }
1822
1823 if (intel_agp_chipsets[i].name == NULL) {
1824 if (cap_ptr)
1825 printk(KERN_WARNING PFX "Unsupported Intel chipset"
1826 "(device id: %04x)\n", pdev->device);
1827 agp_put_bridge(bridge);
1828 return -ENODEV;
1829 }
1830
1831 if (intel_agp_chipsets[i].gmch_chip_id != 0)
1832 bridge->driver = intel_agp_chipsets[i].gmch_driver;
1833 else
1834 bridge->driver = intel_agp_chipsets[i].driver;
1835
1836 if (bridge->driver == NULL) {
1837 printk(KERN_WARNING PFX "Failed to find bridge device "
1838 "(chip_id: %04x)\n", intel_agp_chipsets[i].gmch_chip_id);
1839 agp_put_bridge(bridge);
1840 return -ENODEV;
1841 }
1842
1843 bridge->dev = pdev;
1844 bridge->capndx = cap_ptr;
1845 bridge->dev_private_data = &intel_private;
1846
1847 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1848 intel_agp_chipsets[i].name);
1849
1850 /*
1851 * The following fixes the case where the BIOS has "forgotten" to
1852 * provide an address range for the GART.
1853 * 20030610 - hamish@zot.org
1854 */
1855 r = &pdev->resource[0];
1856 if (!r->start && r->end) {
1857 if (pci_assign_resource(pdev, 0)) {
1858 printk(KERN_ERR PFX "could not assign resource 0\n");
1859 agp_put_bridge(bridge);
1860 return -ENODEV;
1861 }
1862 }
1863
1864 /*
1865 * If the device has not been properly setup, the following will catch
1866 * the problem and should stop the system from crashing.
1867 * 20030610 - hamish@zot.org
1868 */
1869 if (pci_enable_device(pdev)) {
1870 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1871 agp_put_bridge(bridge);
1872 return -ENODEV;
1873 }
1874
1875 /* Fill in the mode register */
1876 if (cap_ptr) {
1877 pci_read_config_dword(pdev,
1878 bridge->capndx+PCI_AGP_STATUS,
1879 &bridge->mode);
1880 }
1881
1882 pci_set_drvdata(pdev, bridge);
1883 return agp_add_bridge(bridge);
1884 }
1885
1886 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1887 {
1888 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1889
1890 agp_remove_bridge(bridge);
1891
1892 if (intel_private.pcidev)
1893 pci_dev_put(intel_private.pcidev);
1894
1895 agp_put_bridge(bridge);
1896 }
1897
1898 #ifdef CONFIG_PM
1899 static int agp_intel_resume(struct pci_dev *pdev)
1900 {
1901 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1902
1903 pci_restore_state(pdev);
1904
1905 /* We should restore our graphics device's config space,
1906 * as host bridge (00:00) resumes before graphics device (02:00),
1907 * then our access to its pci space can work right.
1908 */
1909 if (intel_private.pcidev)
1910 pci_restore_state(intel_private.pcidev);
1911
1912 if (bridge->driver == &intel_generic_driver)
1913 intel_configure();
1914 else if (bridge->driver == &intel_850_driver)
1915 intel_850_configure();
1916 else if (bridge->driver == &intel_845_driver)
1917 intel_845_configure();
1918 else if (bridge->driver == &intel_830mp_driver)
1919 intel_830mp_configure();
1920 else if (bridge->driver == &intel_915_driver)
1921 intel_i915_configure();
1922 else if (bridge->driver == &intel_830_driver)
1923 intel_i830_configure();
1924 else if (bridge->driver == &intel_810_driver)
1925 intel_i810_configure();
1926 else if (bridge->driver == &intel_i965_driver)
1927 intel_i915_configure();
1928
1929 return 0;
1930 }
1931 #endif
1932
1933 static struct pci_device_id agp_intel_pci_table[] = {
1934 #define ID(x) \
1935 { \
1936 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
1937 .class_mask = ~0, \
1938 .vendor = PCI_VENDOR_ID_INTEL, \
1939 .device = x, \
1940 .subvendor = PCI_ANY_ID, \
1941 .subdevice = PCI_ANY_ID, \
1942 }
1943 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
1944 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
1945 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
1946 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
1947 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
1948 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
1949 ID(PCI_DEVICE_ID_INTEL_82815_MC),
1950 ID(PCI_DEVICE_ID_INTEL_82820_HB),
1951 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
1952 ID(PCI_DEVICE_ID_INTEL_82830_HB),
1953 ID(PCI_DEVICE_ID_INTEL_82840_HB),
1954 ID(PCI_DEVICE_ID_INTEL_82845_HB),
1955 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
1956 ID(PCI_DEVICE_ID_INTEL_82850_HB),
1957 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
1958 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
1959 ID(PCI_DEVICE_ID_INTEL_82860_HB),
1960 ID(PCI_DEVICE_ID_INTEL_82865_HB),
1961 ID(PCI_DEVICE_ID_INTEL_82875_HB),
1962 ID(PCI_DEVICE_ID_INTEL_7505_0),
1963 ID(PCI_DEVICE_ID_INTEL_7205_0),
1964 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
1965 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
1966 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
1967 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
1968 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
1969 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
1970 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
1971 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
1972 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
1973 { }
1974 };
1975
1976 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
1977
1978 static struct pci_driver agp_intel_pci_driver = {
1979 .name = "agpgart-intel",
1980 .id_table = agp_intel_pci_table,
1981 .probe = agp_intel_probe,
1982 .remove = __devexit_p(agp_intel_remove),
1983 #ifdef CONFIG_PM
1984 .resume = agp_intel_resume,
1985 #endif
1986 };
1987
1988 static int __init agp_intel_init(void)
1989 {
1990 if (agp_off)
1991 return -EINVAL;
1992 return pci_register_driver(&agp_intel_pci_driver);
1993 }
1994
1995 static void __exit agp_intel_cleanup(void)
1996 {
1997 pci_unregister_driver(&agp_intel_pci_driver);
1998 }
1999
2000 module_init(agp_intel_init);
2001 module_exit(agp_intel_cleanup);
2002
2003 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2004 MODULE_LICENSE("GPL and additional rights");
Support for the Chinese Samsung S3C2440 based development boards