arch/arm/mach-at91/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27 #include <asm/mach-types.h>
  28
  29 #include <asm/hardware.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/cpu.h>
  32
  33 #include "clock.h"
  34
  35
  36 /*
  37  * There's a lot more which can be done with clocks, including cpufreq
  38  * integration, slow clock mode support (for system suspend), letting
  39  * PLLB be used at other rates (on boards that don't need USB), etc.
  40  */
  41
  42 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
  43 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
  44 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
  45 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
  46
  47
  48 static LIST_HEAD(clocks);
  49 static DEFINE_SPINLOCK(clk_lock);
  50
  51 static u32 at91_pllb_usb_init;
  52
  53 /*
  54  * Four primary clock sources:  two crystal oscillators (32K, main), and
  55  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
  56  * 48 MHz (unless no USB function clocks are needed).  The main clock and
  57  * both PLLs are turned off to run in "slow clock mode" (system suspend).
  58  */
  59 static struct clk clk32k = {
  60         .name           = "clk32k",
  61         .rate_hz        = AT91_SLOW_CLOCK,
  62         .users          = 1,            /* always on */
  63         .id             = 0,
  64         .type           = CLK_TYPE_PRIMARY,
  65 };
  66 static struct clk main_clk = {
  67         .name           = "main",
  68         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
  69         .id             = 1,
  70         .type           = CLK_TYPE_PRIMARY,
  71 };
  72 static struct clk plla = {
  73         .name           = "plla",
  74         .parent         = &main_clk,
  75         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
  76         .id             = 2,
  77         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
  78 };
  79
  80 static void pllb_mode(struct clk *clk, int is_on)
  81 {
  82         u32     value;
  83
  84         if (is_on) {
  85                 is_on = AT91_PMC_LOCKB;
  86                 value = at91_pllb_usb_init;
  87         } else
  88                 value = 0;
  89
  90         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
  91         at91_sys_write(AT91_CKGR_PLLBR, value);
  92
  93         do {
  94                 cpu_relax();
  95         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
  96 }
  97
  98 static struct clk pllb = {
  99         .name           = "pllb",
 100         .parent         = &main_clk,
 101         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
 102         .mode           = pllb_mode,
 103         .id             = 3,
 104         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 105 };
 106
 107 static void pmc_sys_mode(struct clk *clk, int is_on)
 108 {
 109         if (is_on)
 110                 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
 111         else
 112                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 113 }
 114
 115 /* USB function clocks (PLLB must be 48 MHz) */
 116 static struct clk udpck = {
 117         .name           = "udpck",
 118         .parent         = &pllb,
 119         .mode           = pmc_sys_mode,
 120 };
 121 static struct clk uhpck = {
 122         .name           = "uhpck",
 123         .parent         = &pllb,
 124         .mode           = pmc_sys_mode,
 125 };
 126
 127
 128 /*
 129  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 130  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 131  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 132  */
 133 static struct clk mck = {
 134         .name           = "mck",
 135         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 136 };
 137
 138 static void pmc_periph_mode(struct clk *clk, int is_on)
 139 {
 140         if (is_on)
 141                 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
 142         else
 143                 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
 144 }
 145
 146 static struct clk __init *at91_css_to_clk(unsigned long css)
 147 {
 148         switch (css) {
 149                 case AT91_PMC_CSS_SLOW:
 150                         return &clk32k;
 151                 case AT91_PMC_CSS_MAIN:
 152                         return &main_clk;
 153                 case AT91_PMC_CSS_PLLA:
 154                         return &plla;
 155                 case AT91_PMC_CSS_PLLB:
 156                         return &pllb;
 157         }
 158
 159         return NULL;
 160 }
 161
 162 /*
 163  * Associate a particular clock with a function (eg, "uart") and device.
 164  * The drivers can then request the same 'function' with several different
 165  * devices and not care about which clock name to use.
 166  */
 167 void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
 168 {
 169         struct clk *clk = clk_get(NULL, id);
 170
 171         if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
 172                 return;
 173
 174         clk->function = func;
 175         clk->dev = dev;
 176 }
 177
 178 /* clocks cannot be de-registered no refcounting necessary */
 179 struct clk *clk_get(struct device *dev, const char *id)
 180 {
 181         struct clk *clk;
 182
 183         list_for_each_entry(clk, &clocks, node) {
 184                 if (strcmp(id, clk->name) == 0)
 185                         return clk;
 186                 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
 187                         return clk;
 188         }
 189
 190         return ERR_PTR(-ENOENT);
 191 }
 192 EXPORT_SYMBOL(clk_get);
 193
 194 void clk_put(struct clk *clk)
 195 {
 196 }
 197 EXPORT_SYMBOL(clk_put);
 198
 199 static void __clk_enable(struct clk *clk)
 200 {
 201         if (clk->parent)
 202                 __clk_enable(clk->parent);
 203         if (clk->users++ == 0 && clk->mode)
 204                 clk->mode(clk, 1);
 205 }
 206
 207 int clk_enable(struct clk *clk)
 208 {
 209         unsigned long   flags;
 210
 211         spin_lock_irqsave(&clk_lock, flags);
 212         __clk_enable(clk);
 213         spin_unlock_irqrestore(&clk_lock, flags);
 214         return 0;
 215 }
 216 EXPORT_SYMBOL(clk_enable);
 217
 218 static void __clk_disable(struct clk *clk)
 219 {
 220         BUG_ON(clk->users == 0);
 221         if (--clk->users == 0 && clk->mode)
 222                 clk->mode(clk, 0);
 223         if (clk->parent)
 224                 __clk_disable(clk->parent);
 225 }
 226
 227 void clk_disable(struct clk *clk)
 228 {
 229         unsigned long   flags;
 230
 231         spin_lock_irqsave(&clk_lock, flags);
 232         __clk_disable(clk);
 233         spin_unlock_irqrestore(&clk_lock, flags);
 234 }
 235 EXPORT_SYMBOL(clk_disable);
 236
 237 unsigned long clk_get_rate(struct clk *clk)
 238 {
 239         unsigned long   flags;
 240         unsigned long   rate;
 241
 242         spin_lock_irqsave(&clk_lock, flags);
 243         for (;;) {
 244                 rate = clk->rate_hz;
 245                 if (rate || !clk->parent)
 246                         break;
 247                 clk = clk->parent;
 248         }
 249         spin_unlock_irqrestore(&clk_lock, flags);
 250         return rate;
 251 }
 252 EXPORT_SYMBOL(clk_get_rate);
 253
 254 /*------------------------------------------------------------------------*/
 255
 256 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 257
 258 /*
 259  * For now, only the programmable clocks support reparenting (MCK could
 260  * do this too, with care) or rate changing (the PLLs could do this too,
 261  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 262  * a better rate match; we don't.
 263  */
 264
 265 long clk_round_rate(struct clk *clk, unsigned long rate)
 266 {
 267         unsigned long   flags;
 268         unsigned        prescale;
 269         unsigned long   actual;
 270
 271         if (!clk_is_programmable(clk))
 272                 return -EINVAL;
 273         spin_lock_irqsave(&clk_lock, flags);
 274
 275         actual = clk->parent->rate_hz;
 276         for (prescale = 0; prescale < 7; prescale++) {
 277                 if (actual && actual <= rate)
 278                         break;
 279                 actual >>= 1;
 280         }
 281
 282         spin_unlock_irqrestore(&clk_lock, flags);
 283         return (prescale < 7) ? actual : -ENOENT;
 284 }
 285 EXPORT_SYMBOL(clk_round_rate);
 286
 287 int clk_set_rate(struct clk *clk, unsigned long rate)
 288 {
 289         unsigned long   flags;
 290         unsigned        prescale;
 291         unsigned long   actual;
 292
 293         if (!clk_is_programmable(clk))
 294                 return -EINVAL;
 295         if (clk->users)
 296                 return -EBUSY;
 297         spin_lock_irqsave(&clk_lock, flags);
 298
 299         actual = clk->parent->rate_hz;
 300         for (prescale = 0; prescale < 7; prescale++) {
 301                 if (actual && actual <= rate) {
 302                         u32     pckr;
 303
 304                         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 305                         pckr &= AT91_PMC_CSS_PLLB;      /* clock selection */
 306                         pckr |= prescale << 2;
 307                         at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
 308                         clk->rate_hz = actual;
 309                         break;
 310                 }
 311                 actual >>= 1;
 312         }
 313
 314         spin_unlock_irqrestore(&clk_lock, flags);
 315         return (prescale < 7) ? actual : -ENOENT;
 316 }
 317 EXPORT_SYMBOL(clk_set_rate);
 318
 319 struct clk *clk_get_parent(struct clk *clk)
 320 {
 321         return clk->parent;
 322 }
 323 EXPORT_SYMBOL(clk_get_parent);
 324
 325 int clk_set_parent(struct clk *clk, struct clk *parent)
 326 {
 327         unsigned long   flags;
 328
 329         if (clk->users)
 330                 return -EBUSY;
 331         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
 332                 return -EINVAL;
 333         spin_lock_irqsave(&clk_lock, flags);
 334
 335         clk->rate_hz = parent->rate_hz;
 336         clk->parent = parent;
 337         at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
 338
 339         spin_unlock_irqrestore(&clk_lock, flags);
 340         return 0;
 341 }
 342 EXPORT_SYMBOL(clk_set_parent);
 343
 344 /* establish PCK0..PCK3 parentage and rate */
 345 static void __init init_programmable_clock(struct clk *clk)
 346 {
 347         struct clk      *parent;
 348         u32             pckr;
 349
 350         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 351         parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
 352         clk->parent = parent;
 353         clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 354 }
 355
 356 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 357
 358 /*------------------------------------------------------------------------*/
 359
 360 #ifdef CONFIG_DEBUG_FS
 361
 362 static int at91_clk_show(struct seq_file *s, void *unused)
 363 {
 364         u32             scsr, pcsr, sr;
 365         struct clk      *clk;
 366
 367         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
 368         seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
 369         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
 370         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
 371         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
 372         seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
 373         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
 374         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 375
 376         seq_printf(s, "\n");
 377
 378         list_for_each_entry(clk, &clocks, node) {
 379                 char    *state;
 380
 381                 if (clk->mode == pmc_sys_mode)
 382                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 383                 else if (clk->mode == pmc_periph_mode)
 384                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
 385                 else if (clk->pmc_mask)
 386                         state = (sr & clk->pmc_mask) ? "on" : "off";
 387                 else if (clk == &clk32k || clk == &main_clk)
 388                         state = "on";
 389                 else
 390                         state = "";
 391
 392                 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
 393                         clk->name, clk->users, state, clk_get_rate(clk),
 394                         clk->parent ? clk->parent->name : "");
 395         }
 396         return 0;
 397 }
 398
 399 static int at91_clk_open(struct inode *inode, struct file *file)
 400 {
 401         return single_open(file, at91_clk_show, NULL);
 402 }
 403
 404 static const struct file_operations at91_clk_operations = {
 405         .open           = at91_clk_open,
 406         .read           = seq_read,
 407         .llseek         = seq_lseek,
 408         .release        = single_release,
 409 };
 410
 411 static int __init at91_clk_debugfs_init(void)
 412 {
 413         /* /sys/kernel/debug/at91_clk */
 414         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 415
 416         return 0;
 417 }
 418 postcore_initcall(at91_clk_debugfs_init);
 419
 420 #endif
 421
 422 /*------------------------------------------------------------------------*/
 423
 424 /* Register a new clock */
 425 int __init clk_register(struct clk *clk)
 426 {
 427         if (clk_is_peripheral(clk)) {
 428                 clk->parent = &mck;
 429                 clk->mode = pmc_periph_mode;
 430                 list_add_tail(&clk->node, &clocks);
 431         }
 432         else if (clk_is_sys(clk)) {
 433                 clk->parent = &mck;
 434                 clk->mode = pmc_sys_mode;
 435
 436                 list_add_tail(&clk->node, &clocks);
 437         }
 438 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 439         else if (clk_is_programmable(clk)) {
 440                 clk->mode = pmc_sys_mode;
 441                 init_programmable_clock(clk);
 442                 list_add_tail(&clk->node, &clocks);
 443         }
 444 #endif
 445
 446         return 0;
 447 }
 448
 449
 450 /*------------------------------------------------------------------------*/
 451
 452 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 453 {
 454         unsigned mul, div;
 455
 456         div = reg & 0xff;
 457         mul = (reg >> 16) & 0x7ff;
 458         if (div && mul) {
 459                 freq /= div;
 460                 freq *= mul + 1;
 461         } else
 462                 freq = 0;
 463
 464         return freq;
 465 }
 466
 467 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 468 {
 469         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 470                 return freq / 2;
 471         else
 472                 return freq;
 473 }
 474
 475 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 476 {
 477         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 478         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 479
 480         /* PLL output max 240 MHz (or 180 MHz per errata) */
 481         if (out_freq > 240000000)
 482                 goto fail;
 483
 484         for (i = 1; i < 256; i++) {
 485                 int diff1;
 486                 unsigned input, mul1;
 487
 488                 /*
 489                  * PLL input between 1MHz and 32MHz per spec, but lower
 490                  * frequences seem necessary in some cases so allow 100K.
 491                  */
 492                 input = main_freq / i;
 493                 if (input < 100000)
 494                         continue;
 495                 if (input > 32000000)
 496                         continue;
 497
 498                 mul1 = out_freq / input;
 499                 if (mul1 > 2048)
 500                         continue;
 501                 if (mul1 < 2)
 502                         goto fail;
 503
 504                 diff1 = out_freq - input * mul1;
 505                 if (diff1 < 0)
 506                         diff1 = -diff1;
 507                 if (diff > diff1) {
 508                         diff = diff1;
 509                         div = i;
 510                         mul = mul1;
 511                         if (diff == 0)
 512                                 break;
 513                 }
 514         }
 515         if (i == 256 && diff > (out_freq >> 5))
 516                 goto fail;
 517         return ret | ((mul - 1) << 16) | div;
 518 fail:
 519         return 0;
 520 }
 521
 522 static struct clk *const standard_pmc_clocks[] __initdata = {
 523         /* four primary clocks */
 524         &clk32k,
 525         &main_clk,
 526         &plla,
 527         &pllb,
 528
 529         /* PLLB children (USB) */
 530         &udpck,
 531         &uhpck,
 532
 533         /* MCK */
 534         &mck
 535 };
 536
 537 int __init at91_clock_init(unsigned long main_clock)
 538 {
 539         unsigned tmp, freq, mckr;
 540         int i;
 541
 542         /*
 543          * When the bootloader initialized the main oscillator correctly,
 544          * there's no problem using the cycle counter.  But if it didn't,
 545          * or when using oscillator bypass mode, we must be told the speed
 546          * of the main clock.
 547          */
 548         if (!main_clock) {
 549                 do {
 550                         tmp = at91_sys_read(AT91_CKGR_MCFR);
 551                 } while (!(tmp & AT91_PMC_MAINRDY));
 552                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 553         }
 554         main_clk.rate_hz = main_clock;
 555
 556         /* report if PLLA is more than mildly overclocked */
 557         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
 558         if (plla.rate_hz > 209000000)
 559                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 560
 561         /*
 562          * USB clock init:  choose 48 MHz PLLB value,
 563          * disable 48MHz clock during usb peripheral suspend.
 564          *
 565          * REVISIT:  assumes MCK doesn't derive from PLLB!
 566          */
 567         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
 568         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 569         if (cpu_is_at91rm9200()) {
 570                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
 571                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
 572                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
 573         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
 574                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 575                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 576         } else if (cpu_is_at91cap9()) {
 577                 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
 578         }
 579         at91_sys_write(AT91_CKGR_PLLBR, 0);
 580
 581         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 582         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 583
 584         /*
 585          * MCK and CPU derive from one of those primary clocks.
 586          * For now, assume this parentage won't change.
 587          */
 588         mckr = at91_sys_read(AT91_PMC_MCKR);
 589         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
 590         freq = mck.parent->rate_hz;
 591         freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
 592         if (cpu_is_at91rm9200())
 593                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 594         else
 595                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 596
 597         /* Register the PMC's standard clocks */
 598         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
 599                 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
 600
 601         /* MCK and CPU clock are "always on" */
 602         clk_enable(&mck);
 603
 604         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 605                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 606                 (unsigned) main_clock / 1000000,
 607                 ((unsigned) main_clock % 1000000) / 1000);
 608
 609         return 0;
 610 }
 611
 612 /*
 613  * Several unused clocks may be active.  Turn them off.
 614  */
 615 static int __init at91_clock_reset(void)
 616 {
 617         unsigned long pcdr = 0;
 618         unsigned long scdr = 0;
 619         struct clk *clk;
 620
 621         list_for_each_entry(clk, &clocks, node) {
 622                 if (clk->users > 0)
 623                         continue;
 624
 625                 if (clk->mode == pmc_periph_mode)
 626                         pcdr |= clk->pmc_mask;
 627
 628                 if (clk->mode == pmc_sys_mode)
 629                         scdr |= clk->pmc_mask;
 630
 631                 pr_debug("Clocks: disable unused %s\n", clk->name);
 632         }
 633
 634         at91_sys_write(AT91_PMC_PCDR, pcdr);
 635         at91_sys_write(AT91_PMC_SCDR, scdr);
 636
 637         return 0;
 638 }
 639 late_initcall(at91_clock_reset);