| blob | 826f3adde5d8a4ac0df29265d88cadd1ab541d05 |
1 /*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
22 /*
23 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
24 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
25 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
26 *
27 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
28 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
29 * by BIOS init).
30 *
31 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
32 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
33 * can be used with gadget ether.
34 */
36 /* debug control */
37 /* #define UDC_VERBOSE */
39 /* Driver strings */
43 /* system */
44 #include <linux/module.h>
45 #include <linux/pci.h>
46 #include <linux/kernel.h>
47 #include <linux/delay.h>
48 #include <linux/ioport.h>
49 #include <linux/sched.h>
50 #include <linux/slab.h>
51 #include <linux/smp_lock.h>
52 #include <linux/errno.h>
53 #include <linux/init.h>
54 #include <linux/timer.h>
55 #include <linux/list.h>
56 #include <linux/interrupt.h>
57 #include <linux/ioctl.h>
58 #include <linux/fs.h>
59 #include <linux/dmapool.h>
60 #include <linux/moduleparam.h>
61 #include <linux/device.h>
62 #include <linux/io.h>
63 #include <linux/irq.h>
65 #include <asm/byteorder.h>
66 #include <asm/system.h>
67 #include <asm/unaligned.h>
69 /* gadget stack */
70 #include <linux/usb/ch9.h>
71 #include <linux/usb/gadget.h>
73 /* udc specific */
92 /* description */
96 /* structure to hold endpoint function pointers */
99 /* received setup data */
102 /* pointer to device object */
105 /* irq spin lock for soft reset */
107 /* stall spin lock */
110 /*
111 * slave mode: pending bytes in rx fifo after nyet,
112 * used if EPIN irq came but no req was available
113 */
116 /* count soft resets after suspend to avoid loop */
120 /* timer */
124 /* set_rde -- Is used to control enabling of RX DMA. Problem is
125 * that UDC has only one bit (RDE) to enable/disable RX DMA for
126 * all OUT endpoints. So we have to handle race conditions like
127 * when OUT data reaches the fifo but no request was queued yet.
128 * This cannot be solved by letting the RX DMA disabled until a
129 * request gets queued because there may be other OUT packets
130 * in the FIFO (important for not blocking control traffic).
131 * The value of set_rde controls the correspondig timer.
132 *
133 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
134 * set_rde 0 == do not touch RDE, do no start the RDE timer
135 * set_rde 1 == timer function will look whether FIFO has data
136 * set_rde 2 == set by timer function to enable RX DMA on next call
137 */
145 /* tasklet for usb disconnect */
150 /* endpoint names used for print */
153 ep0_string,
161 };
163 /* DMA usage flag */
165 /* packet per buffer dma */
167 /* with per descr. update */
169 /* buffer fill mode */
171 /* full speed only mode */
173 /* tx buffer size for high speed */
176 /* module parameters */
187 /*---------------------------------------------------------------------------*/
188 /* Prints UDC device registers and endpoint irq registers */
190 {
211 }
215 }
218 }
220 }
222 /* Masks unused interrupts */
224 {
225 u32 tmp;
227 /* mask all dev interrupts */
238 /* mask all ep interrupts */
242 }
244 /* Enables endpoint 0 interrupts */
246 {
247 u32 tmp;
251 /* read irq mask */
253 /* enable ep0 irq's */
259 }
261 /* Enables device interrupts for SET_INTF and SET_CONFIG */
263 {
264 u32 tmp;
268 /* read irq mask */
271 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
280 }
282 /* Calculates fifo start of endpoint based on preceeding endpoints */
284 {
286 u32 tmp;
295 /* traverse ep's */
298 /* read fifo size */
302 }
303 }
305 }
307 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
311 {
318 }
321 /* Enables endpoint, is called by gadget driver */
322 static int
324 {
327 u32 tmp;
329 u8 udc_csr_epix;
334 || !desc
351 /* set traffic type */
356 /* set max packet size */
363 /* IN ep */
366 /* ep ix in UDC CSR register space */
369 /* set buffer size (tx fifo entries) */
371 /* double buffering: fifo size = 2 x max packet size */
373 tmp,
374 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
376 UDC_EPIN_BUFF_SIZE);
379 /* calc. tx fifo base addr */
382 /* flush fifo */
387 /* OUT ep */
389 /* ep ix in UDC CSR register space */
392 /* set max packet size UDC CSR */
395 UDC_CSR_NE_MAX_PKT);
399 /* alloc and init BNA dummy request */
402 }
406 }
408 /* set ep values */
410 /* max packet */
412 /* ep number */
414 /* ep direction */
416 /* ep type */
418 /* ep config */
420 /* ep interface */
422 /* ep alt */
424 /* write reg */
427 /* enable ep irq */
432 /*
433 * clear NAK by writing CNAK
434 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
435 */
442 }
448 }
450 /* Resets endpoint */
452 {
453 u32 tmp;
461 /* set NAK */
467 /* disable interrupt */
473 /* unset P and IN bit of potential former DMA */
482 /* flush the fifo */
487 }
488 /* reset desc pointer */
490 }
492 /* Disables endpoint, is called by gadget driver */
494 {
514 }
516 /* Allocates request packet, called by gadget driver */
519 {
538 /* ep0 in requests are allocated from data pool here */
544 }
550 /* prevent from using desc. - set HOST BUSY */
552 UDC_DMA_STP_STS_BS_HOST_BUSY,
553 UDC_DMA_STP_STS_BS);
558 }
561 }
563 /* Frees request packet, called by gadget driver */
564 static void
566 {
580 /* free dma chain if created */
583 }
587 }
589 }
591 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
593 {
595 /* set last bit */
597 /* set next pointer to itself */
599 /* set HOST BUSY */
602 UDC_DMA_STP_STS_BS_DMA_DONE,
603 UDC_DMA_STP_STS_BS);
604 #ifdef UDC_VERBOSE
607 #endif
608 }
609 }
611 /* Allocate BNA dummy descriptor */
613 {
617 /* alloc the dummy request */
623 }
625 }
627 /* Write data to TX fifo for IN packets */
628 static void
630 {
650 /* dwords first */
653 }
655 /* remaining bytes must be written by byte access */
659 }
661 /* dummy write confirm */
663 }
665 /* Read dwords from RX fifo for OUT transfers */
667 {
674 }
676 }
678 /* Read bytes from RX fifo for OUT transfers */
680 {
682 u32 tmp;
686 /* dwords first */
689 }
691 /* remaining bytes must be read by byte access */
697 }
698 }
701 }
703 /* Read data from RX fifo for OUT transfers */
704 static int
706 {
712 /* received number bytes */
724 }
726 }
729 /* last packet ? */
734 /* read rx fifo bytes */
739 }
741 /* create/re-init a DMA descriptor or a DMA descriptor chain */
743 {
745 u32 tmp;
751 /* set buffer pointer */
754 /* set last bit */
757 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
765 }
768 /* write tx bytes */
772 UDC_DMA_IN_STS_TXBYTES);
774 }
775 }
777 }
784 /*
785 * if bytes < max packet then tx bytes must
786 * be written in packet per buffer mode
787 */
791 /* write tx bytes */
795 UDC_DMA_IN_STS_TXBYTES);
796 /* reset frame num */
800 UDC_DMA_IN_STS_FRAMENUM);
801 }
802 /* set HOST BUSY */
805 UDC_DMA_STP_STS_BS_HOST_BUSY,
806 UDC_DMA_STP_STS_BS);
809 /* set HOST READY */
812 UDC_DMA_STP_STS_BS_HOST_READY,
813 UDC_DMA_STP_STS_BS);
816 /* clear NAK by writing CNAK */
823 }
825 }
828 }
830 /* Completes request packet ... caller MUST hold lock */
831 static void
835 {
842 /* unmap DMA */
848 PCI_DMA_TODEVICE);
849 else
853 PCI_DMA_FROMDEVICE);
856 }
861 /* set new status if pending */
865 /* remove from ep queue */
875 }
877 /* frees pci pool descriptors of a DMA chain */
879 {
888 /* do not free first desc., will be done by free for request */
898 }
901 }
903 /* Iterates to the end of a DMA chain and returns last descriptor */
905 {
911 }
915 }
917 /* Iterates to the end of a DMA chain and counts bytes received */
919 {
921 u32 count;
924 /* received number bytes */
929 /* received number bytes */
932 UDC_DMA_OUT_STS_RXBYTES);
933 }
934 }
938 }
940 /* Creates or re-inits a DMA chain */
945 )
946 {
949 dma_addr_t dma_addr;
960 /* unset L bit in first desc for OUT */
963 }
965 /* alloc only new desc's if not already available */
968 len++;
969 }
972 /* shorter chain already allocated before */
975 }
978 }
981 /* gen. required number of descriptors and buffers */
983 /* create or determine next desc. */
993 /* first td */
1000 }
1005 else
1008 /* short packet ? */
1012 /* short packet */
1014 }
1016 /* link td and assign tx bytes */
1021 /* req->td_data->next = virt_to_phys(td); */
1022 }
1023 /* write tx bytes */
1025 /* first desc */
1029 UDC_DMA_IN_STS_TXBYTES);
1030 /* second desc */
1032 txbytes,
1033 UDC_DMA_IN_STS_TXBYTES);
1034 }
1039 /* last->next = virt_to_phys(td); */
1040 }
1042 /* write tx bytes */
1044 txbytes,
1045 UDC_DMA_IN_STS_TXBYTES);
1046 }
1047 }
1049 }
1050 /* set last bit */
1053 /* last desc. points to itself */
1055 }
1058 }
1060 /* Enabling RX DMA */
1062 {
1063 u32 tmp;
1066 /* stop RDE timer */
1070 }
1071 /* set RDE */
1075 }
1077 /* Queues a request packet, called by gadget driver */
1078 static int
1080 {
1087 u32 tmp;
1089 /* check the inputs */
1106 /* map dma (usually done before) */
1114 PCI_DMA_TODEVICE);
1115 else
1119 PCI_DMA_FROMDEVICE);
1121 }
1132 /* on empty queue just do first transfer */
1134 /* zlp */
1136 /* IN zlp's are handled by hardware */
1139 /*
1140 * if set_config or set_intf is waiting for ack by zlp
1141 * then set CSR_DONE
1142 */
1148 }
1149 /* setup command is ACK'ed now by zlp */
1151 /* clear NAK by writing CNAK in EP0_IN */
1157 UDC_EP0IN_IX);
1159 }
1161 }
1166 /* write desc pointer to enable DMA */
1168 /* set HOST READY */
1171 UDC_DMA_IN_STS_BS_HOST_READY,
1172 UDC_DMA_IN_STS_BS);
1173 }
1175 /* disabled rx dma while descriptor update */
1177 /* stop RDE timer */
1181 }
1182 /* clear RDE */
1188 /*
1189 * if BNA occurred then let BNA dummy desc.
1190 * point to current desc.
1191 */
1197 }
1198 }
1199 /* write desc pointer */
1202 /* clear NAK by writing CNAK */
1209 }
1212 /* enable ep irq */
1216 }
1217 }
1221 /*
1222 * prep_dma not used for OUT ep's, this is not possible
1223 * for PPB modes, because of chain creation reasons
1224 */
1229 }
1230 }
1232 /* add request to ep queue */
1237 /* open rxfifo if out data queued */
1239 /* enable DMA */
1244 }
1245 /* stop OUT naking */
1250 /*
1251 * read pending bytes afer nyet:
1252 * referring to isr
1253 */
1255 /* finish */
1257 }
1260 }
1261 }
1262 }
1264 finished:
1267 }
1269 /* Empty request queue of an endpoint; caller holds spinlock */
1271 {
1278 queue);
1280 }
1281 }
1283 /* Dequeues a request packet, called by gadget driver */
1285 {
1301 /* request in processing or next one */
1307 u32 tmp;
1308 u32 dma_sts;
1309 /* stop potential receive DMA */
1313 /*
1314 * Cancel transfer later in ISR
1315 * if descriptor was touched.
1316 */
1318 UDC_DMA_OUT_STS_BS);
1325 }
1327 }
1328 }
1329 }
1335 }
1337 /* Halt or clear halt of endpoint */
1338 static int
1340 {
1342 u32 tmp;
1358 /* halt or clear halt */
1363 /*
1364 * set STALL
1365 * rxfifo empty not taken into acount
1366 */
1372 /* setup poll timer */
1375 HZ * UDC_POLLSTALL_TIMER_USECONDS
1380 }
1381 }
1382 }
1384 /* ep is halted by set_halt() before */
1387 /* clear stall bit */
1389 /* clear NAK by writing CNAK */
1394 }
1395 }
1398 }
1400 /* gadget interface */
1412 /* fifo ops not implemented */
1413 };
1415 /*-------------------------------------------------------------------------*/
1417 /* Get frame counter (not implemented) */
1419 {
1421 }
1423 /* Remote wakeup gadget interface */
1425 {
1434 }
1436 /* gadget operations */
1440 };
1442 /* Setups endpoint parameters, adds endpoints to linked list */
1444 {
1445 /* make gadget ep lists */
1454 /* fifo config */
1461 }
1463 /* init registers at driver load time */
1465 {
1466 u32 tmp;
1468 /* init controller by soft reset */
1471 /* mask not needed interrupts */
1474 /* put into initial config */
1476 /* link up all endpoints */
1479 /* program speed */
1485 }
1489 }
1491 /* Inits UDC context */
1493 {
1494 u32 tmp;
1500 /* stop RDE timer */
1504 }
1505 /* stop poll stall timer */
1508 }
1509 /* disable DMA */
1515 /* enable dynamic CSR programming */
1518 /* set self powered */
1520 /* set remote wakeupable */
1528 }
1530 /* Sets initial endpoint parameters */
1532 {
1534 u32 tmp;
1535 u32 reg;
1539 /* read enum speed */
1546 }
1548 /* set basic ep parameters */
1554 /* txfifo size is calculated at enable time */
1557 /* fifo size */
1565 }
1567 /*
1568 * ep will be reset only if ep was not enabled before to avoid
1569 * disabling ep interrupts when ENUM interrupt occurs but ep is
1570 * not enabled by gadget driver
1571 */
1574 }
1577 /*
1578 * ep->dma is not really used, just to indicate that
1579 * DMA is active: remove this
1580 * dma regs = dev control regs
1581 */
1584 /* nak OUT endpoints until enable - not for ep0 */
1587 /* set NAK */
1593 }
1594 }
1595 }
1596 /* EP0 max packet */
1600 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1604 }
1606 /*
1607 * with suspend bug workaround, ep0 params for gadget driver
1608 * are set at gadget driver bind() call
1609 */
1614 /* init cfg/alt/int */
1618 }
1620 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1622 {
1628 /* put into initial config */
1631 /* enable device setup interrupts */
1633 }
1635 /*
1636 * Calls gadget with disconnect event and resets the UDC and makes
1637 * initial bringup to be ready for ep0 events
1638 */
1640 {
1646 /* mask interrupts */
1649 /* REVISIT there doesn't seem to be a point to having this
1650 * talk to a tasklet ... do it directly, we already hold
1651 * the spinlock needed to process the disconnect.
1652 */
1655 }
1657 /* Tasklet for disconnect to be outside of interrupt context */
1659 {
1661 u32 tmp;
1671 /* empty queues */
1674 }
1676 }
1678 /* disable ep0 */
1684 /* init controller by soft reset */
1686 soft_reset_occured++;
1687 }
1689 /* re-enable dev interrupts */
1691 /* back to full speed ? */
1696 }
1699 }
1701 /* Reset the UDC core */
1703 {
1707 /*
1708 * reset possible waiting interrupts, because int.
1709 * status is lost after soft reset,
1710 * ep int. status reset
1711 */
1713 /* device int. status reset */
1721 }
1723 /* RDE timer callback to set RDE bit */
1725 {
1726 u32 tmp;
1731 /*
1732 * open the fifo if fifo was filled on last timer call
1733 * conditionally
1734 */
1736 /* set RDE to receive setup data */
1743 /*
1744 * if fifo empty setup polling, do not just
1745 * open the fifo
1746 */
1750 }
1752 /*
1753 * fifo contains data now, setup timer for opening
1754 * the fifo when timer expires to be able to receive
1755 * setup packets, when data packets gets queued by
1756 * gadget layer then timer will forced to expire with
1757 * set_rde=0 (RDE is set in udc_queue())
1758 */
1759 set_rde++;
1760 /* debug: lhadmot_timer_start = 221070 */
1764 }
1765 }
1773 }
1775 /* Handle halt state, used in stall poll timer */
1777 {
1778 u32 tmp;
1779 /* set stall as long not halted */
1782 /* STALL cleared ? */
1784 /*
1785 * FIXME: MSC spec requires that stall remains
1786 * even on receivng of CLEAR_FEATURE HALT. So
1787 * we would set STALL again here to be compliant.
1788 * But with current mass storage drivers this does
1789 * not work (would produce endless host retries).
1790 * So we clear halt on CLEAR_FEATURE.
1791 *
1792 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1793 tmp |= AMD_BIT(UDC_EPCTL_S);
1794 writel(tmp, &ep->regs->ctl);*/
1796 /* clear NAK by writing CNAK */
1801 }
1802 }
1803 }
1805 /* Stall timer callback to poll S bit and set it again after */
1807 {
1812 /*
1813 * only one IN and OUT endpoints are handled
1814 * IN poll stall
1815 */
1820 /* OUT poll stall */
1826 /* setup timer again when still halted */
1829 HZ * UDC_POLLSTALL_TIMER_USECONDS
1832 }
1837 }
1839 /* Inits endpoint 0 so that SETUP packets are processed */
1841 {
1842 u32 tmp;
1846 /* flush fifo */
1851 /* set ep0 directions */
1855 /* set buffer size (tx fifo entries) of EP0_IN */
1859 UDC_EPIN_BUFF_SIZE);
1862 UDC_EPIN_BUFF_SIZE);
1865 /* set max packet size of EP0_IN */
1869 UDC_EP_MAX_PKT_SIZE);
1872 UDC_EP_MAX_PKT_SIZE);
1875 /* set max packet size of EP0_OUT */
1879 UDC_EP_MAX_PKT_SIZE);
1882 UDC_EP_MAX_PKT_SIZE);
1885 /* set max packet size of EP0 in UDC CSR */
1889 UDC_CSR_NE_MAX_PKT);
1892 UDC_CSR_NE_MAX_PKT);
1898 /* write dma desc address */
1903 /* stop RDE timer */
1907 }
1908 /* stop pollstall timer */
1911 }
1912 /* enable DMA */
1921 }
1923 }
1925 /* clear NAK by writing CNAK for EP0IN */
1932 /* clear NAK by writing CNAK for EP0OUT */
1938 }
1940 /* Make endpoint 0 ready for control traffic */
1942 {
1944 /* enable ep0 interrupts */
1946 /* enable device setup interrupts */
1950 }
1952 /* Called by gadget driver to register itself */
1954 {
1957 u32 tmp;
1973 /* Some gadget drivers use both ep0 directions.
1974 * NOTE: to gadget driver, ep0 is just one endpoint...
1975 */
1985 }
1987 /* get ready for ep0 traffic */
1990 /* clear SD */
1998 }
2001 /* shutdown requests and disconnect from gadget */
2002 static void
2006 {
2009 /* empty queues and init hardware */
2013 }
2019 }
2020 /* init */
2022 }
2024 /* Called by gadget driver to unregister itself */
2026 {
2029 u32 tmp;
2045 /* set SD */
2054 }
2058 /* Clear pending NAK bits */
2060 {
2061 u32 tmp;
2062 u32 reg;
2064 /* check epin's */
2069 /* clear NAK by writing CNAK */
2075 }
2076 }
2077 /* ... and ep0out */
2080 /* clear NAK by writing CNAK */
2087 }
2088 }
2090 /* Enabling RX DMA after setup packet */
2092 {
2094 /*
2095 * only enable RXDMA when no data endpoint enabled
2096 * or data is queued
2097 */
2101 /*
2102 * setup timer for enabling RDE (to not enable
2103 * RXFIFO DMA for data endpoints to early)
2104 */
2111 }
2112 }
2113 }
2114 }
2115 }
2118 /* Interrupt handler for data OUT traffic */
2120 {
2122 u32 tmp;
2134 /* BNA event ? */
2138 /* clear BNA */
2142 else
2146 }
2147 }
2148 /* HE event ? */
2152 /* clear HE */
2156 }
2160 /* next request */
2166 }
2168 /* fifo mode */
2171 /* read fifo */
2175 /* finish */
2177 /* next request */
2183 }
2185 /* DMA */
2189 /* check for DMA done */
2192 UDC_DMA_OUT_STS_BS);
2193 /* packet per buffer mode - rx bytes */
2195 /*
2196 * if BNA occurred then recover desc. from
2197 * BNA dummy desc.
2198 */
2205 }
2208 }
2210 /* buffer fill mode - rx bytes */
2212 /* received number bytes */
2214 UDC_DMA_OUT_STS_RXBYTES);
2216 /* packet per buffer mode - rx bytes */
2220 /* received number bytes */
2222 /* every desc. counts bytes */
2225 /* last desc. counts bytes */
2227 UDC_DMA_OUT_STS_RXBYTES);
2230 /*
2231 * on 64k packets the RXBYTES
2232 * field is zero
2233 */
2235 }
2236 }
2238 }
2246 }
2248 }
2251 /* complete request */
2254 /* next request */
2258 queue);
2259 /*
2260 * DMA may be already started by udc_queue()
2261 * called by gadget drivers completion
2262 * routine. This happens when queue
2263 * holds one request only.
2264 */
2266 /* next dma */
2269 /* write desc pointer */
2273 /* enable DMA */
2275 }
2277 /*
2278 * implant BNA dummy descriptor to allow
2279 * RXFIFO opening by RDE
2280 */
2282 /* write desc pointer */
2286 }
2288 /*
2289 * schedule timer for setting RDE if queue
2290 * remains empty to allow ep0 packets pass
2291 * through
2292 */
2296 jiffies
2301 }
2302 }
2305 }
2308 /*
2309 * RX DMA must be reenabled for each desc in PPBDU mode
2310 * and must be enabled for PPBNDU mode in case of BNA
2311 */
2313 }
2318 }
2320 /* check pending CNAKS */
2322 /* CNAk processing when rxfifo empty only */
2325 }
2326 }
2328 /* clear OUT bits in ep status */
2330 finished:
2332 }
2334 /* Interrupt handler for data IN traffic */
2336 {
2338 u32 tmp;
2339 u32 epsts;
2350 /* BNA ? */
2357 /* clear BNA */
2361 }
2362 }
2363 /* HE event ? */
2369 /* clear HE */
2373 }
2375 /* DMA completion */
2383 /*
2384 * length bytes transfered
2385 * check dma done of last desc. in PPBDU mode
2386 */
2390 dma_done =
2392 UDC_DMA_IN_STS_BS);
2393 /* don't care DMA done */
2396 }
2398 /* assume all bytes transferred */
2400 }
2403 /* complete req */
2406 /* further request available ? */
2408 /* disable interrupt */
2414 }
2416 }
2417 }
2418 }
2421 }
2422 /*
2423 * status reg has IN bit set and TDC not set (if TDC was handled,
2424 * IN must not be handled (UDC defect) ?
2425 */
2430 /* next request */
2433 /* FIFO mode */
2435 /* write fifo */
2443 /* complete req */
2445 }
2446 /* DMA */
2454 /*
2455 * unset L bit of first desc.
2456 * for chain
2457 */
2462 UDC_DMA_IN_STS_L);
2463 }
2465 /* write desc pointer */
2468 /* set HOST READY */
2472 UDC_DMA_IN_STS_BS_HOST_READY,
2473 UDC_DMA_IN_STS_BS);
2475 /* set poll demand bit */
2479 }
2480 }
2482 }
2483 }
2484 /* clear status bits */
2487 finished:
2490 }
2492 /* Interrupt handler for Control OUT traffic */
2496 {
2498 u32 tmp;
2500 u32 count;
2507 /* clear irq */
2511 /* check BNA and clear if set */
2519 }
2521 /* type of data: SETUP or DATA 0 bytes */
2525 /* setup data */
2532 /* set NAK for EP0_IN */
2537 /* get setup data */
2540 /* clear OUT bits in ep status */
2548 /* set HOST READY */
2550 UDC_DMA_STP_STS_BS_HOST_READY;
2552 /* read fifo */
2554 }
2556 /* determine direction of control data */
2559 /* enable RDE */
2564 /*
2565 * implant BNA dummy descriptor to allow RXFIFO opening
2566 * by RDE
2567 */
2569 /* write desc pointer */
2573 }
2577 /*
2578 * setup timer for enabling RDE (to not enable
2579 * RXFIFO DMA for data to early)
2580 */
2587 }
2588 }
2589 }
2591 /*
2592 * mass storage reset must be processed here because
2593 * next packet may be a CLEAR_FEATURE HALT which would not
2594 * clear the stall bit when no STALL handshake was received
2595 * before (autostall can cause this)
2596 */
2600 /*
2601 * clear stall bits
2602 * only one IN and OUT endpoints are handled
2603 */
2608 }
2610 /* call gadget with setup data received */
2617 /* ep0 in returns data (not zlp) on IN phase */
2619 UDC_EP0IN_MAXPACKET) {
2620 /* clear NAK by writing CNAK in EP0_IN */
2626 /* if unsupported request then stall */
2634 /* clear NAK by writing CNAK in EP0_OUT */
2641 }
2644 /* clear OUT bits in ep status */
2647 }
2649 /* data packet 0 bytes */
2651 /* clear OUT bits in ep status */
2654 /* get setup data: only 0 packet */
2656 /* no req if 0 packet, just reactivate */
2660 /* set HOST READY */
2664 UDC_DMA_OUT_STS_BS_HOST_READY,
2665 UDC_DMA_OUT_STS_BS);
2666 /* enable RDE */
2671 /* control write */
2673 /* re-program desc. pointer for possible ZLPs */
2676 /* enable RDE */
2678 }
2681 /* received number bytes */
2684 /* out data for fifo mode not working */
2687 /* 0 packet or real data ? */
2691 /* dummy read confirm */
2694 }
2695 }
2696 }
2698 /* check pending CNAKS */
2700 /* CNAk processing when rxfifo empty only */
2703 }
2704 }
2706 finished:
2708 }
2710 /* Interrupt handler for Control IN traffic */
2712 {
2714 u32 tmp;
2721 /* clear irq */
2725 /* DMA completion */
2730 /* clear TDC bit */
2734 /* status reg has IN bit set ? */
2739 /* clear IN bit */
2742 }
2745 /* halt ep0in */
2751 /* next request */
2756 /* write desc pointer */
2758 /* set HOST READY */
2762 UDC_DMA_STP_STS_BS_HOST_READY,
2763 UDC_DMA_STP_STS_BS);
2765 /* set poll demand bit */
2766 tmp =
2772 /* all bytes will be transferred */
2775 /* complete req */
2779 /* write fifo */
2782 /* lengh bytes transfered */
2790 /* complete req */
2792 }
2793 }
2795 }
2796 }
2800 /* clear IN bit */
2803 }
2804 }
2807 }
2810 /* Interrupt handler for global device events */
2814 {
2816 u32 tmp;
2817 u32 cfg;
2819 u16 i;
2820 u8 udc_csr_epix;
2822 /* SET_CONFIG irq ? */
2826 /* read config value */
2833 /* make usb request for gadget driver */
2838 /* programm the NE registers */
2843 /* ep ix in UDC CSR register space */
2847 /* OUT ep */
2849 /* ep ix in UDC CSR register space */
2851 }
2854 /* ep cfg */
2856 UDC_CSR_NE_CFG);
2857 /* write reg */
2860 /* clear stall bits */
2865 }
2866 /* call gadget zero with setup data received */
2876 /* read interface and alt setting values */
2881 /* make usb request for gadget driver */
2891 /* programm the NE registers */
2896 /* ep ix in UDC CSR register space */
2900 /* OUT ep */
2902 /* ep ix in UDC CSR register space */
2904 }
2906 /* UDC CSR reg */
2907 /* set ep values */
2909 /* ep interface */
2911 UDC_CSR_NE_INTF);
2912 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2913 /* ep alt */
2915 UDC_CSR_NE_ALT);
2916 /* write reg */
2919 /* clear stall bits */
2924 }
2926 /* call gadget zero with setup data received */
2936 /* allow soft reset when suspend occurs */
2942 /* mask not needed interrupts */
2945 /* call gadget to resume and reset configs etc. */
2950 }
2954 /* disable ep0 to empty req queue */
2958 /* soft reset when rxfifo not empty */
2963 soft_reset_after_usbreset_occured++;
2964 }
2966 /*
2967 * DMA reset to kill potential old DMA hw hang,
2968 * POLL bit is already reset by ep_init() through
2969 * disconnect()
2970 */
2976 /* put into initial config */
2979 /* enable device setup interrupts */
2982 /* enable suspend interrupt */
2996 }
3003 /* disable ep0 to empty req queue */
3007 /* link up all endpoints */
3015 }
3017 /* init ep 0 */
3020 /* enable ep0 interrupts */
3022 }
3023 /* session valid change interrupt */
3028 /* check that session is not valid to detect disconnect */
3031 /* disable suspend interrupt */
3036 /* cleanup on disconnect */
3038 }
3040 }
3043 }
3045 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3047 {
3049 u32 reg;
3050 u16 i;
3051 u32 ep_irq;
3056 /* check for ep irq */
3064 /*
3065 * data endpoint
3066 * iterate ep's
3067 */
3073 /* clear irq status */
3076 /* irq for out ep ? */
3079 else
3081 }
3083 }
3086 /* check for dev irq */
3089 /* clear irq */
3092 }
3097 }
3099 /* Tears down device */
3101 {
3104 }
3106 /* Cleanup on device remove */
3108 {
3109 /* remove timer */
3110 stop_timer++;
3115 /* remove pollstall timer */
3116 stop_pollstall_timer++;
3122 }
3124 /* Reset all pci context */
3126 {
3131 /* gadget driver must not be registered */
3134 /* dma pool cleanup */
3139 /* cleanup DMA desc's for ep0in */
3148 }
3150 /* reset controller */
3166 }
3168 /* create dma pools on init */
3170 {
3175 /* consistent DMA mode setting ? */
3181 }
3183 /* DMA setup */
3190 }
3192 /* EP0 in dma regs = dev control regs */
3195 /* dma desc for setup data */
3202 }
3203 /* setup */
3209 }
3212 /* data: 0 packets !? */
3218 }
3222 finished:
3224 }
3226 /* Called by pci bus driver to init pci context */
3230 )
3231 {
3237 /* one udc only */
3241 }
3243 /* init */
3248 }
3250 /* pci setup */
3256 }
3259 /* PCI resource allocation */
3269 }
3279 }
3287 }
3295 }
3300 /* chip revision for Hs AMD5536 */
3306 /* init dma pools */
3311 }
3319 /* general probing */
3323 finished:
3327 }
3329 /* general probe */
3331 {
3333 u32 reg;
3336 /* mark timer as not initialized */
3340 /* device struct setup */
3350 /* udc csr registers base */
3352 /* dev registers base */
3354 /* ep registers base */
3356 /* fifo's base */
3360 /* init registers, interrupts, ... */
3375 }
3384 /* timer init */
3388 /* timer pollstall init */
3393 /* set SD */
3398 /* print dev register info */
3403 finished:
3405 }
3407 /* Initiates a remote wakeup */
3409 {
3411 u32 tmp;
3425 }
3427 /* PCI device parameters */
3429 {
3433 },
3434 {},
3435 };
3438 /* PCI functions */
3444 };
3446 /* Inits driver */
3448 {
3450 }
3453 /* Cleans driver */
3455 {
3457 }