2 * drivers/ata/sata_fsl.c
4 * Freescale 3.0Gbps SATA device driver
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #include <scsi/scsi_host.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <linux/libata.h>
26 #include <linux/of_platform.h>
28 /* Controller information */
30 SATA_FSL_QUEUE_DEPTH
= 16,
31 SATA_FSL_MAX_PRD
= 63,
32 SATA_FSL_MAX_PRD_USABLE
= SATA_FSL_MAX_PRD
- 1,
33 SATA_FSL_MAX_PRD_DIRECT
= 16, /* Direct PRDT entries */
35 SATA_FSL_HOST_FLAGS
= (ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
36 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
38 SATA_FSL_HOST_LFLAGS
= ATA_LFLAG_SKIP_D2H_BSY
,
40 SATA_FSL_MAX_CMDS
= SATA_FSL_QUEUE_DEPTH
,
41 SATA_FSL_CMD_HDR_SIZE
= 16, /* 4 DWORDS */
42 SATA_FSL_CMD_SLOT_SIZE
= (SATA_FSL_MAX_CMDS
* SATA_FSL_CMD_HDR_SIZE
),
45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
46 * chained indirect PRDEs upto a max count of 63.
47 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
48 * be setup as an indirect descriptor, pointing to it's next
49 * (contigious) PRDE. Though chained indirect PRDE arrays are
50 * supported,it will be more efficient to use a direct PRDT and
51 * a single chain/link to indirect PRDE array/PRDT.
54 SATA_FSL_CMD_DESC_CFIS_SZ
= 32,
55 SATA_FSL_CMD_DESC_SFIS_SZ
= 32,
56 SATA_FSL_CMD_DESC_ACMD_SZ
= 16,
57 SATA_FSL_CMD_DESC_RSRVD
= 16,
59 SATA_FSL_CMD_DESC_SIZE
= (SATA_FSL_CMD_DESC_CFIS_SZ
+
60 SATA_FSL_CMD_DESC_SFIS_SZ
+
61 SATA_FSL_CMD_DESC_ACMD_SZ
+
62 SATA_FSL_CMD_DESC_RSRVD
+
63 SATA_FSL_MAX_PRD
* 16),
65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
=
66 (SATA_FSL_CMD_DESC_CFIS_SZ
+
67 SATA_FSL_CMD_DESC_SFIS_SZ
+
68 SATA_FSL_CMD_DESC_ACMD_SZ
+
69 SATA_FSL_CMD_DESC_RSRVD
),
71 SATA_FSL_CMD_DESC_AR_SZ
= (SATA_FSL_CMD_DESC_SIZE
* SATA_FSL_MAX_CMDS
),
72 SATA_FSL_PORT_PRIV_DMA_SZ
= (SATA_FSL_CMD_SLOT_SIZE
+
73 SATA_FSL_CMD_DESC_AR_SZ
),
76 * MPC8315 has two SATA controllers, SATA1 & SATA2
77 * (one port per controller)
78 * MPC837x has 2/4 controllers, one port per controller
81 SATA_FSL_MAX_PORTS
= 1,
83 SATA_FSL_IRQ_FLAG
= IRQF_SHARED
,
87 * Host Controller command register set - per port
103 * Host Status Register (HStatus) bitdefs
106 GOING_OFFLINE
= (1 << 30),
107 BIST_ERR
= (1 << 29),
109 FATAL_ERR_HC_MASTER_ERR
= (1 << 18),
110 FATAL_ERR_PARITY_ERR_TX
= (1 << 17),
111 FATAL_ERR_PARITY_ERR_RX
= (1 << 16),
112 FATAL_ERR_DATA_UNDERRUN
= (1 << 13),
113 FATAL_ERR_DATA_OVERRUN
= (1 << 12),
114 FATAL_ERR_CRC_ERR_TX
= (1 << 11),
115 FATAL_ERR_CRC_ERR_RX
= (1 << 10),
116 FATAL_ERR_FIFO_OVRFL_TX
= (1 << 9),
117 FATAL_ERR_FIFO_OVRFL_RX
= (1 << 8),
119 FATAL_ERROR_DECODE
= FATAL_ERR_HC_MASTER_ERR
|
120 FATAL_ERR_PARITY_ERR_TX
|
121 FATAL_ERR_PARITY_ERR_RX
|
122 FATAL_ERR_DATA_UNDERRUN
|
123 FATAL_ERR_DATA_OVERRUN
|
124 FATAL_ERR_CRC_ERR_TX
|
125 FATAL_ERR_CRC_ERR_RX
|
126 FATAL_ERR_FIFO_OVRFL_TX
| FATAL_ERR_FIFO_OVRFL_RX
,
128 INT_ON_FATAL_ERR
= (1 << 5),
129 INT_ON_PHYRDY_CHG
= (1 << 4),
131 INT_ON_SIGNATURE_UPDATE
= (1 << 3),
132 INT_ON_SNOTIFY_UPDATE
= (1 << 2),
133 INT_ON_SINGL_DEVICE_ERR
= (1 << 1),
134 INT_ON_CMD_COMPLETE
= 1,
136 INT_ON_ERROR
= INT_ON_FATAL_ERR
|
137 INT_ON_PHYRDY_CHG
| INT_ON_SINGL_DEVICE_ERR
,
140 * Host Control Register (HControl) bitdefs
142 HCONTROL_ONLINE_PHY_RST
= (1 << 31),
143 HCONTROL_FORCE_OFFLINE
= (1 << 30),
144 HCONTROL_PARITY_PROT_MOD
= (1 << 14),
145 HCONTROL_DPATH_PARITY
= (1 << 12),
146 HCONTROL_SNOOP_ENABLE
= (1 << 10),
147 HCONTROL_PMP_ATTACHED
= (1 << 9),
148 HCONTROL_COPYOUT_STATFIS
= (1 << 8),
149 IE_ON_FATAL_ERR
= (1 << 5),
150 IE_ON_PHYRDY_CHG
= (1 << 4),
151 IE_ON_SIGNATURE_UPDATE
= (1 << 3),
152 IE_ON_SNOTIFY_UPDATE
= (1 << 2),
153 IE_ON_SINGL_DEVICE_ERR
= (1 << 1),
154 IE_ON_CMD_COMPLETE
= 1,
156 DEFAULT_PORT_IRQ_ENABLE_MASK
= IE_ON_FATAL_ERR
| IE_ON_PHYRDY_CHG
|
157 IE_ON_SIGNATURE_UPDATE
|
158 IE_ON_SINGL_DEVICE_ERR
| IE_ON_CMD_COMPLETE
,
160 EXT_INDIRECT_SEG_PRD_FLAG
= (1 << 31),
161 DATA_SNOOP_ENABLE
= (1 << 22),
165 * SATA Superset Registers
175 * Control Status Register Set
189 /* PHY (link-layer) configuration control */
191 PHY_BIST_ENABLE
= 0x01,
195 * Command Header Table entry, i.e, command slot
196 * 4 Dwords per command slot, command header size == 64 Dwords.
198 struct cmdhdr_tbl_entry
{
206 * Description information bitdefs
209 VENDOR_SPECIFIC_BIST
= (1 << 10),
210 CMD_DESC_SNOOP_ENABLE
= (1 << 9),
211 FPDMA_QUEUED_CMD
= (1 << 8),
214 ATAPI_CMD
= (1 << 5),
220 struct command_desc
{
225 u32 prdt
[SATA_FSL_MAX_PRD_DIRECT
* 4];
226 u32 prdt_indirect
[(SATA_FSL_MAX_PRD
- SATA_FSL_MAX_PRD_DIRECT
) * 4];
230 * Physical region table descriptor(PRD)
240 * ata_port private data
241 * This is our per-port instance data.
243 struct sata_fsl_port_priv
{
244 struct cmdhdr_tbl_entry
*cmdslot
;
245 dma_addr_t cmdslot_paddr
;
246 struct command_desc
*cmdentry
;
247 dma_addr_t cmdentry_paddr
;
250 * SATA FSL controller has a Status FIS which should contain the
251 * received D2H FIS & taskfile registers. This SFIS is present in
252 * the command descriptor, and to have a ready reference to it,
253 * we are caching it here, quite similar to what is done in H/W on
254 * AHCI compliant devices by copying taskfile fields to a 32-bit
258 struct ata_taskfile tf
;
262 * ata_port->host_set private data
264 struct sata_fsl_host_priv
{
265 void __iomem
*hcr_base
;
266 void __iomem
*ssr_base
;
267 void __iomem
*csr_base
;
271 static inline unsigned int sata_fsl_tag(unsigned int tag
,
272 void __iomem
* hcr_base
)
274 /* We let libATA core do actual (queue) tag allocation */
276 /* all non NCQ/queued commands should have tag#0 */
277 if (ata_tag_internal(tag
)) {
278 DPRINTK("mapping internal cmds to tag#0\n");
282 if (unlikely(tag
>= SATA_FSL_QUEUE_DEPTH
)) {
283 DPRINTK("tag %d invalid : out of range\n", tag
);
287 if (unlikely((ioread32(hcr_base
+ CQ
)) & (1 << tag
))) {
288 DPRINTK("tag %d invalid : in use!!\n", tag
);
295 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv
*pp
,
296 unsigned int tag
, u32 desc_info
,
297 u32 data_xfer_len
, u8 num_prde
,
300 dma_addr_t cmd_descriptor_address
;
302 cmd_descriptor_address
= pp
->cmdentry_paddr
+
303 tag
* SATA_FSL_CMD_DESC_SIZE
;
305 /* NOTE: both data_xfer_len & fis_len are Dword counts */
307 pp
->cmdslot
[tag
].cda
= cpu_to_le32(cmd_descriptor_address
);
308 pp
->cmdslot
[tag
].prde_fis_len
=
309 cpu_to_le32((num_prde
<< 16) | (fis_len
<< 2));
310 pp
->cmdslot
[tag
].ttl
= cpu_to_le32(data_xfer_len
& ~0x03);
311 pp
->cmdslot
[tag
].desc_info
= cpu_to_le32((desc_info
| (tag
& 0x1F)));
313 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
314 pp
->cmdslot
[tag
].cda
,
315 pp
->cmdslot
[tag
].prde_fis_len
,
316 pp
->cmdslot
[tag
].ttl
, pp
->cmdslot
[tag
].desc_info
);
320 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_desc
,
321 u32
* ttl
, dma_addr_t cmd_desc_paddr
)
323 struct scatterlist
*sg
;
324 unsigned int num_prde
= 0;
328 * NOTE : direct & indirect prdt's are contigiously allocated
330 struct prde
*prd
= (struct prde
*)&((struct command_desc
*)
333 struct prde
*prd_ptr_to_indirect_ext
= NULL
;
334 unsigned indirect_ext_segment_sz
= 0;
335 dma_addr_t indirect_ext_segment_paddr
;
337 VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc
, prd
);
339 indirect_ext_segment_paddr
= cmd_desc_paddr
+
340 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT
+ SATA_FSL_MAX_PRD_DIRECT
* 16;
342 ata_for_each_sg(sg
, qc
) {
343 dma_addr_t sg_addr
= sg_dma_address(sg
);
344 u32 sg_len
= sg_dma_len(sg
);
346 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
349 /* warn if each s/g element is not dword aligned */
351 ata_port_printk(qc
->ap
, KERN_ERR
,
352 "s/g addr unaligned : 0x%x\n", sg_addr
);
354 ata_port_printk(qc
->ap
, KERN_ERR
,
355 "s/g len unaligned : 0x%x\n", sg_len
);
357 if ((num_prde
== (SATA_FSL_MAX_PRD_DIRECT
- 1)) &&
358 (qc
->n_iter
+ 1 != qc
->n_elem
)) {
359 VPRINTK("setting indirect prde\n");
360 prd_ptr_to_indirect_ext
= prd
;
361 prd
->dba
= cpu_to_le32(indirect_ext_segment_paddr
);
362 indirect_ext_segment_sz
= 0;
367 ttl_dwords
+= sg_len
;
368 prd
->dba
= cpu_to_le32(sg_addr
);
370 cpu_to_le32(DATA_SNOOP_ENABLE
| (sg_len
& ~0x03));
372 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
373 ttl_dwords
, prd
->dba
, prd
->ddc_and_ext
);
377 if (prd_ptr_to_indirect_ext
)
378 indirect_ext_segment_sz
+= sg_len
;
381 if (prd_ptr_to_indirect_ext
) {
382 /* set indirect extension flag along with indirect ext. size */
383 prd_ptr_to_indirect_ext
->ddc_and_ext
=
384 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG
|
386 (indirect_ext_segment_sz
& ~0x03)));
393 static void sata_fsl_qc_prep(struct ata_queued_cmd
*qc
)
395 struct ata_port
*ap
= qc
->ap
;
396 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
397 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
398 void __iomem
*hcr_base
= host_priv
->hcr_base
;
399 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
400 struct command_desc
*cd
;
401 u32 desc_info
= CMD_DESC_SNOOP_ENABLE
;
406 cd
= (struct command_desc
*)pp
->cmdentry
+ tag
;
407 cd_paddr
= pp
->cmdentry_paddr
+ tag
* SATA_FSL_CMD_DESC_SIZE
;
409 ata_tf_to_fis(&qc
->tf
, 0, 1, (u8
*) & cd
->cfis
);
411 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
412 cd
->cfis
[0], cd
->cfis
[1], cd
->cfis
[2]);
414 if (qc
->tf
.protocol
== ATA_PROT_NCQ
) {
415 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
416 cd
->cfis
[3], cd
->cfis
[11]);
419 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
420 if (is_atapi_taskfile(&qc
->tf
)) {
421 desc_info
|= ATAPI_CMD
;
422 memset((void *)&cd
->acmd
, 0, 32);
423 memcpy((void *)&cd
->acmd
, qc
->cdb
, qc
->dev
->cdb_len
);
426 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
427 num_prde
= sata_fsl_fill_sg(qc
, (void *)cd
,
428 &ttl_dwords
, cd_paddr
);
430 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
431 desc_info
|= FPDMA_QUEUED_CMD
;
433 sata_fsl_setup_cmd_hdr_entry(pp
, tag
, desc_info
, ttl_dwords
,
436 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
437 desc_info
, ttl_dwords
, num_prde
);
440 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd
*qc
)
442 struct ata_port
*ap
= qc
->ap
;
443 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
444 void __iomem
*hcr_base
= host_priv
->hcr_base
;
445 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
447 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
448 ioread32(CQ
+ hcr_base
),
449 ioread32(CA
+ hcr_base
),
450 ioread32(CE
+ hcr_base
), ioread32(CC
+ hcr_base
));
452 /* Simply queue command to the controller/device */
453 iowrite32(1 << tag
, CQ
+ hcr_base
);
455 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
456 tag
, ioread32(CQ
+ hcr_base
), ioread32(CA
+ hcr_base
));
458 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
459 ioread32(CE
+ hcr_base
),
460 ioread32(DE
+ hcr_base
),
461 ioread32(CC
+ hcr_base
), ioread32(COMMANDSTAT
+ csr_base
));
466 static int sata_fsl_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
,
469 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
470 void __iomem
*ssr_base
= host_priv
->ssr_base
;
484 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg
);
486 iowrite32(val
, (void __iomem
*)ssr_base
+ (sc_reg
* 4));
490 static int sata_fsl_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
,
493 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
494 void __iomem
*ssr_base
= host_priv
->ssr_base
;
508 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg
);
510 *val
= ioread32((void __iomem
*)ssr_base
+ (sc_reg
* 4));
514 static void sata_fsl_freeze(struct ata_port
*ap
)
516 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
517 void __iomem
*hcr_base
= host_priv
->hcr_base
;
520 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
521 ioread32(CQ
+ hcr_base
),
522 ioread32(CA
+ hcr_base
),
523 ioread32(CE
+ hcr_base
), ioread32(DE
+ hcr_base
));
524 VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base
+ COMMANDSTAT
));
526 /* disable interrupts on the controller/port */
527 temp
= ioread32(hcr_base
+ HCONTROL
);
528 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
530 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
531 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
534 static void sata_fsl_thaw(struct ata_port
*ap
)
536 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
537 void __iomem
*hcr_base
= host_priv
->hcr_base
;
540 /* ack. any pending IRQs for this controller/port */
541 temp
= ioread32(hcr_base
+ HSTATUS
);
543 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp
& 0x3F));
546 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
548 /* enable interrupts on the controller/port */
549 temp
= ioread32(hcr_base
+ HCONTROL
);
550 iowrite32((temp
| DEFAULT_PORT_IRQ_ENABLE_MASK
), hcr_base
+ HCONTROL
);
552 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
553 ioread32(hcr_base
+ HCONTROL
), ioread32(hcr_base
+ HSTATUS
));
557 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
559 static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
563 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
565 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
566 void __iomem
*hcr_base
= host_priv
->hcr_base
;
567 unsigned int tag
= sata_fsl_tag(qc
->tag
, hcr_base
);
568 struct command_desc
*cd
;
570 cd
= pp
->cmdentry
+ tag
;
572 memcpy(fis
, &cd
->sfis
, 6 * 4); /* should we use memcpy_from_io() */
573 ata_tf_from_fis(fis
, &pp
->tf
);
576 static u8
sata_fsl_check_status(struct ata_port
*ap
)
578 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
580 return pp
->tf
.command
;
583 static void sata_fsl_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
585 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
590 static int sata_fsl_port_start(struct ata_port
*ap
)
592 struct device
*dev
= ap
->host
->dev
;
593 struct sata_fsl_port_priv
*pp
;
597 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
598 void __iomem
*hcr_base
= host_priv
->hcr_base
;
601 pp
= kzalloc(sizeof(*pp
), GFP_KERNEL
);
606 * allocate per command dma alignment pad buffer, which is used
607 * internally by libATA to ensure that all transfers ending on
608 * unaligned boundaries are padded, to align on Dword boundaries
610 retval
= ata_pad_alloc(ap
, dev
);
616 mem
= dma_alloc_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
, &mem_dma
,
619 ata_pad_free(ap
, dev
);
623 memset(mem
, 0, SATA_FSL_PORT_PRIV_DMA_SZ
);
626 pp
->cmdslot_paddr
= mem_dma
;
628 mem
+= SATA_FSL_CMD_SLOT_SIZE
;
629 mem_dma
+= SATA_FSL_CMD_SLOT_SIZE
;
632 pp
->cmdentry_paddr
= mem_dma
;
634 ap
->private_data
= pp
;
636 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
637 pp
->cmdslot_paddr
, pp
->cmdentry_paddr
);
639 /* Now, update the CHBA register in host controller cmd register set */
640 iowrite32(pp
->cmdslot_paddr
& 0xffffffff, hcr_base
+ CHBA
);
643 * Now, we can bring the controller on-line & also initiate
644 * the COMINIT sequence, we simply return here and the boot-probing
645 * & device discovery process is re-initiated by libATA using a
646 * Softreset EH (dummy) session. Hence, boot probing and device
647 * discovey will be part of sata_fsl_softreset() callback.
650 temp
= ioread32(hcr_base
+ HCONTROL
);
651 iowrite32((temp
| HCONTROL_ONLINE_PHY_RST
), hcr_base
+ HCONTROL
);
653 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
654 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
655 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base
+ CHBA
));
658 * Workaround for 8315DS board 3gbps link-up issue,
659 * currently limit SATA port to GEN1 speed
661 sata_fsl_scr_read(ap
, SCR_CONTROL
, &temp
);
664 sata_fsl_scr_write(ap
, SCR_CONTROL
, temp
);
666 sata_fsl_scr_read(ap
, SCR_CONTROL
, &temp
);
667 dev_printk(KERN_WARNING
, dev
, "scr_control, speed limited to %x\n",
673 static void sata_fsl_port_stop(struct ata_port
*ap
)
675 struct device
*dev
= ap
->host
->dev
;
676 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
677 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
678 void __iomem
*hcr_base
= host_priv
->hcr_base
;
682 * Force host controller to go off-line, aborting current operations
684 temp
= ioread32(hcr_base
+ HCONTROL
);
685 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
686 temp
|= HCONTROL_FORCE_OFFLINE
;
687 iowrite32(temp
, hcr_base
+ HCONTROL
);
689 /* Poll for controller to go offline - should happen immediately */
690 ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, ONLINE
, 1, 1);
692 ap
->private_data
= NULL
;
693 dma_free_coherent(dev
, SATA_FSL_PORT_PRIV_DMA_SZ
,
694 pp
->cmdslot
, pp
->cmdslot_paddr
);
696 ata_pad_free(ap
, dev
);
700 static unsigned int sata_fsl_dev_classify(struct ata_port
*ap
)
702 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
703 void __iomem
*hcr_base
= host_priv
->hcr_base
;
704 struct ata_taskfile tf
;
707 temp
= ioread32(hcr_base
+ SIGNATURE
);
709 VPRINTK("raw sig = 0x%x\n", temp
);
710 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
711 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
713 tf
.lbah
= (temp
>> 24) & 0xff;
714 tf
.lbam
= (temp
>> 16) & 0xff;
715 tf
.lbal
= (temp
>> 8) & 0xff;
716 tf
.nsect
= temp
& 0xff;
718 return ata_dev_classify(&tf
);
721 static int sata_fsl_softreset(struct ata_link
*link
, unsigned int *class,
722 unsigned long deadline
)
724 struct ata_port
*ap
= link
->ap
;
725 struct sata_fsl_port_priv
*pp
= ap
->private_data
;
726 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
727 void __iomem
*hcr_base
= host_priv
->hcr_base
;
729 struct ata_taskfile tf
;
733 struct ata_queued_cmd qc
;
735 dma_addr_t dma_address
;
736 struct scatterlist
*sg
;
737 unsigned long start_jiffies
;
739 DPRINTK("in xx_softreset\n");
743 * Force host controller to go off-line, aborting current operations
745 temp
= ioread32(hcr_base
+ HCONTROL
);
746 temp
&= ~HCONTROL_ONLINE_PHY_RST
;
747 iowrite32(temp
, hcr_base
+ HCONTROL
);
749 /* Poll for controller to go offline */
750 temp
= ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, ONLINE
, 1, 500);
753 ata_port_printk(ap
, KERN_ERR
,
754 "Softreset failed, not off-lined %d\n", i
);
757 * Try to offline controller atleast twice
763 goto try_offline_again
;
766 DPRINTK("softreset, controller off-lined\n");
767 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
768 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
771 * PHY reset should remain asserted for atleast 1ms
776 * Now, bring the host controller online again, this can take time
777 * as PHY reset and communication establishment, 1st D2H FIS and
778 * device signature update is done, on safe side assume 500ms
779 * NOTE : Host online status may be indicated immediately!!
782 temp
= ioread32(hcr_base
+ HCONTROL
);
783 temp
|= (HCONTROL_ONLINE_PHY_RST
| HCONTROL_SNOOP_ENABLE
);
784 iowrite32(temp
, hcr_base
+ HCONTROL
);
786 temp
= ata_wait_register(hcr_base
+ HSTATUS
, ONLINE
, 0, 1, 500);
788 if (!(temp
& ONLINE
)) {
789 ata_port_printk(ap
, KERN_ERR
,
790 "Softreset failed, not on-lined\n");
794 DPRINTK("softreset, controller off-lined & on-lined\n");
795 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
796 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
799 * First, wait for the PHYRDY change to occur before waiting for
800 * the signature, and also verify if SStatus indicates device
804 temp
= ata_wait_register(hcr_base
+ HSTATUS
, 0xFF, 0, 1, 500);
805 if ((!(temp
& 0x10)) || ata_link_offline(link
)) {
806 ata_port_printk(ap
, KERN_WARNING
,
807 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
808 ioread32(hcr_base
+ HSTATUS
));
813 * Wait for the first D2H from device,i.e,signature update notification
815 start_jiffies
= jiffies
;
816 temp
= ata_wait_register(hcr_base
+ HSTATUS
, 0xFF, 0x10,
817 500, jiffies_to_msecs(deadline
- start_jiffies
));
819 if ((temp
& 0xFF) != 0x18) {
820 ata_port_printk(ap
, KERN_WARNING
, "No Signature Update\n");
823 ata_port_printk(ap
, KERN_INFO
,
824 "Signature Update detected @ %d msecs\n",
825 jiffies_to_msecs(jiffies
- start_jiffies
));
829 * Send a device reset (SRST) explicitly on command slot #0
830 * Check : will the command queue (reg) be cleared during offlining ??
831 * Also we will be online only if Phy commn. has been established
832 * and device presence has been detected, therefore if we have
833 * reached here, we can send a command to the target device
837 goto skip_srst_do_ncq_error_handling
;
839 DPRINTK("Sending SRST/device reset\n");
841 ata_tf_init(link
->device
, &tf
);
842 cfis
= (u8
*) & pp
->cmdentry
->cfis
;
844 /* device reset/SRST is a control register update FIS, uses tag0 */
845 sata_fsl_setup_cmd_hdr_entry(pp
, 0,
846 SRST_CMD
| CMD_DESC_SNOOP_ENABLE
, 0, 0, 5);
848 tf
.ctl
|= ATA_SRST
; /* setup SRST bit in taskfile control reg */
849 ata_tf_to_fis(&tf
, 0, 0, cfis
);
851 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
852 cfis
[0], cfis
[1], cfis
[2], cfis
[3]);
855 * Queue SRST command to the controller/device, ensure that no
856 * other commands are active on the controller/device
859 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
860 ioread32(CQ
+ hcr_base
),
861 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
863 iowrite32(0xFFFF, CC
+ hcr_base
);
864 iowrite32(1, CQ
+ hcr_base
);
866 temp
= ata_wait_register(CQ
+ hcr_base
, 0x1, 0x1, 1, 5000);
868 ata_port_printk(ap
, KERN_WARNING
, "ATA_SRST issue failed\n");
870 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
871 ioread32(CQ
+ hcr_base
),
872 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
874 sata_fsl_scr_read(ap
, SCR_ERROR
, &Serror
);
876 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
877 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
878 DPRINTK("Serror = 0x%x\n", Serror
);
885 * SATA device enters reset state after receving a Control register
886 * FIS with SRST bit asserted and it awaits another H2D Control reg.
887 * FIS with SRST bit cleared, then the device does internal diags &
888 * initialization, followed by indicating it's initialization status
889 * using ATA signature D2H register FIS to the host controller.
892 sata_fsl_setup_cmd_hdr_entry(pp
, 0, CMD_DESC_SNOOP_ENABLE
, 0, 0, 5);
894 tf
.ctl
&= ~ATA_SRST
; /* 2nd H2D Ctl. register FIS */
895 ata_tf_to_fis(&tf
, 0, 0, cfis
);
897 iowrite32(1, CQ
+ hcr_base
);
898 msleep(150); /* ?? */
901 * The above command would have signalled an interrupt on command
902 * complete, which needs special handling, by clearing the Nth
903 * command bit of the CCreg
905 iowrite32(0x01, CC
+ hcr_base
); /* We know it will be cmd#0 always */
906 goto check_device_signature
;
908 skip_srst_do_ncq_error_handling
:
910 VPRINTK("Sending read log ext(10h) command\n");
912 memset(&qc
, 0, sizeof(struct ata_queued_cmd
));
913 ata_tf_init(link
->device
, &tf
);
915 tf
.command
= ATA_CMD_READ_LOG_EXT
;
916 tf
.lbal
= ATA_LOG_SATA_NCQ
;
919 tf
.flags
|= ATA_TFLAG_ISADDR
| ATA_TFLAG_LBA48
| ATA_TFLAG_DEVICE
;
920 tf
.protocol
= ATA_PROT_PIO
;
922 qc
.tag
= ATA_TAG_INTERNAL
;
925 qc
.dev
= link
->device
;
928 qc
.flags
|= ATA_QCFLAG_RESULT_TF
;
929 qc
.dma_dir
= DMA_FROM_DEVICE
;
931 buf
= ap
->sector_buf
;
932 ata_sg_init_one(&qc
, buf
, 1 * ATA_SECT_SIZE
);
935 * Need to DMA-map the memory buffer associated with the command
939 dma_address
= dma_map_single(ap
->dev
, qc
.buf_virt
,
940 sg
->length
, DMA_FROM_DEVICE
);
942 sg_dma_address(sg
) = dma_address
;
943 sg_dma_len(sg
) = sg
->length
;
945 VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address
, sg
->length
);
947 sata_fsl_qc_prep(&qc
);
948 sata_fsl_qc_issue(&qc
);
950 temp
= ata_wait_register(CQ
+ hcr_base
, 0x1, 0x1, 1, 5000);
952 VPRINTK("READ_LOG_EXT_10H issue failed\n");
954 VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
955 ioread32(CQ
+ hcr_base
),
956 ioread32(CA
+ hcr_base
), ioread32(CC
+ hcr_base
));
958 sata_fsl_scr_read(ap
, SCR_ERROR
, &Serror
);
960 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
961 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
962 VPRINTK("Serror = 0x%x\n", Serror
);
966 iowrite32(0x01, CC
+ hcr_base
); /* We know it will be cmd#0 always */
968 check_device_signature
:
970 DPRINTK("SATA FSL : Now checking device signature\n");
972 *class = ATA_DEV_NONE
;
974 /* Verify if SStatus indicates device presence */
975 if (ata_link_online(link
)) {
977 * if we are here, device presence has been detected,
978 * 1st D2H FIS would have been received, but sfis in
979 * command desc. is not updated, but signature register
980 * would have been updated
983 *class = sata_fsl_dev_classify(ap
);
985 DPRINTK("class = %d\n", *class);
986 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base
+ CC
));
987 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base
+ CE
));
996 static int sata_fsl_hardreset(struct ata_port
*ap
, unsigned int *class,
997 unsigned long deadline
)
1001 retval
= sata_std_hardreset(ap
, class, deadline
);
1003 DPRINTK("SATA FSL : in xx_hardreset, retval = 0x%d\n", retval
);
1008 static void sata_fsl_error_handler(struct ata_port
*ap
)
1011 DPRINTK("in xx_error_handler\n");
1013 /* perform recovery */
1014 ata_do_eh(ap
, ata_std_prereset
, sata_fsl_softreset
, sata_fsl_hardreset
,
1018 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd
*qc
)
1020 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1021 qc
->err_mask
|= AC_ERR_OTHER
;
1024 /* make DMA engine forget about the failed command */
1029 static void sata_fsl_irq_clear(struct ata_port
*ap
)
1034 static void sata_fsl_error_intr(struct ata_port
*ap
)
1036 struct ata_link
*link
= &ap
->link
;
1037 struct ata_eh_info
*ehi
= &link
->eh_info
;
1038 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
1039 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1040 u32 hstatus
, dereg
, cereg
= 0, SError
= 0;
1041 unsigned int err_mask
= 0, action
= 0;
1042 struct ata_queued_cmd
*qc
;
1045 hstatus
= ioread32(hcr_base
+ HSTATUS
);
1046 cereg
= ioread32(hcr_base
+ CE
);
1048 ata_ehi_clear_desc(ehi
);
1051 * Handle & Clear SError
1054 sata_fsl_scr_read(ap
, SCR_ERROR
, &SError
);
1055 if (unlikely(SError
& 0xFFFF0000)) {
1056 sata_fsl_scr_write(ap
, SCR_ERROR
, SError
);
1057 err_mask
|= AC_ERR_ATA_BUS
;
1060 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1061 hstatus
, cereg
, ioread32(hcr_base
+ DE
), SError
);
1063 /* handle single device errors */
1066 * clear the command error, also clears queue to the device
1067 * in error, and we can (re)issue commands to this device.
1068 * When a device is in error all commands queued into the
1069 * host controller and at the device are considered aborted
1070 * and the queue for that device is stopped. Now, after
1071 * clearing the device error, we can issue commands to the
1072 * device to interrogate it to find the source of the error.
1074 dereg
= ioread32(hcr_base
+ DE
);
1075 iowrite32(dereg
, hcr_base
+ DE
);
1076 iowrite32(cereg
, hcr_base
+ CE
);
1078 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1079 ioread32(hcr_base
+ CE
), ioread32(hcr_base
+ DE
));
1081 * We should consider this as non fatal error, and TF must
1082 * be updated as done below.
1085 err_mask
|= AC_ERR_DEV
;
1088 /* handle fatal errors */
1089 if (hstatus
& FATAL_ERROR_DECODE
) {
1090 err_mask
|= AC_ERR_ATA_BUS
;
1091 action
|= ATA_EH_SOFTRESET
;
1092 /* how will fatal error interrupts be completed ?? */
1096 /* Handle PHYRDY change notification */
1097 if (hstatus
& INT_ON_PHYRDY_CHG
) {
1098 DPRINTK("SATA FSL: PHYRDY change indication\n");
1100 /* Setup a soft-reset EH action */
1101 ata_ehi_hotplugged(ehi
);
1105 /* record error info */
1106 qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1109 sata_fsl_cache_taskfile_from_d2h_fis(qc
, qc
->ap
);
1110 qc
->err_mask
|= err_mask
;
1112 ehi
->err_mask
|= err_mask
;
1114 ehi
->action
|= action
;
1115 ehi
->serror
|= SError
;
1117 /* freeze or abort */
1119 ata_port_freeze(ap
);
1124 static void sata_fsl_qc_complete(struct ata_queued_cmd
*qc
)
1126 if (qc
->flags
& ATA_QCFLAG_RESULT_TF
) {
1127 DPRINTK("xx_qc_complete called\n");
1128 sata_fsl_cache_taskfile_from_d2h_fis(qc
, qc
->ap
);
1132 static void sata_fsl_host_intr(struct ata_port
*ap
)
1134 struct ata_link
*link
= &ap
->link
;
1135 struct sata_fsl_host_priv
*host_priv
= ap
->host
->private_data
;
1136 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1137 u32 hstatus
, qc_active
= 0;
1138 struct ata_queued_cmd
*qc
;
1141 hstatus
= ioread32(hcr_base
+ HSTATUS
);
1143 sata_fsl_scr_read(ap
, SCR_ERROR
, &SError
);
1145 if (unlikely(SError
& 0xFFFF0000)) {
1146 DPRINTK("serror @host_intr : 0x%x\n", SError
);
1147 sata_fsl_error_intr(ap
);
1151 if (unlikely(hstatus
& INT_ON_ERROR
)) {
1152 DPRINTK("error interrupt!!\n");
1153 sata_fsl_error_intr(ap
);
1157 if (link
->sactive
) { /* only true for NCQ commands */
1159 /* Read command completed register */
1160 qc_active
= ioread32(hcr_base
+ CC
);
1161 /* clear CC bit, this will also complete the interrupt */
1162 iowrite32(qc_active
, hcr_base
+ CC
);
1164 DPRINTK("Status of all queues :\n");
1165 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1166 qc_active
, ioread32(hcr_base
+ CA
),
1167 ioread32(hcr_base
+ CE
));
1169 for (i
= 0; i
< SATA_FSL_QUEUE_DEPTH
; i
++) {
1170 if (qc_active
& (1 << i
)) {
1171 qc
= ata_qc_from_tag(ap
, i
);
1173 sata_fsl_qc_complete(qc
);
1174 ata_qc_complete(qc
);
1177 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1178 i
, ioread32(hcr_base
+ CC
),
1179 ioread32(hcr_base
+ CA
));
1184 } else if (ap
->qc_active
) {
1185 iowrite32(1, hcr_base
+ CC
);
1186 qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1188 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1189 link
->active_tag
, ioread32(hcr_base
+ CC
));
1192 sata_fsl_qc_complete(qc
);
1193 ata_qc_complete(qc
);
1196 /* Spurious Interrupt!! */
1197 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1198 ioread32(hcr_base
+ CC
));
1203 static irqreturn_t
sata_fsl_interrupt(int irq
, void *dev_instance
)
1205 struct ata_host
*host
= dev_instance
;
1206 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1207 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1208 u32 interrupt_enables
;
1209 unsigned handled
= 0;
1210 struct ata_port
*ap
;
1212 /* ack. any pending IRQs for this controller/port */
1213 interrupt_enables
= ioread32(hcr_base
+ HSTATUS
);
1214 interrupt_enables
&= 0x3F;
1216 DPRINTK("interrupt status 0x%x\n", interrupt_enables
);
1218 if (!interrupt_enables
)
1221 spin_lock(&host
->lock
);
1223 /* Assuming one port per host controller */
1225 ap
= host
->ports
[0];
1227 sata_fsl_host_intr(ap
);
1229 dev_printk(KERN_WARNING
, host
->dev
,
1230 "interrupt on disabled port 0\n");
1233 iowrite32(interrupt_enables
, hcr_base
+ HSTATUS
);
1236 spin_unlock(&host
->lock
);
1238 return IRQ_RETVAL(handled
);
1242 * Multiple ports are represented by multiple SATA controllers with
1243 * one port per controller
1245 static int sata_fsl_init_controller(struct ata_host
*host
)
1247 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1248 void __iomem
*hcr_base
= host_priv
->hcr_base
;
1252 * NOTE : We cannot bring the controller online before setting
1253 * the CHBA, hence main controller initialization is done as
1254 * part of the port_start() callback
1257 /* ack. any pending IRQs for this controller/port */
1258 temp
= ioread32(hcr_base
+ HSTATUS
);
1260 iowrite32((temp
& 0x3F), hcr_base
+ HSTATUS
);
1262 /* Keep interrupts disabled on the controller */
1263 temp
= ioread32(hcr_base
+ HCONTROL
);
1264 iowrite32((temp
& ~0x3F), hcr_base
+ HCONTROL
);
1266 /* Disable interrupt coalescing control(icc), for the moment */
1267 DPRINTK("icc = 0x%x\n", ioread32(hcr_base
+ ICC
));
1268 iowrite32(0x01000000, hcr_base
+ ICC
);
1270 /* clear error registers, SError is cleared by libATA */
1271 iowrite32(0x00000FFFF, hcr_base
+ CE
);
1272 iowrite32(0x00000FFFF, hcr_base
+ DE
);
1274 /* initially assuming no Port multiplier, set CQPMP to 0 */
1275 iowrite32(0x0, hcr_base
+ CQPMP
);
1278 * host controller will be brought on-line, during xx_port_start()
1279 * callback, that should also initiate the OOB, COMINIT sequence
1282 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base
+ HSTATUS
));
1283 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base
+ HCONTROL
));
1289 * scsi mid-layer and libata interface structures
1291 static struct scsi_host_template sata_fsl_sht
= {
1292 .module
= THIS_MODULE
,
1294 .ioctl
= ata_scsi_ioctl
,
1295 .queuecommand
= ata_scsi_queuecmd
,
1296 .change_queue_depth
= ata_scsi_change_queue_depth
,
1297 .can_queue
= SATA_FSL_QUEUE_DEPTH
,
1298 .this_id
= ATA_SHT_THIS_ID
,
1299 .sg_tablesize
= SATA_FSL_MAX_PRD_USABLE
,
1300 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
1301 .emulated
= ATA_SHT_EMULATED
,
1302 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
1303 .proc_name
= "sata_fsl",
1304 .dma_boundary
= ATA_DMA_BOUNDARY
,
1305 .slave_configure
= ata_scsi_slave_config
,
1306 .slave_destroy
= ata_scsi_slave_destroy
,
1307 .bios_param
= ata_std_bios_param
,
1309 .suspend
= ata_scsi_device_suspend
,
1310 .resume
= ata_scsi_device_resume
,
1314 static const struct ata_port_operations sata_fsl_ops
= {
1315 .check_status
= sata_fsl_check_status
,
1316 .check_altstatus
= sata_fsl_check_status
,
1317 .dev_select
= ata_noop_dev_select
,
1319 .tf_read
= sata_fsl_tf_read
,
1321 .qc_prep
= sata_fsl_qc_prep
,
1322 .qc_issue
= sata_fsl_qc_issue
,
1323 .irq_clear
= sata_fsl_irq_clear
,
1325 .scr_read
= sata_fsl_scr_read
,
1326 .scr_write
= sata_fsl_scr_write
,
1328 .freeze
= sata_fsl_freeze
,
1329 .thaw
= sata_fsl_thaw
,
1330 .error_handler
= sata_fsl_error_handler
,
1331 .post_internal_cmd
= sata_fsl_post_internal_cmd
,
1333 .port_start
= sata_fsl_port_start
,
1334 .port_stop
= sata_fsl_port_stop
,
1337 static const struct ata_port_info sata_fsl_port_info
[] = {
1339 .flags
= SATA_FSL_HOST_FLAGS
,
1340 .link_flags
= SATA_FSL_HOST_LFLAGS
,
1341 .pio_mask
= 0x1f, /* pio 0-4 */
1342 .udma_mask
= 0x7f, /* udma 0-6 */
1343 .port_ops
= &sata_fsl_ops
,
1347 static int sata_fsl_probe(struct of_device
*ofdev
,
1348 const struct of_device_id
*match
)
1351 void __iomem
*hcr_base
= NULL
;
1352 void __iomem
*ssr_base
= NULL
;
1353 void __iomem
*csr_base
= NULL
;
1354 struct sata_fsl_host_priv
*host_priv
= NULL
;
1357 struct ata_host
*host
;
1359 struct ata_port_info pi
= sata_fsl_port_info
[0];
1360 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1362 dev_printk(KERN_INFO
, &ofdev
->dev
,
1363 "Sata FSL Platform/CSB Driver init\n");
1365 r
= kmalloc(sizeof(struct resource
), GFP_KERNEL
);
1367 hcr_base
= of_iomap(ofdev
->node
, 0);
1369 goto error_exit_with_cleanup
;
1371 ssr_base
= hcr_base
+ 0x100;
1372 csr_base
= hcr_base
+ 0x140;
1374 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base
+ TRANSCFG
));
1375 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc
));
1376 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE
);
1378 host_priv
= kzalloc(sizeof(struct sata_fsl_host_priv
), GFP_KERNEL
);
1380 goto error_exit_with_cleanup
;
1382 host_priv
->hcr_base
= hcr_base
;
1383 host_priv
->ssr_base
= ssr_base
;
1384 host_priv
->csr_base
= csr_base
;
1386 irq
= irq_of_parse_and_map(ofdev
->node
, 0);
1388 dev_printk(KERN_ERR
, &ofdev
->dev
, "invalid irq from platform\n");
1389 goto error_exit_with_cleanup
;
1391 host_priv
->irq
= irq
;
1393 /* allocate host structure */
1394 host
= ata_host_alloc_pinfo(&ofdev
->dev
, ppi
, SATA_FSL_MAX_PORTS
);
1396 /* host->iomap is not used currently */
1397 host
->private_data
= host_priv
;
1401 host
->ports
[0]->ioaddr
.cmd_addr
= host_priv
->hcr_base
;
1402 host
->ports
[0]->ioaddr
.scr_addr
= host_priv
->ssr_base
;
1404 /* initialize host controller */
1405 sata_fsl_init_controller(host
);
1408 * Now, register with libATA core, this will also initiate the
1409 * device discovery process, invoking our port_start() handler &
1410 * error_handler() to execute a dummy Softreset EH session
1412 ata_host_activate(host
, irq
, sata_fsl_interrupt
, SATA_FSL_IRQ_FLAG
,
1415 dev_set_drvdata(&ofdev
->dev
, host
);
1419 error_exit_with_cleanup
:
1429 static int sata_fsl_remove(struct of_device
*ofdev
)
1431 struct ata_host
*host
= dev_get_drvdata(&ofdev
->dev
);
1432 struct sata_fsl_host_priv
*host_priv
= host
->private_data
;
1434 ata_host_detach(host
);
1436 dev_set_drvdata(&ofdev
->dev
, NULL
);
1438 irq_dispose_mapping(host_priv
->irq
);
1439 iounmap(host_priv
->hcr_base
);
1445 static struct of_device_id fsl_sata_match
[] = {
1447 .compatible
= "fsl,mpc8315-sata",
1450 .compatible
= "fsl,mpc8379-sata",
1455 MODULE_DEVICE_TABLE(of
, fsl_sata_match
);
1457 static struct of_platform_driver fsl_sata_driver
= {
1459 .match_table
= fsl_sata_match
,
1460 .probe
= sata_fsl_probe
,
1461 .remove
= sata_fsl_remove
,
1464 static int __init
sata_fsl_init(void)
1466 of_register_platform_driver(&fsl_sata_driver
);
1470 static void __exit
sata_fsl_exit(void)
1472 of_unregister_platform_driver(&fsl_sata_driver
);
1475 MODULE_LICENSE("GPL");
1476 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1477 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1478 MODULE_VERSION("1.10");
1480 module_init(sata_fsl_init
);
1481 module_exit(sata_fsl_exit
);