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Blackfin SPI Driver: Make mmc_spi driver work on Blackfin
[linux-2.6/mini2440.git] / drivers / spi / spi_bfin5xx.c
blobe1d9eae1fae16db3878450058c16274599ec379f
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/dma.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
28 #include <asm/cacheflush.h>
29
30 #define DRV_NAME "bfin-spi"
31 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
32 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
33 #define DRV_VERSION "1.0"
34
35 MODULE_AUTHOR(DRV_AUTHOR);
36 MODULE_DESCRIPTION(DRV_DESC);
37 MODULE_LICENSE("GPL");
38
39 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
40
41 #define START_STATE ((void *)0)
42 #define RUNNING_STATE ((void *)1)
43 #define DONE_STATE ((void *)2)
44 #define ERROR_STATE ((void *)-1)
45 #define QUEUE_RUNNING 0
46 #define QUEUE_STOPPED 1
47
48 /* Value to send if no TX value is supplied */
49 #define SPI_IDLE_TXVAL 0x0000
50
51 struct driver_data {
52 /* Driver model hookup */
53 struct platform_device *pdev;
54
55 /* SPI framework hookup */
56 struct spi_master *master;
57
58 /* Regs base of SPI controller */
59 void __iomem *regs_base;
60
61 /* Pin request list */
62 u16 *pin_req;
63
64 /* BFIN hookup */
65 struct bfin5xx_spi_master *master_info;
66
67 /* Driver message queue */
68 struct workqueue_struct *workqueue;
69 struct work_struct pump_messages;
70 spinlock_t lock;
71 struct list_head queue;
72 int busy;
73 int run;
74
75 /* Message Transfer pump */
76 struct tasklet_struct pump_transfers;
77
78 /* Current message transfer state info */
79 struct spi_message *cur_msg;
80 struct spi_transfer *cur_transfer;
81 struct chip_data *cur_chip;
82 size_t len_in_bytes;
83 size_t len;
84 void *tx;
85 void *tx_end;
86 void *rx;
87 void *rx_end;
88
89 /* DMA stuffs */
90 int dma_channel;
91 int dma_mapped;
92 int dma_requested;
93 dma_addr_t rx_dma;
94 dma_addr_t tx_dma;
95
96 size_t rx_map_len;
97 size_t tx_map_len;
98 u8 n_bytes;
99 int cs_change;
100 void (*write) (struct driver_data *);
101 void (*read) (struct driver_data *);
102 void (*duplex) (struct driver_data *);
103 };
104
105 struct chip_data {
106 u16 ctl_reg;
107 u16 baud;
108 u16 flag;
109
110 u8 chip_select_num;
111 u8 n_bytes;
112 u8 width; /* 0 or 1 */
113 u8 enable_dma;
114 u8 bits_per_word; /* 8 or 16 */
115 u8 cs_change_per_word;
116 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
117 u32 cs_gpio;
118 u16 idle_tx_val;
119 void (*write) (struct driver_data *);
120 void (*read) (struct driver_data *);
121 void (*duplex) (struct driver_data *);
122 };
123
124 #define DEFINE_SPI_REG(reg, off) \
125 static inline u16 read_##reg(struct driver_data *drv_data) \
126 { return bfin_read16(drv_data->regs_base + off); } \
127 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
128 { bfin_write16(drv_data->regs_base + off, v); }
129
130 DEFINE_SPI_REG(CTRL, 0x00)
131 DEFINE_SPI_REG(FLAG, 0x04)
132 DEFINE_SPI_REG(STAT, 0x08)
133 DEFINE_SPI_REG(TDBR, 0x0C)
134 DEFINE_SPI_REG(RDBR, 0x10)
135 DEFINE_SPI_REG(BAUD, 0x14)
136 DEFINE_SPI_REG(SHAW, 0x18)
137
138 static void bfin_spi_enable(struct driver_data *drv_data)
139 {
140 u16 cr;
141
142 cr = read_CTRL(drv_data);
143 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
144 }
145
146 static void bfin_spi_disable(struct driver_data *drv_data)
147 {
148 u16 cr;
149
150 cr = read_CTRL(drv_data);
151 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
152 }
153
154 /* Caculate the SPI_BAUD register value based on input HZ */
155 static u16 hz_to_spi_baud(u32 speed_hz)
156 {
157 u_long sclk = get_sclk();
158 u16 spi_baud = (sclk / (2 * speed_hz));
159
160 if ((sclk % (2 * speed_hz)) > 0)
161 spi_baud++;
162
163 if (spi_baud < MIN_SPI_BAUD_VAL)
164 spi_baud = MIN_SPI_BAUD_VAL;
165
166 return spi_baud;
167 }
168
169 static int bfin_spi_flush(struct driver_data *drv_data)
170 {
171 unsigned long limit = loops_per_jiffy << 1;
172
173 /* wait for stop and clear stat */
174 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
175 cpu_relax();
176
177 write_STAT(drv_data, BIT_STAT_CLR);
178
179 return limit;
180 }
181
182 /* Chip select operation functions for cs_change flag */
183 static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
184 {
185 if (likely(chip->chip_select_num)) {
186 u16 flag = read_FLAG(drv_data);
187
188 flag |= chip->flag;
189 flag &= ~(chip->flag << 8);
190
191 write_FLAG(drv_data, flag);
192 } else {
193 gpio_set_value(chip->cs_gpio, 0);
194 }
195 }
196
197 static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
198 {
199 if (likely(chip->chip_select_num)) {
200 u16 flag = read_FLAG(drv_data);
201
202 flag &= ~chip->flag;
203 flag |= (chip->flag << 8);
204
205 write_FLAG(drv_data, flag);
206 } else {
207 gpio_set_value(chip->cs_gpio, 1);
208 }
209
210 /* Move delay here for consistency */
211 if (chip->cs_chg_udelay)
212 udelay(chip->cs_chg_udelay);
213 }
214
215 /* stop controller and re-config current chip*/
216 static void bfin_spi_restore_state(struct driver_data *drv_data)
217 {
218 struct chip_data *chip = drv_data->cur_chip;
219
220 /* Clear status and disable clock */
221 write_STAT(drv_data, BIT_STAT_CLR);
222 bfin_spi_disable(drv_data);
223 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
224
225 /* Load the registers */
226 write_CTRL(drv_data, chip->ctl_reg);
227 write_BAUD(drv_data, chip->baud);
228
229 bfin_spi_enable(drv_data);
230 bfin_spi_cs_active(drv_data, chip);
231 }
232
233 /* used to kick off transfer in rx mode and read unwanted RX data */
234 static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
235 {
236 (void) read_RDBR(drv_data);
237 }
238
239 static void bfin_spi_null_writer(struct driver_data *drv_data)
240 {
241 u8 n_bytes = drv_data->n_bytes;
242 u16 tx_val = drv_data->cur_chip->idle_tx_val;
243
244 /* clear RXS (we check for RXS inside the loop) */
245 bfin_spi_dummy_read(drv_data);
246
247 while (drv_data->tx < drv_data->tx_end) {
248 write_TDBR(drv_data, tx_val);
249 drv_data->tx += n_bytes;
250 /* wait until transfer finished.
251 checking SPIF or TXS may not guarantee transfer completion */
252 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
253 cpu_relax();
254 /* discard RX data and clear RXS */
255 bfin_spi_dummy_read(drv_data);
256 }
257 }
258
259 static void bfin_spi_null_reader(struct driver_data *drv_data)
260 {
261 u8 n_bytes = drv_data->n_bytes;
262 u16 tx_val = drv_data->cur_chip->idle_tx_val;
263
264 /* discard old RX data and clear RXS */
265 bfin_spi_dummy_read(drv_data);
266
267 while (drv_data->rx < drv_data->rx_end) {
268 write_TDBR(drv_data, tx_val);
269 drv_data->rx += n_bytes;
270 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
271 cpu_relax();
272 bfin_spi_dummy_read(drv_data);
273 }
274 }
275
276 static void bfin_spi_u8_writer(struct driver_data *drv_data)
277 {
278 /* clear RXS (we check for RXS inside the loop) */
279 bfin_spi_dummy_read(drv_data);
280
281 while (drv_data->tx < drv_data->tx_end) {
282 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
283 /* wait until transfer finished.
284 checking SPIF or TXS may not guarantee transfer completion */
285 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
286 cpu_relax();
287 /* discard RX data and clear RXS */
288 bfin_spi_dummy_read(drv_data);
289 }
290 }
291
292 static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
293 {
294 struct chip_data *chip = drv_data->cur_chip;
295
296 /* clear RXS (we check for RXS inside the loop) */
297 bfin_spi_dummy_read(drv_data);
298
299 while (drv_data->tx < drv_data->tx_end) {
300 bfin_spi_cs_active(drv_data, chip);
301 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
302 /* make sure transfer finished before deactiving CS */
303 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
304 cpu_relax();
305 bfin_spi_dummy_read(drv_data);
306 bfin_spi_cs_deactive(drv_data, chip);
307 }
308 }
309
310 static void bfin_spi_u8_reader(struct driver_data *drv_data)
311 {
312 u16 tx_val = drv_data->cur_chip->idle_tx_val;
313
314 /* discard old RX data and clear RXS */
315 bfin_spi_dummy_read(drv_data);
316
317 while (drv_data->rx < drv_data->rx_end) {
318 write_TDBR(drv_data, tx_val);
319 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
320 cpu_relax();
321 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
322 }
323 }
324
325 static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
326 {
327 struct chip_data *chip = drv_data->cur_chip;
328 u16 tx_val = chip->idle_tx_val;
329
330 /* discard old RX data and clear RXS */
331 bfin_spi_dummy_read(drv_data);
332
333 while (drv_data->rx < drv_data->rx_end) {
334 bfin_spi_cs_active(drv_data, chip);
335 write_TDBR(drv_data, tx_val);
336 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
337 cpu_relax();
338 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
339 bfin_spi_cs_deactive(drv_data, chip);
340 }
341 }
342
343 static void bfin_spi_u8_duplex(struct driver_data *drv_data)
344 {
345 /* discard old RX data and clear RXS */
346 bfin_spi_dummy_read(drv_data);
347
348 while (drv_data->rx < drv_data->rx_end) {
349 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
350 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
351 cpu_relax();
352 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
353 }
354 }
355
356 static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
357 {
358 struct chip_data *chip = drv_data->cur_chip;
359
360 /* discard old RX data and clear RXS */
361 bfin_spi_dummy_read(drv_data);
362
363 while (drv_data->rx < drv_data->rx_end) {
364 bfin_spi_cs_active(drv_data, chip);
365 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
367 cpu_relax();
368 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
369 bfin_spi_cs_deactive(drv_data, chip);
370 }
371 }
372
373 static void bfin_spi_u16_writer(struct driver_data *drv_data)
374 {
375 /* clear RXS (we check for RXS inside the loop) */
376 bfin_spi_dummy_read(drv_data);
377
378 while (drv_data->tx < drv_data->tx_end) {
379 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
380 drv_data->tx += 2;
381 /* wait until transfer finished.
382 checking SPIF or TXS may not guarantee transfer completion */
383 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
384 cpu_relax();
385 /* discard RX data and clear RXS */
386 bfin_spi_dummy_read(drv_data);
387 }
388 }
389
390 static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
391 {
392 struct chip_data *chip = drv_data->cur_chip;
393
394 /* clear RXS (we check for RXS inside the loop) */
395 bfin_spi_dummy_read(drv_data);
396
397 while (drv_data->tx < drv_data->tx_end) {
398 bfin_spi_cs_active(drv_data, chip);
399 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
400 drv_data->tx += 2;
401 /* make sure transfer finished before deactiving CS */
402 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
403 cpu_relax();
404 bfin_spi_dummy_read(drv_data);
405 bfin_spi_cs_deactive(drv_data, chip);
406 }
407 }
408
409 static void bfin_spi_u16_reader(struct driver_data *drv_data)
410 {
411 u16 tx_val = drv_data->cur_chip->idle_tx_val;
412
413 /* discard old RX data and clear RXS */
414 bfin_spi_dummy_read(drv_data);
415
416 while (drv_data->rx < drv_data->rx_end) {
417 write_TDBR(drv_data, tx_val);
418 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
419 cpu_relax();
420 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
421 drv_data->rx += 2;
422 }
423 }
424
425 static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
426 {
427 struct chip_data *chip = drv_data->cur_chip;
428 u16 tx_val = chip->idle_tx_val;
429
430 /* discard old RX data and clear RXS */
431 bfin_spi_dummy_read(drv_data);
432
433 while (drv_data->rx < drv_data->rx_end) {
434 bfin_spi_cs_active(drv_data, chip);
435 write_TDBR(drv_data, tx_val);
436 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
437 cpu_relax();
438 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
439 drv_data->rx += 2;
440 bfin_spi_cs_deactive(drv_data, chip);
441 }
442 }
443
444 static void bfin_spi_u16_duplex(struct driver_data *drv_data)
445 {
446 /* discard old RX data and clear RXS */
447 bfin_spi_dummy_read(drv_data);
448
449 while (drv_data->rx < drv_data->rx_end) {
450 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
451 drv_data->tx += 2;
452 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
453 cpu_relax();
454 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
455 drv_data->rx += 2;
456 }
457 }
458
459 static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
460 {
461 struct chip_data *chip = drv_data->cur_chip;
462
463 /* discard old RX data and clear RXS */
464 bfin_spi_dummy_read(drv_data);
465
466 while (drv_data->rx < drv_data->rx_end) {
467 bfin_spi_cs_active(drv_data, chip);
468 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
469 drv_data->tx += 2;
470 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
471 cpu_relax();
472 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
473 drv_data->rx += 2;
474 bfin_spi_cs_deactive(drv_data, chip);
475 }
476 }
477
478 /* test if ther is more transfer to be done */
479 static void *bfin_spi_next_transfer(struct driver_data *drv_data)
480 {
481 struct spi_message *msg = drv_data->cur_msg;
482 struct spi_transfer *trans = drv_data->cur_transfer;
483
484 /* Move to next transfer */
485 if (trans->transfer_list.next != &msg->transfers) {
486 drv_data->cur_transfer =
487 list_entry(trans->transfer_list.next,
488 struct spi_transfer, transfer_list);
489 return RUNNING_STATE;
490 } else
491 return DONE_STATE;
492 }
493
494 /*
495 * caller already set message->status;
496 * dma and pio irqs are blocked give finished message back
497 */
498 static void bfin_spi_giveback(struct driver_data *drv_data)
499 {
500 struct chip_data *chip = drv_data->cur_chip;
501 struct spi_transfer *last_transfer;
502 unsigned long flags;
503 struct spi_message *msg;
504
505 spin_lock_irqsave(&drv_data->lock, flags);
506 msg = drv_data->cur_msg;
507 drv_data->cur_msg = NULL;
508 drv_data->cur_transfer = NULL;
509 drv_data->cur_chip = NULL;
510 queue_work(drv_data->workqueue, &drv_data->pump_messages);
511 spin_unlock_irqrestore(&drv_data->lock, flags);
512
513 last_transfer = list_entry(msg->transfers.prev,
514 struct spi_transfer, transfer_list);
515
516 msg->state = NULL;
517
518 if (!drv_data->cs_change)
519 bfin_spi_cs_deactive(drv_data, chip);
520
521 /* Not stop spi in autobuffer mode */
522 if (drv_data->tx_dma != 0xFFFF)
523 bfin_spi_disable(drv_data);
524
525 if (msg->complete)
526 msg->complete(msg->context);
527 }
528
529 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
530 {
531 struct driver_data *drv_data = dev_id;
532 struct chip_data *chip = drv_data->cur_chip;
533 struct spi_message *msg = drv_data->cur_msg;
534 unsigned long timeout;
535 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
536 u16 spistat = read_STAT(drv_data);
537
538 dev_dbg(&drv_data->pdev->dev,
539 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
540 dmastat, spistat);
541
542 clear_dma_irqstat(drv_data->dma_channel);
543
544 /* Wait for DMA to complete */
545 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
546 cpu_relax();
547
548 /*
549 * wait for the last transaction shifted out. HRM states:
550 * at this point there may still be data in the SPI DMA FIFO waiting
551 * to be transmitted ... software needs to poll TXS in the SPI_STAT
552 * register until it goes low for 2 successive reads
553 */
554 if (drv_data->tx != NULL) {
555 while ((read_STAT(drv_data) & TXS) ||
556 (read_STAT(drv_data) & TXS))
557 cpu_relax();
558 }
559
560 dev_dbg(&drv_data->pdev->dev,
561 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
562 dmastat, read_STAT(drv_data));
563
564 timeout = jiffies + HZ;
565 while (!(read_STAT(drv_data) & SPIF))
566 if (!time_before(jiffies, timeout)) {
567 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
568 break;
569 } else
570 cpu_relax();
571
572 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
573 msg->state = ERROR_STATE;
574 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
575 } else {
576 msg->actual_length += drv_data->len_in_bytes;
577
578 if (drv_data->cs_change)
579 bfin_spi_cs_deactive(drv_data, chip);
580
581 /* Move to next transfer */
582 msg->state = bfin_spi_next_transfer(drv_data);
583 }
584
585 /* Schedule transfer tasklet */
586 tasklet_schedule(&drv_data->pump_transfers);
587
588 /* free the irq handler before next transfer */
589 dev_dbg(&drv_data->pdev->dev,
590 "disable dma channel irq%d\n",
591 drv_data->dma_channel);
592 dma_disable_irq(drv_data->dma_channel);
593
594 return IRQ_HANDLED;
595 }
596
597 static void bfin_spi_pump_transfers(unsigned long data)
598 {
599 struct driver_data *drv_data = (struct driver_data *)data;
600 struct spi_message *message = NULL;
601 struct spi_transfer *transfer = NULL;
602 struct spi_transfer *previous = NULL;
603 struct chip_data *chip = NULL;
604 u8 width;
605 u16 cr, dma_width, dma_config;
606 u32 tranf_success = 1;
607 u8 full_duplex = 0;
608
609 /* Get current state information */
610 message = drv_data->cur_msg;
611 transfer = drv_data->cur_transfer;
612 chip = drv_data->cur_chip;
613
614 /*
615 * if msg is error or done, report it back using complete() callback
616 */
617
618 /* Handle for abort */
619 if (message->state == ERROR_STATE) {
620 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
621 message->status = -EIO;
622 bfin_spi_giveback(drv_data);
623 return;
624 }
625
626 /* Handle end of message */
627 if (message->state == DONE_STATE) {
628 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
629 message->status = 0;
630 bfin_spi_giveback(drv_data);
631 return;
632 }
633
634 /* Delay if requested at end of transfer */
635 if (message->state == RUNNING_STATE) {
636 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
637 previous = list_entry(transfer->transfer_list.prev,
638 struct spi_transfer, transfer_list);
639 if (previous->delay_usecs)
640 udelay(previous->delay_usecs);
641 }
642
643 /* Setup the transfer state based on the type of transfer */
644 if (bfin_spi_flush(drv_data) == 0) {
645 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
646 message->status = -EIO;
647 bfin_spi_giveback(drv_data);
648 return;
649 }
650
651 if (transfer->len == 0) {
652 /* Move to next transfer of this msg */
653 message->state = bfin_spi_next_transfer(drv_data);
654 /* Schedule next transfer tasklet */
655 tasklet_schedule(&drv_data->pump_transfers);
656 }
657
658 if (transfer->tx_buf != NULL) {
659 drv_data->tx = (void *)transfer->tx_buf;
660 drv_data->tx_end = drv_data->tx + transfer->len;
661 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
662 transfer->tx_buf, drv_data->tx_end);
663 } else {
664 drv_data->tx = NULL;
665 }
666
667 if (transfer->rx_buf != NULL) {
668 full_duplex = transfer->tx_buf != NULL;
669 drv_data->rx = transfer->rx_buf;
670 drv_data->rx_end = drv_data->rx + transfer->len;
671 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
672 transfer->rx_buf, drv_data->rx_end);
673 } else {
674 drv_data->rx = NULL;
675 }
676
677 drv_data->rx_dma = transfer->rx_dma;
678 drv_data->tx_dma = transfer->tx_dma;
679 drv_data->len_in_bytes = transfer->len;
680 drv_data->cs_change = transfer->cs_change;
681
682 /* Bits per word setup */
683 switch (transfer->bits_per_word) {
684 case 8:
685 drv_data->n_bytes = 1;
686 width = CFG_SPI_WORDSIZE8;
687 drv_data->read = chip->cs_change_per_word ?
688 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
689 drv_data->write = chip->cs_change_per_word ?
690 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
691 drv_data->duplex = chip->cs_change_per_word ?
692 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
693 break;
694
695 case 16:
696 drv_data->n_bytes = 2;
697 width = CFG_SPI_WORDSIZE16;
698 drv_data->read = chip->cs_change_per_word ?
699 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
700 drv_data->write = chip->cs_change_per_word ?
701 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
702 drv_data->duplex = chip->cs_change_per_word ?
703 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
704 break;
705
706 default:
707 /* No change, the same as default setting */
708 drv_data->n_bytes = chip->n_bytes;
709 width = chip->width;
710 drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer;
711 drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader;
712 drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer;
713 break;
714 }
715 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
716 cr |= (width << 8);
717 write_CTRL(drv_data, cr);
718
719 if (width == CFG_SPI_WORDSIZE16) {
720 drv_data->len = (transfer->len) >> 1;
721 } else {
722 drv_data->len = transfer->len;
723 }
724 dev_dbg(&drv_data->pdev->dev,
725 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
726 drv_data->write, chip->write, bfin_spi_null_writer);
727
728 /* speed and width has been set on per message */
729 message->state = RUNNING_STATE;
730 dma_config = 0;
731
732 /* Speed setup (surely valid because already checked) */
733 if (transfer->speed_hz)
734 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
735 else
736 write_BAUD(drv_data, chip->baud);
737
738 write_STAT(drv_data, BIT_STAT_CLR);
739 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
740 if (drv_data->cs_change)
741 bfin_spi_cs_active(drv_data, chip);
742
743 dev_dbg(&drv_data->pdev->dev,
744 "now pumping a transfer: width is %d, len is %d\n",
745 width, transfer->len);
746
747 /*
748 * Try to map dma buffer and do a dma transfer. If successful use,
749 * different way to r/w according to the enable_dma settings and if
750 * we are not doing a full duplex transfer (since the hardware does
751 * not support full duplex DMA transfers).
752 */
753 if (!full_duplex && drv_data->cur_chip->enable_dma
754 && drv_data->len > 6) {
755
756 unsigned long dma_start_addr, flags;
757
758 disable_dma(drv_data->dma_channel);
759 clear_dma_irqstat(drv_data->dma_channel);
760
761 /* config dma channel */
762 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
763 set_dma_x_count(drv_data->dma_channel, drv_data->len);
764 if (width == CFG_SPI_WORDSIZE16) {
765 set_dma_x_modify(drv_data->dma_channel, 2);
766 dma_width = WDSIZE_16;
767 } else {
768 set_dma_x_modify(drv_data->dma_channel, 1);
769 dma_width = WDSIZE_8;
770 }
771
772 /* poll for SPI completion before start */
773 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
774 cpu_relax();
775
776 /* dirty hack for autobuffer DMA mode */
777 if (drv_data->tx_dma == 0xFFFF) {
778 dev_dbg(&drv_data->pdev->dev,
779 "doing autobuffer DMA out.\n");
780
781 /* no irq in autobuffer mode */
782 dma_config =
783 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
784 set_dma_config(drv_data->dma_channel, dma_config);
785 set_dma_start_addr(drv_data->dma_channel,
786 (unsigned long)drv_data->tx);
787 enable_dma(drv_data->dma_channel);
788
789 /* start SPI transfer */
790 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
791
792 /* just return here, there can only be one transfer
793 * in this mode
794 */
795 message->status = 0;
796 bfin_spi_giveback(drv_data);
797 return;
798 }
799
800 /* In dma mode, rx or tx must be NULL in one transfer */
801 dma_config = (RESTART | dma_width | DI_EN);
802 if (drv_data->rx != NULL) {
803 /* set transfer mode, and enable SPI */
804 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
805 drv_data->rx, drv_data->len_in_bytes);
806
807 /* invalidate caches, if needed */
808 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
809 invalidate_dcache_range((unsigned long) drv_data->rx,
810 (unsigned long) (drv_data->rx +
811 drv_data->len_in_bytes));
812
813 dma_config |= WNR;
814 dma_start_addr = (unsigned long)drv_data->rx;
815 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
816
817 } else if (drv_data->tx != NULL) {
818 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
819
820 /* flush caches, if needed */
821 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
822 flush_dcache_range((unsigned long) drv_data->tx,
823 (unsigned long) (drv_data->tx +
824 drv_data->len_in_bytes));
825
826 dma_start_addr = (unsigned long)drv_data->tx;
827 cr |= BIT_CTL_TIMOD_DMA_TX;
828
829 } else
830 BUG();
831
832 /* oh man, here there be monsters ... and i dont mean the
833 * fluffy cute ones from pixar, i mean the kind that'll eat
834 * your data, kick your dog, and love it all. do *not* try
835 * and change these lines unless you (1) heavily test DMA
836 * with SPI flashes on a loaded system (e.g. ping floods),
837 * (2) know just how broken the DMA engine interaction with
838 * the SPI peripheral is, and (3) have someone else to blame
839 * when you screw it all up anyways.
840 */
841 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
842 set_dma_config(drv_data->dma_channel, dma_config);
843 local_irq_save(flags);
844 SSYNC();
845 write_CTRL(drv_data, cr);
846 enable_dma(drv_data->dma_channel);
847 dma_enable_irq(drv_data->dma_channel);
848 local_irq_restore(flags);
849
850 } else {
851 /* IO mode write then read */
852 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
853
854 /* we always use SPI_WRITE mode. SPI_READ mode
855 seems to have problems with setting up the
856 output value in TDBR prior to the transfer. */
857 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
858
859 if (full_duplex) {
860 /* full duplex mode */
861 BUG_ON((drv_data->tx_end - drv_data->tx) !=
862 (drv_data->rx_end - drv_data->rx));
863 dev_dbg(&drv_data->pdev->dev,
864 "IO duplex: cr is 0x%x\n", cr);
865
866 drv_data->duplex(drv_data);
867
868 if (drv_data->tx != drv_data->tx_end)
869 tranf_success = 0;
870 } else if (drv_data->tx != NULL) {
871 /* write only half duplex */
872 dev_dbg(&drv_data->pdev->dev,
873 "IO write: cr is 0x%x\n", cr);
874
875 drv_data->write(drv_data);
876
877 if (drv_data->tx != drv_data->tx_end)
878 tranf_success = 0;
879 } else if (drv_data->rx != NULL) {
880 /* read only half duplex */
881 dev_dbg(&drv_data->pdev->dev,
882 "IO read: cr is 0x%x\n", cr);
883
884 drv_data->read(drv_data);
885 if (drv_data->rx != drv_data->rx_end)
886 tranf_success = 0;
887 }
888
889 if (!tranf_success) {
890 dev_dbg(&drv_data->pdev->dev,
891 "IO write error!\n");
892 message->state = ERROR_STATE;
893 } else {
894 /* Update total byte transfered */
895 message->actual_length += drv_data->len_in_bytes;
896 /* Move to next transfer of this msg */
897 message->state = bfin_spi_next_transfer(drv_data);
898 if (drv_data->cs_change)
899 bfin_spi_cs_deactive(drv_data, chip);
900 }
901 /* Schedule next transfer tasklet */
902 tasklet_schedule(&drv_data->pump_transfers);
903 }
904 }
905
906 /* pop a msg from queue and kick off real transfer */
907 static void bfin_spi_pump_messages(struct work_struct *work)
908 {
909 struct driver_data *drv_data;
910 unsigned long flags;
911
912 drv_data = container_of(work, struct driver_data, pump_messages);
913
914 /* Lock queue and check for queue work */
915 spin_lock_irqsave(&drv_data->lock, flags);
916 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
917 /* pumper kicked off but no work to do */
918 drv_data->busy = 0;
919 spin_unlock_irqrestore(&drv_data->lock, flags);
920 return;
921 }
922
923 /* Make sure we are not already running a message */
924 if (drv_data->cur_msg) {
925 spin_unlock_irqrestore(&drv_data->lock, flags);
926 return;
927 }
928
929 /* Extract head of queue */
930 drv_data->cur_msg = list_entry(drv_data->queue.next,
931 struct spi_message, queue);
932
933 /* Setup the SSP using the per chip configuration */
934 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
935 bfin_spi_restore_state(drv_data);
936
937 list_del_init(&drv_data->cur_msg->queue);
938
939 /* Initial message state */
940 drv_data->cur_msg->state = START_STATE;
941 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
942 struct spi_transfer, transfer_list);
943
944 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
945 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
946 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
947 drv_data->cur_chip->ctl_reg);
948
949 dev_dbg(&drv_data->pdev->dev,
950 "the first transfer len is %d\n",
951 drv_data->cur_transfer->len);
952
953 /* Mark as busy and launch transfers */
954 tasklet_schedule(&drv_data->pump_transfers);
955
956 drv_data->busy = 1;
957 spin_unlock_irqrestore(&drv_data->lock, flags);
958 }
959
960 /*
961 * got a msg to transfer, queue it in drv_data->queue.
962 * And kick off message pumper
963 */
964 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
965 {
966 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
967 unsigned long flags;
968
969 spin_lock_irqsave(&drv_data->lock, flags);
970
971 if (drv_data->run == QUEUE_STOPPED) {
972 spin_unlock_irqrestore(&drv_data->lock, flags);
973 return -ESHUTDOWN;
974 }
975
976 msg->actual_length = 0;
977 msg->status = -EINPROGRESS;
978 msg->state = START_STATE;
979
980 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
981 list_add_tail(&msg->queue, &drv_data->queue);
982
983 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
984 queue_work(drv_data->workqueue, &drv_data->pump_messages);
985
986 spin_unlock_irqrestore(&drv_data->lock, flags);
987
988 return 0;
989 }
990
991 #define MAX_SPI_SSEL 7
992
993 static u16 ssel[][MAX_SPI_SSEL] = {
994 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
995 P_SPI0_SSEL4, P_SPI0_SSEL5,
996 P_SPI0_SSEL6, P_SPI0_SSEL7},
997
998 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
999 P_SPI1_SSEL4, P_SPI1_SSEL5,
1000 P_SPI1_SSEL6, P_SPI1_SSEL7},
1001
1002 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1003 P_SPI2_SSEL4, P_SPI2_SSEL5,
1004 P_SPI2_SSEL6, P_SPI2_SSEL7},
1005 };
1006
1007 /* first setup for new devices */
1008 static int bfin_spi_setup(struct spi_device *spi)
1009 {
1010 struct bfin5xx_spi_chip *chip_info = NULL;
1011 struct chip_data *chip;
1012 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1013 int ret;
1014
1015 /* Abort device setup if requested features are not supported */
1016 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1017 dev_err(&spi->dev, "requested mode not fully supported\n");
1018 return -EINVAL;
1019 }
1020
1021 /* Zero (the default) here means 8 bits */
1022 if (!spi->bits_per_word)
1023 spi->bits_per_word = 8;
1024
1025 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1026 return -EINVAL;
1027
1028 /* Only alloc (or use chip_info) on first setup */
1029 chip = spi_get_ctldata(spi);
1030 if (chip == NULL) {
1031 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1032 if (!chip)
1033 return -ENOMEM;
1034
1035 chip->enable_dma = 0;
1036 chip_info = spi->controller_data;
1037 }
1038
1039 /* chip_info isn't always needed */
1040 if (chip_info) {
1041 /* Make sure people stop trying to set fields via ctl_reg
1042 * when they should actually be using common SPI framework.
1043 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1044 * Not sure if a user actually needs/uses any of these,
1045 * but let's assume (for now) they do.
1046 */
1047 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1048 dev_err(&spi->dev, "do not set bits in ctl_reg "
1049 "that the SPI framework manages\n");
1050 return -EINVAL;
1051 }
1052
1053 chip->enable_dma = chip_info->enable_dma != 0
1054 && drv_data->master_info->enable_dma;
1055 chip->ctl_reg = chip_info->ctl_reg;
1056 chip->bits_per_word = chip_info->bits_per_word;
1057 chip->cs_change_per_word = chip_info->cs_change_per_word;
1058 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1059 chip->cs_gpio = chip_info->cs_gpio;
1060 chip->idle_tx_val = chip_info->idle_tx_val;
1061 }
1062
1063 /* translate common spi framework into our register */
1064 if (spi->mode & SPI_CPOL)
1065 chip->ctl_reg |= CPOL;
1066 if (spi->mode & SPI_CPHA)
1067 chip->ctl_reg |= CPHA;
1068 if (spi->mode & SPI_LSB_FIRST)
1069 chip->ctl_reg |= LSBF;
1070 /* we dont support running in slave mode (yet?) */
1071 chip->ctl_reg |= MSTR;
1072
1073 /*
1074 * if any one SPI chip is registered and wants DMA, request the
1075 * DMA channel for it
1076 */
1077 if (chip->enable_dma && !drv_data->dma_requested) {
1078 /* register dma irq handler */
1079 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
1080 dev_dbg(&spi->dev,
1081 "Unable to request BlackFin SPI DMA channel\n");
1082 return -ENODEV;
1083 }
1084 if (set_dma_callback(drv_data->dma_channel,
1085 bfin_spi_dma_irq_handler, drv_data) < 0) {
1086 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1087 return -EPERM;
1088 }
1089 dma_disable_irq(drv_data->dma_channel);
1090 drv_data->dma_requested = 1;
1091 }
1092
1093 /*
1094 * Notice: for blackfin, the speed_hz is the value of register
1095 * SPI_BAUD, not the real baudrate
1096 */
1097 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1098 chip->flag = 1 << (spi->chip_select);
1099 chip->chip_select_num = spi->chip_select;
1100
1101 if (chip->chip_select_num == 0) {
1102 ret = gpio_request(chip->cs_gpio, spi->modalias);
1103 if (ret) {
1104 if (drv_data->dma_requested)
1105 free_dma(drv_data->dma_channel);
1106 return ret;
1107 }
1108 gpio_direction_output(chip->cs_gpio, 1);
1109 }
1110
1111 switch (chip->bits_per_word) {
1112 case 8:
1113 chip->n_bytes = 1;
1114 chip->width = CFG_SPI_WORDSIZE8;
1115 chip->read = chip->cs_change_per_word ?
1116 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
1117 chip->write = chip->cs_change_per_word ?
1118 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
1119 chip->duplex = chip->cs_change_per_word ?
1120 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
1121 break;
1122
1123 case 16:
1124 chip->n_bytes = 2;
1125 chip->width = CFG_SPI_WORDSIZE16;
1126 chip->read = chip->cs_change_per_word ?
1127 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
1128 chip->write = chip->cs_change_per_word ?
1129 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
1130 chip->duplex = chip->cs_change_per_word ?
1131 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
1132 break;
1133
1134 default:
1135 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1136 chip->bits_per_word);
1137 if (chip_info)
1138 kfree(chip);
1139 return -ENODEV;
1140 }
1141
1142 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1143 spi->modalias, chip->width, chip->enable_dma);
1144 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1145 chip->ctl_reg, chip->flag);
1146
1147 spi_set_ctldata(spi, chip);
1148
1149 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1150 if ((chip->chip_select_num > 0)
1151 && (chip->chip_select_num <= spi->master->num_chipselect))
1152 peripheral_request(ssel[spi->master->bus_num]
1153 [chip->chip_select_num-1], spi->modalias);
1154
1155 bfin_spi_cs_deactive(drv_data, chip);
1156
1157 return 0;
1158 }
1159
1160 /*
1161 * callback for spi framework.
1162 * clean driver specific data
1163 */
1164 static void bfin_spi_cleanup(struct spi_device *spi)
1165 {
1166 struct chip_data *chip = spi_get_ctldata(spi);
1167
1168 if (!chip)
1169 return;
1170
1171 if ((chip->chip_select_num > 0)
1172 && (chip->chip_select_num <= spi->master->num_chipselect))
1173 peripheral_free(ssel[spi->master->bus_num]
1174 [chip->chip_select_num-1]);
1175
1176 if (chip->chip_select_num == 0)
1177 gpio_free(chip->cs_gpio);
1178
1179 kfree(chip);
1180 }
1181
1182 static inline int bfin_spi_init_queue(struct driver_data *drv_data)
1183 {
1184 INIT_LIST_HEAD(&drv_data->queue);
1185 spin_lock_init(&drv_data->lock);
1186
1187 drv_data->run = QUEUE_STOPPED;
1188 drv_data->busy = 0;
1189
1190 /* init transfer tasklet */
1191 tasklet_init(&drv_data->pump_transfers,
1192 bfin_spi_pump_transfers, (unsigned long)drv_data);
1193
1194 /* init messages workqueue */
1195 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1196 drv_data->workqueue = create_singlethread_workqueue(
1197 dev_name(drv_data->master->dev.parent));
1198 if (drv_data->workqueue == NULL)
1199 return -EBUSY;
1200
1201 return 0;
1202 }
1203
1204 static inline int bfin_spi_start_queue(struct driver_data *drv_data)
1205 {
1206 unsigned long flags;
1207
1208 spin_lock_irqsave(&drv_data->lock, flags);
1209
1210 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1211 spin_unlock_irqrestore(&drv_data->lock, flags);
1212 return -EBUSY;
1213 }
1214
1215 drv_data->run = QUEUE_RUNNING;
1216 drv_data->cur_msg = NULL;
1217 drv_data->cur_transfer = NULL;
1218 drv_data->cur_chip = NULL;
1219 spin_unlock_irqrestore(&drv_data->lock, flags);
1220
1221 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1222
1223 return 0;
1224 }
1225
1226 static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
1227 {
1228 unsigned long flags;
1229 unsigned limit = 500;
1230 int status = 0;
1231
1232 spin_lock_irqsave(&drv_data->lock, flags);
1233
1234 /*
1235 * This is a bit lame, but is optimized for the common execution path.
1236 * A wait_queue on the drv_data->busy could be used, but then the common
1237 * execution path (pump_messages) would be required to call wake_up or
1238 * friends on every SPI message. Do this instead
1239 */
1240 drv_data->run = QUEUE_STOPPED;
1241 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1242 spin_unlock_irqrestore(&drv_data->lock, flags);
1243 msleep(10);
1244 spin_lock_irqsave(&drv_data->lock, flags);
1245 }
1246
1247 if (!list_empty(&drv_data->queue) || drv_data->busy)
1248 status = -EBUSY;
1249
1250 spin_unlock_irqrestore(&drv_data->lock, flags);
1251
1252 return status;
1253 }
1254
1255 static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
1256 {
1257 int status;
1258
1259 status = bfin_spi_stop_queue(drv_data);
1260 if (status != 0)
1261 return status;
1262
1263 destroy_workqueue(drv_data->workqueue);
1264
1265 return 0;
1266 }
1267
1268 static int __init bfin_spi_probe(struct platform_device *pdev)
1269 {
1270 struct device *dev = &pdev->dev;
1271 struct bfin5xx_spi_master *platform_info;
1272 struct spi_master *master;
1273 struct driver_data *drv_data = 0;
1274 struct resource *res;
1275 int status = 0;
1276
1277 platform_info = dev->platform_data;
1278
1279 /* Allocate master with space for drv_data */
1280 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1281 if (!master) {
1282 dev_err(&pdev->dev, "can not alloc spi_master\n");
1283 return -ENOMEM;
1284 }
1285
1286 drv_data = spi_master_get_devdata(master);
1287 drv_data->master = master;
1288 drv_data->master_info = platform_info;
1289 drv_data->pdev = pdev;
1290 drv_data->pin_req = platform_info->pin_req;
1291
1292 master->bus_num = pdev->id;
1293 master->num_chipselect = platform_info->num_chipselect;
1294 master->cleanup = bfin_spi_cleanup;
1295 master->setup = bfin_spi_setup;
1296 master->transfer = bfin_spi_transfer;
1297
1298 /* Find and map our resources */
1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 if (res == NULL) {
1301 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1302 status = -ENOENT;
1303 goto out_error_get_res;
1304 }
1305
1306 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1307 if (drv_data->regs_base == NULL) {
1308 dev_err(dev, "Cannot map IO\n");
1309 status = -ENXIO;
1310 goto out_error_ioremap;
1311 }
1312
1313 drv_data->dma_channel = platform_get_irq(pdev, 0);
1314 if (drv_data->dma_channel < 0) {
1315 dev_err(dev, "No DMA channel specified\n");
1316 status = -ENOENT;
1317 goto out_error_no_dma_ch;
1318 }
1319
1320 /* Initial and start queue */
1321 status = bfin_spi_init_queue(drv_data);
1322 if (status != 0) {
1323 dev_err(dev, "problem initializing queue\n");
1324 goto out_error_queue_alloc;
1325 }
1326
1327 status = bfin_spi_start_queue(drv_data);
1328 if (status != 0) {
1329 dev_err(dev, "problem starting queue\n");
1330 goto out_error_queue_alloc;
1331 }
1332
1333 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1334 if (status != 0) {
1335 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1336 goto out_error_queue_alloc;
1337 }
1338
1339 /* Register with the SPI framework */
1340 platform_set_drvdata(pdev, drv_data);
1341 status = spi_register_master(master);
1342 if (status != 0) {
1343 dev_err(dev, "problem registering spi master\n");
1344 goto out_error_queue_alloc;
1345 }
1346
1347 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1348 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1349 drv_data->dma_channel);
1350 return status;
1351
1352 out_error_queue_alloc:
1353 bfin_spi_destroy_queue(drv_data);
1354 out_error_no_dma_ch:
1355 iounmap((void *) drv_data->regs_base);
1356 out_error_ioremap:
1357 out_error_get_res:
1358 spi_master_put(master);
1359
1360 return status;
1361 }
1362
1363 /* stop hardware and remove the driver */
1364 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1365 {
1366 struct driver_data *drv_data = platform_get_drvdata(pdev);
1367 int status = 0;
1368
1369 if (!drv_data)
1370 return 0;
1371
1372 /* Remove the queue */
1373 status = bfin_spi_destroy_queue(drv_data);
1374 if (status != 0)
1375 return status;
1376
1377 /* Disable the SSP at the peripheral and SOC level */
1378 bfin_spi_disable(drv_data);
1379
1380 /* Release DMA */
1381 if (drv_data->master_info->enable_dma) {
1382 if (dma_channel_active(drv_data->dma_channel))
1383 free_dma(drv_data->dma_channel);
1384 }
1385
1386 /* Disconnect from the SPI framework */
1387 spi_unregister_master(drv_data->master);
1388
1389 peripheral_free_list(drv_data->pin_req);
1390
1391 /* Prevent double remove */
1392 platform_set_drvdata(pdev, NULL);
1393
1394 return 0;
1395 }
1396
1397 #ifdef CONFIG_PM
1398 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1399 {
1400 struct driver_data *drv_data = platform_get_drvdata(pdev);
1401 int status = 0;
1402
1403 status = bfin_spi_stop_queue(drv_data);
1404 if (status != 0)
1405 return status;
1406
1407 /* stop hardware */
1408 bfin_spi_disable(drv_data);
1409
1410 return 0;
1411 }
1412
1413 static int bfin_spi_resume(struct platform_device *pdev)
1414 {
1415 struct driver_data *drv_data = platform_get_drvdata(pdev);
1416 int status = 0;
1417
1418 /* Enable the SPI interface */
1419 bfin_spi_enable(drv_data);
1420
1421 /* Start the queue running */
1422 status = bfin_spi_start_queue(drv_data);
1423 if (status != 0) {
1424 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1425 return status;
1426 }
1427
1428 return 0;
1429 }
1430 #else
1431 #define bfin_spi_suspend NULL
1432 #define bfin_spi_resume NULL
1433 #endif /* CONFIG_PM */
1434
1435 MODULE_ALIAS("platform:bfin-spi");
1436 static struct platform_driver bfin_spi_driver = {
1437 .driver = {
1438 .name = DRV_NAME,
1439 .owner = THIS_MODULE,
1440 },
1441 .suspend = bfin_spi_suspend,
1442 .resume = bfin_spi_resume,
1443 .remove = __devexit_p(bfin_spi_remove),
1444 };
1445
1446 static int __init bfin_spi_init(void)
1447 {
1448 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1449 }
1450 module_init(bfin_spi_init);
1451
1452 static void __exit bfin_spi_exit(void)
1453 {
1454 platform_driver_unregister(&bfin_spi_driver);
1455 }
1456 module_exit(bfin_spi_exit);
Support for the Chinese Samsung S3C2440 based development boards