2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2008 MontaVista Software, Inc.
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
20 * Note that final HPT370 support was done by force extraction of GPL.
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * Alan Cox <alan@lxorguk.ukuu.org.uk>
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
122 #include <linux/types.h>
123 #include <linux/module.h>
124 #include <linux/kernel.h>
125 #include <linux/delay.h>
126 #include <linux/blkdev.h>
127 #include <linux/interrupt.h>
128 #include <linux/pci.h>
129 #include <linux/init.h>
130 #include <linux/ide.h>
132 #include <asm/uaccess.h>
135 #define DRV_NAME "hpt366"
137 /* various tuning parameters */
138 #undef HPT_RESET_STATE_ENGINE
139 #undef HPT_DELAY_INTERRUPT
141 static const char *quirk_drives
[] = {
142 "QUANTUM FIREBALLlct08 08",
143 "QUANTUM FIREBALLP KA6.4",
144 "QUANTUM FIREBALLP LM20.4",
145 "QUANTUM FIREBALLP LM20.5",
149 static const char *bad_ata100_5
[] = {
168 static const char *bad_ata66_4
[] = {
184 "MAXTOR STM3320620A",
188 static const char *bad_ata66_3
[] = {
193 static const char *bad_ata33
[] = {
194 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
195 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
196 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
198 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
199 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
200 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
204 static u8 xfer_speeds
[] = {
224 /* Key for bus clock timings
227 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
229 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
231 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
233 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
235 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
236 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
237 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
239 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
240 * task file register access.
243 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
248 static u32 forty_base_hpt36x
[] = {
249 /* XFER_UDMA_6 */ 0x900fd943,
250 /* XFER_UDMA_5 */ 0x900fd943,
251 /* XFER_UDMA_4 */ 0x900fd943,
252 /* XFER_UDMA_3 */ 0x900ad943,
253 /* XFER_UDMA_2 */ 0x900bd943,
254 /* XFER_UDMA_1 */ 0x9008d943,
255 /* XFER_UDMA_0 */ 0x9008d943,
257 /* XFER_MW_DMA_2 */ 0xa008d943,
258 /* XFER_MW_DMA_1 */ 0xa010d955,
259 /* XFER_MW_DMA_0 */ 0xa010d9fc,
261 /* XFER_PIO_4 */ 0xc008d963,
262 /* XFER_PIO_3 */ 0xc010d974,
263 /* XFER_PIO_2 */ 0xc010d997,
264 /* XFER_PIO_1 */ 0xc010d9c7,
265 /* XFER_PIO_0 */ 0xc018d9d9
268 static u32 thirty_three_base_hpt36x
[] = {
269 /* XFER_UDMA_6 */ 0x90c9a731,
270 /* XFER_UDMA_5 */ 0x90c9a731,
271 /* XFER_UDMA_4 */ 0x90c9a731,
272 /* XFER_UDMA_3 */ 0x90cfa731,
273 /* XFER_UDMA_2 */ 0x90caa731,
274 /* XFER_UDMA_1 */ 0x90cba731,
275 /* XFER_UDMA_0 */ 0x90c8a731,
277 /* XFER_MW_DMA_2 */ 0xa0c8a731,
278 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
279 /* XFER_MW_DMA_0 */ 0xa0c8a797,
281 /* XFER_PIO_4 */ 0xc0c8a731,
282 /* XFER_PIO_3 */ 0xc0c8a742,
283 /* XFER_PIO_2 */ 0xc0d0a753,
284 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
285 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
288 static u32 twenty_five_base_hpt36x
[] = {
289 /* XFER_UDMA_6 */ 0x90c98521,
290 /* XFER_UDMA_5 */ 0x90c98521,
291 /* XFER_UDMA_4 */ 0x90c98521,
292 /* XFER_UDMA_3 */ 0x90cf8521,
293 /* XFER_UDMA_2 */ 0x90cf8521,
294 /* XFER_UDMA_1 */ 0x90cb8521,
295 /* XFER_UDMA_0 */ 0x90cb8521,
297 /* XFER_MW_DMA_2 */ 0xa0ca8521,
298 /* XFER_MW_DMA_1 */ 0xa0ca8532,
299 /* XFER_MW_DMA_0 */ 0xa0ca8575,
301 /* XFER_PIO_4 */ 0xc0ca8521,
302 /* XFER_PIO_3 */ 0xc0ca8532,
303 /* XFER_PIO_2 */ 0xc0ca8542,
304 /* XFER_PIO_1 */ 0xc0d08572,
305 /* XFER_PIO_0 */ 0xc0d08585
309 /* These are the timing tables from the HighPoint open source drivers... */
310 static u32 thirty_three_base_hpt37x
[] = {
311 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
312 /* XFER_UDMA_5 */ 0x12446231,
313 /* XFER_UDMA_4 */ 0x12446231,
314 /* XFER_UDMA_3 */ 0x126c6231,
315 /* XFER_UDMA_2 */ 0x12486231,
316 /* XFER_UDMA_1 */ 0x124c6233,
317 /* XFER_UDMA_0 */ 0x12506297,
319 /* XFER_MW_DMA_2 */ 0x22406c31,
320 /* XFER_MW_DMA_1 */ 0x22406c33,
321 /* XFER_MW_DMA_0 */ 0x22406c97,
323 /* XFER_PIO_4 */ 0x06414e31,
324 /* XFER_PIO_3 */ 0x06414e42,
325 /* XFER_PIO_2 */ 0x06414e53,
326 /* XFER_PIO_1 */ 0x06814e93,
327 /* XFER_PIO_0 */ 0x06814ea7
330 static u32 fifty_base_hpt37x
[] = {
331 /* XFER_UDMA_6 */ 0x12848242,
332 /* XFER_UDMA_5 */ 0x12848242,
333 /* XFER_UDMA_4 */ 0x12ac8242,
334 /* XFER_UDMA_3 */ 0x128c8242,
335 /* XFER_UDMA_2 */ 0x120c8242,
336 /* XFER_UDMA_1 */ 0x12148254,
337 /* XFER_UDMA_0 */ 0x121882ea,
339 /* XFER_MW_DMA_2 */ 0x22808242,
340 /* XFER_MW_DMA_1 */ 0x22808254,
341 /* XFER_MW_DMA_0 */ 0x228082ea,
343 /* XFER_PIO_4 */ 0x0a81f442,
344 /* XFER_PIO_3 */ 0x0a81f443,
345 /* XFER_PIO_2 */ 0x0a81f454,
346 /* XFER_PIO_1 */ 0x0ac1f465,
347 /* XFER_PIO_0 */ 0x0ac1f48a
350 static u32 sixty_six_base_hpt37x
[] = {
351 /* XFER_UDMA_6 */ 0x1c869c62,
352 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
353 /* XFER_UDMA_4 */ 0x1c8a9c62,
354 /* XFER_UDMA_3 */ 0x1c8e9c62,
355 /* XFER_UDMA_2 */ 0x1c929c62,
356 /* XFER_UDMA_1 */ 0x1c9a9c62,
357 /* XFER_UDMA_0 */ 0x1c829c62,
359 /* XFER_MW_DMA_2 */ 0x2c829c62,
360 /* XFER_MW_DMA_1 */ 0x2c829c66,
361 /* XFER_MW_DMA_0 */ 0x2c829d2e,
363 /* XFER_PIO_4 */ 0x0c829c62,
364 /* XFER_PIO_3 */ 0x0c829c84,
365 /* XFER_PIO_2 */ 0x0c829ca6,
366 /* XFER_PIO_1 */ 0x0d029d26,
367 /* XFER_PIO_0 */ 0x0d029d5e
371 * The following are the new timing tables with PIO mode data/taskfile transfer
372 * overclocking fixed...
375 /* This table is taken from the HPT370 data manual rev. 1.02 */
376 static u32 thirty_three_base_hpt37x
[] = {
377 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
378 /* XFER_UDMA_5 */ 0x16455031,
379 /* XFER_UDMA_4 */ 0x16455031,
380 /* XFER_UDMA_3 */ 0x166d5031,
381 /* XFER_UDMA_2 */ 0x16495031,
382 /* XFER_UDMA_1 */ 0x164d5033,
383 /* XFER_UDMA_0 */ 0x16515097,
385 /* XFER_MW_DMA_2 */ 0x26515031,
386 /* XFER_MW_DMA_1 */ 0x26515033,
387 /* XFER_MW_DMA_0 */ 0x26515097,
389 /* XFER_PIO_4 */ 0x06515021,
390 /* XFER_PIO_3 */ 0x06515022,
391 /* XFER_PIO_2 */ 0x06515033,
392 /* XFER_PIO_1 */ 0x06915065,
393 /* XFER_PIO_0 */ 0x06d1508a
396 static u32 fifty_base_hpt37x
[] = {
397 /* XFER_UDMA_6 */ 0x1a861842,
398 /* XFER_UDMA_5 */ 0x1a861842,
399 /* XFER_UDMA_4 */ 0x1aae1842,
400 /* XFER_UDMA_3 */ 0x1a8e1842,
401 /* XFER_UDMA_2 */ 0x1a0e1842,
402 /* XFER_UDMA_1 */ 0x1a161854,
403 /* XFER_UDMA_0 */ 0x1a1a18ea,
405 /* XFER_MW_DMA_2 */ 0x2a821842,
406 /* XFER_MW_DMA_1 */ 0x2a821854,
407 /* XFER_MW_DMA_0 */ 0x2a8218ea,
409 /* XFER_PIO_4 */ 0x0a821842,
410 /* XFER_PIO_3 */ 0x0a821843,
411 /* XFER_PIO_2 */ 0x0a821855,
412 /* XFER_PIO_1 */ 0x0ac218a8,
413 /* XFER_PIO_0 */ 0x0b02190c
416 static u32 sixty_six_base_hpt37x
[] = {
417 /* XFER_UDMA_6 */ 0x1c86fe62,
418 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
419 /* XFER_UDMA_4 */ 0x1c8afe62,
420 /* XFER_UDMA_3 */ 0x1c8efe62,
421 /* XFER_UDMA_2 */ 0x1c92fe62,
422 /* XFER_UDMA_1 */ 0x1c9afe62,
423 /* XFER_UDMA_0 */ 0x1c82fe62,
425 /* XFER_MW_DMA_2 */ 0x2c82fe62,
426 /* XFER_MW_DMA_1 */ 0x2c82fe66,
427 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
429 /* XFER_PIO_4 */ 0x0c82fe62,
430 /* XFER_PIO_3 */ 0x0c82fe84,
431 /* XFER_PIO_2 */ 0x0c82fea6,
432 /* XFER_PIO_1 */ 0x0d02ff26,
433 /* XFER_PIO_0 */ 0x0d42ff7f
437 #define HPT366_DEBUG_DRIVE_INFO 0
438 #define HPT371_ALLOW_ATA133_6 1
439 #define HPT302_ALLOW_ATA133_6 1
440 #define HPT372_ALLOW_ATA133_6 1
441 #define HPT370_ALLOW_ATA100_5 0
442 #define HPT366_ALLOW_ATA66_4 1
443 #define HPT366_ALLOW_ATA66_3 1
444 #define HPT366_MAX_DEVS 8
446 /* Supported ATA clock frequencies */
460 u32
*clock_table
[NUM_ATA_CLOCKS
];
464 * Hold all the HighPoint chip information in one place.
468 char *chip_name
; /* Chip name */
469 u8 chip_type
; /* Chip type */
470 u8 udma_mask
; /* Allowed UltraDMA modes mask. */
471 u8 dpll_clk
; /* DPLL clock in MHz */
472 u8 pci_clk
; /* PCI clock in MHz */
473 struct hpt_timings
*timings
; /* Chipset timing data */
474 u8 clock
; /* ATA clock selected */
477 /* Supported HighPoint chips */
492 static struct hpt_timings hpt36x_timings
= {
493 .pio_mask
= 0xc1f8ffff,
494 .dma_mask
= 0x303800ff,
495 .ultra_mask
= 0x30070000,
497 [ATA_CLOCK_25MHZ
] = twenty_five_base_hpt36x
,
498 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt36x
,
499 [ATA_CLOCK_40MHZ
] = forty_base_hpt36x
,
500 [ATA_CLOCK_50MHZ
] = NULL
,
501 [ATA_CLOCK_66MHZ
] = NULL
505 static struct hpt_timings hpt37x_timings
= {
506 .pio_mask
= 0xcfc3ffff,
507 .dma_mask
= 0x31c001ff,
508 .ultra_mask
= 0x303c0000,
510 [ATA_CLOCK_25MHZ
] = NULL
,
511 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt37x
,
512 [ATA_CLOCK_40MHZ
] = NULL
,
513 [ATA_CLOCK_50MHZ
] = fifty_base_hpt37x
,
514 [ATA_CLOCK_66MHZ
] = sixty_six_base_hpt37x
518 static const struct hpt_info hpt36x __devinitdata
= {
519 .chip_name
= "HPT36x",
521 .udma_mask
= HPT366_ALLOW_ATA66_3
? (HPT366_ALLOW_ATA66_4
? ATA_UDMA4
: ATA_UDMA3
) : ATA_UDMA2
,
522 .dpll_clk
= 0, /* no DPLL */
523 .timings
= &hpt36x_timings
526 static const struct hpt_info hpt370 __devinitdata
= {
527 .chip_name
= "HPT370",
529 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
531 .timings
= &hpt37x_timings
534 static const struct hpt_info hpt370a __devinitdata
= {
535 .chip_name
= "HPT370A",
536 .chip_type
= HPT370A
,
537 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
539 .timings
= &hpt37x_timings
542 static const struct hpt_info hpt374 __devinitdata
= {
543 .chip_name
= "HPT374",
545 .udma_mask
= ATA_UDMA5
,
547 .timings
= &hpt37x_timings
550 static const struct hpt_info hpt372 __devinitdata
= {
551 .chip_name
= "HPT372",
553 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
555 .timings
= &hpt37x_timings
558 static const struct hpt_info hpt372a __devinitdata
= {
559 .chip_name
= "HPT372A",
560 .chip_type
= HPT372A
,
561 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
563 .timings
= &hpt37x_timings
566 static const struct hpt_info hpt302 __devinitdata
= {
567 .chip_name
= "HPT302",
569 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
571 .timings
= &hpt37x_timings
574 static const struct hpt_info hpt371 __devinitdata
= {
575 .chip_name
= "HPT371",
577 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
579 .timings
= &hpt37x_timings
582 static const struct hpt_info hpt372n __devinitdata
= {
583 .chip_name
= "HPT372N",
584 .chip_type
= HPT372N
,
585 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
587 .timings
= &hpt37x_timings
590 static const struct hpt_info hpt302n __devinitdata
= {
591 .chip_name
= "HPT302N",
592 .chip_type
= HPT302N
,
593 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
595 .timings
= &hpt37x_timings
598 static const struct hpt_info hpt371n __devinitdata
= {
599 .chip_name
= "HPT371N",
600 .chip_type
= HPT371N
,
601 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
603 .timings
= &hpt37x_timings
606 static int check_in_drive_list(ide_drive_t
*drive
, const char **list
)
608 char *m
= (char *)&drive
->id
[ATA_ID_PROD
];
611 if (!strcmp(*list
++, m
))
616 static struct hpt_info
*hpt3xx_get_info(struct device
*dev
)
618 struct ide_host
*host
= dev_get_drvdata(dev
);
619 struct hpt_info
*info
= (struct hpt_info
*)host
->host_priv
;
621 return dev
== host
->dev
[1] ? info
+ 1 : info
;
625 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
626 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
629 static u8
hpt3xx_udma_filter(ide_drive_t
*drive
)
631 ide_hwif_t
*hwif
= drive
->hwif
;
632 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
633 u8 mask
= hwif
->ultra_mask
;
635 switch (info
->chip_type
) {
637 if (!HPT366_ALLOW_ATA66_4
||
638 check_in_drive_list(drive
, bad_ata66_4
))
641 if (!HPT366_ALLOW_ATA66_3
||
642 check_in_drive_list(drive
, bad_ata66_3
))
646 if (!HPT370_ALLOW_ATA100_5
||
647 check_in_drive_list(drive
, bad_ata100_5
))
651 if (!HPT370_ALLOW_ATA100_5
||
652 check_in_drive_list(drive
, bad_ata100_5
))
658 if (ata_id_is_sata(drive
->id
))
665 return check_in_drive_list(drive
, bad_ata33
) ? 0x00 : mask
;
668 static u8
hpt3xx_mdma_filter(ide_drive_t
*drive
)
670 ide_hwif_t
*hwif
= drive
->hwif
;
671 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
673 switch (info
->chip_type
) {
678 if (ata_id_is_sata(drive
->id
))
686 static u32
get_speed_setting(u8 speed
, struct hpt_info
*info
)
691 * Lookup the transfer mode table to get the index into
694 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
696 for (i
= 0; i
< ARRAY_SIZE(xfer_speeds
) - 1; i
++)
697 if (xfer_speeds
[i
] == speed
)
700 return info
->timings
->clock_table
[info
->clock
][i
];
703 static void hpt3xx_set_mode(ide_drive_t
*drive
, const u8 speed
)
705 ide_hwif_t
*hwif
= drive
->hwif
;
706 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
707 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
708 struct hpt_timings
*t
= info
->timings
;
709 u8 itr_addr
= 0x40 + (drive
->dn
* 4);
711 u32 new_itr
= get_speed_setting(speed
, info
);
712 u32 itr_mask
= speed
< XFER_MW_DMA_0
? t
->pio_mask
:
713 (speed
< XFER_UDMA_0
? t
->dma_mask
:
716 pci_read_config_dword(dev
, itr_addr
, &old_itr
);
717 new_itr
= (old_itr
& ~itr_mask
) | (new_itr
& itr_mask
);
719 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
720 * to avoid problems handling I/O errors later
722 new_itr
&= ~0xc0000000;
724 pci_write_config_dword(dev
, itr_addr
, new_itr
);
727 static void hpt3xx_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
729 hpt3xx_set_mode(drive
, XFER_PIO_0
+ pio
);
732 static void hpt3xx_quirkproc(ide_drive_t
*drive
)
734 char *m
= (char *)&drive
->id
[ATA_ID_PROD
];
735 const char **list
= quirk_drives
;
738 if (strstr(m
, *list
++)) {
739 drive
->quirk_list
= 1;
743 drive
->quirk_list
= 0;
746 static void hpt3xx_maskproc(ide_drive_t
*drive
, int mask
)
748 ide_hwif_t
*hwif
= drive
->hwif
;
749 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
750 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
752 if (drive
->quirk_list
== 0)
755 if (info
->chip_type
>= HPT370
) {
758 pci_read_config_byte(dev
, 0x5a, &scr1
);
759 if (((scr1
& 0x10) >> 4) != mask
) {
764 pci_write_config_byte(dev
, 0x5a, scr1
);
767 disable_irq(hwif
->irq
);
769 enable_irq(hwif
->irq
);
773 * This is specific to the HPT366 UDMA chipset
774 * by HighPoint|Triones Technologies, Inc.
776 static void hpt366_dma_lost_irq(ide_drive_t
*drive
)
778 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
779 u8 mcr1
= 0, mcr3
= 0, scr1
= 0;
781 pci_read_config_byte(dev
, 0x50, &mcr1
);
782 pci_read_config_byte(dev
, 0x52, &mcr3
);
783 pci_read_config_byte(dev
, 0x5a, &scr1
);
784 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
785 drive
->name
, __func__
, mcr1
, mcr3
, scr1
);
787 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
788 ide_dma_lost_irq(drive
);
791 static void hpt370_clear_engine(ide_drive_t
*drive
)
793 ide_hwif_t
*hwif
= drive
->hwif
;
794 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
796 pci_write_config_byte(dev
, hwif
->select_data
, 0x37);
800 static void hpt370_irq_timeout(ide_drive_t
*drive
)
802 ide_hwif_t
*hwif
= drive
->hwif
;
803 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
807 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
808 printk(KERN_DEBUG
"%s: %d bytes in FIFO\n", drive
->name
, bfifo
& 0x1ff);
810 /* get DMA command mode */
811 dma_cmd
= inb(hwif
->dma_base
+ ATA_DMA_CMD
);
813 outb(dma_cmd
& ~0x1, hwif
->dma_base
+ ATA_DMA_CMD
);
814 hpt370_clear_engine(drive
);
817 static void hpt370_dma_start(ide_drive_t
*drive
)
819 #ifdef HPT_RESET_STATE_ENGINE
820 hpt370_clear_engine(drive
);
822 ide_dma_start(drive
);
825 static int hpt370_dma_end(ide_drive_t
*drive
)
827 ide_hwif_t
*hwif
= drive
->hwif
;
828 u8 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
830 if (dma_stat
& 0x01) {
833 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
835 hpt370_irq_timeout(drive
);
837 return ide_dma_end(drive
);
840 static void hpt370_dma_timeout(ide_drive_t
*drive
)
842 hpt370_irq_timeout(drive
);
843 ide_dma_timeout(drive
);
846 /* returns 1 if DMA IRQ issued, 0 otherwise */
847 static int hpt374_dma_test_irq(ide_drive_t
*drive
)
849 ide_hwif_t
*hwif
= drive
->hwif
;
850 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
854 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
856 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
860 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
861 /* return 1 if INTR asserted */
868 static int hpt374_dma_end(ide_drive_t
*drive
)
870 ide_hwif_t
*hwif
= drive
->hwif
;
871 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
872 u8 mcr
= 0, mcr_addr
= hwif
->select_data
;
873 u8 bwsr
= 0, mask
= hwif
->channel
? 0x02 : 0x01;
875 pci_read_config_byte(dev
, 0x6a, &bwsr
);
876 pci_read_config_byte(dev
, mcr_addr
, &mcr
);
878 pci_write_config_byte(dev
, mcr_addr
, mcr
| 0x30);
879 return ide_dma_end(drive
);
883 * hpt3xxn_set_clock - perform clock switching dance
884 * @hwif: hwif to switch
885 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
887 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
890 static void hpt3xxn_set_clock(ide_hwif_t
*hwif
, u8 mode
)
892 unsigned long base
= hwif
->extra_base
;
893 u8 scr2
= inb(base
+ 0x6b);
895 if ((scr2
& 0x7f) == mode
)
898 /* Tristate the bus */
899 outb(0x80, base
+ 0x63);
900 outb(0x80, base
+ 0x67);
902 /* Switch clock and reset channels */
903 outb(mode
, base
+ 0x6b);
904 outb(0xc0, base
+ 0x69);
907 * Reset the state machines.
908 * NOTE: avoid accidentally enabling the disabled channels.
910 outb(inb(base
+ 0x60) | 0x32, base
+ 0x60);
911 outb(inb(base
+ 0x64) | 0x32, base
+ 0x64);
914 outb(0x00, base
+ 0x69);
916 /* Reconnect channels to bus */
917 outb(0x00, base
+ 0x63);
918 outb(0x00, base
+ 0x67);
922 * hpt3xxn_rw_disk - prepare for I/O
923 * @drive: drive for command
924 * @rq: block request structure
926 * This is called when a disk I/O is issued to HPT3xxN.
927 * We need it because of the clock switching.
930 static void hpt3xxn_rw_disk(ide_drive_t
*drive
, struct request
*rq
)
932 hpt3xxn_set_clock(drive
->hwif
, rq_data_dir(rq
) ? 0x23 : 0x21);
936 * hpt37x_calibrate_dpll - calibrate the DPLL
939 * Perform a calibration cycle on the DPLL.
940 * Returns 1 if this succeeds
942 static int hpt37x_calibrate_dpll(struct pci_dev
*dev
, u16 f_low
, u16 f_high
)
944 u32 dpll
= (f_high
<< 16) | f_low
| 0x100;
948 pci_write_config_dword(dev
, 0x5c, dpll
);
950 /* Wait for oscillator ready */
951 for(i
= 0; i
< 0x5000; ++i
) {
953 pci_read_config_byte(dev
, 0x5b, &scr2
);
957 /* See if it stays ready (we'll just bail out if it's not yet) */
958 for(i
= 0; i
< 0x1000; ++i
) {
959 pci_read_config_byte(dev
, 0x5b, &scr2
);
960 /* DPLL destabilized? */
964 /* Turn off tuning, we have the DPLL set */
965 pci_read_config_dword (dev
, 0x5c, &dpll
);
966 pci_write_config_dword(dev
, 0x5c, (dpll
& ~0x100));
970 static void hpt3xx_disable_fast_irq(struct pci_dev
*dev
, u8 mcr_addr
)
972 struct ide_host
*host
= pci_get_drvdata(dev
);
973 struct hpt_info
*info
= host
->host_priv
+ (&dev
->dev
== host
->dev
[1]);
974 u8 chip_type
= info
->chip_type
;
975 u8 new_mcr
, old_mcr
= 0;
978 * Disable the "fast interrupt" prediction. Don't hold off
979 * on interrupts. (== 0x01 despite what the docs say)
981 pci_read_config_byte(dev
, mcr_addr
+ 1, &old_mcr
);
983 if (chip_type
>= HPT374
)
984 new_mcr
= old_mcr
& ~0x07;
985 else if (chip_type
>= HPT370
) {
988 #ifdef HPT_DELAY_INTERRUPT
993 } else /* HPT366 and HPT368 */
994 new_mcr
= old_mcr
& ~0x80;
996 if (new_mcr
!= old_mcr
)
997 pci_write_config_byte(dev
, mcr_addr
+ 1, new_mcr
);
1000 static unsigned int init_chipset_hpt366(struct pci_dev
*dev
)
1002 unsigned long io_base
= pci_resource_start(dev
, 4);
1003 struct hpt_info
*info
= hpt3xx_get_info(&dev
->dev
);
1004 const char *name
= DRV_NAME
;
1005 u8 pci_clk
, dpll_clk
= 0; /* PCI and DPLL clock in MHz */
1007 enum ata_clock clock
;
1009 chip_type
= info
->chip_type
;
1011 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (L1_CACHE_BYTES
/ 4));
1012 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x78);
1013 pci_write_config_byte(dev
, PCI_MIN_GNT
, 0x08);
1014 pci_write_config_byte(dev
, PCI_MAX_LAT
, 0x08);
1017 * First, try to estimate the PCI clock frequency...
1019 if (chip_type
>= HPT370
) {
1024 /* Interrupt force enable. */
1025 pci_read_config_byte(dev
, 0x5a, &scr1
);
1027 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
1030 * HighPoint does this for HPT372A.
1031 * NOTE: This register is only writeable via I/O space.
1033 if (chip_type
== HPT372A
)
1034 outb(0x0e, io_base
+ 0x9c);
1037 * Default to PCI clock. Make sure MA15/16 are set to output
1038 * to prevent drives having problems with 40-pin cables.
1040 pci_write_config_byte(dev
, 0x5b, 0x23);
1043 * We'll have to read f_CNT value in order to determine
1044 * the PCI clock frequency according to the following ratio:
1046 * f_CNT = Fpci * 192 / Fdpll
1048 * First try reading the register in which the HighPoint BIOS
1049 * saves f_CNT value before reprogramming the DPLL from its
1050 * default setting (which differs for the various chips).
1052 * NOTE: This register is only accessible via I/O space;
1053 * HPT374 BIOS only saves it for the function 0, so we have to
1054 * always read it from there -- no need to check the result of
1055 * pci_get_slot() for the function 0 as the whole device has
1056 * been already "pinned" (via function 1) in init_setup_hpt374()
1058 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1059 struct pci_dev
*dev1
= pci_get_slot(dev
->bus
,
1061 unsigned long io_base
= pci_resource_start(dev1
, 4);
1063 temp
= inl(io_base
+ 0x90);
1066 temp
= inl(io_base
+ 0x90);
1069 * In case the signature check fails, we'll have to
1070 * resort to reading the f_CNT register itself in hopes
1071 * that nobody has touched the DPLL yet...
1073 if ((temp
& 0xFFFFF000) != 0xABCDE000) {
1076 printk(KERN_WARNING
"%s %s: no clock data saved by "
1077 "BIOS\n", name
, pci_name(dev
));
1079 /* Calculate the average value of f_CNT. */
1080 for (temp
= i
= 0; i
< 128; i
++) {
1081 pci_read_config_word(dev
, 0x78, &f_cnt
);
1082 temp
+= f_cnt
& 0x1ff;
1087 f_cnt
= temp
& 0x1ff;
1089 dpll_clk
= info
->dpll_clk
;
1090 pci_clk
= (f_cnt
* dpll_clk
) / 192;
1092 /* Clamp PCI clock to bands. */
1095 else if(pci_clk
< 45)
1097 else if(pci_clk
< 55)
1102 printk(KERN_INFO
"%s %s: DPLL base: %d MHz, f_CNT: %d, "
1103 "assuming %d MHz PCI\n", name
, pci_name(dev
),
1104 dpll_clk
, f_cnt
, pci_clk
);
1108 pci_read_config_dword(dev
, 0x40, &itr1
);
1110 /* Detect PCI clock by looking at cmd_high_time. */
1111 switch((itr1
>> 8) & 0x07) {
1125 /* Let's assume we'll use PCI clock for the ATA clock... */
1128 clock
= ATA_CLOCK_25MHZ
;
1132 clock
= ATA_CLOCK_33MHZ
;
1135 clock
= ATA_CLOCK_40MHZ
;
1138 clock
= ATA_CLOCK_50MHZ
;
1141 clock
= ATA_CLOCK_66MHZ
;
1146 * Only try the DPLL if we don't have a table for the PCI clock that
1147 * we are running at for HPT370/A, always use it for anything newer...
1149 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1150 * We also don't like using the DPLL because this causes glitches
1151 * on PRST-/SRST- when the state engine gets reset...
1153 if (chip_type
>= HPT374
|| info
->timings
->clock_table
[clock
] == NULL
) {
1154 u16 f_low
, delta
= pci_clk
< 50 ? 2 : 4;
1158 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1159 * supported/enabled, use 50 MHz DPLL clock otherwise...
1161 if (info
->udma_mask
== ATA_UDMA6
) {
1163 clock
= ATA_CLOCK_66MHZ
;
1164 } else if (dpll_clk
) { /* HPT36x chips don't have DPLL */
1166 clock
= ATA_CLOCK_50MHZ
;
1169 if (info
->timings
->clock_table
[clock
] == NULL
) {
1170 printk(KERN_ERR
"%s %s: unknown bus timing!\n",
1171 name
, pci_name(dev
));
1175 /* Select the DPLL clock. */
1176 pci_write_config_byte(dev
, 0x5b, 0x21);
1179 * Adjust the DPLL based upon PCI clock, enable it,
1180 * and wait for stabilization...
1182 f_low
= (pci_clk
* 48) / dpll_clk
;
1184 for (adjust
= 0; adjust
< 8; adjust
++) {
1185 if(hpt37x_calibrate_dpll(dev
, f_low
, f_low
+ delta
))
1189 * See if it'll settle at a fractionally different clock
1192 f_low
-= adjust
>> 1;
1194 f_low
+= adjust
>> 1;
1197 printk(KERN_ERR
"%s %s: DPLL did not stabilize!\n",
1198 name
, pci_name(dev
));
1202 printk(KERN_INFO
"%s %s: using %d MHz DPLL clock\n",
1203 name
, pci_name(dev
), dpll_clk
);
1205 /* Mark the fact that we're not using the DPLL. */
1208 printk(KERN_INFO
"%s %s: using %d MHz PCI clock\n",
1209 name
, pci_name(dev
), pci_clk
);
1212 /* Store the clock frequencies. */
1213 info
->dpll_clk
= dpll_clk
;
1214 info
->pci_clk
= pci_clk
;
1215 info
->clock
= clock
;
1217 if (chip_type
>= HPT370
) {
1221 * Reset the state engines.
1222 * NOTE: Avoid accidentally enabling the disabled channels.
1224 pci_read_config_byte (dev
, 0x50, &mcr1
);
1225 pci_read_config_byte (dev
, 0x54, &mcr4
);
1226 pci_write_config_byte(dev
, 0x50, (mcr1
| 0x32));
1227 pci_write_config_byte(dev
, 0x54, (mcr4
| 0x32));
1232 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1233 * the MISC. register to stretch the UltraDMA Tss timing.
1234 * NOTE: This register is only writeable via I/O space.
1236 if (chip_type
== HPT371N
&& clock
== ATA_CLOCK_66MHZ
)
1237 outb(inb(io_base
+ 0x9c) | 0x04, io_base
+ 0x9c);
1239 hpt3xx_disable_fast_irq(dev
, 0x50);
1240 hpt3xx_disable_fast_irq(dev
, 0x54);
1245 static u8
hpt3xx_cable_detect(ide_hwif_t
*hwif
)
1247 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1248 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
1249 u8 chip_type
= info
->chip_type
;
1250 u8 scr1
= 0, ata66
= hwif
->channel
? 0x01 : 0x02;
1253 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1254 * address lines to access an external EEPROM. To read valid
1255 * cable detect state the pins must be enabled as inputs.
1257 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1259 * HPT374 PCI function 1
1260 * - set bit 15 of reg 0x52 to enable TCBLID as input
1261 * - set bit 15 of reg 0x56 to enable FCBLID as input
1263 u8 mcr_addr
= hwif
->select_data
+ 2;
1266 pci_read_config_word(dev
, mcr_addr
, &mcr
);
1267 pci_write_config_word(dev
, mcr_addr
, (mcr
| 0x8000));
1268 /* now read cable id register */
1269 pci_read_config_byte(dev
, 0x5a, &scr1
);
1270 pci_write_config_word(dev
, mcr_addr
, mcr
);
1271 } else if (chip_type
>= HPT370
) {
1273 * HPT370/372 and 374 pcifn 0
1274 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1278 pci_read_config_byte(dev
, 0x5b, &scr2
);
1279 pci_write_config_byte(dev
, 0x5b, (scr2
& ~1));
1280 /* now read cable id register */
1281 pci_read_config_byte(dev
, 0x5a, &scr1
);
1282 pci_write_config_byte(dev
, 0x5b, scr2
);
1284 pci_read_config_byte(dev
, 0x5a, &scr1
);
1286 return (scr1
& ata66
) ? ATA_CBL_PATA40
: ATA_CBL_PATA80
;
1289 static void __devinit
init_hwif_hpt366(ide_hwif_t
*hwif
)
1291 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
1292 u8 chip_type
= info
->chip_type
;
1294 /* Cache the channel's MISC. control registers' offset */
1295 hwif
->select_data
= hwif
->channel
? 0x54 : 0x50;
1298 * HPT3xxN chips have some complications:
1300 * - on 33 MHz PCI we must clock switch
1301 * - on 66 MHz PCI we must NOT use the PCI clock
1303 if (chip_type
>= HPT372N
&& info
->dpll_clk
&& info
->pci_clk
< 66) {
1305 * Clock is shared between the channels,
1306 * so we'll have to serialize them... :-(
1308 hwif
->host
->host_flags
|= IDE_HFLAG_SERIALIZE
;
1309 hwif
->rw_disk
= &hpt3xxn_rw_disk
;
1313 static int __devinit
init_dma_hpt366(ide_hwif_t
*hwif
,
1314 const struct ide_port_info
*d
)
1316 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1317 unsigned long flags
, base
= ide_pci_dma_base(hwif
, d
);
1318 u8 dma_old
, dma_new
, masterdma
= 0, slavedma
= 0;
1323 hwif
->dma_base
= base
;
1325 if (ide_pci_check_simplex(hwif
, d
) < 0)
1328 if (ide_pci_set_master(dev
, d
->name
) < 0)
1331 dma_old
= inb(base
+ 2);
1333 local_irq_save(flags
);
1336 pci_read_config_byte(dev
, hwif
->channel
? 0x4b : 0x43, &masterdma
);
1337 pci_read_config_byte(dev
, hwif
->channel
? 0x4f : 0x47, &slavedma
);
1339 if (masterdma
& 0x30) dma_new
|= 0x20;
1340 if ( slavedma
& 0x30) dma_new
|= 0x40;
1341 if (dma_new
!= dma_old
)
1342 outb(dma_new
, base
+ 2);
1344 local_irq_restore(flags
);
1346 printk(KERN_INFO
" %s: BM-DMA at 0x%04lx-0x%04lx\n",
1347 hwif
->name
, base
, base
+ 7);
1349 hwif
->extra_base
= base
+ (hwif
->channel
? 8 : 16);
1351 if (ide_allocate_dma_engine(hwif
))
1357 static void __devinit
hpt374_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1359 if (dev2
->irq
!= dev
->irq
) {
1360 /* FIXME: we need a core pci_set_interrupt() */
1361 dev2
->irq
= dev
->irq
;
1362 printk(KERN_INFO DRV_NAME
" %s: PCI config space interrupt "
1363 "fixed\n", pci_name(dev2
));
1367 static void __devinit
hpt371_init(struct pci_dev
*dev
)
1372 * HPT371 chips physically have only one channel, the secondary one,
1373 * but the primary channel registers do exist! Go figure...
1374 * So, we manually disable the non-existing channel here
1375 * (if the BIOS hasn't done this already).
1377 pci_read_config_byte(dev
, 0x50, &mcr1
);
1379 pci_write_config_byte(dev
, 0x50, mcr1
& ~0x04);
1382 static int __devinit
hpt36x_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1384 u8 mcr1
= 0, pin1
= 0, pin2
= 0;
1387 * Now we'll have to force both channels enabled if
1388 * at least one of them has been enabled by BIOS...
1390 pci_read_config_byte(dev
, 0x50, &mcr1
);
1392 pci_write_config_byte(dev
, 0x50, mcr1
| 0x30);
1394 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin1
);
1395 pci_read_config_byte(dev2
, PCI_INTERRUPT_PIN
, &pin2
);
1397 if (pin1
!= pin2
&& dev
->irq
== dev2
->irq
) {
1398 printk(KERN_INFO DRV_NAME
" %s: onboard version of chipset, "
1399 "pin1=%d pin2=%d\n", pci_name(dev
), pin1
, pin2
);
1406 #define IDE_HFLAGS_HPT3XX \
1407 (IDE_HFLAG_NO_ATAPI_DMA | \
1408 IDE_HFLAG_OFF_BOARD)
1410 static const struct ide_port_ops hpt3xx_port_ops
= {
1411 .set_pio_mode
= hpt3xx_set_pio_mode
,
1412 .set_dma_mode
= hpt3xx_set_mode
,
1413 .quirkproc
= hpt3xx_quirkproc
,
1414 .maskproc
= hpt3xx_maskproc
,
1415 .mdma_filter
= hpt3xx_mdma_filter
,
1416 .udma_filter
= hpt3xx_udma_filter
,
1417 .cable_detect
= hpt3xx_cable_detect
,
1420 static const struct ide_dma_ops hpt37x_dma_ops
= {
1421 .dma_host_set
= ide_dma_host_set
,
1422 .dma_setup
= ide_dma_setup
,
1423 .dma_exec_cmd
= ide_dma_exec_cmd
,
1424 .dma_start
= ide_dma_start
,
1425 .dma_end
= hpt374_dma_end
,
1426 .dma_test_irq
= hpt374_dma_test_irq
,
1427 .dma_lost_irq
= ide_dma_lost_irq
,
1428 .dma_timeout
= ide_dma_timeout
,
1429 .dma_sff_read_status
= ide_dma_sff_read_status
,
1432 static const struct ide_dma_ops hpt370_dma_ops
= {
1433 .dma_host_set
= ide_dma_host_set
,
1434 .dma_setup
= ide_dma_setup
,
1435 .dma_exec_cmd
= ide_dma_exec_cmd
,
1436 .dma_start
= hpt370_dma_start
,
1437 .dma_end
= hpt370_dma_end
,
1438 .dma_test_irq
= ide_dma_test_irq
,
1439 .dma_lost_irq
= ide_dma_lost_irq
,
1440 .dma_timeout
= hpt370_dma_timeout
,
1441 .dma_sff_read_status
= ide_dma_sff_read_status
,
1444 static const struct ide_dma_ops hpt36x_dma_ops
= {
1445 .dma_host_set
= ide_dma_host_set
,
1446 .dma_setup
= ide_dma_setup
,
1447 .dma_exec_cmd
= ide_dma_exec_cmd
,
1448 .dma_start
= ide_dma_start
,
1449 .dma_end
= ide_dma_end
,
1450 .dma_test_irq
= ide_dma_test_irq
,
1451 .dma_lost_irq
= hpt366_dma_lost_irq
,
1452 .dma_timeout
= ide_dma_timeout
,
1453 .dma_sff_read_status
= ide_dma_sff_read_status
,
1456 static const struct ide_port_info hpt366_chipsets
[] __devinitdata
= {
1459 .init_chipset
= init_chipset_hpt366
,
1460 .init_hwif
= init_hwif_hpt366
,
1461 .init_dma
= init_dma_hpt366
,
1463 * HPT36x chips have one channel per function and have
1464 * both channel enable bits located differently and visible
1465 * to both functions -- really stupid design decision... :-(
1466 * Bit 4 is for the primary channel, bit 5 for the secondary.
1468 .enablebits
= {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1469 .port_ops
= &hpt3xx_port_ops
,
1470 .dma_ops
= &hpt36x_dma_ops
,
1471 .host_flags
= IDE_HFLAGS_HPT3XX
| IDE_HFLAG_SINGLE
,
1472 .pio_mask
= ATA_PIO4
,
1473 .mwdma_mask
= ATA_MWDMA2
,
1477 .init_chipset
= init_chipset_hpt366
,
1478 .init_hwif
= init_hwif_hpt366
,
1479 .init_dma
= init_dma_hpt366
,
1480 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1481 .port_ops
= &hpt3xx_port_ops
,
1482 .dma_ops
= &hpt37x_dma_ops
,
1483 .host_flags
= IDE_HFLAGS_HPT3XX
,
1484 .pio_mask
= ATA_PIO4
,
1485 .mwdma_mask
= ATA_MWDMA2
,
1490 * hpt366_init_one - called when an HPT366 is found
1491 * @dev: the hpt366 device
1492 * @id: the matching pci id
1494 * Called when the PCI registration layer (or the IDE initialization)
1495 * finds a device matching our IDE device tables.
1497 static int __devinit
hpt366_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1499 const struct hpt_info
*info
= NULL
;
1500 struct hpt_info
*dyn_info
;
1501 struct pci_dev
*dev2
= NULL
;
1502 struct ide_port_info d
;
1503 u8 idx
= id
->driver_data
;
1504 u8 rev
= dev
->revision
;
1507 if ((idx
== 0 || idx
== 4) && (PCI_FUNC(dev
->devfn
) & 1))
1515 switch (min_t(u8
, rev
, 6)) {
1516 case 3: info
= &hpt370
; break;
1517 case 4: info
= &hpt370a
; break;
1518 case 5: info
= &hpt372
; break;
1519 case 6: info
= &hpt372n
; break;
1525 info
= (rev
> 1) ? &hpt372n
: &hpt372a
;
1528 info
= (rev
> 1) ? &hpt302n
: &hpt302
;
1532 info
= (rev
> 1) ? &hpt371n
: &hpt371
;
1542 printk(KERN_INFO DRV_NAME
": %s chipset detected\n", info
->chip_name
);
1544 d
= hpt366_chipsets
[min_t(u8
, idx
, 1)];
1546 d
.udma_mask
= info
->udma_mask
;
1548 /* fixup ->dma_ops for HPT370/HPT370A */
1549 if (info
== &hpt370
|| info
== &hpt370a
)
1550 d
.dma_ops
= &hpt370_dma_ops
;
1552 if (info
== &hpt36x
|| info
== &hpt374
)
1553 dev2
= pci_get_slot(dev
->bus
, dev
->devfn
+ 1);
1555 dyn_info
= kzalloc(sizeof(*dyn_info
) * (dev2
? 2 : 1), GFP_KERNEL
);
1556 if (dyn_info
== NULL
) {
1557 printk(KERN_ERR
"%s %s: out of memory!\n",
1558 d
.name
, pci_name(dev
));
1564 * Copy everything from a static "template" structure
1565 * to just allocated per-chip hpt_info structure.
1567 memcpy(dyn_info
, info
, sizeof(*dyn_info
));
1570 memcpy(dyn_info
+ 1, info
, sizeof(*dyn_info
));
1572 if (info
== &hpt374
)
1573 hpt374_init(dev
, dev2
);
1575 if (hpt36x_init(dev
, dev2
))
1576 d
.host_flags
&= ~IDE_HFLAG_NON_BOOTABLE
;
1579 ret
= ide_pci_init_two(dev
, dev2
, &d
, dyn_info
);
1587 ret
= ide_pci_init_one(dev
, &d
, dyn_info
);
1594 static void __devexit
hpt366_remove(struct pci_dev
*dev
)
1596 struct ide_host
*host
= pci_get_drvdata(dev
);
1597 struct ide_info
*info
= host
->host_priv
;
1598 struct pci_dev
*dev2
= host
->dev
[1] ? to_pci_dev(host
->dev
[1]) : NULL
;
1600 ide_pci_remove(dev
);
1605 static const struct pci_device_id hpt366_pci_tbl
[] __devinitconst
= {
1606 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT366
), 0 },
1607 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372
), 1 },
1608 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT302
), 2 },
1609 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT371
), 3 },
1610 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT374
), 4 },
1611 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372N
), 5 },
1614 MODULE_DEVICE_TABLE(pci
, hpt366_pci_tbl
);
1616 static struct pci_driver hpt366_pci_driver
= {
1617 .name
= "HPT366_IDE",
1618 .id_table
= hpt366_pci_tbl
,
1619 .probe
= hpt366_init_one
,
1620 .remove
= __devexit_p(hpt366_remove
),
1621 .suspend
= ide_pci_suspend
,
1622 .resume
= ide_pci_resume
,
1625 static int __init
hpt366_ide_init(void)
1627 return ide_pci_register_driver(&hpt366_pci_driver
);
1630 static void __exit
hpt366_ide_exit(void)
1632 pci_unregister_driver(&hpt366_pci_driver
);
1635 module_init(hpt366_ide_init
);
1636 module_exit(hpt366_ide_exit
);
1638 MODULE_AUTHOR("Andre Hedrick");
1639 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1640 MODULE_LICENSE("GPL");