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signals: dequeue_signal: don't check SIGNAL_GROUP_EXIT when setting SIGNAL_STOP_DEQUEUED
[linux-2.6/mini2440.git] / drivers / edac / mpc85xx_edac.c
blobd49361bfe670e09a4af2dfae7ec99d9646851716
1 /*
2 * Freescale MPC85xx Memory Controller kenel module
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/interrupt.h>
16 #include <linux/ctype.h>
17 #include <linux/io.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/edac.h>
20
21 #include <linux/of_platform.h>
22 #include <linux/of_device.h>
23 #include "edac_module.h"
24 #include "edac_core.h"
25 #include "mpc85xx_edac.h"
26
27 static int edac_dev_idx;
28 static int edac_pci_idx;
29 static int edac_mc_idx;
30
31 static u32 orig_ddr_err_disable;
32 static u32 orig_ddr_err_sbe;
33
34 /*
35 * PCI Err defines
36 */
37 #ifdef CONFIG_PCI
38 static u32 orig_pci_err_cap_dr;
39 static u32 orig_pci_err_en;
40 #endif
41
42 static u32 orig_l2_err_disable;
43 static u32 orig_hid1;
44
45 /************************ MC SYSFS parts ***********************************/
46
47 static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
48 char *data)
49 {
50 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
51 return sprintf(data, "0x%08x",
52 in_be32(pdata->mc_vbase +
53 MPC85XX_MC_DATA_ERR_INJECT_HI));
54 }
55
56 static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
57 char *data)
58 {
59 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
60 return sprintf(data, "0x%08x",
61 in_be32(pdata->mc_vbase +
62 MPC85XX_MC_DATA_ERR_INJECT_LO));
63 }
64
65 static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
66 {
67 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
68 return sprintf(data, "0x%08x",
69 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
70 }
71
72 static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
73 const char *data, size_t count)
74 {
75 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
76 if (isdigit(*data)) {
77 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
78 simple_strtoul(data, NULL, 0));
79 return count;
80 }
81 return 0;
82 }
83
84 static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
85 const char *data, size_t count)
86 {
87 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
88 if (isdigit(*data)) {
89 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
90 simple_strtoul(data, NULL, 0));
91 return count;
92 }
93 return 0;
94 }
95
96 static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
97 const char *data, size_t count)
98 {
99 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
100 if (isdigit(*data)) {
101 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
102 simple_strtoul(data, NULL, 0));
103 return count;
104 }
105 return 0;
106 }
107
108 static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
109 {
110 .attr = {
111 .name = "inject_data_hi",
112 .mode = (S_IRUGO | S_IWUSR)
113 },
114 .show = mpc85xx_mc_inject_data_hi_show,
115 .store = mpc85xx_mc_inject_data_hi_store},
116 {
117 .attr = {
118 .name = "inject_data_lo",
119 .mode = (S_IRUGO | S_IWUSR)
120 },
121 .show = mpc85xx_mc_inject_data_lo_show,
122 .store = mpc85xx_mc_inject_data_lo_store},
123 {
124 .attr = {
125 .name = "inject_ctrl",
126 .mode = (S_IRUGO | S_IWUSR)
127 },
128 .show = mpc85xx_mc_inject_ctrl_show,
129 .store = mpc85xx_mc_inject_ctrl_store},
130
131 /* End of list */
132 {
133 .attr = {.name = NULL}
134 }
135 };
136
137 static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
138 {
139 mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
140 }
141
142 /**************************** PCI Err device ***************************/
143 #ifdef CONFIG_PCI
144
145 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
146 {
147 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
148 u32 err_detect;
149
150 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
151
152 /* master aborts can happen during PCI config cycles */
153 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
154 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
155 return;
156 }
157
158 printk(KERN_ERR "PCI error(s) detected\n");
159 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
160
161 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
162 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
163 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
164 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
165 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
166 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
167 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
168 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
169 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
170 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
171
172 /* clear error bits */
173 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
174
175 if (err_detect & PCI_EDE_PERR_MASK)
176 edac_pci_handle_pe(pci, pci->ctl_name);
177
178 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
179 edac_pci_handle_npe(pci, pci->ctl_name);
180 }
181
182 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
183 {
184 struct edac_pci_ctl_info *pci = dev_id;
185 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
186 u32 err_detect;
187
188 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
189
190 if (!err_detect)
191 return IRQ_NONE;
192
193 mpc85xx_pci_check(pci);
194
195 return IRQ_HANDLED;
196 }
197
198 static int __devinit mpc85xx_pci_err_probe(struct platform_device *pdev)
199 {
200 struct edac_pci_ctl_info *pci;
201 struct mpc85xx_pci_pdata *pdata;
202 struct resource *r;
203 int res = 0;
204
205 if (!devres_open_group(&pdev->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
206 return -ENOMEM;
207
208 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
209 if (!pci)
210 return -ENOMEM;
211
212 pdata = pci->pvt_info;
213 pdata->name = "mpc85xx_pci_err";
214 pdata->irq = NO_IRQ;
215 platform_set_drvdata(pdev, pci);
216 pci->dev = &pdev->dev;
217 pci->mod_name = EDAC_MOD_STR;
218 pci->ctl_name = pdata->name;
219 pci->dev_name = pdev->dev.bus_id;
220
221 if (edac_op_state == EDAC_OPSTATE_POLL)
222 pci->edac_check = mpc85xx_pci_check;
223
224 pdata->edac_idx = edac_pci_idx++;
225
226 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
227 if (!r) {
228 printk(KERN_ERR "%s: Unable to get resource for "
229 "PCI err regs\n", __func__);
230 goto err;
231 }
232
233 if (!devm_request_mem_region(&pdev->dev, r->start,
234 r->end - r->start + 1, pdata->name)) {
235 printk(KERN_ERR "%s: Error while requesting mem region\n",
236 __func__);
237 res = -EBUSY;
238 goto err;
239 }
240
241 pdata->pci_vbase = devm_ioremap(&pdev->dev, r->start,
242 r->end - r->start + 1);
243 if (!pdata->pci_vbase) {
244 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
245 res = -ENOMEM;
246 goto err;
247 }
248
249 orig_pci_err_cap_dr =
250 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
251
252 /* PCI master abort is expected during config cycles */
253 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
254
255 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
256
257 /* disable master abort reporting */
258 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
259
260 /* clear error bits */
261 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
262
263 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
264 debugf3("%s(): failed edac_pci_add_device()\n", __func__);
265 goto err;
266 }
267
268 if (edac_op_state == EDAC_OPSTATE_INT) {
269 pdata->irq = platform_get_irq(pdev, 0);
270 res = devm_request_irq(&pdev->dev, pdata->irq,
271 mpc85xx_pci_isr, IRQF_DISABLED,
272 "[EDAC] PCI err", pci);
273 if (res < 0) {
274 printk(KERN_ERR
275 "%s: Unable to requiest irq %d for "
276 "MPC85xx PCI err\n", __func__, pdata->irq);
277 res = -ENODEV;
278 goto err2;
279 }
280
281 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
282 pdata->irq);
283 }
284
285 devres_remove_group(&pdev->dev, mpc85xx_pci_err_probe);
286 debugf3("%s(): success\n", __func__);
287 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
288
289 return 0;
290
291 err2:
292 edac_pci_del_device(&pdev->dev);
293 err:
294 edac_pci_free_ctl_info(pci);
295 devres_release_group(&pdev->dev, mpc85xx_pci_err_probe);
296 return res;
297 }
298
299 static int mpc85xx_pci_err_remove(struct platform_device *pdev)
300 {
301 struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);
302 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
303
304 debugf0("%s()\n", __func__);
305
306 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
307 orig_pci_err_cap_dr);
308
309 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
310
311 edac_pci_del_device(pci->dev);
312
313 if (edac_op_state == EDAC_OPSTATE_INT)
314 irq_dispose_mapping(pdata->irq);
315
316 edac_pci_free_ctl_info(pci);
317
318 return 0;
319 }
320
321 static struct platform_driver mpc85xx_pci_err_driver = {
322 .probe = mpc85xx_pci_err_probe,
323 .remove = __devexit_p(mpc85xx_pci_err_remove),
324 .driver = {
325 .name = "mpc85xx_pci_err",
326 }
327 };
328
329 #endif /* CONFIG_PCI */
330
331 /**************************** L2 Err device ***************************/
332
333 /************************ L2 SYSFS parts ***********************************/
334
335 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
336 *edac_dev, char *data)
337 {
338 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
339 return sprintf(data, "0x%08x",
340 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
341 }
342
343 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
344 *edac_dev, char *data)
345 {
346 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
347 return sprintf(data, "0x%08x",
348 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
349 }
350
351 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
352 *edac_dev, char *data)
353 {
354 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
355 return sprintf(data, "0x%08x",
356 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
357 }
358
359 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
360 *edac_dev, const char *data,
361 size_t count)
362 {
363 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
364 if (isdigit(*data)) {
365 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
366 simple_strtoul(data, NULL, 0));
367 return count;
368 }
369 return 0;
370 }
371
372 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
373 *edac_dev, const char *data,
374 size_t count)
375 {
376 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
377 if (isdigit(*data)) {
378 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
379 simple_strtoul(data, NULL, 0));
380 return count;
381 }
382 return 0;
383 }
384
385 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
386 *edac_dev, const char *data,
387 size_t count)
388 {
389 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
390 if (isdigit(*data)) {
391 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
392 simple_strtoul(data, NULL, 0));
393 return count;
394 }
395 return 0;
396 }
397
398 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
399 {
400 .attr = {
401 .name = "inject_data_hi",
402 .mode = (S_IRUGO | S_IWUSR)
403 },
404 .show = mpc85xx_l2_inject_data_hi_show,
405 .store = mpc85xx_l2_inject_data_hi_store},
406 {
407 .attr = {
408 .name = "inject_data_lo",
409 .mode = (S_IRUGO | S_IWUSR)
410 },
411 .show = mpc85xx_l2_inject_data_lo_show,
412 .store = mpc85xx_l2_inject_data_lo_store},
413 {
414 .attr = {
415 .name = "inject_ctrl",
416 .mode = (S_IRUGO | S_IWUSR)
417 },
418 .show = mpc85xx_l2_inject_ctrl_show,
419 .store = mpc85xx_l2_inject_ctrl_store},
420
421 /* End of list */
422 {
423 .attr = {.name = NULL}
424 }
425 };
426
427 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
428 *edac_dev)
429 {
430 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
431 }
432
433 /***************************** L2 ops ***********************************/
434
435 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
436 {
437 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
438 u32 err_detect;
439
440 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
441
442 if (!(err_detect & L2_EDE_MASK))
443 return;
444
445 printk(KERN_ERR "ECC Error in CPU L2 cache\n");
446 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
447 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
448 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
449 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
450 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
451 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
452 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
453 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
454 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
455 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
456 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
457
458 /* clear error detect register */
459 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
460
461 if (err_detect & L2_EDE_CE_MASK)
462 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
463
464 if (err_detect & L2_EDE_UE_MASK)
465 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
466 }
467
468 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
469 {
470 struct edac_device_ctl_info *edac_dev = dev_id;
471 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
472 u32 err_detect;
473
474 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
475
476 if (!(err_detect & L2_EDE_MASK))
477 return IRQ_NONE;
478
479 mpc85xx_l2_check(edac_dev);
480
481 return IRQ_HANDLED;
482 }
483
484 static int __devinit mpc85xx_l2_err_probe(struct of_device *op,
485 const struct of_device_id *match)
486 {
487 struct edac_device_ctl_info *edac_dev;
488 struct mpc85xx_l2_pdata *pdata;
489 struct resource r;
490 int res;
491
492 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
493 return -ENOMEM;
494
495 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
496 "cpu", 1, "L", 1, 2, NULL, 0,
497 edac_dev_idx);
498 if (!edac_dev) {
499 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
500 return -ENOMEM;
501 }
502
503 pdata = edac_dev->pvt_info;
504 pdata->name = "mpc85xx_l2_err";
505 pdata->irq = NO_IRQ;
506 edac_dev->dev = &op->dev;
507 dev_set_drvdata(edac_dev->dev, edac_dev);
508 edac_dev->ctl_name = pdata->name;
509 edac_dev->dev_name = pdata->name;
510
511 res = of_address_to_resource(op->node, 0, &r);
512 if (res) {
513 printk(KERN_ERR "%s: Unable to get resource for "
514 "L2 err regs\n", __func__);
515 goto err;
516 }
517
518 /* we only need the error registers */
519 r.start += 0xe00;
520
521 if (!devm_request_mem_region(&op->dev, r.start,
522 r.end - r.start + 1, pdata->name)) {
523 printk(KERN_ERR "%s: Error while requesting mem region\n",
524 __func__);
525 res = -EBUSY;
526 goto err;
527 }
528
529 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
530 if (!pdata->l2_vbase) {
531 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
532 res = -ENOMEM;
533 goto err;
534 }
535
536 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
537
538 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
539
540 /* clear the err_dis */
541 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
542
543 edac_dev->mod_name = EDAC_MOD_STR;
544
545 if (edac_op_state == EDAC_OPSTATE_POLL)
546 edac_dev->edac_check = mpc85xx_l2_check;
547
548 mpc85xx_set_l2_sysfs_attributes(edac_dev);
549
550 pdata->edac_idx = edac_dev_idx++;
551
552 if (edac_device_add_device(edac_dev) > 0) {
553 debugf3("%s(): failed edac_device_add_device()\n", __func__);
554 goto err;
555 }
556
557 if (edac_op_state == EDAC_OPSTATE_INT) {
558 pdata->irq = irq_of_parse_and_map(op->node, 0);
559 res = devm_request_irq(&op->dev, pdata->irq,
560 mpc85xx_l2_isr, IRQF_DISABLED,
561 "[EDAC] L2 err", edac_dev);
562 if (res < 0) {
563 printk(KERN_ERR
564 "%s: Unable to requiest irq %d for "
565 "MPC85xx L2 err\n", __func__, pdata->irq);
566 irq_dispose_mapping(pdata->irq);
567 res = -ENODEV;
568 goto err2;
569 }
570
571 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
572 pdata->irq);
573
574 edac_dev->op_state = OP_RUNNING_INTERRUPT;
575
576 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
577 }
578
579 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
580
581 debugf3("%s(): success\n", __func__);
582 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
583
584 return 0;
585
586 err2:
587 edac_device_del_device(&op->dev);
588 err:
589 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
590 edac_device_free_ctl_info(edac_dev);
591 return res;
592 }
593
594 static int mpc85xx_l2_err_remove(struct of_device *op)
595 {
596 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
597 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
598
599 debugf0("%s()\n", __func__);
600
601 if (edac_op_state == EDAC_OPSTATE_INT) {
602 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
603 irq_dispose_mapping(pdata->irq);
604 }
605
606 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
607 edac_device_del_device(&op->dev);
608 edac_device_free_ctl_info(edac_dev);
609 return 0;
610 }
611
612 static struct of_device_id mpc85xx_l2_err_of_match[] = {
613 {
614 .compatible = "fsl,8540-l2-cache-controller",
615 },
616 {
617 .compatible = "fsl,8541-l2-cache-controller",
618 },
619 {
620 .compatible = "fsl,8544-l2-cache-controller",
621 },
622 {
623 .compatible = "fsl,8548-l2-cache-controller",
624 },
625 {
626 .compatible = "fsl,8555-l2-cache-controller",
627 },
628 {
629 .compatible = "fsl,8568-l2-cache-controller",
630 },
631 {},
632 };
633
634 static struct of_platform_driver mpc85xx_l2_err_driver = {
635 .owner = THIS_MODULE,
636 .name = "mpc85xx_l2_err",
637 .match_table = mpc85xx_l2_err_of_match,
638 .probe = mpc85xx_l2_err_probe,
639 .remove = mpc85xx_l2_err_remove,
640 .driver = {
641 .name = "mpc85xx_l2_err",
642 .owner = THIS_MODULE,
643 },
644 };
645
646 /**************************** MC Err device ***************************/
647
648 static void mpc85xx_mc_check(struct mem_ctl_info *mci)
649 {
650 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
651 struct csrow_info *csrow;
652 u32 err_detect;
653 u32 syndrome;
654 u32 err_addr;
655 u32 pfn;
656 int row_index;
657
658 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
659 if (err_detect)
660 return;
661
662 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
663 err_detect);
664
665 /* no more processing if not ECC bit errors */
666 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
667 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
668 return;
669 }
670
671 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
672 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
673 pfn = err_addr >> PAGE_SHIFT;
674
675 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
676 csrow = &mci->csrows[row_index];
677 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
678 break;
679 }
680
681 mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n",
682 in_be32(pdata->mc_vbase +
683 MPC85XX_MC_CAPTURE_DATA_HI));
684 mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n",
685 in_be32(pdata->mc_vbase +
686 MPC85XX_MC_CAPTURE_DATA_LO));
687 mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome);
688 mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr);
689 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
690
691 /* we are out of range */
692 if (row_index == mci->nr_csrows)
693 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
694
695 if (err_detect & DDR_EDE_SBE)
696 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
697 syndrome, row_index, 0, mci->ctl_name);
698
699 if (err_detect & DDR_EDE_MBE)
700 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
701 row_index, mci->ctl_name);
702
703 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
704 }
705
706 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
707 {
708 struct mem_ctl_info *mci = dev_id;
709 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
710 u32 err_detect;
711
712 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
713 if (!err_detect)
714 return IRQ_NONE;
715
716 mpc85xx_mc_check(mci);
717
718 return IRQ_HANDLED;
719 }
720
721 static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
722 {
723 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
724 struct csrow_info *csrow;
725 u32 sdram_ctl;
726 u32 sdtype;
727 enum mem_type mtype;
728 u32 cs_bnds;
729 int index;
730
731 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
732
733 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
734 if (sdram_ctl & DSC_RD_EN) {
735 switch (sdtype) {
736 case DSC_SDTYPE_DDR:
737 mtype = MEM_RDDR;
738 break;
739 case DSC_SDTYPE_DDR2:
740 mtype = MEM_RDDR2;
741 break;
742 default:
743 mtype = MEM_UNKNOWN;
744 break;
745 }
746 } else {
747 switch (sdtype) {
748 case DSC_SDTYPE_DDR:
749 mtype = MEM_DDR;
750 break;
751 case DSC_SDTYPE_DDR2:
752 mtype = MEM_DDR2;
753 break;
754 default:
755 mtype = MEM_UNKNOWN;
756 break;
757 }
758 }
759
760 for (index = 0; index < mci->nr_csrows; index++) {
761 u32 start;
762 u32 end;
763
764 csrow = &mci->csrows[index];
765 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
766 (index * MPC85XX_MC_CS_BNDS_OFS));
767 start = (cs_bnds & 0xfff0000) << 4;
768 end = ((cs_bnds & 0xfff) << 20);
769 if (start)
770 start |= 0xfffff;
771 if (end)
772 end |= 0xfffff;
773
774 if (start == end)
775 continue; /* not populated */
776
777 csrow->first_page = start >> PAGE_SHIFT;
778 csrow->last_page = end >> PAGE_SHIFT;
779 csrow->nr_pages = csrow->last_page + 1 - csrow->first_page;
780 csrow->grain = 8;
781 csrow->mtype = mtype;
782 csrow->dtype = DEV_UNKNOWN;
783 if (sdram_ctl & DSC_X32_EN)
784 csrow->dtype = DEV_X32;
785 csrow->edac_mode = EDAC_SECDED;
786 }
787 }
788
789 static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
790 const struct of_device_id *match)
791 {
792 struct mem_ctl_info *mci;
793 struct mpc85xx_mc_pdata *pdata;
794 struct resource r;
795 u32 sdram_ctl;
796 int res;
797
798 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
799 return -ENOMEM;
800
801 mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
802 if (!mci) {
803 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
804 return -ENOMEM;
805 }
806
807 pdata = mci->pvt_info;
808 pdata->name = "mpc85xx_mc_err";
809 pdata->irq = NO_IRQ;
810 mci->dev = &op->dev;
811 pdata->edac_idx = edac_mc_idx++;
812 dev_set_drvdata(mci->dev, mci);
813 mci->ctl_name = pdata->name;
814 mci->dev_name = pdata->name;
815
816 res = of_address_to_resource(op->node, 0, &r);
817 if (res) {
818 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
819 __func__);
820 goto err;
821 }
822
823 if (!devm_request_mem_region(&op->dev, r.start,
824 r.end - r.start + 1, pdata->name)) {
825 printk(KERN_ERR "%s: Error while requesting mem region\n",
826 __func__);
827 res = -EBUSY;
828 goto err;
829 }
830
831 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
832 if (!pdata->mc_vbase) {
833 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
834 res = -ENOMEM;
835 goto err;
836 }
837
838 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
839 if (!(sdram_ctl & DSC_ECC_EN)) {
840 /* no ECC */
841 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
842 res = -ENODEV;
843 goto err;
844 }
845
846 debugf3("%s(): init mci\n", __func__);
847 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
848 MEM_FLAG_DDR | MEM_FLAG_DDR2;
849 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
850 mci->edac_cap = EDAC_FLAG_SECDED;
851 mci->mod_name = EDAC_MOD_STR;
852 mci->mod_ver = MPC85XX_REVISION;
853
854 if (edac_op_state == EDAC_OPSTATE_POLL)
855 mci->edac_check = mpc85xx_mc_check;
856
857 mci->ctl_page_to_phys = NULL;
858
859 mci->scrub_mode = SCRUB_SW_SRC;
860
861 mpc85xx_set_mc_sysfs_attributes(mci);
862
863 mpc85xx_init_csrows(mci);
864
865 #ifdef CONFIG_EDAC_DEBUG
866 edac_mc_register_mcidev_debug((struct attribute **)debug_attr);
867 #endif
868
869 /* store the original error disable bits */
870 orig_ddr_err_disable =
871 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
872 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
873
874 /* clear all error bits */
875 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
876
877 if (edac_mc_add_mc(mci)) {
878 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
879 goto err;
880 }
881
882 if (edac_op_state == EDAC_OPSTATE_INT) {
883 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
884 DDR_EIE_MBEE | DDR_EIE_SBEE);
885
886 /* store the original error management threshold */
887 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
888 MPC85XX_MC_ERR_SBE) & 0xff0000;
889
890 /* set threshold to 1 error per interrupt */
891 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
892
893 /* register interrupts */
894 pdata->irq = irq_of_parse_and_map(op->node, 0);
895 res = devm_request_irq(&op->dev, pdata->irq,
896 mpc85xx_mc_isr, IRQF_DISABLED,
897 "[EDAC] MC err", mci);
898 if (res < 0) {
899 printk(KERN_ERR "%s: Unable to request irq %d for "
900 "MPC85xx DRAM ERR\n", __func__, pdata->irq);
901 irq_dispose_mapping(pdata->irq);
902 res = -ENODEV;
903 goto err2;
904 }
905
906 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
907 pdata->irq);
908 }
909
910 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
911 debugf3("%s(): success\n", __func__);
912 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
913
914 return 0;
915
916 err2:
917 edac_mc_del_mc(&op->dev);
918 err:
919 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
920 edac_mc_free(mci);
921 return res;
922 }
923
924 static int mpc85xx_mc_err_remove(struct of_device *op)
925 {
926 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
927 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
928
929 debugf0("%s()\n", __func__);
930
931 if (edac_op_state == EDAC_OPSTATE_INT) {
932 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
933 irq_dispose_mapping(pdata->irq);
934 }
935
936 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
937 orig_ddr_err_disable);
938 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
939
940 edac_mc_del_mc(&op->dev);
941 edac_mc_free(mci);
942 return 0;
943 }
944
945 static struct of_device_id mpc85xx_mc_err_of_match[] = {
946 {
947 .compatible = "fsl,8540-memory-controller",
948 },
949 {
950 .compatible = "fsl,8541-memory-controller",
951 },
952 {
953 .compatible = "fsl,8544-memory-controller",
954 },
955 {
956 .compatible = "fsl,8548-memory-controller",
957 },
958 {
959 .compatible = "fsl,8555-memory-controller",
960 },
961 {
962 .compatible = "fsl,8568-memory-controller",
963 },
964 {},
965 };
966
967 static struct of_platform_driver mpc85xx_mc_err_driver = {
968 .owner = THIS_MODULE,
969 .name = "mpc85xx_mc_err",
970 .match_table = mpc85xx_mc_err_of_match,
971 .probe = mpc85xx_mc_err_probe,
972 .remove = mpc85xx_mc_err_remove,
973 .driver = {
974 .name = "mpc85xx_mc_err",
975 .owner = THIS_MODULE,
976 },
977 };
978
979 static int __init mpc85xx_mc_init(void)
980 {
981 int res = 0;
982
983 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
984 "(C) 2006 Montavista Software\n");
985
986 /* make sure error reporting method is sane */
987 switch (edac_op_state) {
988 case EDAC_OPSTATE_POLL:
989 case EDAC_OPSTATE_INT:
990 break;
991 default:
992 edac_op_state = EDAC_OPSTATE_INT;
993 break;
994 }
995
996 res = of_register_platform_driver(&mpc85xx_mc_err_driver);
997 if (res)
998 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
999
1000 res = of_register_platform_driver(&mpc85xx_l2_err_driver);
1001 if (res)
1002 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1003
1004 #ifdef CONFIG_PCI
1005 res = platform_driver_register(&mpc85xx_pci_err_driver);
1006 if (res)
1007 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1008 #endif
1009
1010 /*
1011 * need to clear HID1[RFXE] to disable machine check int
1012 * so we can catch it
1013 */
1014 if (edac_op_state == EDAC_OPSTATE_INT) {
1015 orig_hid1 = mfspr(SPRN_HID1);
1016 mtspr(SPRN_HID1, (orig_hid1 & ~0x20000));
1017 }
1018
1019 return 0;
1020 }
1021
1022 module_init(mpc85xx_mc_init);
1023
1024 static void __exit mpc85xx_mc_exit(void)
1025 {
1026 mtspr(SPRN_HID1, orig_hid1);
1027 #ifdef CONFIG_PCI
1028 platform_driver_unregister(&mpc85xx_pci_err_driver);
1029 #endif
1030 of_unregister_platform_driver(&mpc85xx_l2_err_driver);
1031 of_unregister_platform_driver(&mpc85xx_mc_err_driver);
1032 }
1033
1034 module_exit(mpc85xx_mc_exit);
1035
1036 MODULE_LICENSE("GPL");
1037 MODULE_AUTHOR("Montavista Software, Inc.");
1038 module_param(edac_op_state, int, 0444);
1039 MODULE_PARM_DESC(edac_op_state,
1040 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
Support for the Chinese Samsung S3C2440 based development boards