arch/arm/mm/cache-xsc3l2.c

   1 /*
   2  * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
   3  *
   4  * Copyright (C) 2007 ARM Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18  */
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21
  22 #include <asm/system.h>
  23 #include <asm/cacheflush.h>
  24 #include <asm/io.h>
  25
  26 #define CR_L2   (1 << 26)
  27
  28 #define CACHE_LINE_SIZE         32
  29 #define CACHE_LINE_SHIFT        5
  30 #define CACHE_WAY_PER_SET       8
  31
  32 #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
  33 #define CACHE_SET_SIZE(l2ctype) (CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)
  34
  35 static inline int xsc3_l2_present(void)
  36 {
  37         unsigned long l2ctype;
  38
  39         __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
  40
  41         return !!(l2ctype & 0xf8);
  42 }
  43
  44 static inline void xsc3_l2_clean_mva(unsigned long addr)
  45 {
  46         __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr));
  47 }
  48
  49 static inline void xsc3_l2_clean_pa(unsigned long addr)
  50 {
  51         xsc3_l2_clean_mva(__phys_to_virt(addr));
  52 }
  53
  54 static inline void xsc3_l2_inv_mva(unsigned long addr)
  55 {
  56         __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr));
  57 }
  58
  59 static inline void xsc3_l2_inv_pa(unsigned long addr)
  60 {
  61         xsc3_l2_inv_mva(__phys_to_virt(addr));
  62 }
  63
  64 static inline void xsc3_l2_inv_all(void)
  65 {
  66         unsigned long l2ctype, set_way;
  67         int set, way;
  68
  69         __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
  70
  71         for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
  72                 for (way = 0; way < CACHE_WAY_PER_SET; way++) {
  73                         set_way = (way << 29) | (set << 5);
  74                         __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way));
  75                 }
  76         }
  77
  78         dsb();
  79 }
  80
  81 static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
  82 {
  83         if (start == 0 && end == -1ul) {
  84                 xsc3_l2_inv_all();
  85                 return;
  86         }
  87
  88         /*
  89          * Clean and invalidate partial first cache line.
  90          */
  91         if (start & (CACHE_LINE_SIZE - 1)) {
  92                 xsc3_l2_clean_pa(start & ~(CACHE_LINE_SIZE - 1));
  93                 xsc3_l2_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
  94                 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
  95         }
  96
  97         /*
  98          * Clean and invalidate partial last cache line.
  99          */
 100         if (end & (CACHE_LINE_SIZE - 1)) {
 101                 xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1));
 102                 xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
 103                 end &= ~(CACHE_LINE_SIZE - 1);
 104         }
 105
 106         /*
 107          * Invalidate all full cache lines between 'start' and 'end'.
 108          */
 109         while (start != end) {
 110                 xsc3_l2_inv_pa(start);
 111                 start += CACHE_LINE_SIZE;
 112         }
 113
 114         dsb();
 115 }
 116
 117 static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
 118 {
 119         start &= ~(CACHE_LINE_SIZE - 1);
 120         while (start < end) {
 121                 xsc3_l2_clean_pa(start);
 122                 start += CACHE_LINE_SIZE;
 123         }
 124
 125         dsb();
 126 }
 127
 128 /*
 129  * optimize L2 flush all operation by set/way format
 130  */
 131 static inline void xsc3_l2_flush_all(void)
 132 {
 133         unsigned long l2ctype, set_way;
 134         int set, way;
 135
 136         __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
 137
 138         for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
 139                 for (way = 0; way < CACHE_WAY_PER_SET; way++) {
 140                         set_way = (way << 29) | (set << 5);
 141                         __asm__("mcr p15, 1, %0, c7, c15, 2" : : "r"(set_way));
 142                 }
 143         }
 144
 145         dsb();
 146 }
 147
 148 static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
 149 {
 150         if (start == 0 && end == -1ul) {
 151                 xsc3_l2_flush_all();
 152                 return;
 153         }
 154
 155         start &= ~(CACHE_LINE_SIZE - 1);
 156         while (start < end) {
 157                 xsc3_l2_clean_pa(start);
 158                 xsc3_l2_inv_pa(start);
 159                 start += CACHE_LINE_SIZE;
 160         }
 161
 162         dsb();
 163 }
 164
 165 static int __init xsc3_l2_init(void)
 166 {
 167         if (!cpu_is_xsc3() || !xsc3_l2_present())
 168                 return 0;
 169
 170         if (!(get_cr() & CR_L2)) {
 171                 pr_info("XScale3 L2 cache enabled.\n");
 172                 adjust_cr(CR_L2, CR_L2);
 173                 xsc3_l2_inv_all();
 174         }
 175
 176         outer_cache.inv_range = xsc3_l2_inv_range;
 177         outer_cache.clean_range = xsc3_l2_clean_range;
 178         outer_cache.flush_range = xsc3_l2_flush_range;
 179
 180         return 0;
 181 }
 182 core_initcall(xsc3_l2_init);