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Char: mxser, ratelimit ioctl warning
[linux-2.6/mini2440.git] / drivers / net / smc91x.h
blob22209b6f14057e0fadadebe9d441e5b33172d334
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON)
47
48 #include <asm/mach-types.h>
49
50 /* Now the bus width is specified in the platform data
51 * pretend here to support all I/O access types
52 */
53 #define SMC_CAN_USE_8BIT 1
54 #define SMC_CAN_USE_16BIT 1
55 #define SMC_CAN_USE_32BIT 1
56 #define SMC_NOWAIT 1
57
58 #define SMC_IO_SHIFT (lp->io_shift)
59
60 #define SMC_inb(a, r) readb((a) + (r))
61 #define SMC_inw(a, r) readw((a) + (r))
62 #define SMC_inl(a, r) readl((a) + (r))
63 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
64 #define SMC_outl(v, a, r) writel(v, (a) + (r))
65 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
66 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
67 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
68 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
69 #define SMC_IRQ_FLAGS (-1) /* from resource */
70
71 /* We actually can't write halfwords properly if not word aligned */
72 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
73 {
74 if (machine_is_mainstone() && reg & 2) {
75 unsigned int v = val << 16;
76 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
77 writel(v, ioaddr + (reg & ~2));
78 } else {
79 writew(val, ioaddr + reg);
80 }
81 }
82
83 #elif defined(CONFIG_BLACKFIN)
84
85 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
86 #define RPC_LSA_DEFAULT RPC_LED_100_10
87 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
88
89 # if defined (CONFIG_BFIN561_EZKIT)
90 #define SMC_CAN_USE_8BIT 0
91 #define SMC_CAN_USE_16BIT 1
92 #define SMC_CAN_USE_32BIT 1
93 #define SMC_IO_SHIFT 0
94 #define SMC_NOWAIT 1
95 #define SMC_USE_BFIN_DMA 0
96
97
98 #define SMC_inw(a, r) readw((a) + (r))
99 #define SMC_outw(v, a, r) writew(v, (a) + (r))
100 #define SMC_inl(a, r) readl((a) + (r))
101 #define SMC_outl(v, a, r) writel(v, (a) + (r))
102 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
103 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
104 # else
105 #define SMC_CAN_USE_8BIT 0
106 #define SMC_CAN_USE_16BIT 1
107 #define SMC_CAN_USE_32BIT 0
108 #define SMC_IO_SHIFT 0
109 #define SMC_NOWAIT 1
110 #define SMC_USE_BFIN_DMA 0
111
112
113 #define SMC_inw(a, r) readw((a) + (r))
114 #define SMC_outw(v, a, r) writew(v, (a) + (r))
115 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
116 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
117 # endif
118 /* check if the mac in reg is valid */
119 #define SMC_GET_MAC_ADDR(lp, addr) \
120 do { \
121 unsigned int __v; \
122 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
123 addr[0] = __v; addr[1] = __v >> 8; \
124 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
125 addr[2] = __v; addr[3] = __v >> 8; \
126 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
127 addr[4] = __v; addr[5] = __v >> 8; \
128 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
129 random_ether_addr(addr); \
130 } \
131 } while (0)
132 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
133
134 /* We can only do 16-bit reads and writes in the static memory space. */
135 #define SMC_CAN_USE_8BIT 0
136 #define SMC_CAN_USE_16BIT 1
137 #define SMC_CAN_USE_32BIT 0
138 #define SMC_NOWAIT 1
139
140 #define SMC_IO_SHIFT 0
141
142 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
143 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
144 #define SMC_insw(a, r, p, l) \
145 do { \
146 unsigned long __port = (a) + (r); \
147 u16 *__p = (u16 *)(p); \
148 int __l = (l); \
149 insw(__port, __p, __l); \
150 while (__l > 0) { \
151 *__p = swab16(*__p); \
152 __p++; \
153 __l--; \
154 } \
155 } while (0)
156 #define SMC_outsw(a, r, p, l) \
157 do { \
158 unsigned long __port = (a) + (r); \
159 u16 *__p = (u16 *)(p); \
160 int __l = (l); \
161 while (__l > 0) { \
162 /* Believe it or not, the swab isn't needed. */ \
163 outw( /* swab16 */ (*__p++), __port); \
164 __l--; \
165 } \
166 } while (0)
167 #define SMC_IRQ_FLAGS (0)
168
169 #elif defined(CONFIG_SA1100_PLEB)
170 /* We can only do 16-bit reads and writes in the static memory space. */
171 #define SMC_CAN_USE_8BIT 1
172 #define SMC_CAN_USE_16BIT 1
173 #define SMC_CAN_USE_32BIT 0
174 #define SMC_IO_SHIFT 0
175 #define SMC_NOWAIT 1
176
177 #define SMC_inb(a, r) readb((a) + (r))
178 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
179 #define SMC_inw(a, r) readw((a) + (r))
180 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
181 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
182 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
183 #define SMC_outw(v, a, r) writew(v, (a) + (r))
184 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
185
186 #define SMC_IRQ_FLAGS (-1)
187
188 #elif defined(CONFIG_SA1100_ASSABET)
189
190 #include <asm/arch/neponset.h>
191
192 /* We can only do 8-bit reads and writes in the static memory space. */
193 #define SMC_CAN_USE_8BIT 1
194 #define SMC_CAN_USE_16BIT 0
195 #define SMC_CAN_USE_32BIT 0
196 #define SMC_NOWAIT 1
197
198 /* The first two address lines aren't connected... */
199 #define SMC_IO_SHIFT 2
200
201 #define SMC_inb(a, r) readb((a) + (r))
202 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
203 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
204 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
205 #define SMC_IRQ_FLAGS (-1) /* from resource */
206
207 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
208
209 #define SMC_CAN_USE_8BIT 0
210 #define SMC_CAN_USE_16BIT 1
211 #define SMC_CAN_USE_32BIT 0
212 #define SMC_IO_SHIFT 0
213 #define SMC_NOWAIT 1
214
215 #define SMC_inw(a, r) readw((a) + (r))
216 #define SMC_outw(v, a, r) writew(v, (a) + (r))
217 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
218 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
219
220 #elif defined(CONFIG_ARCH_INNOKOM) || \
221 defined(CONFIG_ARCH_PXA_IDP) || \
222 defined(CONFIG_ARCH_RAMSES) || \
223 defined(CONFIG_ARCH_PCM027)
224
225 #define SMC_CAN_USE_8BIT 1
226 #define SMC_CAN_USE_16BIT 1
227 #define SMC_CAN_USE_32BIT 1
228 #define SMC_IO_SHIFT 0
229 #define SMC_NOWAIT 1
230 #define SMC_USE_PXA_DMA 1
231
232 #define SMC_inb(a, r) readb((a) + (r))
233 #define SMC_inw(a, r) readw((a) + (r))
234 #define SMC_inl(a, r) readl((a) + (r))
235 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
236 #define SMC_outl(v, a, r) writel(v, (a) + (r))
237 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
238 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
239 #define SMC_IRQ_FLAGS (-1) /* from resource */
240
241 /* We actually can't write halfwords properly if not word aligned */
242 static inline void
243 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
244 {
245 if (reg & 2) {
246 unsigned int v = val << 16;
247 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
248 writel(v, ioaddr + (reg & ~2));
249 } else {
250 writew(val, ioaddr + reg);
251 }
252 }
253
254 #elif defined(CONFIG_ARCH_OMAP)
255
256 /* We can only do 16-bit reads and writes in the static memory space. */
257 #define SMC_CAN_USE_8BIT 0
258 #define SMC_CAN_USE_16BIT 1
259 #define SMC_CAN_USE_32BIT 0
260 #define SMC_IO_SHIFT 0
261 #define SMC_NOWAIT 1
262
263 #define SMC_inw(a, r) readw((a) + (r))
264 #define SMC_outw(v, a, r) writew(v, (a) + (r))
265 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
266 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
267 #define SMC_IRQ_FLAGS (-1) /* from resource */
268
269 #elif defined(CONFIG_SH_SH4202_MICRODEV)
270
271 #define SMC_CAN_USE_8BIT 0
272 #define SMC_CAN_USE_16BIT 1
273 #define SMC_CAN_USE_32BIT 0
274
275 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
276 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
277 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
278 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
279 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
280 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
281 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
282 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
283 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
284 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
285
286 #define SMC_IRQ_FLAGS (0)
287
288 #elif defined(CONFIG_ISA)
289
290 #define SMC_CAN_USE_8BIT 1
291 #define SMC_CAN_USE_16BIT 1
292 #define SMC_CAN_USE_32BIT 0
293
294 #define SMC_inb(a, r) inb((a) + (r))
295 #define SMC_inw(a, r) inw((a) + (r))
296 #define SMC_outb(v, a, r) outb(v, (a) + (r))
297 #define SMC_outw(v, a, r) outw(v, (a) + (r))
298 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
299 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
300
301 #elif defined(CONFIG_M32R)
302
303 #define SMC_CAN_USE_8BIT 0
304 #define SMC_CAN_USE_16BIT 1
305 #define SMC_CAN_USE_32BIT 0
306
307 #define SMC_inb(a, r) inb(((u32)a) + (r))
308 #define SMC_inw(a, r) inw(((u32)a) + (r))
309 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
310 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
311 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
312 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
313
314 #define SMC_IRQ_FLAGS (0)
315
316 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
317 #define RPC_LSB_DEFAULT RPC_LED_100_10
318
319 #elif defined(CONFIG_MACH_LPD79520) \
320 || defined(CONFIG_MACH_LPD7A400) \
321 || defined(CONFIG_MACH_LPD7A404)
322
323 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
324 * way that the CPU handles chip selects and the way that the SMC chip
325 * expects the chip select to operate. Refer to
326 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
327 * IOBARRIER is a byte, in order that we read the least-common
328 * denominator. It would be wasteful to read 32 bits from an 8-bit
329 * accessible region.
330 *
331 * There is no explicit protection against interrupts intervening
332 * between the writew and the IOBARRIER. In SMC ISR there is a
333 * preamble that performs an IOBARRIER in the extremely unlikely event
334 * that the driver interrupts itself between a writew to the chip an
335 * the IOBARRIER that follows *and* the cache is large enough that the
336 * first off-chip access while handing the interrupt is to the SMC
337 * chip. Other devices in the same address space as the SMC chip must
338 * be aware of the potential for trouble and perform a similar
339 * IOBARRIER on entry to their ISR.
340 */
341
342 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
343
344 #define SMC_CAN_USE_8BIT 0
345 #define SMC_CAN_USE_16BIT 1
346 #define SMC_CAN_USE_32BIT 0
347 #define SMC_NOWAIT 0
348 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
349
350 #define SMC_inw(a,r)\
351 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
352 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
353
354 #define SMC_insw LPD7_SMC_insw
355 static inline void LPD7_SMC_insw (unsigned char* a, int r,
356 unsigned char* p, int l)
357 {
358 unsigned short* ps = (unsigned short*) p;
359 while (l-- > 0) {
360 *ps++ = readw (a + r);
361 LPD7X_IOBARRIER;
362 }
363 }
364
365 #define SMC_outsw LPD7_SMC_outsw
366 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
367 unsigned char* p, int l)
368 {
369 unsigned short* ps = (unsigned short*) p;
370 while (l-- > 0) {
371 writew (*ps++, a + r);
372 LPD7X_IOBARRIER;
373 }
374 }
375
376 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
377
378 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
379 #define RPC_LSB_DEFAULT RPC_LED_100_10
380
381 #elif defined(CONFIG_SOC_AU1X00)
382
383 #include <au1xxx.h>
384
385 /* We can only do 16-bit reads and writes in the static memory space. */
386 #define SMC_CAN_USE_8BIT 0
387 #define SMC_CAN_USE_16BIT 1
388 #define SMC_CAN_USE_32BIT 0
389 #define SMC_IO_SHIFT 0
390 #define SMC_NOWAIT 1
391
392 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
393 #define SMC_insw(a, r, p, l) \
394 do { \
395 unsigned long _a = (unsigned long)((a) + (r)); \
396 int _l = (l); \
397 u16 *_p = (u16 *)(p); \
398 while (_l-- > 0) \
399 *_p++ = au_readw(_a); \
400 } while(0)
401 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
402 #define SMC_outsw(a, r, p, l) \
403 do { \
404 unsigned long _a = (unsigned long)((a) + (r)); \
405 int _l = (l); \
406 const u16 *_p = (const u16 *)(p); \
407 while (_l-- > 0) \
408 au_writew(*_p++ , _a); \
409 } while(0)
410
411 #define SMC_IRQ_FLAGS (0)
412
413 #elif defined(CONFIG_ARCH_VERSATILE)
414
415 #define SMC_CAN_USE_8BIT 1
416 #define SMC_CAN_USE_16BIT 1
417 #define SMC_CAN_USE_32BIT 1
418 #define SMC_NOWAIT 1
419
420 #define SMC_inb(a, r) readb((a) + (r))
421 #define SMC_inw(a, r) readw((a) + (r))
422 #define SMC_inl(a, r) readl((a) + (r))
423 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
424 #define SMC_outw(v, a, r) writew(v, (a) + (r))
425 #define SMC_outl(v, a, r) writel(v, (a) + (r))
426 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
427 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
428 #define SMC_IRQ_FLAGS (-1) /* from resource */
429
430 #elif defined(CONFIG_MN10300)
431
432 /*
433 * MN10300/AM33 configuration
434 */
435
436 #include <asm/unit/smc91111.h>
437
438 #else
439
440 /*
441 * Default configuration
442 */
443
444 #define SMC_CAN_USE_8BIT 1
445 #define SMC_CAN_USE_16BIT 1
446 #define SMC_CAN_USE_32BIT 1
447 #define SMC_NOWAIT 1
448
449 #define SMC_inb(a, r) readb((a) + (r))
450 #define SMC_inw(a, r) readw((a) + (r))
451 #define SMC_inl(a, r) readl((a) + (r))
452 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
453 #define SMC_outw(v, a, r) writew(v, (a) + (r))
454 #define SMC_outl(v, a, r) writel(v, (a) + (r))
455 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
456 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
457 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
458 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
459
460 #define RPC_LSA_DEFAULT RPC_LED_100_10
461 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
462
463 #endif
464
465
466 /* store this information for the driver.. */
467 struct smc_local {
468 /*
469 * If I have to wait until memory is available to send a
470 * packet, I will store the skbuff here, until I get the
471 * desired memory. Then, I'll send it out and free it.
472 */
473 struct sk_buff *pending_tx_skb;
474 struct tasklet_struct tx_task;
475
476 /* version/revision of the SMC91x chip */
477 int version;
478
479 /* Contains the current active transmission mode */
480 int tcr_cur_mode;
481
482 /* Contains the current active receive mode */
483 int rcr_cur_mode;
484
485 /* Contains the current active receive/phy mode */
486 int rpc_cur_mode;
487 int ctl_rfduplx;
488 int ctl_rspeed;
489
490 u32 msg_enable;
491 u32 phy_type;
492 struct mii_if_info mii;
493
494 /* work queue */
495 struct work_struct phy_configure;
496 struct net_device *dev;
497 int work_pending;
498
499 spinlock_t lock;
500
501 #ifdef CONFIG_ARCH_PXA
502 /* DMA needs the physical address of the chip */
503 u_long physaddr;
504 struct device *device;
505 #endif
506 void __iomem *base;
507 void __iomem *datacs;
508
509 /* the low address lines on some platforms aren't connected... */
510 int io_shift;
511
512 struct smc91x_platdata cfg;
513 };
514
515 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
516 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
517 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
518
519 #ifdef CONFIG_ARCH_PXA
520 /*
521 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
522 * always happening in irq context so no need to worry about races. TX is
523 * different and probably not worth it for that reason, and not as critical
524 * as RX which can overrun memory and lose packets.
525 */
526 #include <linux/dma-mapping.h>
527 #include <asm/dma.h>
528 #include <asm/arch/pxa-regs.h>
529
530 #ifdef SMC_insl
531 #undef SMC_insl
532 #define SMC_insl(a, r, p, l) \
533 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
534 static inline void
535 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
536 u_char *buf, int len)
537 {
538 u_long physaddr = lp->physaddr;
539 dma_addr_t dmabuf;
540
541 /* fallback if no DMA available */
542 if (dma == (unsigned char)-1) {
543 readsl(ioaddr + reg, buf, len);
544 return;
545 }
546
547 /* 64 bit alignment is required for memory to memory DMA */
548 if ((long)buf & 4) {
549 *((u32 *)buf) = SMC_inl(ioaddr, reg);
550 buf += 4;
551 len--;
552 }
553
554 len *= 4;
555 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
556 DCSR(dma) = DCSR_NODESC;
557 DTADR(dma) = dmabuf;
558 DSADR(dma) = physaddr + reg;
559 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
560 DCMD_WIDTH4 | (DCMD_LENGTH & len));
561 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
562 while (!(DCSR(dma) & DCSR_STOPSTATE))
563 cpu_relax();
564 DCSR(dma) = 0;
565 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
566 }
567 #endif
568
569 #ifdef SMC_insw
570 #undef SMC_insw
571 #define SMC_insw(a, r, p, l) \
572 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
573 static inline void
574 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
575 u_char *buf, int len)
576 {
577 u_long physaddr = lp->physaddr;
578 dma_addr_t dmabuf;
579
580 /* fallback if no DMA available */
581 if (dma == (unsigned char)-1) {
582 readsw(ioaddr + reg, buf, len);
583 return;
584 }
585
586 /* 64 bit alignment is required for memory to memory DMA */
587 while ((long)buf & 6) {
588 *((u16 *)buf) = SMC_inw(ioaddr, reg);
589 buf += 2;
590 len--;
591 }
592
593 len *= 2;
594 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
595 DCSR(dma) = DCSR_NODESC;
596 DTADR(dma) = dmabuf;
597 DSADR(dma) = physaddr + reg;
598 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
599 DCMD_WIDTH2 | (DCMD_LENGTH & len));
600 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
601 while (!(DCSR(dma) & DCSR_STOPSTATE))
602 cpu_relax();
603 DCSR(dma) = 0;
604 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
605 }
606 #endif
607
608 static void
609 smc_pxa_dma_irq(int dma, void *dummy)
610 {
611 DCSR(dma) = 0;
612 }
613 #endif /* CONFIG_ARCH_PXA */
614
615
616 /*
617 * Everything a particular hardware setup needs should have been defined
618 * at this point. Add stubs for the undefined cases, mainly to avoid
619 * compilation warnings since they'll be optimized away, or to prevent buggy
620 * use of them.
621 */
622
623 #if ! SMC_CAN_USE_32BIT
624 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
625 #define SMC_outl(x, ioaddr, reg) BUG()
626 #define SMC_insl(a, r, p, l) BUG()
627 #define SMC_outsl(a, r, p, l) BUG()
628 #endif
629
630 #if !defined(SMC_insl) || !defined(SMC_outsl)
631 #define SMC_insl(a, r, p, l) BUG()
632 #define SMC_outsl(a, r, p, l) BUG()
633 #endif
634
635 #if ! SMC_CAN_USE_16BIT
636
637 /*
638 * Any 16-bit access is performed with two 8-bit accesses if the hardware
639 * can't do it directly. Most registers are 16-bit so those are mandatory.
640 */
641 #define SMC_outw(x, ioaddr, reg) \
642 do { \
643 unsigned int __val16 = (x); \
644 SMC_outb( __val16, ioaddr, reg ); \
645 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
646 } while (0)
647 #define SMC_inw(ioaddr, reg) \
648 ({ \
649 unsigned int __val16; \
650 __val16 = SMC_inb( ioaddr, reg ); \
651 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
652 __val16; \
653 })
654
655 #define SMC_insw(a, r, p, l) BUG()
656 #define SMC_outsw(a, r, p, l) BUG()
657
658 #endif
659
660 #if !defined(SMC_insw) || !defined(SMC_outsw)
661 #define SMC_insw(a, r, p, l) BUG()
662 #define SMC_outsw(a, r, p, l) BUG()
663 #endif
664
665 #if ! SMC_CAN_USE_8BIT
666 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
667 #define SMC_outb(x, ioaddr, reg) BUG()
668 #define SMC_insb(a, r, p, l) BUG()
669 #define SMC_outsb(a, r, p, l) BUG()
670 #endif
671
672 #if !defined(SMC_insb) || !defined(SMC_outsb)
673 #define SMC_insb(a, r, p, l) BUG()
674 #define SMC_outsb(a, r, p, l) BUG()
675 #endif
676
677 #ifndef SMC_CAN_USE_DATACS
678 #define SMC_CAN_USE_DATACS 0
679 #endif
680
681 #ifndef SMC_IO_SHIFT
682 #define SMC_IO_SHIFT 0
683 #endif
684
685 #ifndef SMC_IRQ_FLAGS
686 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
687 #endif
688
689 #ifndef SMC_INTERRUPT_PREAMBLE
690 #define SMC_INTERRUPT_PREAMBLE
691 #endif
692
693
694 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
695 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
696 #define SMC_DATA_EXTENT (4)
697
698 /*
699 . Bank Select Register:
700 .
701 . yyyy yyyy 0000 00xx
702 . xx = bank number
703 . yyyy yyyy = 0x33, for identification purposes.
704 */
705 #define BANK_SELECT (14 << SMC_IO_SHIFT)
706
707
708 // Transmit Control Register
709 /* BANK 0 */
710 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
711 #define TCR_ENABLE 0x0001 // When 1 we can transmit
712 #define TCR_LOOP 0x0002 // Controls output pin LBK
713 #define TCR_FORCOL 0x0004 // When 1 will force a collision
714 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
715 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
716 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
717 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
718 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
719 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
720 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
721
722 #define TCR_CLEAR 0 /* do NOTHING */
723 /* the default settings for the TCR register : */
724 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
725
726
727 // EPH Status Register
728 /* BANK 0 */
729 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
730 #define ES_TX_SUC 0x0001 // Last TX was successful
731 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
732 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
733 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
734 #define ES_16COL 0x0010 // 16 Collisions Reached
735 #define ES_SQET 0x0020 // Signal Quality Error Test
736 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
737 #define ES_TXDEFR 0x0080 // Transmit Deferred
738 #define ES_LATCOL 0x0200 // Late collision detected on last tx
739 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
740 #define ES_EXC_DEF 0x0800 // Excessive Deferral
741 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
742 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
743 #define ES_TXUNRN 0x8000 // Tx Underrun
744
745
746 // Receive Control Register
747 /* BANK 0 */
748 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
749 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
750 #define RCR_PRMS 0x0002 // Enable promiscuous mode
751 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
752 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
753 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
754 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
755 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
756 #define RCR_SOFTRST 0x8000 // resets the chip
757
758 /* the normal settings for the RCR register : */
759 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
760 #define RCR_CLEAR 0x0 // set it to a base state
761
762
763 // Counter Register
764 /* BANK 0 */
765 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
766
767
768 // Memory Information Register
769 /* BANK 0 */
770 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
771
772
773 // Receive/Phy Control Register
774 /* BANK 0 */
775 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
776 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
777 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
778 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
779 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
780 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
781 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
782 #define RPC_LED_RES (0x01) // LED = Reserved
783 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
784 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
785 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
786 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
787 #define RPC_LED_TX (0x06) // LED = TX packet occurred
788 #define RPC_LED_RX (0x07) // LED = RX packet occurred
789
790 #ifndef RPC_LSA_DEFAULT
791 #define RPC_LSA_DEFAULT RPC_LED_100
792 #endif
793 #ifndef RPC_LSB_DEFAULT
794 #define RPC_LSB_DEFAULT RPC_LED_FD
795 #endif
796
797 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
798
799
800 /* Bank 0 0x0C is reserved */
801
802 // Bank Select Register
803 /* All Banks */
804 #define BSR_REG 0x000E
805
806
807 // Configuration Reg
808 /* BANK 1 */
809 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
810 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
811 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
812 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
813 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
814
815 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
816 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
817
818
819 // Base Address Register
820 /* BANK 1 */
821 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
822
823
824 // Individual Address Registers
825 /* BANK 1 */
826 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
827 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
828 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
829
830
831 // General Purpose Register
832 /* BANK 1 */
833 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
834
835
836 // Control Register
837 /* BANK 1 */
838 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
839 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
840 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
841 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
842 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
843 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
844 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
845 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
846 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
847
848
849 // MMU Command Register
850 /* BANK 2 */
851 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
852 #define MC_BUSY 1 // When 1 the last release has not completed
853 #define MC_NOP (0<<5) // No Op
854 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
855 #define MC_RESET (2<<5) // Reset MMU to initial state
856 #define MC_REMOVE (3<<5) // Remove the current rx packet
857 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
858 #define MC_FREEPKT (5<<5) // Release packet in PNR register
859 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
860 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
861
862
863 // Packet Number Register
864 /* BANK 2 */
865 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
866
867
868 // Allocation Result Register
869 /* BANK 2 */
870 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
871 #define AR_FAILED 0x80 // Alocation Failed
872
873
874 // TX FIFO Ports Register
875 /* BANK 2 */
876 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
877 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
878
879 // RX FIFO Ports Register
880 /* BANK 2 */
881 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
882 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
883
884 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
885
886 // Pointer Register
887 /* BANK 2 */
888 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
889 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
890 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
891 #define PTR_READ 0x2000 // When 1 the operation is a read
892
893
894 // Data Register
895 /* BANK 2 */
896 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
897
898
899 // Interrupt Status/Acknowledge Register
900 /* BANK 2 */
901 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
902
903
904 // Interrupt Mask Register
905 /* BANK 2 */
906 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
907 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
908 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
909 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
910 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
911 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
912 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
913 #define IM_TX_INT 0x02 // Transmit Interrupt
914 #define IM_RCV_INT 0x01 // Receive Interrupt
915
916
917 // Multicast Table Registers
918 /* BANK 3 */
919 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
920 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
921 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
922 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
923
924
925 // Management Interface Register (MII)
926 /* BANK 3 */
927 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
928 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
929 #define MII_MDOE 0x0008 // MII Output Enable
930 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
931 #define MII_MDI 0x0002 // MII Input, pin MDI
932 #define MII_MDO 0x0001 // MII Output, pin MDO
933
934
935 // Revision Register
936 /* BANK 3 */
937 /* ( hi: chip id low: rev # ) */
938 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
939
940
941 // Early RCV Register
942 /* BANK 3 */
943 /* this is NOT on SMC9192 */
944 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
945 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
946 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
947
948
949 // External Register
950 /* BANK 7 */
951 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
952
953
954 #define CHIP_9192 3
955 #define CHIP_9194 4
956 #define CHIP_9195 5
957 #define CHIP_9196 6
958 #define CHIP_91100 7
959 #define CHIP_91100FD 8
960 #define CHIP_91111FD 9
961
962 static const char * chip_ids[ 16 ] = {
963 NULL, NULL, NULL,
964 /* 3 */ "SMC91C90/91C92",
965 /* 4 */ "SMC91C94",
966 /* 5 */ "SMC91C95",
967 /* 6 */ "SMC91C96",
968 /* 7 */ "SMC91C100",
969 /* 8 */ "SMC91C100FD",
970 /* 9 */ "SMC91C11xFD",
971 NULL, NULL, NULL,
972 NULL, NULL, NULL};
973
974
975 /*
976 . Receive status bits
977 */
978 #define RS_ALGNERR 0x8000
979 #define RS_BRODCAST 0x4000
980 #define RS_BADCRC 0x2000
981 #define RS_ODDFRAME 0x1000
982 #define RS_TOOLONG 0x0800
983 #define RS_TOOSHORT 0x0400
984 #define RS_MULTICAST 0x0001
985 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
986
987
988 /*
989 * PHY IDs
990 * LAN83C183 == LAN91C111 Internal PHY
991 */
992 #define PHY_LAN83C183 0x0016f840
993 #define PHY_LAN83C180 0x02821c50
994
995 /*
996 * PHY Register Addresses (LAN91C111 Internal PHY)
997 *
998 * Generic PHY registers can be found in <linux/mii.h>
999 *
1000 * These phy registers are specific to our on-board phy.
1001 */
1002
1003 // PHY Configuration Register 1
1004 #define PHY_CFG1_REG 0x10
1005 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1006 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1007 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1008 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1009 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1010 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1011 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1012 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1013 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1014 #define PHY_CFG1_TLVL_MASK 0x003C
1015 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1016
1017
1018 // PHY Configuration Register 2
1019 #define PHY_CFG2_REG 0x11
1020 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1021 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1022 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1023 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1024
1025 // PHY Status Output (and Interrupt status) Register
1026 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1027 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1028 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1029 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1030 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1031 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1032 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1033 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1034 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1035 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1036 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1037
1038 // PHY Interrupt/Status Mask Register
1039 #define PHY_MASK_REG 0x13 // Interrupt Mask
1040 // Uses the same bit definitions as PHY_INT_REG
1041
1042
1043 /*
1044 * SMC91C96 ethernet config and status registers.
1045 * These are in the "attribute" space.
1046 */
1047 #define ECOR 0x8000
1048 #define ECOR_RESET 0x80
1049 #define ECOR_LEVEL_IRQ 0x40
1050 #define ECOR_WR_ATTRIB 0x04
1051 #define ECOR_ENABLE 0x01
1052
1053 #define ECSR 0x8002
1054 #define ECSR_IOIS8 0x20
1055 #define ECSR_PWRDWN 0x04
1056 #define ECSR_INT 0x02
1057
1058 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1059
1060
1061 /*
1062 * Macros to abstract register access according to the data bus
1063 * capabilities. Please use those and not the in/out primitives.
1064 * Note: the following macros do *not* select the bank -- this must
1065 * be done separately as needed in the main code. The SMC_REG() macro
1066 * only uses the bank argument for debugging purposes (when enabled).
1067 *
1068 * Note: despite inline functions being safer, everything leading to this
1069 * should preferably be macros to let BUG() display the line number in
1070 * the core source code since we're interested in the top call site
1071 * not in any inline function location.
1072 */
1073
1074 #if SMC_DEBUG > 0
1075 #define SMC_REG(lp, reg, bank) \
1076 ({ \
1077 int __b = SMC_CURRENT_BANK(lp); \
1078 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1079 printk( "%s: bank reg screwed (0x%04x)\n", \
1080 CARDNAME, __b ); \
1081 BUG(); \
1082 } \
1083 reg<<SMC_IO_SHIFT; \
1084 })
1085 #else
1086 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1087 #endif
1088
1089 /*
1090 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1091 * aligned to a 32 bit boundary. I tell you that does exist!
1092 * Fortunately the affected register accesses can be easily worked around
1093 * since we can write zeroes to the preceeding 16 bits without adverse
1094 * effects and use a 32-bit access.
1095 *
1096 * Enforce it on any 32-bit capable setup for now.
1097 */
1098 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1099
1100 #define SMC_GET_PN(lp) \
1101 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1102 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1103
1104 #define SMC_SET_PN(lp, x) \
1105 do { \
1106 if (SMC_MUST_ALIGN_WRITE(lp)) \
1107 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1108 else if (SMC_8BIT(lp)) \
1109 SMC_outb(x, ioaddr, PN_REG(lp)); \
1110 else \
1111 SMC_outw(x, ioaddr, PN_REG(lp)); \
1112 } while (0)
1113
1114 #define SMC_GET_AR(lp) \
1115 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1116 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1117
1118 #define SMC_GET_TXFIFO(lp) \
1119 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1120 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1121
1122 #define SMC_GET_RXFIFO(lp) \
1123 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1124 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1125
1126 #define SMC_GET_INT(lp) \
1127 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1128 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1129
1130 #define SMC_ACK_INT(lp, x) \
1131 do { \
1132 if (SMC_8BIT(lp)) \
1133 SMC_outb(x, ioaddr, INT_REG(lp)); \
1134 else { \
1135 unsigned long __flags; \
1136 int __mask; \
1137 local_irq_save(__flags); \
1138 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1139 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1140 local_irq_restore(__flags); \
1141 } \
1142 } while (0)
1143
1144 #define SMC_GET_INT_MASK(lp) \
1145 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1146 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1147
1148 #define SMC_SET_INT_MASK(lp, x) \
1149 do { \
1150 if (SMC_8BIT(lp)) \
1151 SMC_outb(x, ioaddr, IM_REG(lp)); \
1152 else \
1153 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1154 } while (0)
1155
1156 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1157
1158 #define SMC_SELECT_BANK(lp, x) \
1159 do { \
1160 if (SMC_MUST_ALIGN_WRITE(lp)) \
1161 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1162 else \
1163 SMC_outw(x, ioaddr, BANK_SELECT); \
1164 } while (0)
1165
1166 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1167
1168 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1169
1170 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1171
1172 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1173
1174 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1175
1176 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1177
1178 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1179
1180 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1181
1182 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1183
1184 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1185
1186 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1187
1188 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1189
1190 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1191
1192 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1193
1194 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1195
1196 #define SMC_SET_PTR(lp, x) \
1197 do { \
1198 if (SMC_MUST_ALIGN_WRITE(lp)) \
1199 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1200 else \
1201 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1202 } while (0)
1203
1204 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1205
1206 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1207
1208 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1209
1210 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1211
1212 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1213
1214 #define SMC_SET_RPC(lp, x) \
1215 do { \
1216 if (SMC_MUST_ALIGN_WRITE(lp)) \
1217 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1218 else \
1219 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1220 } while (0)
1221
1222 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1223
1224 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1225
1226 #ifndef SMC_GET_MAC_ADDR
1227 #define SMC_GET_MAC_ADDR(lp, addr) \
1228 do { \
1229 unsigned int __v; \
1230 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1231 addr[0] = __v; addr[1] = __v >> 8; \
1232 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1233 addr[2] = __v; addr[3] = __v >> 8; \
1234 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1235 addr[4] = __v; addr[5] = __v >> 8; \
1236 } while (0)
1237 #endif
1238
1239 #define SMC_SET_MAC_ADDR(lp, addr) \
1240 do { \
1241 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1242 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1243 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1244 } while (0)
1245
1246 #define SMC_SET_MCAST(lp, x) \
1247 do { \
1248 const unsigned char *mt = (x); \
1249 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1250 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1251 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1252 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1253 } while (0)
1254
1255 #define SMC_PUT_PKT_HDR(lp, status, length) \
1256 do { \
1257 if (SMC_32BIT(lp)) \
1258 SMC_outl((status) | (length)<<16, ioaddr, \
1259 DATA_REG(lp)); \
1260 else { \
1261 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1262 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1263 } \
1264 } while (0)
1265
1266 #define SMC_GET_PKT_HDR(lp, status, length) \
1267 do { \
1268 if (SMC_32BIT(lp)) { \
1269 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1270 (status) = __val & 0xffff; \
1271 (length) = __val >> 16; \
1272 } else { \
1273 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1274 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1275 } \
1276 } while (0)
1277
1278 #define SMC_PUSH_DATA(lp, p, l) \
1279 do { \
1280 if (SMC_32BIT(lp)) { \
1281 void *__ptr = (p); \
1282 int __len = (l); \
1283 void __iomem *__ioaddr = ioaddr; \
1284 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1285 __len -= 2; \
1286 SMC_outw(*(u16 *)__ptr, ioaddr, \
1287 DATA_REG(lp)); \
1288 __ptr += 2; \
1289 } \
1290 if (SMC_CAN_USE_DATACS && lp->datacs) \
1291 __ioaddr = lp->datacs; \
1292 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1293 if (__len & 2) { \
1294 __ptr += (__len & ~3); \
1295 SMC_outw(*((u16 *)__ptr), ioaddr, \
1296 DATA_REG(lp)); \
1297 } \
1298 } else if (SMC_16BIT(lp)) \
1299 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1300 else if (SMC_8BIT(lp)) \
1301 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1302 } while (0)
1303
1304 #define SMC_PULL_DATA(lp, p, l) \
1305 do { \
1306 if (SMC_32BIT(lp)) { \
1307 void *__ptr = (p); \
1308 int __len = (l); \
1309 void __iomem *__ioaddr = ioaddr; \
1310 if ((unsigned long)__ptr & 2) { \
1311 /* \
1312 * We want 32bit alignment here. \
1313 * Since some buses perform a full \
1314 * 32bit fetch even for 16bit data \
1315 * we can't use SMC_inw() here. \
1316 * Back both source (on-chip) and \
1317 * destination pointers of 2 bytes. \
1318 * This is possible since the call to \
1319 * SMC_GET_PKT_HDR() already advanced \
1320 * the source pointer of 4 bytes, and \
1321 * the skb_reserve(skb, 2) advanced \
1322 * the destination pointer of 2 bytes. \
1323 */ \
1324 __ptr -= 2; \
1325 __len += 2; \
1326 SMC_SET_PTR(lp, \
1327 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1328 } \
1329 if (SMC_CAN_USE_DATACS && lp->datacs) \
1330 __ioaddr = lp->datacs; \
1331 __len += 2; \
1332 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1333 } else if (SMC_16BIT(lp)) \
1334 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1335 else if (SMC_8BIT(lp)) \
1336 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1337 } while (0)
1338
1339 #endif /* _SMC91X_H_ */
Support for the Chinese Samsung S3C2440 based development boards