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Char: mxser, ratelimit ioctl warning
[linux-2.6/mini2440.git] / drivers / net / bnx2x.h
blob4bf4f7b205f24a62d3ed8fefcbc7cbdb443cc197
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2008 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 /* error/debug prints */
24
25 #define DRV_MODULE_NAME "bnx2x"
26 #define PFX DRV_MODULE_NAME ": "
27
28 /* for messages that are currently off */
29 #define BNX2X_MSG_OFF 0
30 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
31 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
32 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
33 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
34 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
35 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
36
37 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
38
39 /* regular debug print */
40 #define DP(__mask, __fmt, __args...) do { \
41 if (bp->msglevel & (__mask)) \
42 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
43 bp->dev?(bp->dev->name):"?", ##__args); \
44 } while (0)
45
46 /* errors debug print */
47 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
48 if (bp->msglevel & NETIF_MSG_PROBE) \
49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
50 bp->dev?(bp->dev->name):"?", ##__args); \
51 } while (0)
52
53 /* for errors (never masked) */
54 #define BNX2X_ERR(__fmt, __args...) do { \
55 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
56 bp->dev?(bp->dev->name):"?", ##__args); \
57 } while (0)
58
59 /* before we have a dev->name use dev_info() */
60 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
61 if (bp->msglevel & NETIF_MSG_PROBE) \
62 dev_info(&bp->pdev->dev, __fmt, ##__args); \
63 } while (0)
64
65
66 #ifdef BNX2X_STOP_ON_ERROR
67 #define bnx2x_panic() do { \
68 bp->panic = 1; \
69 BNX2X_ERR("driver assert\n"); \
70 bnx2x_int_disable(bp); \
71 bnx2x_panic_dump(bp); \
72 } while (0)
73 #else
74 #define bnx2x_panic() do { \
75 BNX2X_ERR("driver assert\n"); \
76 bnx2x_panic_dump(bp); \
77 } while (0)
78 #endif
79
80
81 #ifdef NETIF_F_HW_VLAN_TX
82 #define BCM_VLAN 1
83 #endif
84
85
86 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
87 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
88 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
89
90
91 #define REG_ADDR(bp, offset) (bp->regview + offset)
92
93 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
94 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
95 #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
96
97 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
98 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
99 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
100 #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
101
102 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
103 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
104
105 #define REG_RD_DMAE(bp, offset, valp, len32) \
106 do { \
107 bnx2x_read_dmae(bp, offset, len32);\
108 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
109 } while (0)
110
111 #define REG_WR_DMAE(bp, offset, valp, len32) \
112 do { \
113 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
114 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
115 offset, len32); \
116 } while (0)
117
118 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
119 offsetof(struct shmem_region, field))
120 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
121 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
122
123 #define NIG_WR(reg, val) REG_WR(bp, reg, val)
124 #define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
125 #define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
126
127
128 #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
129
130 #define for_each_nondefault_queue(bp, var) \
131 for (var = 1; var < bp->num_queues; var++)
132 #define is_multi(bp) (bp->num_queues > 1)
133
134
135 /* fast path */
136
137 struct sw_rx_bd {
138 struct sk_buff *skb;
139 DECLARE_PCI_UNMAP_ADDR(mapping)
140 };
141
142 struct sw_tx_bd {
143 struct sk_buff *skb;
144 u16 first_bd;
145 };
146
147 struct sw_rx_page {
148 struct page *page;
149 DECLARE_PCI_UNMAP_ADDR(mapping)
150 };
151
152
153 /* MC hsi */
154 #define BCM_PAGE_SHIFT 12
155 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
156 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
157 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
158
159 #define PAGES_PER_SGE_SHIFT 0
160 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
161
162 /* SGE ring related macros */
163 #define NUM_RX_SGE_PAGES 2
164 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
165 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
166 /* RX_SGE_CNT is promissed to be a power of 2 */
167 #define RX_SGE_MASK (RX_SGE_CNT - 1)
168 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
169 #define MAX_RX_SGE (NUM_RX_SGE - 1)
170 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
171 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
172 #define RX_SGE(x) ((x) & MAX_RX_SGE)
173
174 /* SGE producer mask related macros */
175 /* Number of bits in one sge_mask array element */
176 #define RX_SGE_MASK_ELEM_SZ 64
177 #define RX_SGE_MASK_ELEM_SHIFT 6
178 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
179
180 /* Creates a bitmask of all ones in less significant bits.
181 idx - index of the most significant bit in the created mask */
182 #define RX_SGE_ONES_MASK(idx) \
183 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
184 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
185
186 /* Number of u64 elements in SGE mask array */
187 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
188 RX_SGE_MASK_ELEM_SZ)
189 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
190 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
191
192
193 struct bnx2x_fastpath {
194
195 struct napi_struct napi;
196
197 struct host_status_block *status_blk;
198 dma_addr_t status_blk_mapping;
199
200 struct eth_tx_db_data *hw_tx_prods;
201 dma_addr_t tx_prods_mapping;
202
203 struct sw_tx_bd *tx_buf_ring;
204
205 struct eth_tx_bd *tx_desc_ring;
206 dma_addr_t tx_desc_mapping;
207
208 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
209 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
210
211 struct eth_rx_bd *rx_desc_ring;
212 dma_addr_t rx_desc_mapping;
213
214 union eth_rx_cqe *rx_comp_ring;
215 dma_addr_t rx_comp_mapping;
216
217 /* SGE ring */
218 struct eth_rx_sge *rx_sge_ring;
219 dma_addr_t rx_sge_mapping;
220
221 u64 sge_mask[RX_SGE_MASK_LEN];
222
223 int state;
224 #define BNX2X_FP_STATE_CLOSED 0
225 #define BNX2X_FP_STATE_IRQ 0x80000
226 #define BNX2X_FP_STATE_OPENING 0x90000
227 #define BNX2X_FP_STATE_OPEN 0xa0000
228 #define BNX2X_FP_STATE_HALTING 0xb0000
229 #define BNX2X_FP_STATE_HALTED 0xc0000
230
231 u8 index; /* number in fp array */
232 u8 cl_id; /* eth client id */
233 u8 sb_id; /* status block number in HW */
234 #define FP_IDX(fp) (fp->index)
235 #define FP_CL_ID(fp) (fp->cl_id)
236 #define BP_CL_ID(bp) (bp->fp[0].cl_id)
237 #define FP_SB_ID(fp) (fp->sb_id)
238 #define CNIC_SB_ID 0
239
240 u16 tx_pkt_prod;
241 u16 tx_pkt_cons;
242 u16 tx_bd_prod;
243 u16 tx_bd_cons;
244 u16 *tx_cons_sb;
245
246 u16 fp_c_idx;
247 u16 fp_u_idx;
248
249 u16 rx_bd_prod;
250 u16 rx_bd_cons;
251 u16 rx_comp_prod;
252 u16 rx_comp_cons;
253 u16 rx_sge_prod;
254 /* The last maximal completed SGE */
255 u16 last_max_sge;
256 u16 *rx_cons_sb;
257 u16 *rx_bd_cons_sb;
258
259 unsigned long tx_pkt,
260 rx_pkt,
261 rx_calls,
262 rx_alloc_failed;
263 /* TPA related */
264 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
265 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
266 #define BNX2X_TPA_START 1
267 #define BNX2X_TPA_STOP 2
268 u8 disable_tpa;
269 #ifdef BNX2X_STOP_ON_ERROR
270 u64 tpa_queue_used;
271 #endif
272
273 struct bnx2x *bp; /* parent */
274 };
275
276 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
277
278
279 /* MC hsi */
280 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
281 #define RX_COPY_THRESH 92
282
283 #define NUM_TX_RINGS 16
284 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
285 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
286 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
287 #define MAX_TX_BD (NUM_TX_BD - 1)
288 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
289 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
290 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
291 #define TX_BD(x) ((x) & MAX_TX_BD)
292 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
293
294 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
295 #define NUM_RX_RINGS 8
296 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
297 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
298 #define RX_DESC_MASK (RX_DESC_CNT - 1)
299 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
300 #define MAX_RX_BD (NUM_RX_BD - 1)
301 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
302 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
303 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
304 #define RX_BD(x) ((x) & MAX_RX_BD)
305
306 /* As long as CQE is 4 times bigger than BD entry we have to allocate
307 4 times more pages for CQ ring in order to keep it balanced with
308 BD ring */
309 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
310 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
311 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
312 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
313 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
314 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
315 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
316 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
317 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
318
319
320 /* This is needed for determening of last_max */
321 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
322
323 #define __SGE_MASK_SET_BIT(el, bit) \
324 do { \
325 el = ((el) | ((u64)0x1 << (bit))); \
326 } while (0)
327
328 #define __SGE_MASK_CLEAR_BIT(el, bit) \
329 do { \
330 el = ((el) & (~((u64)0x1 << (bit)))); \
331 } while (0)
332
333 #define SGE_MASK_SET_BIT(fp, idx) \
334 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
335 ((idx) & RX_SGE_MASK_ELEM_MASK))
336
337 #define SGE_MASK_CLEAR_BIT(fp, idx) \
338 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
339 ((idx) & RX_SGE_MASK_ELEM_MASK))
340
341
342 /* used on a CID received from the HW */
343 #define SW_CID(x) (le32_to_cpu(x) & \
344 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
345 #define CQE_CMD(x) (le32_to_cpu(x) >> \
346 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
347
348 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
349 le32_to_cpu((bd)->addr_lo))
350 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
351
352
353 #define DPM_TRIGER_TYPE 0x40
354 #define DOORBELL(bp, cid, val) \
355 do { \
356 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
357 DPM_TRIGER_TYPE); \
358 } while (0)
359
360
361 /* TX CSUM helpers */
362 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
363 skb->csum_offset)
364 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
365 skb->csum_offset))
366
367 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
368
369 #define XMIT_PLAIN 0
370 #define XMIT_CSUM_V4 0x1
371 #define XMIT_CSUM_V6 0x2
372 #define XMIT_CSUM_TCP 0x4
373 #define XMIT_GSO_V4 0x8
374 #define XMIT_GSO_V6 0x10
375
376 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
377 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
378
379
380 /* stuff added to make the code fit 80Col */
381
382 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
383
384 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
385 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
386 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
387 (TPA_TYPE_START | TPA_TYPE_END))
388
389 #define BNX2X_RX_SUM_OK(cqe) \
390 (!(cqe->fast_path_cqe.status_flags & \
391 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
392 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
393
394 #define BNX2X_RX_SUM_FIX(cqe) \
395 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
396 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
397 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
398
399 #define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
400 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
401 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
402
403
404 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
405 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
406
407 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
408 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
409 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
410
411 #define BNX2X_RX_SB_INDEX \
412 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
413
414 #define BNX2X_RX_SB_BD_INDEX \
415 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
416
417 #define BNX2X_RX_SB_INDEX_NUM \
418 (((U_SB_ETH_RX_CQ_INDEX << \
419 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
420 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
421 ((U_SB_ETH_RX_BD_INDEX << \
422 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
423 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
424
425 #define BNX2X_TX_SB_INDEX \
426 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
427
428
429 /* end of fast path */
430
431 /* common */
432
433 struct bnx2x_common {
434
435 u32 chip_id;
436 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
437 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
438
439 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
440 #define CHIP_NUM_57710 0x164e
441 #define CHIP_NUM_57711 0x164f
442 #define CHIP_NUM_57711E 0x1650
443 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
444 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
445 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
446 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
447 CHIP_IS_57711E(bp))
448 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
449
450 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
451 #define CHIP_REV_Ax 0x00000000
452 /* assume maximum 5 revisions */
453 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
454 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
455 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
456 !(CHIP_REV(bp) & 0x00001000))
457 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
458 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
459 (CHIP_REV(bp) & 0x00001000))
460
461 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
462 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
463
464 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
465 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
466
467 int flash_size;
468 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
469 #define NVRAM_TIMEOUT_COUNT 30000
470 #define NVRAM_PAGE_SIZE 256
471
472 u32 shmem_base;
473
474 u32 hw_config;
475 u32 board;
476
477 u32 bc_ver;
478
479 char *name;
480 };
481
482
483 /* end of common */
484
485 /* port */
486
487 struct nig_stats {
488 u32 brb_discard;
489 u32 brb_packet;
490 u32 brb_truncate;
491 u32 flow_ctrl_discard;
492 u32 flow_ctrl_octets;
493 u32 flow_ctrl_packet;
494 u32 mng_discard;
495 u32 mng_octet_inp;
496 u32 mng_octet_out;
497 u32 mng_packet_inp;
498 u32 mng_packet_out;
499 u32 pbf_octets;
500 u32 pbf_packet;
501 u32 safc_inp;
502 u32 egress_mac_pkt0_lo;
503 u32 egress_mac_pkt0_hi;
504 u32 egress_mac_pkt1_lo;
505 u32 egress_mac_pkt1_hi;
506 };
507
508 struct bnx2x_port {
509 u32 pmf;
510
511 u32 link_config;
512
513 u32 supported;
514 /* link settings - missing defines */
515 #define SUPPORTED_2500baseX_Full (1 << 15)
516
517 u32 advertising;
518 /* link settings - missing defines */
519 #define ADVERTISED_2500baseX_Full (1 << 15)
520
521 u32 phy_addr;
522
523 /* used to synchronize phy accesses */
524 struct mutex phy_mutex;
525
526 u32 port_stx;
527
528 struct nig_stats old_nig_stats;
529 };
530
531 /* end of port */
532
533
534 enum bnx2x_stats_event {
535 STATS_EVENT_PMF = 0,
536 STATS_EVENT_LINK_UP,
537 STATS_EVENT_UPDATE,
538 STATS_EVENT_STOP,
539 STATS_EVENT_MAX
540 };
541
542 enum bnx2x_stats_state {
543 STATS_STATE_DISABLED = 0,
544 STATS_STATE_ENABLED,
545 STATS_STATE_MAX
546 };
547
548 struct bnx2x_eth_stats {
549 u32 total_bytes_received_hi;
550 u32 total_bytes_received_lo;
551 u32 total_bytes_transmitted_hi;
552 u32 total_bytes_transmitted_lo;
553 u32 total_unicast_packets_received_hi;
554 u32 total_unicast_packets_received_lo;
555 u32 total_multicast_packets_received_hi;
556 u32 total_multicast_packets_received_lo;
557 u32 total_broadcast_packets_received_hi;
558 u32 total_broadcast_packets_received_lo;
559 u32 total_unicast_packets_transmitted_hi;
560 u32 total_unicast_packets_transmitted_lo;
561 u32 total_multicast_packets_transmitted_hi;
562 u32 total_multicast_packets_transmitted_lo;
563 u32 total_broadcast_packets_transmitted_hi;
564 u32 total_broadcast_packets_transmitted_lo;
565 u32 valid_bytes_received_hi;
566 u32 valid_bytes_received_lo;
567
568 u32 error_bytes_received_hi;
569 u32 error_bytes_received_lo;
570
571 u32 rx_stat_ifhcinbadoctets_hi;
572 u32 rx_stat_ifhcinbadoctets_lo;
573 u32 tx_stat_ifhcoutbadoctets_hi;
574 u32 tx_stat_ifhcoutbadoctets_lo;
575 u32 rx_stat_dot3statsfcserrors_hi;
576 u32 rx_stat_dot3statsfcserrors_lo;
577 u32 rx_stat_dot3statsalignmenterrors_hi;
578 u32 rx_stat_dot3statsalignmenterrors_lo;
579 u32 rx_stat_dot3statscarriersenseerrors_hi;
580 u32 rx_stat_dot3statscarriersenseerrors_lo;
581 u32 rx_stat_falsecarriererrors_hi;
582 u32 rx_stat_falsecarriererrors_lo;
583 u32 rx_stat_etherstatsundersizepkts_hi;
584 u32 rx_stat_etherstatsundersizepkts_lo;
585 u32 rx_stat_dot3statsframestoolong_hi;
586 u32 rx_stat_dot3statsframestoolong_lo;
587 u32 rx_stat_etherstatsfragments_hi;
588 u32 rx_stat_etherstatsfragments_lo;
589 u32 rx_stat_etherstatsjabbers_hi;
590 u32 rx_stat_etherstatsjabbers_lo;
591 u32 rx_stat_maccontrolframesreceived_hi;
592 u32 rx_stat_maccontrolframesreceived_lo;
593 u32 rx_stat_bmac_xpf_hi;
594 u32 rx_stat_bmac_xpf_lo;
595 u32 rx_stat_bmac_xcf_hi;
596 u32 rx_stat_bmac_xcf_lo;
597 u32 rx_stat_xoffstateentered_hi;
598 u32 rx_stat_xoffstateentered_lo;
599 u32 rx_stat_xonpauseframesreceived_hi;
600 u32 rx_stat_xonpauseframesreceived_lo;
601 u32 rx_stat_xoffpauseframesreceived_hi;
602 u32 rx_stat_xoffpauseframesreceived_lo;
603 u32 tx_stat_outxonsent_hi;
604 u32 tx_stat_outxonsent_lo;
605 u32 tx_stat_outxoffsent_hi;
606 u32 tx_stat_outxoffsent_lo;
607 u32 tx_stat_flowcontroldone_hi;
608 u32 tx_stat_flowcontroldone_lo;
609 u32 tx_stat_etherstatscollisions_hi;
610 u32 tx_stat_etherstatscollisions_lo;
611 u32 tx_stat_dot3statssinglecollisionframes_hi;
612 u32 tx_stat_dot3statssinglecollisionframes_lo;
613 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
614 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
615 u32 tx_stat_dot3statsdeferredtransmissions_hi;
616 u32 tx_stat_dot3statsdeferredtransmissions_lo;
617 u32 tx_stat_dot3statsexcessivecollisions_hi;
618 u32 tx_stat_dot3statsexcessivecollisions_lo;
619 u32 tx_stat_dot3statslatecollisions_hi;
620 u32 tx_stat_dot3statslatecollisions_lo;
621 u32 tx_stat_etherstatspkts64octets_hi;
622 u32 tx_stat_etherstatspkts64octets_lo;
623 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
624 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
625 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
626 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
627 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
628 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
629 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
630 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
631 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
632 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
633 u32 tx_stat_etherstatspktsover1522octets_hi;
634 u32 tx_stat_etherstatspktsover1522octets_lo;
635 u32 tx_stat_bmac_2047_hi;
636 u32 tx_stat_bmac_2047_lo;
637 u32 tx_stat_bmac_4095_hi;
638 u32 tx_stat_bmac_4095_lo;
639 u32 tx_stat_bmac_9216_hi;
640 u32 tx_stat_bmac_9216_lo;
641 u32 tx_stat_bmac_16383_hi;
642 u32 tx_stat_bmac_16383_lo;
643 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
644 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
645 u32 tx_stat_bmac_ufl_hi;
646 u32 tx_stat_bmac_ufl_lo;
647
648 u32 brb_drop_hi;
649 u32 brb_drop_lo;
650
651 u32 jabber_packets_received;
652
653 u32 etherstatspkts1024octetsto1522octets_hi;
654 u32 etherstatspkts1024octetsto1522octets_lo;
655 u32 etherstatspktsover1522octets_hi;
656 u32 etherstatspktsover1522octets_lo;
657
658 u32 no_buff_discard;
659
660 u32 mac_filter_discard;
661 u32 xxoverflow_discard;
662 u32 brb_truncate_discard;
663 u32 mac_discard;
664
665 u32 driver_xoff;
666 };
667
668 #define STATS_OFFSET32(stat_name) \
669 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
670
671
672 #ifdef BNX2X_MULTI
673 #define MAX_CONTEXT 16
674 #else
675 #define MAX_CONTEXT 1
676 #endif
677
678 union cdu_context {
679 struct eth_context eth;
680 char pad[1024];
681 };
682
683 #define MAX_DMAE_C 8
684
685 /* DMA memory not used in fastpath */
686 struct bnx2x_slowpath {
687 union cdu_context context[MAX_CONTEXT];
688 struct eth_stats_query fw_stats;
689 struct mac_configuration_cmd mac_config;
690 struct mac_configuration_cmd mcast_config;
691
692 /* used by dmae command executer */
693 struct dmae_command dmae[MAX_DMAE_C];
694
695 u32 stats_comp;
696 union mac_stats mac_stats;
697 struct nig_stats nig_stats;
698 struct host_port_stats port_stats;
699 struct host_func_stats func_stats;
700
701 u32 wb_comp;
702 u32 wb_data[4];
703 };
704
705 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
706 #define bnx2x_sp_mapping(bp, var) \
707 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
708
709
710 /* attn group wiring */
711 #define MAX_DYNAMIC_ATTN_GRPS 8
712
713 struct attn_route {
714 u32 sig[4];
715 };
716
717 struct bnx2x {
718 /* Fields used in the tx and intr/napi performance paths
719 * are grouped together in the beginning of the structure
720 */
721 struct bnx2x_fastpath fp[MAX_CONTEXT];
722 void __iomem *regview;
723 void __iomem *doorbells;
724 #define BNX2X_DB_SIZE (16*2048)
725
726 struct net_device *dev;
727 struct pci_dev *pdev;
728
729 atomic_t intr_sem;
730 struct msix_entry msix_table[MAX_CONTEXT+1];
731
732 int tx_ring_size;
733
734 #ifdef BCM_VLAN
735 struct vlan_group *vlgrp;
736 #endif
737
738 u32 rx_csum;
739 u32 rx_offset;
740 u32 rx_buf_use_size; /* useable size */
741 u32 rx_buf_size; /* with alignment */
742 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
743 #define ETH_MIN_PACKET_SIZE 60
744 #define ETH_MAX_PACKET_SIZE 1500
745 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
746
747 struct host_def_status_block *def_status_blk;
748 #define DEF_SB_ID 16
749 u16 def_c_idx;
750 u16 def_u_idx;
751 u16 def_x_idx;
752 u16 def_t_idx;
753 u16 def_att_idx;
754 u32 attn_state;
755 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
756 u32 aeu_mask;
757 u32 nig_mask;
758
759 /* slow path ring */
760 struct eth_spe *spq;
761 dma_addr_t spq_mapping;
762 u16 spq_prod_idx;
763 struct eth_spe *spq_prod_bd;
764 struct eth_spe *spq_last_bd;
765 u16 *dsb_sp_prod;
766 u16 spq_left; /* serialize spq */
767 /* used to synchronize spq accesses */
768 spinlock_t spq_lock;
769
770 /* Flags for marking that there is a STAT_QUERY or
771 SET_MAC ramrod pending */
772 u8 stats_pending;
773 u8 set_mac_pending;
774
775 /* End of fileds used in the performance code paths */
776
777 int panic;
778 int msglevel;
779
780 u32 flags;
781 #define PCIX_FLAG 1
782 #define PCI_32BIT_FLAG 2
783 #define ONE_TDMA_FLAG 4 /* no longer used */
784 #define NO_WOL_FLAG 8
785 #define USING_DAC_FLAG 0x10
786 #define USING_MSIX_FLAG 0x20
787 #define ASF_ENABLE_FLAG 0x40
788 #define TPA_ENABLE_FLAG 0x80
789 #define NO_MCP_FLAG 0x100
790 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
791
792 int func;
793 #define BP_PORT(bp) (bp->func % PORT_MAX)
794 #define BP_FUNC(bp) (bp->func)
795 #define BP_E1HVN(bp) (bp->func >> 1)
796 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
797 /* assorted E1HVN */
798 #define IS_E1HMF(bp) (bp->e1hmf != 0)
799 #define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
800
801 int pm_cap;
802 int pcie_cap;
803
804 struct work_struct sp_task;
805 struct work_struct reset_task;
806
807 struct timer_list timer;
808 int timer_interval;
809 int current_interval;
810
811 u16 fw_seq;
812 u16 fw_drv_pulse_wr_seq;
813 u32 func_stx;
814
815 struct link_params link_params;
816 struct link_vars link_vars;
817
818 struct bnx2x_common common;
819 struct bnx2x_port port;
820
821 u32 mf_config;
822 u16 e1hov;
823 u8 e1hmf;
824
825 u8 wol;
826
827 int rx_ring_size;
828
829 u16 tx_quick_cons_trip_int;
830 u16 tx_quick_cons_trip;
831 u16 tx_ticks_int;
832 u16 tx_ticks;
833
834 u16 rx_quick_cons_trip_int;
835 u16 rx_quick_cons_trip;
836 u16 rx_ticks_int;
837 u16 rx_ticks;
838
839 u32 stats_ticks;
840 u32 lin_cnt;
841
842 int state;
843 #define BNX2X_STATE_CLOSED 0x0
844 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
845 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
846 #define BNX2X_STATE_OPEN 0x3000
847 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
848 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
849 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
850 #define BNX2X_STATE_DISABLED 0xd000
851 #define BNX2X_STATE_DIAG 0xe000
852 #define BNX2X_STATE_ERROR 0xf000
853
854 int num_queues;
855
856 u32 rx_mode;
857 #define BNX2X_RX_MODE_NONE 0
858 #define BNX2X_RX_MODE_NORMAL 1
859 #define BNX2X_RX_MODE_ALLMULTI 2
860 #define BNX2X_RX_MODE_PROMISC 3
861 #define BNX2X_MAX_MULTICAST 64
862 #define BNX2X_MAX_EMUL_MULTI 16
863
864 dma_addr_t def_status_blk_mapping;
865
866 struct bnx2x_slowpath *slowpath;
867 dma_addr_t slowpath_mapping;
868
869 #ifdef BCM_ISCSI
870 void *t1;
871 dma_addr_t t1_mapping;
872 void *t2;
873 dma_addr_t t2_mapping;
874 void *timers;
875 dma_addr_t timers_mapping;
876 void *qm;
877 dma_addr_t qm_mapping;
878 #endif
879
880 int dmae_ready;
881 /* used to synchronize dmae accesses */
882 struct mutex dmae_mutex;
883 struct dmae_command init_dmae;
884
885 /* used to synchronize stats collecting */
886 int stats_state;
887 /* used by dmae command loader */
888 struct dmae_command stats_dmae;
889 int executer_idx;
890
891 u16 stats_counter;
892 struct tstorm_per_client_stats old_tclient;
893 struct xstorm_per_client_stats old_xclient;
894 struct bnx2x_eth_stats eth_stats;
895
896 struct z_stream_s *strm;
897 void *gunzip_buf;
898 dma_addr_t gunzip_mapping;
899 int gunzip_outlen;
900 #define FW_BUF_SIZE 0x8000
901
902 };
903
904
905 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
906 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
907 u32 len32);
908 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
909
910 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
911 int wait)
912 {
913 u32 val;
914
915 do {
916 val = REG_RD(bp, reg);
917 if (val == expected)
918 break;
919 ms -= wait;
920 msleep(wait);
921
922 } while (ms > 0);
923
924 return val;
925 }
926
927
928 /* load/unload mode */
929 #define LOAD_NORMAL 0
930 #define LOAD_OPEN 1
931 #define LOAD_DIAG 2
932 #define UNLOAD_NORMAL 0
933 #define UNLOAD_CLOSE 1
934
935
936 /* DMAE command defines */
937 #define DMAE_CMD_SRC_PCI 0
938 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
939
940 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
941 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
942
943 #define DMAE_CMD_C_DST_PCI 0
944 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
945
946 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
947
948 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
949 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
950 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
951 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
952
953 #define DMAE_CMD_PORT_0 0
954 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
955
956 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
957 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
958 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
959
960 #define DMAE_LEN32_RD_MAX 0x80
961 #define DMAE_LEN32_WR_MAX 0x400
962
963 #define DMAE_COMP_VAL 0xe0d0d0ae
964
965 #define MAX_DMAE_C_PER_PORT 8
966 #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
967 BP_E1HVN(bp))
968 #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
969 E1HVN_MAX)
970
971
972 /* PCIE link and speed */
973 #define PCICFG_LINK_WIDTH 0x1f00000
974 #define PCICFG_LINK_WIDTH_SHIFT 20
975 #define PCICFG_LINK_SPEED 0xf0000
976 #define PCICFG_LINK_SPEED_SHIFT 16
977
978
979 #define BNX2X_NUM_STATS 39
980 #define BNX2X_NUM_TESTS 8
981
982 #define BNX2X_MAC_LOOPBACK 0
983 #define BNX2X_PHY_LOOPBACK 1
984 #define BNX2X_MAC_LOOPBACK_FAILED 1
985 #define BNX2X_PHY_LOOPBACK_FAILED 2
986 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
987 BNX2X_PHY_LOOPBACK_FAILED)
988
989
990 #define STROM_ASSERT_ARRAY_SIZE 50
991
992
993 /* must be used on a CID before placing it on a HW ring */
994 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
995
996 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
997 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
998
999
1000 #define BNX2X_BTR 3
1001 #define MAX_SPQ_PENDING 8
1002
1003
1004 /* CMNG constants
1005 derived from lab experiments, and not from system spec calculations !!! */
1006 #define DEF_MIN_RATE 100
1007 /* resolution of the rate shaping timer - 100 usec */
1008 #define RS_PERIODIC_TIMEOUT_USEC 100
1009 /* resolution of fairness algorithm in usecs -
1010 coefficient for clauclating the actuall t fair */
1011 #define T_FAIR_COEF 10000000
1012 /* number of bytes in single QM arbitration cycle -
1013 coeffiecnt for calculating the fairness timer */
1014 #define QM_ARB_BYTES 40000
1015 #define FAIR_MEM 2
1016
1017
1018 #define ATTN_NIG_FOR_FUNC (1L << 8)
1019 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1020 #define GPIO_2_FUNC (1L << 10)
1021 #define GPIO_3_FUNC (1L << 11)
1022 #define GPIO_4_FUNC (1L << 12)
1023 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1024 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1025 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1026 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1027 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1028 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1029
1030 #define ATTN_HARD_WIRED_MASK 0xff00
1031 #define ATTENTION_ID 4
1032
1033
1034 /* stuff added to make the code fit 80Col */
1035
1036 #define BNX2X_PMF_LINK_ASSERT \
1037 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1038
1039 #define BNX2X_MC_ASSERT_BITS \
1040 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1041 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1042 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1043 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1044
1045 #define BNX2X_MCP_ASSERT \
1046 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1047
1048 #define BNX2X_DOORQ_ASSERT \
1049 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1050
1051 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1052 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1053 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1054 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1055 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1056 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1057 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1058
1059 #define HW_INTERRUT_ASSERT_SET_0 \
1060 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1061 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1062 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1063 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1064 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1065 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1066 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1067 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1068 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1069 #define HW_INTERRUT_ASSERT_SET_1 \
1070 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1071 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1072 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1073 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1074 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1075 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1076 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1077 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1078 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1079 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1080 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1081 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1082 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1083 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1084 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1085 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1086 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1087 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1088 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1089 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1090 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1091 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1092 #define HW_INTERRUT_ASSERT_SET_2 \
1093 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1094 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1095 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1096 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1097 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1098 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1099 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1100 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1101 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1102 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1103 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1104 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1105
1106
1107 #define MULTI_FLAGS \
1108 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1109 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1110 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1111 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1112 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1113
1114 #define MULTI_MASK 0x7f
1115
1116
1117 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1118 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1119 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1120 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1121
1122 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1123
1124 #define BNX2X_SP_DSB_INDEX \
1125 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1126
1127
1128 #define CAM_IS_INVALID(x) \
1129 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1130
1131 #define CAM_INVALIDATE(x) \
1132 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1133
1134
1135 /* Number of u32 elements in MC hash array */
1136 #define MC_HASH_SIZE 8
1137 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1138 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1139
1140
1141 #ifndef PXP2_REG_PXP2_INT_STS
1142 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1143 #endif
1144
1145 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1146
1147 #endif /* bnx2x.h */
Support for the Chinese Samsung S3C2440 based development boards