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[ALSA] Fix build error without CONFIG_HAS_DMA
[linux-2.6/mini2440.git] / drivers / net / ipg.c
blob68887235d7e995f9b939ee8e11c9435d30cbf64b
1 /*
2 * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
3 *
4 * Copyright (C) 2003, 2007 IC Plus Corp
5 *
6 * Original Author:
7 *
8 * Craig Rich
9 * Sundance Technology, Inc.
10 * www.sundanceti.com
11 * craig_rich@sundanceti.com
12 *
13 * Current Maintainer:
14 *
15 * Sorbica Shieh.
16 * http://www.icplus.com.tw
17 * sorbica@icplus.com.tw
18 *
19 * Jesse Huang
20 * http://www.icplus.com.tw
21 * jesse@icplus.com.tw
22 */
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/mutex.h>
27
28 #include <asm/div64.h>
29
30 #define IPG_RX_RING_BYTES (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31 #define IPG_TX_RING_BYTES (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32 #define IPG_RESET_MASK \
33 (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34 IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
35 IPG_AC_AUTO_INIT)
36
37 #define ipg_w32(val32,reg) iowrite32((val32), ioaddr + (reg))
38 #define ipg_w16(val16,reg) iowrite16((val16), ioaddr + (reg))
39 #define ipg_w8(val8,reg) iowrite8((val8), ioaddr + (reg))
40
41 #define ipg_r32(reg) ioread32(ioaddr + (reg))
42 #define ipg_r16(reg) ioread16(ioaddr + (reg))
43 #define ipg_r8(reg) ioread8(ioaddr + (reg))
44
45 #define JUMBO_FRAME_4k_ONLY
46 enum {
47 netdev_io_size = 128
48 };
49
50 #include "ipg.h"
51 #define DRV_NAME "ipg"
52
53 MODULE_AUTHOR("IC Plus Corp. 2003");
54 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver "
55 DrvVer);
56 MODULE_LICENSE("GPL");
57
58 static const char *ipg_brand_name[] = {
59 "IC PLUS IP1000 1000/100/10 based NIC",
60 "Sundance Technology ST2021 based NIC",
61 "Tamarack Microelectronics TC9020/9021 based NIC",
62 "Tamarack Microelectronics TC9020/9021 based NIC",
63 "D-Link NIC",
64 "D-Link NIC IP1000A"
65 };
66
67 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
68 { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
69 { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
70 { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
71 { PCI_VDEVICE(DLINK, 0x9021), 3 },
72 { PCI_VDEVICE(DLINK, 0x4000), 4 },
73 { PCI_VDEVICE(DLINK, 0x4020), 5 },
74 { 0, }
75 };
76
77 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
78
79 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
80 {
81 struct ipg_nic_private *sp = netdev_priv(dev);
82 return sp->ioaddr;
83 }
84
85 #ifdef IPG_DEBUG
86 static void ipg_dump_rfdlist(struct net_device *dev)
87 {
88 struct ipg_nic_private *sp = netdev_priv(dev);
89 void __iomem *ioaddr = sp->ioaddr;
90 unsigned int i;
91 u32 offset;
92
93 IPG_DEBUG_MSG("_dump_rfdlist\n");
94
95 printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
96 printk(KERN_INFO "rx_dirty = %2.2x\n", sp->rx_dirty);
97 printk(KERN_INFO "RFDList start address = %16.16lx\n",
98 (unsigned long) sp->rxd_map);
99 printk(KERN_INFO "RFDListPtr register = %8.8x%8.8x\n",
100 ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
101
102 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
103 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
104 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
105 offset, (unsigned long) sp->rxd[i].next_desc);
106 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
107 printk(KERN_INFO "%2.2x %4.4x RFS = %16.16lx\n", i,
108 offset, (unsigned long) sp->rxd[i].rfs);
109 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
110 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
111 offset, (unsigned long) sp->rxd[i].frag_info);
112 }
113 }
114
115 static void ipg_dump_tfdlist(struct net_device *dev)
116 {
117 struct ipg_nic_private *sp = netdev_priv(dev);
118 void __iomem *ioaddr = sp->ioaddr;
119 unsigned int i;
120 u32 offset;
121
122 IPG_DEBUG_MSG("_dump_tfdlist\n");
123
124 printk(KERN_INFO "tx_current = %2.2x\n", sp->tx_current);
125 printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
126 printk(KERN_INFO "TFDList start address = %16.16lx\n",
127 (unsigned long) sp->txd_map);
128 printk(KERN_INFO "TFDListPtr register = %8.8x%8.8x\n",
129 ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
130
131 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
132 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
133 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
134 offset, (unsigned long) sp->txd[i].next_desc);
135
136 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
137 printk(KERN_INFO "%2.2x %4.4x TFC = %16.16lx\n", i,
138 offset, (unsigned long) sp->txd[i].tfc);
139 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
140 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
141 offset, (unsigned long) sp->txd[i].frag_info);
142 }
143 }
144 #endif
145
146 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
147 {
148 ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
149 ndelay(IPG_PC_PHYCTRLWAIT_NS);
150 }
151
152 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
153 {
154 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
155 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
156 }
157
158 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
159 {
160 phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
161
162 ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
163 }
164
165 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
166 {
167 ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
168 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
169 }
170
171 static u16 read_phy_bit(void __iomem * ioaddr, u8 phyctrlpolarity)
172 {
173 u16 bit_data;
174
175 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
176
177 bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
178
179 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
180
181 return bit_data;
182 }
183
184 /*
185 * Read a register from the Physical Layer device located
186 * on the IPG NIC, using the IPG PHYCTRL register.
187 */
188 static int mdio_read(struct net_device * dev, int phy_id, int phy_reg)
189 {
190 void __iomem *ioaddr = ipg_ioaddr(dev);
191 /*
192 * The GMII mangement frame structure for a read is as follows:
193 *
194 * |Preamble|st|op|phyad|regad|ta| data |idle|
195 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
196 *
197 * <32 1s> = 32 consecutive logic 1 values
198 * A = bit of Physical Layer device address (MSB first)
199 * R = bit of register address (MSB first)
200 * z = High impedance state
201 * D = bit of read data (MSB first)
202 *
203 * Transmission order is 'Preamble' field first, bits transmitted
204 * left to right (first to last).
205 */
206 struct {
207 u32 field;
208 unsigned int len;
209 } p[] = {
210 { GMII_PREAMBLE, 32 }, /* Preamble */
211 { GMII_ST, 2 }, /* ST */
212 { GMII_READ, 2 }, /* OP */
213 { phy_id, 5 }, /* PHYAD */
214 { phy_reg, 5 }, /* REGAD */
215 { 0x0000, 2 }, /* TA */
216 { 0x0000, 16 }, /* DATA */
217 { 0x0000, 1 } /* IDLE */
218 };
219 unsigned int i, j;
220 u8 polarity, data;
221
222 polarity = ipg_r8(PHY_CTRL);
223 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
224
225 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
226 for (j = 0; j < 5; j++) {
227 for (i = 0; i < p[j].len; i++) {
228 /* For each variable length field, the MSB must be
229 * transmitted first. Rotate through the field bits,
230 * starting with the MSB, and move each bit into the
231 * the 1st (2^1) bit position (this is the bit position
232 * corresponding to the MgmtData bit of the PhyCtrl
233 * register for the IPG).
234 *
235 * Example: ST = 01;
236 *
237 * First write a '0' to bit 1 of the PhyCtrl
238 * register, then write a '1' to bit 1 of the
239 * PhyCtrl register.
240 *
241 * To do this, right shift the MSB of ST by the value:
242 * [field length - 1 - #ST bits already written]
243 * then left shift this result by 1.
244 */
245 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
246 data &= IPG_PC_MGMTDATA;
247 data |= polarity | IPG_PC_MGMTDIR;
248
249 ipg_drive_phy_ctl_low_high(ioaddr, data);
250 }
251 }
252
253 send_three_state(ioaddr, polarity);
254
255 read_phy_bit(ioaddr, polarity);
256
257 /*
258 * For a read cycle, the bits for the next two fields (TA and
259 * DATA) are driven by the PHY (the IPG reads these bits).
260 */
261 for (i = 0; i < p[6].len; i++) {
262 p[6].field |=
263 (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
264 }
265
266 send_three_state(ioaddr, polarity);
267 send_three_state(ioaddr, polarity);
268 send_three_state(ioaddr, polarity);
269 send_end(ioaddr, polarity);
270
271 /* Return the value of the DATA field. */
272 return p[6].field;
273 }
274
275 /*
276 * Write to a register from the Physical Layer device located
277 * on the IPG NIC, using the IPG PHYCTRL register.
278 */
279 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
280 {
281 void __iomem *ioaddr = ipg_ioaddr(dev);
282 /*
283 * The GMII mangement frame structure for a read is as follows:
284 *
285 * |Preamble|st|op|phyad|regad|ta| data |idle|
286 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
287 *
288 * <32 1s> = 32 consecutive logic 1 values
289 * A = bit of Physical Layer device address (MSB first)
290 * R = bit of register address (MSB first)
291 * z = High impedance state
292 * D = bit of write data (MSB first)
293 *
294 * Transmission order is 'Preamble' field first, bits transmitted
295 * left to right (first to last).
296 */
297 struct {
298 u32 field;
299 unsigned int len;
300 } p[] = {
301 { GMII_PREAMBLE, 32 }, /* Preamble */
302 { GMII_ST, 2 }, /* ST */
303 { GMII_WRITE, 2 }, /* OP */
304 { phy_id, 5 }, /* PHYAD */
305 { phy_reg, 5 }, /* REGAD */
306 { 0x0002, 2 }, /* TA */
307 { val & 0xffff, 16 }, /* DATA */
308 { 0x0000, 1 } /* IDLE */
309 };
310 unsigned int i, j;
311 u8 polarity, data;
312
313 polarity = ipg_r8(PHY_CTRL);
314 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
315
316 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
317 for (j = 0; j < 7; j++) {
318 for (i = 0; i < p[j].len; i++) {
319 /* For each variable length field, the MSB must be
320 * transmitted first. Rotate through the field bits,
321 * starting with the MSB, and move each bit into the
322 * the 1st (2^1) bit position (this is the bit position
323 * corresponding to the MgmtData bit of the PhyCtrl
324 * register for the IPG).
325 *
326 * Example: ST = 01;
327 *
328 * First write a '0' to bit 1 of the PhyCtrl
329 * register, then write a '1' to bit 1 of the
330 * PhyCtrl register.
331 *
332 * To do this, right shift the MSB of ST by the value:
333 * [field length - 1 - #ST bits already written]
334 * then left shift this result by 1.
335 */
336 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
337 data &= IPG_PC_MGMTDATA;
338 data |= polarity | IPG_PC_MGMTDIR;
339
340 ipg_drive_phy_ctl_low_high(ioaddr, data);
341 }
342 }
343
344 /* The last cycle is a tri-state, so read from the PHY. */
345 for (j = 7; j < 8; j++) {
346 for (i = 0; i < p[j].len; i++) {
347 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
348
349 p[j].field |= ((ipg_r8(PHY_CTRL) &
350 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
351
352 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
353 }
354 }
355 }
356
357 /* Set LED_Mode JES20040127EEPROM */
358 static void ipg_set_led_mode(struct net_device *dev)
359 {
360 struct ipg_nic_private *sp = netdev_priv(dev);
361 void __iomem *ioaddr = sp->ioaddr;
362 u32 mode;
363
364 mode = ipg_r32(ASIC_CTRL);
365 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
366
367 if ((sp->LED_Mode & 0x03) > 1)
368 mode |= IPG_AC_LED_MODE_BIT_1; /* Write Asic Control Bit 29 */
369
370 if ((sp->LED_Mode & 0x01) == 1)
371 mode |= IPG_AC_LED_MODE; /* Write Asic Control Bit 14 */
372
373 if ((sp->LED_Mode & 0x08) == 8)
374 mode |= IPG_AC_LED_SPEED; /* Write Asic Control Bit 27 */
375
376 ipg_w32(mode, ASIC_CTRL);
377 }
378
379 /* Set PHYSet JES20040127EEPROM */
380 static void ipg_set_phy_set(struct net_device *dev)
381 {
382 struct ipg_nic_private *sp = netdev_priv(dev);
383 void __iomem *ioaddr = sp->ioaddr;
384 int physet;
385
386 physet = ipg_r8(PHY_SET);
387 physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
388 physet |= ((sp->LED_Mode & 0x70) >> 4);
389 ipg_w8(physet, PHY_SET);
390 }
391
392 static int ipg_reset(struct net_device *dev, u32 resetflags)
393 {
394 /* Assert functional resets via the IPG AsicCtrl
395 * register as specified by the 'resetflags' input
396 * parameter.
397 */
398 void __iomem *ioaddr = ipg_ioaddr(dev); //JES20040127EEPROM:
399 unsigned int timeout_count = 0;
400
401 IPG_DEBUG_MSG("_reset\n");
402
403 ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
404
405 /* Delay added to account for problem with 10Mbps reset. */
406 mdelay(IPG_AC_RESETWAIT);
407
408 while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
409 mdelay(IPG_AC_RESETWAIT);
410 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
411 return -ETIME;
412 }
413 /* Set LED Mode in Asic Control JES20040127EEPROM */
414 ipg_set_led_mode(dev);
415
416 /* Set PHYSet Register Value JES20040127EEPROM */
417 ipg_set_phy_set(dev);
418 return 0;
419 }
420
421 /* Find the GMII PHY address. */
422 static int ipg_find_phyaddr(struct net_device *dev)
423 {
424 unsigned int phyaddr, i;
425
426 for (i = 0; i < 32; i++) {
427 u32 status;
428
429 /* Search for the correct PHY address among 32 possible. */
430 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
431
432 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
433 GMII_PHY_ID1
434 */
435
436 status = mdio_read(dev, phyaddr, MII_BMSR);
437
438 if ((status != 0xFFFF) && (status != 0))
439 return phyaddr;
440 }
441
442 return 0x1f;
443 }
444
445 /*
446 * Configure IPG based on result of IEEE 802.3 PHY
447 * auto-negotiation.
448 */
449 static int ipg_config_autoneg(struct net_device *dev)
450 {
451 struct ipg_nic_private *sp = netdev_priv(dev);
452 void __iomem *ioaddr = sp->ioaddr;
453 unsigned int txflowcontrol;
454 unsigned int rxflowcontrol;
455 unsigned int fullduplex;
456 unsigned int gig;
457 u32 mac_ctrl_val;
458 u32 asicctrl;
459 u8 phyctrl;
460
461 IPG_DEBUG_MSG("_config_autoneg\n");
462
463 asicctrl = ipg_r32(ASIC_CTRL);
464 phyctrl = ipg_r8(PHY_CTRL);
465 mac_ctrl_val = ipg_r32(MAC_CTRL);
466
467 /* Set flags for use in resolving auto-negotation, assuming
468 * non-1000Mbps, half duplex, no flow control.
469 */
470 fullduplex = 0;
471 txflowcontrol = 0;
472 rxflowcontrol = 0;
473 gig = 0;
474
475 /* To accomodate a problem in 10Mbps operation,
476 * set a global flag if PHY running in 10Mbps mode.
477 */
478 sp->tenmbpsmode = 0;
479
480 printk(KERN_INFO "%s: Link speed = ", dev->name);
481
482 /* Determine actual speed of operation. */
483 switch (phyctrl & IPG_PC_LINK_SPEED) {
484 case IPG_PC_LINK_SPEED_10MBPS:
485 printk("10Mbps.\n");
486 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
487 dev->name);
488 sp->tenmbpsmode = 1;
489 break;
490 case IPG_PC_LINK_SPEED_100MBPS:
491 printk("100Mbps.\n");
492 break;
493 case IPG_PC_LINK_SPEED_1000MBPS:
494 printk("1000Mbps.\n");
495 gig = 1;
496 break;
497 default:
498 printk("undefined!\n");
499 return 0;
500 }
501
502 if (phyctrl & IPG_PC_DUPLEX_STATUS) {
503 fullduplex = 1;
504 txflowcontrol = 1;
505 rxflowcontrol = 1;
506 }
507
508 /* Configure full duplex, and flow control. */
509 if (fullduplex == 1) {
510 /* Configure IPG for full duplex operation. */
511 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
512
513 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
514
515 if (txflowcontrol == 1) {
516 printk("TX flow control");
517 mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
518 } else {
519 printk("no TX flow control");
520 mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
521 }
522
523 if (rxflowcontrol == 1) {
524 printk(", RX flow control.");
525 mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
526 } else {
527 printk(", no RX flow control.");
528 mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
529 }
530
531 printk("\n");
532 } else {
533 /* Configure IPG for half duplex operation. */
534 printk(KERN_INFO "%s: setting half duplex, "
535 "no TX flow control, no RX flow control.\n", dev->name);
536
537 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
538 ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
539 ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
540 }
541 ipg_w32(mac_ctrl_val, MAC_CTRL);
542 return 0;
543 }
544
545 /* Determine and configure multicast operation and set
546 * receive mode for IPG.
547 */
548 static void ipg_nic_set_multicast_list(struct net_device *dev)
549 {
550 void __iomem *ioaddr = ipg_ioaddr(dev);
551 struct dev_mc_list *mc_list_ptr;
552 unsigned int hashindex;
553 u32 hashtable[2];
554 u8 receivemode;
555
556 IPG_DEBUG_MSG("_nic_set_multicast_list\n");
557
558 receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
559
560 if (dev->flags & IFF_PROMISC) {
561 /* NIC to be configured in promiscuous mode. */
562 receivemode = IPG_RM_RECEIVEALLFRAMES;
563 } else if ((dev->flags & IFF_ALLMULTI) ||
564 (dev->flags & IFF_MULTICAST &
565 (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
566 /* NIC to be configured to receive all multicast
567 * frames. */
568 receivemode |= IPG_RM_RECEIVEMULTICAST;
569 } else if (dev->flags & IFF_MULTICAST & (dev->mc_count > 0)) {
570 /* NIC to be configured to receive selected
571 * multicast addresses. */
572 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
573 }
574
575 /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
576 * The IPG applies a cyclic-redundancy-check (the same CRC
577 * used to calculate the frame data FCS) to the destination
578 * address all incoming multicast frames whose destination
579 * address has the multicast bit set. The least significant
580 * 6 bits of the CRC result are used as an addressing index
581 * into the hash table. If the value of the bit addressed by
582 * this index is a 1, the frame is passed to the host system.
583 */
584
585 /* Clear hashtable. */
586 hashtable[0] = 0x00000000;
587 hashtable[1] = 0x00000000;
588
589 /* Cycle through all multicast addresses to filter. */
590 for (mc_list_ptr = dev->mc_list;
591 mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
592 /* Calculate CRC result for each multicast address. */
593 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
594 ETH_ALEN);
595
596 /* Use only the least significant 6 bits. */
597 hashindex = hashindex & 0x3F;
598
599 /* Within "hashtable", set bit number "hashindex"
600 * to a logic 1.
601 */
602 set_bit(hashindex, (void *)hashtable);
603 }
604
605 /* Write the value of the hashtable, to the 4, 16 bit
606 * HASHTABLE IPG registers.
607 */
608 ipg_w32(hashtable[0], HASHTABLE_0);
609 ipg_w32(hashtable[1], HASHTABLE_1);
610
611 ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
612
613 IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
614 }
615
616 static int ipg_io_config(struct net_device *dev)
617 {
618 void __iomem *ioaddr = ipg_ioaddr(dev);
619 u32 origmacctrl;
620 u32 restoremacctrl;
621
622 IPG_DEBUG_MSG("_io_config\n");
623
624 origmacctrl = ipg_r32(MAC_CTRL);
625
626 restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
627
628 /* Based on compilation option, determine if FCS is to be
629 * stripped on receive frames by IPG.
630 */
631 if (!IPG_STRIP_FCS_ON_RX)
632 restoremacctrl |= IPG_MC_RCV_FCS;
633
634 /* Determine if transmitter and/or receiver are
635 * enabled so we may restore MACCTRL correctly.
636 */
637 if (origmacctrl & IPG_MC_TX_ENABLED)
638 restoremacctrl |= IPG_MC_TX_ENABLE;
639
640 if (origmacctrl & IPG_MC_RX_ENABLED)
641 restoremacctrl |= IPG_MC_RX_ENABLE;
642
643 /* Transmitter and receiver must be disabled before setting
644 * IFSSelect.
645 */
646 ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
647 IPG_MC_RSVD_MASK, MAC_CTRL);
648
649 /* Now that transmitter and receiver are disabled, write
650 * to IFSSelect.
651 */
652 ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
653
654 /* Set RECEIVEMODE register. */
655 ipg_nic_set_multicast_list(dev);
656
657 ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
658
659 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD);
660 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
661 ipg_w8(IPG_RXDMABURSTTHRESH_VALUE, RX_DMA_BURST_THRESH);
662 ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE, TX_DMA_POLL_PERIOD);
663 ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
664 ipg_w8(IPG_TXDMABURSTTHRESH_VALUE, TX_DMA_BURST_THRESH);
665 ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
666 IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
667 IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
668 IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
669 ipg_w16(IPG_FLOWONTHRESH_VALUE, FLOW_ON_THRESH);
670 ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
671
672 /* IPG multi-frag frame bug workaround.
673 * Per silicon revision B3 eratta.
674 */
675 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
676
677 /* IPG TX poll now bug workaround.
678 * Per silicon revision B3 eratta.
679 */
680 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
681
682 /* IPG RX poll now bug workaround.
683 * Per silicon revision B3 eratta.
684 */
685 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
686
687 /* Now restore MACCTRL to original setting. */
688 ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
689
690 /* Disable unused RMON statistics. */
691 ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
692
693 /* Disable unused MIB statistics. */
694 ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
695 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
696 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
697 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
698 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
699 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
700
701 return 0;
702 }
703
704 /*
705 * Create a receive buffer within system memory and update
706 * NIC private structure appropriately.
707 */
708 static int ipg_get_rxbuff(struct net_device *dev, int entry)
709 {
710 struct ipg_nic_private *sp = netdev_priv(dev);
711 struct ipg_rx *rxfd = sp->rxd + entry;
712 struct sk_buff *skb;
713 u64 rxfragsize;
714
715 IPG_DEBUG_MSG("_get_rxbuff\n");
716
717 skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
718 if (!skb) {
719 sp->RxBuff[entry] = NULL;
720 return -ENOMEM;
721 }
722
723 /* Adjust the data start location within the buffer to
724 * align IP address field to a 16 byte boundary.
725 */
726 skb_reserve(skb, NET_IP_ALIGN);
727
728 /* Associate the receive buffer with the IPG NIC. */
729 skb->dev = dev;
730
731 /* Save the address of the sk_buff structure. */
732 sp->RxBuff[entry] = skb;
733
734 rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
735 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
736
737 /* Set the RFD fragment length. */
738 rxfragsize = IPG_RXFRAG_SIZE;
739 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
740
741 return 0;
742 }
743
744 static int init_rfdlist(struct net_device *dev)
745 {
746 struct ipg_nic_private *sp = netdev_priv(dev);
747 void __iomem *ioaddr = sp->ioaddr;
748 unsigned int i;
749
750 IPG_DEBUG_MSG("_init_rfdlist\n");
751
752 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
753 struct ipg_rx *rxfd = sp->rxd + i;
754
755 if (sp->RxBuff[i]) {
756 pci_unmap_single(sp->pdev,
757 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
758 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
759 IPG_DEV_KFREE_SKB(sp->RxBuff[i]);
760 sp->RxBuff[i] = NULL;
761 }
762
763 /* Clear out the RFS field. */
764 rxfd->rfs = 0x0000000000000000;
765
766 if (ipg_get_rxbuff(dev, i) < 0) {
767 /*
768 * A receive buffer was not ready, break the
769 * RFD list here.
770 */
771 IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
772
773 /* Just in case we cannot allocate a single RFD.
774 * Should not occur.
775 */
776 if (i == 0) {
777 printk(KERN_ERR "%s: No memory available"
778 " for RFD list.\n", dev->name);
779 return -ENOMEM;
780 }
781 }
782
783 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
784 sizeof(struct ipg_rx)*(i + 1));
785 }
786 sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
787
788 sp->rx_current = 0;
789 sp->rx_dirty = 0;
790
791 /* Write the location of the RFDList to the IPG. */
792 ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
793 ipg_w32(0x00000000, RFD_LIST_PTR_1);
794
795 return 0;
796 }
797
798 static void init_tfdlist(struct net_device *dev)
799 {
800 struct ipg_nic_private *sp = netdev_priv(dev);
801 void __iomem *ioaddr = sp->ioaddr;
802 unsigned int i;
803
804 IPG_DEBUG_MSG("_init_tfdlist\n");
805
806 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
807 struct ipg_tx *txfd = sp->txd + i;
808
809 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
810
811 if (sp->TxBuff[i]) {
812 IPG_DEV_KFREE_SKB(sp->TxBuff[i]);
813 sp->TxBuff[i] = NULL;
814 }
815
816 txfd->next_desc = cpu_to_le64(sp->txd_map +
817 sizeof(struct ipg_tx)*(i + 1));
818 }
819 sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
820
821 sp->tx_current = 0;
822 sp->tx_dirty = 0;
823
824 /* Write the location of the TFDList to the IPG. */
825 IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
826 (u32) sp->txd_map);
827 ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
828 ipg_w32(0x00000000, TFD_LIST_PTR_1);
829
830 sp->ResetCurrentTFD = 1;
831 }
832
833 /*
834 * Free all transmit buffers which have already been transfered
835 * via DMA to the IPG.
836 */
837 static void ipg_nic_txfree(struct net_device *dev)
838 {
839 struct ipg_nic_private *sp = netdev_priv(dev);
840 void __iomem *ioaddr = sp->ioaddr;
841 unsigned int curr;
842 u64 txd_map;
843 unsigned int released, pending;
844
845 txd_map = (u64)sp->txd_map;
846 curr = ipg_r32(TFD_LIST_PTR_0) -
847 do_div(txd_map, sizeof(struct ipg_tx)) - 1;
848
849 IPG_DEBUG_MSG("_nic_txfree\n");
850
851 pending = sp->tx_current - sp->tx_dirty;
852
853 for (released = 0; released < pending; released++) {
854 unsigned int dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
855 struct sk_buff *skb = sp->TxBuff[dirty];
856 struct ipg_tx *txfd = sp->txd + dirty;
857
858 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
859
860 /* Look at each TFD's TFC field beginning
861 * at the last freed TFD up to the current TFD.
862 * If the TFDDone bit is set, free the associated
863 * buffer.
864 */
865 if (dirty == curr)
866 break;
867
868 /* Setup TFDDONE for compatible issue. */
869 txfd->tfc |= cpu_to_le64(IPG_TFC_TFDDONE);
870
871 /* Free the transmit buffer. */
872 if (skb) {
873 pci_unmap_single(sp->pdev,
874 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
875 skb->len, PCI_DMA_TODEVICE);
876
877 IPG_DEV_KFREE_SKB(skb);
878
879 sp->TxBuff[dirty] = NULL;
880 }
881 }
882
883 sp->tx_dirty += released;
884
885 if (netif_queue_stopped(dev) &&
886 (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
887 netif_wake_queue(dev);
888 }
889 }
890
891 static void ipg_tx_timeout(struct net_device *dev)
892 {
893 struct ipg_nic_private *sp = netdev_priv(dev);
894 void __iomem *ioaddr = sp->ioaddr;
895
896 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
897 IPG_AC_FIFO);
898
899 spin_lock_irq(&sp->lock);
900
901 /* Re-configure after DMA reset. */
902 if (ipg_io_config(dev) < 0) {
903 printk(KERN_INFO "%s: Error during re-configuration.\n",
904 dev->name);
905 }
906
907 init_tfdlist(dev);
908
909 spin_unlock_irq(&sp->lock);
910
911 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
912 MAC_CTRL);
913 }
914
915 /*
916 * For TxComplete interrupts, free all transmit
917 * buffers which have already been transfered via DMA
918 * to the IPG.
919 */
920 static void ipg_nic_txcleanup(struct net_device *dev)
921 {
922 struct ipg_nic_private *sp = netdev_priv(dev);
923 void __iomem *ioaddr = sp->ioaddr;
924 unsigned int i;
925
926 IPG_DEBUG_MSG("_nic_txcleanup\n");
927
928 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
929 /* Reading the TXSTATUS register clears the
930 * TX_COMPLETE interrupt.
931 */
932 u32 txstatusdword = ipg_r32(TX_STATUS);
933
934 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
935
936 /* Check for Transmit errors. Error bits only valid if
937 * TX_COMPLETE bit in the TXSTATUS register is a 1.
938 */
939 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
940 break;
941
942 /* If in 10Mbps mode, indicate transmit is ready. */
943 if (sp->tenmbpsmode) {
944 netif_wake_queue(dev);
945 }
946
947 /* Transmit error, increment stat counters. */
948 if (txstatusdword & IPG_TS_TX_ERROR) {
949 IPG_DEBUG_MSG("Transmit error.\n");
950 sp->stats.tx_errors++;
951 }
952
953 /* Late collision, re-enable transmitter. */
954 if (txstatusdword & IPG_TS_LATE_COLLISION) {
955 IPG_DEBUG_MSG("Late collision on transmit.\n");
956 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
957 IPG_MC_RSVD_MASK, MAC_CTRL);
958 }
959
960 /* Maximum collisions, re-enable transmitter. */
961 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
962 IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
963 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
964 IPG_MC_RSVD_MASK, MAC_CTRL);
965 }
966
967 /* Transmit underrun, reset and re-enable
968 * transmitter.
969 */
970 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
971 IPG_DEBUG_MSG("Transmitter underrun.\n");
972 sp->stats.tx_fifo_errors++;
973 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
974 IPG_AC_NETWORK | IPG_AC_FIFO);
975
976 /* Re-configure after DMA reset. */
977 if (ipg_io_config(dev) < 0) {
978 printk(KERN_INFO
979 "%s: Error during re-configuration.\n",
980 dev->name);
981 }
982 init_tfdlist(dev);
983
984 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
985 IPG_MC_RSVD_MASK, MAC_CTRL);
986 }
987 }
988
989 ipg_nic_txfree(dev);
990 }
991
992 /* Provides statistical information about the IPG NIC. */
993 struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
994 {
995 struct ipg_nic_private *sp = netdev_priv(dev);
996 void __iomem *ioaddr = sp->ioaddr;
997 u16 temp1;
998 u16 temp2;
999
1000 IPG_DEBUG_MSG("_nic_get_stats\n");
1001
1002 /* Check to see if the NIC has been initialized via nic_open,
1003 * before trying to read statistic registers.
1004 */
1005 if (!test_bit(__LINK_STATE_START, &dev->state))
1006 return &sp->stats;
1007
1008 sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1009 sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1010 sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1011 sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1012 temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1013 sp->stats.rx_errors += temp1;
1014 sp->stats.rx_missed_errors += temp1;
1015 temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1016 ipg_r32(IPG_LATECOLLISIONS);
1017 temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1018 sp->stats.collisions += temp1;
1019 sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1020 sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1021 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1022 sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1023
1024 /* detailed tx_errors */
1025 sp->stats.tx_carrier_errors += temp2;
1026
1027 /* detailed rx_errors */
1028 sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1029 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1030 sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1031
1032 /* Unutilized IPG statistic registers. */
1033 ipg_r32(IPG_MCSTFRAMESRCVDOK);
1034
1035 return &sp->stats;
1036 }
1037
1038 /* Restore used receive buffers. */
1039 static int ipg_nic_rxrestore(struct net_device *dev)
1040 {
1041 struct ipg_nic_private *sp = netdev_priv(dev);
1042 const unsigned int curr = sp->rx_current;
1043 unsigned int dirty = sp->rx_dirty;
1044
1045 IPG_DEBUG_MSG("_nic_rxrestore\n");
1046
1047 for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1048 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1049
1050 /* rx_copybreak may poke hole here and there. */
1051 if (sp->RxBuff[entry])
1052 continue;
1053
1054 /* Generate a new receive buffer to replace the
1055 * current buffer (which will be released by the
1056 * Linux system).
1057 */
1058 if (ipg_get_rxbuff(dev, entry) < 0) {
1059 IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1060
1061 break;
1062 }
1063
1064 /* Reset the RFS field. */
1065 sp->rxd[entry].rfs = 0x0000000000000000;
1066 }
1067 sp->rx_dirty = dirty;
1068
1069 return 0;
1070 }
1071
1072 #ifdef JUMBO_FRAME
1073
1074 /* use jumboindex and jumbosize to control jumbo frame status
1075 initial status is jumboindex=-1 and jumbosize=0
1076 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1077 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1078 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1079 previous receiving and need to continue dumping the current one
1080 */
1081 enum {
1082 NormalPacket,
1083 ErrorPacket
1084 };
1085
1086 enum {
1087 Frame_NoStart_NoEnd = 0,
1088 Frame_WithStart = 1,
1089 Frame_WithEnd = 10,
1090 Frame_WithStart_WithEnd = 11
1091 };
1092
1093 inline void ipg_nic_rx_free_skb(struct net_device *dev)
1094 {
1095 struct ipg_nic_private *sp = netdev_priv(dev);
1096 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1097
1098 if (sp->RxBuff[entry]) {
1099 struct ipg_rx *rxfd = sp->rxd + entry;
1100
1101 pci_unmap_single(sp->pdev,
1102 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1103 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1104 IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1105 sp->RxBuff[entry] = NULL;
1106 }
1107 }
1108
1109 inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1110 {
1111 struct ipg_nic_private *sp = netdev_priv(dev);
1112 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1113 int type = Frame_NoStart_NoEnd;
1114
1115 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1116 type += Frame_WithStart;
1117 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1118 type += Frame_WithEnd;
1119 return type;
1120 }
1121
1122 inline int ipg_nic_rx_check_error(struct net_device *dev)
1123 {
1124 struct ipg_nic_private *sp = netdev_priv(dev);
1125 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1126 struct ipg_rx *rxfd = sp->rxd + entry;
1127
1128 if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1129 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1130 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1131 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1132 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1133 (unsigned long) rxfd->rfs);
1134
1135 /* Increment general receive error statistic. */
1136 sp->stats.rx_errors++;
1137
1138 /* Increment detailed receive error statistics. */
1139 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1140 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1141
1142 sp->stats.rx_fifo_errors++;
1143 }
1144
1145 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1146 IPG_DEBUG_MSG("RX runt occured.\n");
1147 sp->stats.rx_length_errors++;
1148 }
1149
1150 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1151 * error count handled by a IPG statistic register.
1152 */
1153
1154 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1155 IPG_DEBUG_MSG("RX alignment error occured.\n");
1156 sp->stats.rx_frame_errors++;
1157 }
1158
1159 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1160 * handled by a IPG statistic register.
1161 */
1162
1163 /* Free the memory associated with the RX
1164 * buffer since it is erroneous and we will
1165 * not pass it to higher layer processes.
1166 */
1167 if (sp->RxBuff[entry]) {
1168 pci_unmap_single(sp->pdev,
1169 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1170 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1171
1172 IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1173 sp->RxBuff[entry] = NULL;
1174 }
1175 return ErrorPacket;
1176 }
1177 return NormalPacket;
1178 }
1179
1180 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1181 struct ipg_nic_private *sp,
1182 struct ipg_rx *rxfd, unsigned entry)
1183 {
1184 struct SJumbo *jumbo = &sp->Jumbo;
1185 struct sk_buff *skb;
1186 int framelen;
1187
1188 if (jumbo->FoundStart) {
1189 IPG_DEV_KFREE_SKB(jumbo->skb);
1190 jumbo->FoundStart = 0;
1191 jumbo->CurrentSize = 0;
1192 jumbo->skb = NULL;
1193 }
1194
1195 // 1: found error, 0 no error
1196 if (ipg_nic_rx_check_error(dev) != NormalPacket)
1197 return;
1198
1199 skb = sp->RxBuff[entry];
1200 if (!skb)
1201 return;
1202
1203 // accept this frame and send to upper layer
1204 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1205 if (framelen > IPG_RXFRAG_SIZE)
1206 framelen = IPG_RXFRAG_SIZE;
1207
1208 skb_put(skb, framelen);
1209 skb->protocol = eth_type_trans(skb, dev);
1210 skb->ip_summed = CHECKSUM_NONE;
1211 netif_rx(skb);
1212 dev->last_rx = jiffies;
1213 sp->RxBuff[entry] = NULL;
1214 }
1215
1216 static void ipg_nic_rx_with_start(struct net_device *dev,
1217 struct ipg_nic_private *sp,
1218 struct ipg_rx *rxfd, unsigned entry)
1219 {
1220 struct SJumbo *jumbo = &sp->Jumbo;
1221 struct pci_dev *pdev = sp->pdev;
1222 struct sk_buff *skb;
1223
1224 // 1: found error, 0 no error
1225 if (ipg_nic_rx_check_error(dev) != NormalPacket)
1226 return;
1227
1228 // accept this frame and send to upper layer
1229 skb = sp->RxBuff[entry];
1230 if (!skb)
1231 return;
1232
1233 if (jumbo->FoundStart)
1234 IPG_DEV_KFREE_SKB(jumbo->skb);
1235
1236 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1237 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1238
1239 skb_put(skb, IPG_RXFRAG_SIZE);
1240
1241 jumbo->FoundStart = 1;
1242 jumbo->CurrentSize = IPG_RXFRAG_SIZE;
1243 jumbo->skb = skb;
1244
1245 sp->RxBuff[entry] = NULL;
1246 dev->last_rx = jiffies;
1247 }
1248
1249 static void ipg_nic_rx_with_end(struct net_device *dev,
1250 struct ipg_nic_private *sp,
1251 struct ipg_rx *rxfd, unsigned entry)
1252 {
1253 struct SJumbo *jumbo = &sp->Jumbo;
1254
1255 //1: found error, 0 no error
1256 if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1257 struct sk_buff *skb = sp->RxBuff[entry];
1258
1259 if (!skb)
1260 return;
1261
1262 if (jumbo->FoundStart) {
1263 int framelen, endframelen;
1264
1265 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1266
1267 endframeLen = framelen - jumbo->CurrentSize;
1268 /*
1269 if (framelen > IPG_RXFRAG_SIZE)
1270 framelen=IPG_RXFRAG_SIZE;
1271 */
1272 if (framelen > IPG_RXSUPPORT_SIZE)
1273 IPG_DEV_KFREE_SKB(jumbo->skb);
1274 else {
1275 memcpy(skb_put(jumbo->skb, endframeLen),
1276 skb->data, endframeLen);
1277
1278 jumbo->skb->protocol =
1279 eth_type_trans(jumbo->skb, dev);
1280
1281 jumbo->skb->ip_summed = CHECKSUM_NONE;
1282 netif_rx(jumbo->skb);
1283 }
1284 }
1285
1286 dev->last_rx = jiffies;
1287 jumbo->FoundStart = 0;
1288 jumbo->CurrentSize = 0;
1289 jumbo->skb = NULL;
1290
1291 ipg_nic_rx_free_skb(dev);
1292 } else {
1293 IPG_DEV_KFREE_SKB(jumbo->skb);
1294 jumbo->FoundStart = 0;
1295 jumbo->CurrentSize = 0;
1296 jumbo->skb = NULL;
1297 }
1298 }
1299
1300 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1301 struct ipg_nic_private *sp,
1302 struct ipg_rx *rxfd, unsigned entry)
1303 {
1304 struct SJumbo *jumbo = &sp->Jumbo;
1305
1306 //1: found error, 0 no error
1307 if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1308 struct sk_buff *skb = sp->RxBuff[entry];
1309
1310 if (skb) {
1311 if (jumbo->FoundStart) {
1312 jumbo->CurrentSize += IPG_RXFRAG_SIZE;
1313 if (jumbo->CurrentSize <= IPG_RXSUPPORT_SIZE) {
1314 memcpy(skb_put(jumbo->skb,
1315 IPG_RXFRAG_SIZE),
1316 skb->data, IPG_RXFRAG_SIZE);
1317 }
1318 }
1319 dev->last_rx = jiffies;
1320 ipg_nic_rx_free_skb(dev);
1321 }
1322 } else {
1323 IPG_DEV_KFREE_SKB(jumbo->skb);
1324 jumbo->FoundStart = 0;
1325 jumbo->CurrentSize = 0;
1326 jumbo->skb = NULL;
1327 }
1328 }
1329
1330 static int ipg_nic_rx(struct net_device *dev)
1331 {
1332 struct ipg_nic_private *sp = netdev_priv(dev);
1333 unsigned int curr = sp->rx_current;
1334 void __iomem *ioaddr = sp->ioaddr;
1335 unsigned int i;
1336
1337 IPG_DEBUG_MSG("_nic_rx\n");
1338
1339 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1340 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1341 struct ipg_rx *rxfd = sp->rxd + entry;
1342
1343 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1344 break;
1345
1346 switch (ipg_nic_rx_check_frame_type(dev)) {
1347 case Frame_WithStart_WithEnd:
1348 ipg_nic_rx_with_start_and_end(dev, tp, rxfd, entry);
1349 break;
1350 case Frame_WithStart:
1351 ipg_nic_rx_with_start(dev, tp, rxfd, entry);
1352 break;
1353 case Frame_WithEnd:
1354 ipg_nic_rx_with_end(dev, tp, rxfd, entry);
1355 break;
1356 case Frame_NoStart_NoEnd:
1357 ipg_nic_rx_no_start_no_end(dev, tp, rxfd, entry);
1358 break;
1359 }
1360 }
1361
1362 sp->rx_current = curr;
1363
1364 if (i == IPG_MAXRFDPROCESS_COUNT) {
1365 /* There are more RFDs to process, however the
1366 * allocated amount of RFD processing time has
1367 * expired. Assert Interrupt Requested to make
1368 * sure we come back to process the remaining RFDs.
1369 */
1370 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1371 }
1372
1373 ipg_nic_rxrestore(dev);
1374
1375 return 0;
1376 }
1377
1378 #else
1379 static int ipg_nic_rx(struct net_device *dev)
1380 {
1381 /* Transfer received Ethernet frames to higher network layers. */
1382 struct ipg_nic_private *sp = netdev_priv(dev);
1383 unsigned int curr = sp->rx_current;
1384 void __iomem *ioaddr = sp->ioaddr;
1385 struct ipg_rx *rxfd;
1386 unsigned int i;
1387
1388 IPG_DEBUG_MSG("_nic_rx\n");
1389
1390 #define __RFS_MASK \
1391 cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1392
1393 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1394 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1395 struct sk_buff *skb = sp->RxBuff[entry];
1396 unsigned int framelen;
1397
1398 rxfd = sp->rxd + entry;
1399
1400 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1401 break;
1402
1403 /* Get received frame length. */
1404 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1405
1406 /* Check for jumbo frame arrival with too small
1407 * RXFRAG_SIZE.
1408 */
1409 if (framelen > IPG_RXFRAG_SIZE) {
1410 IPG_DEBUG_MSG
1411 ("RFS FrameLen > allocated fragment size.\n");
1412
1413 framelen = IPG_RXFRAG_SIZE;
1414 }
1415
1416 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1417 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1418 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1419 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1420
1421 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1422 (unsigned long int) rxfd->rfs);
1423
1424 /* Increment general receive error statistic. */
1425 sp->stats.rx_errors++;
1426
1427 /* Increment detailed receive error statistics. */
1428 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1429 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1430 sp->stats.rx_fifo_errors++;
1431 }
1432
1433 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1434 IPG_DEBUG_MSG("RX runt occured.\n");
1435 sp->stats.rx_length_errors++;
1436 }
1437
1438 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1439 /* Do nothing, error count handled by a IPG
1440 * statistic register.
1441 */
1442
1443 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1444 IPG_DEBUG_MSG("RX alignment error occured.\n");
1445 sp->stats.rx_frame_errors++;
1446 }
1447
1448 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1449 /* Do nothing, error count handled by a IPG
1450 * statistic register.
1451 */
1452
1453 /* Free the memory associated with the RX
1454 * buffer since it is erroneous and we will
1455 * not pass it to higher layer processes.
1456 */
1457 if (skb) {
1458 __le64 info = rxfd->frag_info;
1459
1460 pci_unmap_single(sp->pdev,
1461 le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1462 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1463
1464 IPG_DEV_KFREE_SKB(skb);
1465 }
1466 } else {
1467
1468 /* Adjust the new buffer length to accomodate the size
1469 * of the received frame.
1470 */
1471 skb_put(skb, framelen);
1472
1473 /* Set the buffer's protocol field to Ethernet. */
1474 skb->protocol = eth_type_trans(skb, dev);
1475
1476 /* If the frame contains an IP/TCP/UDP frame,
1477 * determine if upper layer must check IP/TCP/UDP
1478 * checksums.
1479 *
1480 * NOTE: DO NOT RELY ON THE TCP/UDP CHECKSUM
1481 * VERIFICATION FOR SILICON REVISIONS B3
1482 * AND EARLIER!
1483 *
1484 if ((le64_to_cpu(rxfd->rfs &
1485 (IPG_RFS_TCPDETECTED | IPG_RFS_UDPDETECTED |
1486 IPG_RFS_IPDETECTED))) &&
1487 !(le64_to_cpu(rxfd->rfs &
1488 (IPG_RFS_TCPERROR | IPG_RFS_UDPERROR |
1489 IPG_RFS_IPERROR)))) {
1490 * Indicate IP checksums were performed
1491 * by the IPG.
1492 *
1493 skb->ip_summed = CHECKSUM_UNNECESSARY;
1494 } else
1495 */
1496 {
1497 /* The IPG encountered an error with (or
1498 * there were no) IP/TCP/UDP checksums.
1499 * This may or may not indicate an invalid
1500 * IP/TCP/UDP frame was received. Let the
1501 * upper layer decide.
1502 */
1503 skb->ip_summed = CHECKSUM_NONE;
1504 }
1505
1506 /* Hand off frame for higher layer processing.
1507 * The function netif_rx() releases the sk_buff
1508 * when processing completes.
1509 */
1510 netif_rx(skb);
1511
1512 /* Record frame receive time (jiffies = Linux
1513 * kernel current time stamp).
1514 */
1515 dev->last_rx = jiffies;
1516 }
1517
1518 /* Assure RX buffer is not reused by IPG. */
1519 sp->RxBuff[entry] = NULL;
1520 }
1521
1522 /*
1523 * If there are more RFDs to proces and the allocated amount of RFD
1524 * processing time has expired, assert Interrupt Requested to make
1525 * sure we come back to process the remaining RFDs.
1526 */
1527 if (i == IPG_MAXRFDPROCESS_COUNT)
1528 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1529
1530 #ifdef IPG_DEBUG
1531 /* Check if the RFD list contained no receive frame data. */
1532 if (!i)
1533 sp->EmptyRFDListCount++;
1534 #endif
1535 while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1536 !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1537 (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1538 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1539
1540 rxfd = sp->rxd + entry;
1541
1542 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1543
1544 /* An unexpected event, additional code needed to handle
1545 * properly. So for the time being, just disregard the
1546 * frame.
1547 */
1548
1549 /* Free the memory associated with the RX
1550 * buffer since it is erroneous and we will
1551 * not pass it to higher layer processes.
1552 */
1553 if (sp->RxBuff[entry]) {
1554 pci_unmap_single(sp->pdev,
1555 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1556 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1557 IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1558 }
1559
1560 /* Assure RX buffer is not reused by IPG. */
1561 sp->RxBuff[entry] = NULL;
1562 }
1563
1564 sp->rx_current = curr;
1565
1566 /* Check to see if there are a minimum number of used
1567 * RFDs before restoring any (should improve performance.)
1568 */
1569 if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1570 ipg_nic_rxrestore(dev);
1571
1572 return 0;
1573 }
1574 #endif
1575
1576 static void ipg_reset_after_host_error(struct work_struct *work)
1577 {
1578 struct ipg_nic_private *sp =
1579 container_of(work, struct ipg_nic_private, task.work);
1580 struct net_device *dev = sp->dev;
1581
1582 IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1583
1584 /*
1585 * Acknowledge HostError interrupt by resetting
1586 * IPG DMA and HOST.
1587 */
1588 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1589
1590 init_rfdlist(dev);
1591 init_tfdlist(dev);
1592
1593 if (ipg_io_config(dev) < 0) {
1594 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1595 dev->name);
1596 schedule_delayed_work(&sp->task, HZ);
1597 }
1598 }
1599
1600 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1601 {
1602 struct net_device *dev = dev_inst;
1603 struct ipg_nic_private *sp = netdev_priv(dev);
1604 void __iomem *ioaddr = sp->ioaddr;
1605 unsigned int handled = 0;
1606 u16 status;
1607
1608 IPG_DEBUG_MSG("_interrupt_handler\n");
1609
1610 #ifdef JUMBO_FRAME
1611 ipg_nic_rxrestore(dev);
1612 #endif
1613 /* Get interrupt source information, and acknowledge
1614 * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1615 * IntRequested, MacControlFrame, LinkEvent) interrupts
1616 * if issued. Also, all IPG interrupts are disabled by
1617 * reading IntStatusAck.
1618 */
1619 status = ipg_r16(INT_STATUS_ACK);
1620
1621 IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1622
1623 /* Shared IRQ of remove event. */
1624 if (!(status & IPG_IS_RSVD_MASK))
1625 goto out_enable;
1626
1627 handled = 1;
1628
1629 if (unlikely(!netif_running(dev)))
1630 goto out;
1631
1632 spin_lock(&sp->lock);
1633
1634 /* If RFDListEnd interrupt, restore all used RFDs. */
1635 if (status & IPG_IS_RFD_LIST_END) {
1636 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1637
1638 /* The RFD list end indicates an RFD was encountered
1639 * with a 0 NextPtr, or with an RFDDone bit set to 1
1640 * (indicating the RFD is not read for use by the
1641 * IPG.) Try to restore all RFDs.
1642 */
1643 ipg_nic_rxrestore(dev);
1644
1645 #ifdef IPG_DEBUG
1646 /* Increment the RFDlistendCount counter. */
1647 sp->RFDlistendCount++;
1648 #endif
1649 }
1650
1651 /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1652 * IntRequested interrupt, process received frames. */
1653 if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1654 (status & IPG_IS_RFD_LIST_END) ||
1655 (status & IPG_IS_RX_DMA_COMPLETE) ||
1656 (status & IPG_IS_INT_REQUESTED)) {
1657 #ifdef IPG_DEBUG
1658 /* Increment the RFD list checked counter if interrupted
1659 * only to check the RFD list. */
1660 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1661 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1662 (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1663 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1664 IPG_IS_UPDATE_STATS)))
1665 sp->RFDListCheckedCount++;
1666 #endif
1667
1668 ipg_nic_rx(dev);
1669 }
1670
1671 /* If TxDMAComplete interrupt, free used TFDs. */
1672 if (status & IPG_IS_TX_DMA_COMPLETE)
1673 ipg_nic_txfree(dev);
1674
1675 /* TxComplete interrupts indicate one of numerous actions.
1676 * Determine what action to take based on TXSTATUS register.
1677 */
1678 if (status & IPG_IS_TX_COMPLETE)
1679 ipg_nic_txcleanup(dev);
1680
1681 /* If UpdateStats interrupt, update Linux Ethernet statistics */
1682 if (status & IPG_IS_UPDATE_STATS)
1683 ipg_nic_get_stats(dev);
1684
1685 /* If HostError interrupt, reset IPG. */
1686 if (status & IPG_IS_HOST_ERROR) {
1687 IPG_DDEBUG_MSG("HostError Interrupt\n");
1688
1689 schedule_delayed_work(&sp->task, 0);
1690 }
1691
1692 /* If LinkEvent interrupt, resolve autonegotiation. */
1693 if (status & IPG_IS_LINK_EVENT) {
1694 if (ipg_config_autoneg(dev) < 0)
1695 printk(KERN_INFO "%s: Auto-negotiation error.\n",
1696 dev->name);
1697 }
1698
1699 /* If MACCtrlFrame interrupt, do nothing. */
1700 if (status & IPG_IS_MAC_CTRL_FRAME)
1701 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1702
1703 /* If RxComplete interrupt, do nothing. */
1704 if (status & IPG_IS_RX_COMPLETE)
1705 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1706
1707 /* If RxEarly interrupt, do nothing. */
1708 if (status & IPG_IS_RX_EARLY)
1709 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1710
1711 out_enable:
1712 /* Re-enable IPG interrupts. */
1713 ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1714 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1715 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1716
1717 spin_unlock(&sp->lock);
1718 out:
1719 return IRQ_RETVAL(handled);
1720 }
1721
1722 static void ipg_rx_clear(struct ipg_nic_private *sp)
1723 {
1724 unsigned int i;
1725
1726 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1727 if (sp->RxBuff[i]) {
1728 struct ipg_rx *rxfd = sp->rxd + i;
1729
1730 IPG_DEV_KFREE_SKB(sp->RxBuff[i]);
1731 sp->RxBuff[i] = NULL;
1732 pci_unmap_single(sp->pdev,
1733 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1734 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1735 }
1736 }
1737 }
1738
1739 static void ipg_tx_clear(struct ipg_nic_private *sp)
1740 {
1741 unsigned int i;
1742
1743 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1744 if (sp->TxBuff[i]) {
1745 struct ipg_tx *txfd = sp->txd + i;
1746
1747 pci_unmap_single(sp->pdev,
1748 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1749 sp->TxBuff[i]->len, PCI_DMA_TODEVICE);
1750
1751 IPG_DEV_KFREE_SKB(sp->TxBuff[i]);
1752
1753 sp->TxBuff[i] = NULL;
1754 }
1755 }
1756 }
1757
1758 static int ipg_nic_open(struct net_device *dev)
1759 {
1760 struct ipg_nic_private *sp = netdev_priv(dev);
1761 void __iomem *ioaddr = sp->ioaddr;
1762 struct pci_dev *pdev = sp->pdev;
1763 int rc;
1764
1765 IPG_DEBUG_MSG("_nic_open\n");
1766
1767 sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1768
1769 /* Check for interrupt line conflicts, and request interrupt
1770 * line for IPG.
1771 *
1772 * IMPORTANT: Disable IPG interrupts prior to registering
1773 * IRQ.
1774 */
1775 ipg_w16(0x0000, INT_ENABLE);
1776
1777 /* Register the interrupt line to be used by the IPG within
1778 * the Linux system.
1779 */
1780 rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1781 dev->name, dev);
1782 if (rc < 0) {
1783 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1784 dev->name);
1785 goto out;
1786 }
1787
1788 dev->irq = pdev->irq;
1789
1790 rc = -ENOMEM;
1791
1792 sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1793 &sp->rxd_map, GFP_KERNEL);
1794 if (!sp->rxd)
1795 goto err_free_irq_0;
1796
1797 sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1798 &sp->txd_map, GFP_KERNEL);
1799 if (!sp->txd)
1800 goto err_free_rx_1;
1801
1802 rc = init_rfdlist(dev);
1803 if (rc < 0) {
1804 printk(KERN_INFO "%s: Error during configuration.\n",
1805 dev->name);
1806 goto err_free_tx_2;
1807 }
1808
1809 init_tfdlist(dev);
1810
1811 rc = ipg_io_config(dev);
1812 if (rc < 0) {
1813 printk(KERN_INFO "%s: Error during configuration.\n",
1814 dev->name);
1815 goto err_release_tfdlist_3;
1816 }
1817
1818 /* Resolve autonegotiation. */
1819 if (ipg_config_autoneg(dev) < 0)
1820 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1821
1822 #ifdef JUMBO_FRAME
1823 /* initialize JUMBO Frame control variable */
1824 sp->Jumbo.FoundStart = 0;
1825 sp->Jumbo.CurrentSize = 0;
1826 sp->Jumbo.skb = 0;
1827 dev->mtu = IPG_TXFRAG_SIZE;
1828 #endif
1829
1830 /* Enable transmit and receive operation of the IPG. */
1831 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1832 IPG_MC_RSVD_MASK, MAC_CTRL);
1833
1834 netif_start_queue(dev);
1835 out:
1836 return rc;
1837
1838 err_release_tfdlist_3:
1839 ipg_tx_clear(sp);
1840 ipg_rx_clear(sp);
1841 err_free_tx_2:
1842 dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1843 err_free_rx_1:
1844 dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1845 err_free_irq_0:
1846 free_irq(pdev->irq, dev);
1847 goto out;
1848 }
1849
1850 static int ipg_nic_stop(struct net_device *dev)
1851 {
1852 struct ipg_nic_private *sp = netdev_priv(dev);
1853 void __iomem *ioaddr = sp->ioaddr;
1854 struct pci_dev *pdev = sp->pdev;
1855
1856 IPG_DEBUG_MSG("_nic_stop\n");
1857
1858 netif_stop_queue(dev);
1859
1860 IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1861 IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1862 IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1863 IPG_DUMPTFDLIST(dev);
1864
1865 do {
1866 (void) ipg_r16(INT_STATUS_ACK);
1867
1868 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1869
1870 synchronize_irq(pdev->irq);
1871 } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1872
1873 ipg_rx_clear(sp);
1874
1875 ipg_tx_clear(sp);
1876
1877 pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1878 pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1879
1880 free_irq(pdev->irq, dev);
1881
1882 return 0;
1883 }
1884
1885 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1886 {
1887 struct ipg_nic_private *sp = netdev_priv(dev);
1888 void __iomem *ioaddr = sp->ioaddr;
1889 unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1890 unsigned long flags;
1891 struct ipg_tx *txfd;
1892
1893 IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1894
1895 /* If in 10Mbps mode, stop the transmit queue so
1896 * no more transmit frames are accepted.
1897 */
1898 if (sp->tenmbpsmode)
1899 netif_stop_queue(dev);
1900
1901 if (sp->ResetCurrentTFD) {
1902 sp->ResetCurrentTFD = 0;
1903 entry = 0;
1904 }
1905
1906 txfd = sp->txd + entry;
1907
1908 sp->TxBuff[entry] = skb;
1909
1910 /* Clear all TFC fields, except TFDDONE. */
1911 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1912
1913 /* Specify the TFC field within the TFD. */
1914 txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1915 (IPG_TFC_FRAMEID & cpu_to_le64(sp->tx_current)) |
1916 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1917
1918 /* Request TxComplete interrupts at an interval defined
1919 * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1920 * Request TxComplete interrupt for every frame
1921 * if in 10Mbps mode to accomodate problem with 10Mbps
1922 * processing.
1923 */
1924 if (sp->tenmbpsmode)
1925 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1926 else if (!((sp->tx_current - sp->tx_dirty + 1) >
1927 IPG_FRAMESBETWEENTXDMACOMPLETES)) {
1928 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1929 }
1930 /* Based on compilation option, determine if FCS is to be
1931 * appended to transmit frame by IPG.
1932 */
1933 if (!(IPG_APPEND_FCS_ON_TX))
1934 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1935
1936 /* Based on compilation option, determine if IP, TCP and/or
1937 * UDP checksums are to be added to transmit frame by IPG.
1938 */
1939 if (IPG_ADD_IPCHECKSUM_ON_TX)
1940 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1941
1942 if (IPG_ADD_TCPCHECKSUM_ON_TX)
1943 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1944
1945 if (IPG_ADD_UDPCHECKSUM_ON_TX)
1946 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1947
1948 /* Based on compilation option, determine if VLAN tag info is to be
1949 * inserted into transmit frame by IPG.
1950 */
1951 if (IPG_INSERT_MANUAL_VLAN_TAG) {
1952 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1953 ((u64) IPG_MANUAL_VLAN_VID << 32) |
1954 ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1955 ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1956 }
1957
1958 /* The fragment start location within system memory is defined
1959 * by the sk_buff structure's data field. The physical address
1960 * of this location within the system's virtual memory space
1961 * is determined using the IPG_HOST2BUS_MAP function.
1962 */
1963 txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1964 skb->len, PCI_DMA_TODEVICE));
1965
1966 /* The length of the fragment within system memory is defined by
1967 * the sk_buff structure's len field.
1968 */
1969 txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1970 ((u64) (skb->len & 0xffff) << 48));
1971
1972 /* Clear the TFDDone bit last to indicate the TFD is ready
1973 * for transfer to the IPG.
1974 */
1975 txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1976
1977 spin_lock_irqsave(&sp->lock, flags);
1978
1979 sp->tx_current++;
1980
1981 mmiowb();
1982
1983 ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1984
1985 if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1986 netif_wake_queue(dev);
1987
1988 spin_unlock_irqrestore(&sp->lock, flags);
1989
1990 return NETDEV_TX_OK;
1991 }
1992
1993 static void ipg_set_phy_default_param(unsigned char rev,
1994 struct net_device *dev, int phy_address)
1995 {
1996 unsigned short length;
1997 unsigned char revision;
1998 unsigned short *phy_param;
1999 unsigned short address, value;
2000
2001 phy_param = &DefaultPhyParam[0];
2002 length = *phy_param & 0x00FF;
2003 revision = (unsigned char)((*phy_param) >> 8);
2004 phy_param++;
2005 while (length != 0) {
2006 if (rev == revision) {
2007 while (length > 1) {
2008 address = *phy_param;
2009 value = *(phy_param + 1);
2010 phy_param += 2;
2011 mdio_write(dev, phy_address, address, value);
2012 length -= 4;
2013 }
2014 break;
2015 } else {
2016 phy_param += length / 2;
2017 length = *phy_param & 0x00FF;
2018 revision = (unsigned char)((*phy_param) >> 8);
2019 phy_param++;
2020 }
2021 }
2022 }
2023
2024 /* JES20040127EEPROM */
2025 static int read_eeprom(struct net_device *dev, int eep_addr)
2026 {
2027 void __iomem *ioaddr = ipg_ioaddr(dev);
2028 unsigned int i;
2029 int ret = 0;
2030 u16 value;
2031
2032 value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2033 ipg_w16(value, EEPROM_CTRL);
2034
2035 for (i = 0; i < 1000; i++) {
2036 u16 data;
2037
2038 mdelay(10);
2039 data = ipg_r16(EEPROM_CTRL);
2040 if (!(data & IPG_EC_EEPROM_BUSY)) {
2041 ret = ipg_r16(EEPROM_DATA);
2042 break;
2043 }
2044 }
2045 return ret;
2046 }
2047
2048 static void ipg_init_mii(struct net_device *dev)
2049 {
2050 struct ipg_nic_private *sp = netdev_priv(dev);
2051 struct mii_if_info *mii_if = &sp->mii_if;
2052 int phyaddr;
2053
2054 mii_if->dev = dev;
2055 mii_if->mdio_read = mdio_read;
2056 mii_if->mdio_write = mdio_write;
2057 mii_if->phy_id_mask = 0x1f;
2058 mii_if->reg_num_mask = 0x1f;
2059
2060 mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2061
2062 if (phyaddr != 0x1f) {
2063 u16 mii_phyctrl, mii_1000cr;
2064 u8 revisionid = 0;
2065
2066 mii_1000cr = mdio_read(dev, phyaddr, MII_CTRL1000);
2067 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2068 GMII_PHY_1000BASETCONTROL_PreferMaster;
2069 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2070
2071 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2072
2073 /* Set default phyparam */
2074 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2075 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2076
2077 /* Reset PHY */
2078 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2079 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2080
2081 }
2082 }
2083
2084 static int ipg_hw_init(struct net_device *dev)
2085 {
2086 struct ipg_nic_private *sp = netdev_priv(dev);
2087 void __iomem *ioaddr = sp->ioaddr;
2088 unsigned int i;
2089 int rc;
2090
2091 /* Read/Write and Reset EEPROM Value Jesse20040128EEPROM_VALUE */
2092 /* Read LED Mode Configuration from EEPROM */
2093 sp->LED_Mode = read_eeprom(dev, 6);
2094
2095 /* Reset all functions within the IPG. Do not assert
2096 * RST_OUT as not compatible with some PHYs.
2097 */
2098 rc = ipg_reset(dev, IPG_RESET_MASK);
2099 if (rc < 0)
2100 goto out;
2101
2102 ipg_init_mii(dev);
2103
2104 /* Read MAC Address from EEPROM */
2105 for (i = 0; i < 3; i++)
2106 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2107
2108 for (i = 0; i < 3; i++)
2109 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2110
2111 /* Set station address in ethernet_device structure. */
2112 dev->dev_addr[0] = ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2113 dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2114 dev->dev_addr[2] = ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2115 dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2116 dev->dev_addr[4] = ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2117 dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2118 out:
2119 return rc;
2120 }
2121
2122 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2123 {
2124 struct ipg_nic_private *sp = netdev_priv(dev);
2125 int rc;
2126
2127 mutex_lock(&sp->mii_mutex);
2128 rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2129 mutex_unlock(&sp->mii_mutex);
2130
2131 return rc;
2132 }
2133
2134 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2135 {
2136 /* Function to accomodate changes to Maximum Transfer Unit
2137 * (or MTU) of IPG NIC. Cannot use default function since
2138 * the default will not allow for MTU > 1500 bytes.
2139 */
2140
2141 IPG_DEBUG_MSG("_nic_change_mtu\n");
2142
2143 /* Check that the new MTU value is between 68 (14 byte header, 46
2144 * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2145 * corresponds to the MAXFRAMESIZE register in the IPG.
2146 */
2147 if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2148 return -EINVAL;
2149
2150 dev->mtu = new_mtu;
2151
2152 return 0;
2153 }
2154
2155 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2156 {
2157 struct ipg_nic_private *sp = netdev_priv(dev);
2158 int rc;
2159
2160 mutex_lock(&sp->mii_mutex);
2161 rc = mii_ethtool_gset(&sp->mii_if, cmd);
2162 mutex_unlock(&sp->mii_mutex);
2163
2164 return rc;
2165 }
2166
2167 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2168 {
2169 struct ipg_nic_private *sp = netdev_priv(dev);
2170 int rc;
2171
2172 mutex_lock(&sp->mii_mutex);
2173 rc = mii_ethtool_sset(&sp->mii_if, cmd);
2174 mutex_unlock(&sp->mii_mutex);
2175
2176 return rc;
2177 }
2178
2179 static int ipg_nway_reset(struct net_device *dev)
2180 {
2181 struct ipg_nic_private *sp = netdev_priv(dev);
2182 int rc;
2183
2184 mutex_lock(&sp->mii_mutex);
2185 rc = mii_nway_restart(&sp->mii_if);
2186 mutex_unlock(&sp->mii_mutex);
2187
2188 return rc;
2189 }
2190
2191 static struct ethtool_ops ipg_ethtool_ops = {
2192 .get_settings = ipg_get_settings,
2193 .set_settings = ipg_set_settings,
2194 .nway_reset = ipg_nway_reset,
2195 };
2196
2197 static void ipg_remove(struct pci_dev *pdev)
2198 {
2199 struct net_device *dev = pci_get_drvdata(pdev);
2200 struct ipg_nic_private *sp = netdev_priv(dev);
2201
2202 IPG_DEBUG_MSG("_remove\n");
2203
2204 /* Un-register Ethernet device. */
2205 unregister_netdev(dev);
2206
2207 pci_iounmap(pdev, sp->ioaddr);
2208
2209 pci_release_regions(pdev);
2210
2211 free_netdev(dev);
2212 pci_disable_device(pdev);
2213 pci_set_drvdata(pdev, NULL);
2214 }
2215
2216 static int __devinit ipg_probe(struct pci_dev *pdev,
2217 const struct pci_device_id *id)
2218 {
2219 unsigned int i = id->driver_data;
2220 struct ipg_nic_private *sp;
2221 struct net_device *dev;
2222 void __iomem *ioaddr;
2223 int rc;
2224
2225 rc = pci_enable_device(pdev);
2226 if (rc < 0)
2227 goto out;
2228
2229 printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2230
2231 pci_set_master(pdev);
2232
2233 rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2234 if (rc < 0) {
2235 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2236 if (rc < 0) {
2237 printk(KERN_ERR "%s: DMA config failed.\n",
2238 pci_name(pdev));
2239 goto err_disable_0;
2240 }
2241 }
2242
2243 /*
2244 * Initialize net device.
2245 */
2246 dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2247 if (!dev) {
2248 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2249 rc = -ENOMEM;
2250 goto err_disable_0;
2251 }
2252
2253 sp = netdev_priv(dev);
2254 spin_lock_init(&sp->lock);
2255 mutex_init(&sp->mii_mutex);
2256
2257 /* Declare IPG NIC functions for Ethernet device methods.
2258 */
2259 dev->open = &ipg_nic_open;
2260 dev->stop = &ipg_nic_stop;
2261 dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2262 dev->get_stats = &ipg_nic_get_stats;
2263 dev->set_multicast_list = &ipg_nic_set_multicast_list;
2264 dev->do_ioctl = ipg_ioctl;
2265 dev->tx_timeout = ipg_tx_timeout;
2266 dev->change_mtu = &ipg_nic_change_mtu;
2267
2268 SET_NETDEV_DEV(dev, &pdev->dev);
2269 SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2270
2271 rc = pci_request_regions(pdev, DRV_NAME);
2272 if (rc)
2273 goto err_free_dev_1;
2274
2275 ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2276 if (!ioaddr) {
2277 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2278 rc = -EIO;
2279 goto err_release_regions_2;
2280 }
2281
2282 /* Save the pointer to the PCI device information. */
2283 sp->ioaddr = ioaddr;
2284 sp->pdev = pdev;
2285 sp->dev = dev;
2286
2287 INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2288
2289 pci_set_drvdata(pdev, dev);
2290
2291 rc = ipg_hw_init(dev);
2292 if (rc < 0)
2293 goto err_unmap_3;
2294
2295 rc = register_netdev(dev);
2296 if (rc < 0)
2297 goto err_unmap_3;
2298
2299 printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2300 out:
2301 return rc;
2302
2303 err_unmap_3:
2304 pci_iounmap(pdev, ioaddr);
2305 err_release_regions_2:
2306 pci_release_regions(pdev);
2307 err_free_dev_1:
2308 free_netdev(dev);
2309 err_disable_0:
2310 pci_disable_device(pdev);
2311 goto out;
2312 }
2313
2314 static struct pci_driver ipg_pci_driver = {
2315 .name = IPG_DRIVER_NAME,
2316 .id_table = ipg_pci_tbl,
2317 .probe = ipg_probe,
2318 .remove = __devexit_p(ipg_remove),
2319 };
2320
2321 static int __init ipg_init_module(void)
2322 {
2323 return pci_register_driver(&ipg_pci_driver);
2324 }
2325
2326 static void __exit ipg_exit_module(void)
2327 {
2328 pci_unregister_driver(&ipg_pci_driver);
2329 }
2330
2331 module_init(ipg_init_module);
2332 module_exit(ipg_exit_module);
Support for the Chinese Samsung S3C2440 based development boards