[ALSA] Fix build error without CONFIG_HAS_DMA
[linux-2.6/mini2440.git] / drivers / net / fec.c
blob2b5782056ddae658343fd0f280ee05b38d2420d5
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
11 * Right now, I am very wasteful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets.
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
21 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
25 * Copyright (c) 2004-2006 Macq Electronique SA.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/string.h>
31 #include <linux/ptrace.h>
32 #include <linux/errno.h>
33 #include <linux/ioport.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
46 #include <asm/irq.h>
47 #include <asm/uaccess.h>
48 #include <asm/io.h>
49 #include <asm/pgtable.h>
50 #include <asm/cacheflush.h>
52 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
53 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
54 defined(CONFIG_M520x) || defined(CONFIG_M532x)
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
57 #include "fec.h"
58 #else
59 #include <asm/8xx_immap.h>
60 #include <asm/mpc8xx.h>
61 #include "commproc.h"
62 #endif
64 #if defined(CONFIG_FEC2)
65 #define FEC_MAX_PORTS 2
66 #else
67 #define FEC_MAX_PORTS 1
68 #endif
71 * Define the fixed address of the FEC hardware.
73 static unsigned int fec_hw[] = {
74 #if defined(CONFIG_M5272)
75 (MCF_MBAR + 0x840),
76 #elif defined(CONFIG_M527x)
77 (MCF_MBAR + 0x1000),
78 (MCF_MBAR + 0x1800),
79 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
80 (MCF_MBAR + 0x1000),
81 #elif defined(CONFIG_M520x)
82 (MCF_MBAR+0x30000),
83 #elif defined(CONFIG_M532x)
84 (MCF_MBAR+0xfc030000),
85 #else
86 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
87 #endif
90 static unsigned char fec_mac_default[] = {
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
95 * Some hardware gets it MAC address out of local flash memory.
96 * if this is non-zero then assume it is the address to get MAC from.
98 #if defined(CONFIG_NETtel)
99 #define FEC_FLASHMAC 0xf0006006
100 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
101 #define FEC_FLASHMAC 0xf0006000
102 #elif defined(CONFIG_CANCam)
103 #define FEC_FLASHMAC 0xf0020000
104 #elif defined (CONFIG_M5272C3)
105 #define FEC_FLASHMAC (0xffe04000 + 4)
106 #elif defined(CONFIG_MOD5272)
107 #define FEC_FLASHMAC 0xffc0406b
108 #else
109 #define FEC_FLASHMAC 0
110 #endif
112 /* Forward declarations of some structures to support different PHYs
115 typedef struct {
116 uint mii_data;
117 void (*funct)(uint mii_reg, struct net_device *dev);
118 } phy_cmd_t;
120 typedef struct {
121 uint id;
122 char *name;
124 const phy_cmd_t *config;
125 const phy_cmd_t *startup;
126 const phy_cmd_t *ack_int;
127 const phy_cmd_t *shutdown;
128 } phy_info_t;
130 /* The number of Tx and Rx buffers. These are allocated from the page
131 * pool. The code may assume these are power of two, so it it best
132 * to keep them that size.
133 * We don't need to allocate pages for the transmitter. We just use
134 * the skbuffer directly.
136 #define FEC_ENET_RX_PAGES 8
137 #define FEC_ENET_RX_FRSIZE 2048
138 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
139 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
140 #define FEC_ENET_TX_FRSIZE 2048
141 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
142 #define TX_RING_SIZE 16 /* Must be power of two */
143 #define TX_RING_MOD_MASK 15 /* for this to work */
145 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
146 #error "FEC: descriptor ring size constants too large"
147 #endif
149 /* Interrupt events/masks.
151 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
152 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
153 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
154 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
155 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
156 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
157 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
158 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
159 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
160 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
162 /* The FEC stores dest/src/type, data, and checksum for receive packets.
164 #define PKT_MAXBUF_SIZE 1518
165 #define PKT_MINBUF_SIZE 64
166 #define PKT_MAXBLR_SIZE 1520
170 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
171 * size bits. Other FEC hardware does not, so we need to take that into
172 * account when setting it.
174 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
175 defined(CONFIG_M520x) || defined(CONFIG_M532x)
176 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
177 #else
178 #define OPT_FRAME_SIZE 0
179 #endif
181 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
182 * tx_bd_base always point to the base of the buffer descriptors. The
183 * cur_rx and cur_tx point to the currently available buffer.
184 * The dirty_tx tracks the current buffer that is being sent by the
185 * controller. The cur_tx and dirty_tx are equal under both completely
186 * empty and completely full conditions. The empty/ready indicator in
187 * the buffer descriptor determines the actual condition.
189 struct fec_enet_private {
190 /* Hardware registers of the FEC device */
191 volatile fec_t *hwp;
193 struct net_device *netdev;
195 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
196 unsigned char *tx_bounce[TX_RING_SIZE];
197 struct sk_buff* tx_skbuff[TX_RING_SIZE];
198 ushort skb_cur;
199 ushort skb_dirty;
201 /* CPM dual port RAM relative addresses.
203 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
204 cbd_t *tx_bd_base;
205 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
206 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
207 uint tx_full;
208 spinlock_t lock;
210 uint phy_id;
211 uint phy_id_done;
212 uint phy_status;
213 uint phy_speed;
214 phy_info_t const *phy;
215 struct work_struct phy_task;
217 uint sequence_done;
218 uint mii_phy_task_queued;
220 uint phy_addr;
222 int index;
223 int opened;
224 int link;
225 int old_link;
226 int full_duplex;
229 static int fec_enet_open(struct net_device *dev);
230 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
231 static void fec_enet_mii(struct net_device *dev);
232 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
233 static void fec_enet_tx(struct net_device *dev);
234 static void fec_enet_rx(struct net_device *dev);
235 static int fec_enet_close(struct net_device *dev);
236 static void set_multicast_list(struct net_device *dev);
237 static void fec_restart(struct net_device *dev, int duplex);
238 static void fec_stop(struct net_device *dev);
239 static void fec_set_mac_address(struct net_device *dev);
242 /* MII processing. We keep this as simple as possible. Requests are
243 * placed on the list (if there is room). When the request is finished
244 * by the MII, an optional function may be called.
246 typedef struct mii_list {
247 uint mii_regval;
248 void (*mii_func)(uint val, struct net_device *dev);
249 struct mii_list *mii_next;
250 } mii_list_t;
252 #define NMII 20
253 static mii_list_t mii_cmds[NMII];
254 static mii_list_t *mii_free;
255 static mii_list_t *mii_head;
256 static mii_list_t *mii_tail;
258 static int mii_queue(struct net_device *dev, int request,
259 void (*func)(uint, struct net_device *));
261 /* Make MII read/write commands for the FEC.
263 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
264 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
265 (VAL & 0xffff))
266 #define mk_mii_end 0
268 /* Transmitter timeout.
270 #define TX_TIMEOUT (2*HZ)
272 /* Register definitions for the PHY.
275 #define MII_REG_CR 0 /* Control Register */
276 #define MII_REG_SR 1 /* Status Register */
277 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
278 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
279 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
280 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
281 #define MII_REG_ANER 6 /* A-N Expansion Register */
282 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
283 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
285 /* values for phy_status */
287 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
288 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
289 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
290 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
291 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
292 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
293 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
295 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
296 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
297 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
298 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
299 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
300 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
301 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
302 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
305 static int
306 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
308 struct fec_enet_private *fep;
309 volatile fec_t *fecp;
310 volatile cbd_t *bdp;
311 unsigned short status;
313 fep = netdev_priv(dev);
314 fecp = (volatile fec_t*)dev->base_addr;
316 if (!fep->link) {
317 /* Link is down or autonegotiation is in progress. */
318 return 1;
321 /* Fill in a Tx ring entry */
322 bdp = fep->cur_tx;
324 status = bdp->cbd_sc;
325 #ifndef final_version
326 if (status & BD_ENET_TX_READY) {
327 /* Ooops. All transmit buffers are full. Bail out.
328 * This should not happen, since dev->tbusy should be set.
330 printk("%s: tx queue full!.\n", dev->name);
331 return 1;
333 #endif
335 /* Clear all of the status flags.
337 status &= ~BD_ENET_TX_STATS;
339 /* Set buffer length and buffer pointer.
341 bdp->cbd_bufaddr = __pa(skb->data);
342 bdp->cbd_datlen = skb->len;
345 * On some FEC implementations data must be aligned on
346 * 4-byte boundaries. Use bounce buffers to copy data
347 * and get it aligned. Ugh.
349 if (bdp->cbd_bufaddr & 0x3) {
350 unsigned int index;
351 index = bdp - fep->tx_bd_base;
352 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
353 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
356 /* Save skb pointer.
358 fep->tx_skbuff[fep->skb_cur] = skb;
360 dev->stats.tx_bytes += skb->len;
361 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
363 /* Push the data cache so the CPM does not get stale memory
364 * data.
366 flush_dcache_range((unsigned long)skb->data,
367 (unsigned long)skb->data + skb->len);
369 spin_lock_irq(&fep->lock);
371 /* Send it on its way. Tell FEC it's ready, interrupt when done,
372 * it's the last BD of the frame, and to put the CRC on the end.
375 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
376 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
377 bdp->cbd_sc = status;
379 dev->trans_start = jiffies;
381 /* Trigger transmission start */
382 fecp->fec_x_des_active = 0;
384 /* If this was the last BD in the ring, start at the beginning again.
386 if (status & BD_ENET_TX_WRAP) {
387 bdp = fep->tx_bd_base;
388 } else {
389 bdp++;
392 if (bdp == fep->dirty_tx) {
393 fep->tx_full = 1;
394 netif_stop_queue(dev);
397 fep->cur_tx = (cbd_t *)bdp;
399 spin_unlock_irq(&fep->lock);
401 return 0;
404 static void
405 fec_timeout(struct net_device *dev)
407 struct fec_enet_private *fep = netdev_priv(dev);
409 printk("%s: transmit timed out.\n", dev->name);
410 dev->stats.tx_errors++;
411 #ifndef final_version
413 int i;
414 cbd_t *bdp;
416 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
417 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
418 (unsigned long)fep->dirty_tx,
419 (unsigned long)fep->cur_rx);
421 bdp = fep->tx_bd_base;
422 printk(" tx: %u buffers\n", TX_RING_SIZE);
423 for (i = 0 ; i < TX_RING_SIZE; i++) {
424 printk(" %08x: %04x %04x %08x\n",
425 (uint) bdp,
426 bdp->cbd_sc,
427 bdp->cbd_datlen,
428 (int) bdp->cbd_bufaddr);
429 bdp++;
432 bdp = fep->rx_bd_base;
433 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
434 for (i = 0 ; i < RX_RING_SIZE; i++) {
435 printk(" %08x: %04x %04x %08x\n",
436 (uint) bdp,
437 bdp->cbd_sc,
438 bdp->cbd_datlen,
439 (int) bdp->cbd_bufaddr);
440 bdp++;
443 #endif
444 fec_restart(dev, fep->full_duplex);
445 netif_wake_queue(dev);
448 /* The interrupt handler.
449 * This is called from the MPC core interrupt.
451 static irqreturn_t
452 fec_enet_interrupt(int irq, void * dev_id)
454 struct net_device *dev = dev_id;
455 volatile fec_t *fecp;
456 uint int_events;
457 int handled = 0;
459 fecp = (volatile fec_t*)dev->base_addr;
461 /* Get the interrupt events that caused us to be here.
463 while ((int_events = fecp->fec_ievent) != 0) {
464 fecp->fec_ievent = int_events;
466 /* Handle receive event in its own function.
468 if (int_events & FEC_ENET_RXF) {
469 handled = 1;
470 fec_enet_rx(dev);
473 /* Transmit OK, or non-fatal error. Update the buffer
474 descriptors. FEC handles all errors, we just discover
475 them as part of the transmit process.
477 if (int_events & FEC_ENET_TXF) {
478 handled = 1;
479 fec_enet_tx(dev);
482 if (int_events & FEC_ENET_MII) {
483 handled = 1;
484 fec_enet_mii(dev);
488 return IRQ_RETVAL(handled);
492 static void
493 fec_enet_tx(struct net_device *dev)
495 struct fec_enet_private *fep;
496 volatile cbd_t *bdp;
497 unsigned short status;
498 struct sk_buff *skb;
500 fep = netdev_priv(dev);
501 spin_lock(&fep->lock);
502 bdp = fep->dirty_tx;
504 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
505 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
507 skb = fep->tx_skbuff[fep->skb_dirty];
508 /* Check for errors. */
509 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
510 BD_ENET_TX_RL | BD_ENET_TX_UN |
511 BD_ENET_TX_CSL)) {
512 dev->stats.tx_errors++;
513 if (status & BD_ENET_TX_HB) /* No heartbeat */
514 dev->stats.tx_heartbeat_errors++;
515 if (status & BD_ENET_TX_LC) /* Late collision */
516 dev->stats.tx_window_errors++;
517 if (status & BD_ENET_TX_RL) /* Retrans limit */
518 dev->stats.tx_aborted_errors++;
519 if (status & BD_ENET_TX_UN) /* Underrun */
520 dev->stats.tx_fifo_errors++;
521 if (status & BD_ENET_TX_CSL) /* Carrier lost */
522 dev->stats.tx_carrier_errors++;
523 } else {
524 dev->stats.tx_packets++;
527 #ifndef final_version
528 if (status & BD_ENET_TX_READY)
529 printk("HEY! Enet xmit interrupt and TX_READY.\n");
530 #endif
531 /* Deferred means some collisions occurred during transmit,
532 * but we eventually sent the packet OK.
534 if (status & BD_ENET_TX_DEF)
535 dev->stats.collisions++;
537 /* Free the sk buffer associated with this last transmit.
539 dev_kfree_skb_any(skb);
540 fep->tx_skbuff[fep->skb_dirty] = NULL;
541 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
543 /* Update pointer to next buffer descriptor to be transmitted.
545 if (status & BD_ENET_TX_WRAP)
546 bdp = fep->tx_bd_base;
547 else
548 bdp++;
550 /* Since we have freed up a buffer, the ring is no longer
551 * full.
553 if (fep->tx_full) {
554 fep->tx_full = 0;
555 if (netif_queue_stopped(dev))
556 netif_wake_queue(dev);
559 fep->dirty_tx = (cbd_t *)bdp;
560 spin_unlock(&fep->lock);
564 /* During a receive, the cur_rx points to the current incoming buffer.
565 * When we update through the ring, if the next incoming buffer has
566 * not been given to the system, we just set the empty indicator,
567 * effectively tossing the packet.
569 static void
570 fec_enet_rx(struct net_device *dev)
572 struct fec_enet_private *fep;
573 volatile fec_t *fecp;
574 volatile cbd_t *bdp;
575 unsigned short status;
576 struct sk_buff *skb;
577 ushort pkt_len;
578 __u8 *data;
580 #ifdef CONFIG_M532x
581 flush_cache_all();
582 #endif
584 fep = netdev_priv(dev);
585 fecp = (volatile fec_t*)dev->base_addr;
587 /* First, grab all of the stats for the incoming packet.
588 * These get messed up if we get called due to a busy condition.
590 bdp = fep->cur_rx;
592 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
594 #ifndef final_version
595 /* Since we have allocated space to hold a complete frame,
596 * the last indicator should be set.
598 if ((status & BD_ENET_RX_LAST) == 0)
599 printk("FEC ENET: rcv is not +last\n");
600 #endif
602 if (!fep->opened)
603 goto rx_processing_done;
605 /* Check for errors. */
606 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
607 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
608 dev->stats.rx_errors++;
609 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
610 /* Frame too long or too short. */
611 dev->stats.rx_length_errors++;
613 if (status & BD_ENET_RX_NO) /* Frame alignment */
614 dev->stats.rx_frame_errors++;
615 if (status & BD_ENET_RX_CR) /* CRC Error */
616 dev->stats.rx_crc_errors++;
617 if (status & BD_ENET_RX_OV) /* FIFO overrun */
618 dev->stats.rx_fifo_errors++;
621 /* Report late collisions as a frame error.
622 * On this error, the BD is closed, but we don't know what we
623 * have in the buffer. So, just drop this frame on the floor.
625 if (status & BD_ENET_RX_CL) {
626 dev->stats.rx_errors++;
627 dev->stats.rx_frame_errors++;
628 goto rx_processing_done;
631 /* Process the incoming frame.
633 dev->stats.rx_packets++;
634 pkt_len = bdp->cbd_datlen;
635 dev->stats.rx_bytes += pkt_len;
636 data = (__u8*)__va(bdp->cbd_bufaddr);
638 /* This does 16 byte alignment, exactly what we need.
639 * The packet length includes FCS, but we don't want to
640 * include that when passing upstream as it messes up
641 * bridging applications.
643 skb = dev_alloc_skb(pkt_len-4);
645 if (skb == NULL) {
646 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
647 dev->stats.rx_dropped++;
648 } else {
649 skb_put(skb,pkt_len-4); /* Make room */
650 skb_copy_to_linear_data(skb, data, pkt_len-4);
651 skb->protocol=eth_type_trans(skb,dev);
652 netif_rx(skb);
654 rx_processing_done:
656 /* Clear the status flags for this buffer.
658 status &= ~BD_ENET_RX_STATS;
660 /* Mark the buffer empty.
662 status |= BD_ENET_RX_EMPTY;
663 bdp->cbd_sc = status;
665 /* Update BD pointer to next entry.
667 if (status & BD_ENET_RX_WRAP)
668 bdp = fep->rx_bd_base;
669 else
670 bdp++;
672 #if 1
673 /* Doing this here will keep the FEC running while we process
674 * incoming frames. On a heavily loaded network, we should be
675 * able to keep up at the expense of system resources.
677 fecp->fec_r_des_active = 0;
678 #endif
679 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
680 fep->cur_rx = (cbd_t *)bdp;
682 #if 0
683 /* Doing this here will allow us to process all frames in the
684 * ring before the FEC is allowed to put more there. On a heavily
685 * loaded network, some frames may be lost. Unfortunately, this
686 * increases the interrupt overhead since we can potentially work
687 * our way back to the interrupt return only to come right back
688 * here.
690 fecp->fec_r_des_active = 0;
691 #endif
695 /* called from interrupt context */
696 static void
697 fec_enet_mii(struct net_device *dev)
699 struct fec_enet_private *fep;
700 volatile fec_t *ep;
701 mii_list_t *mip;
702 uint mii_reg;
704 fep = netdev_priv(dev);
705 ep = fep->hwp;
706 mii_reg = ep->fec_mii_data;
708 spin_lock(&fep->lock);
710 if ((mip = mii_head) == NULL) {
711 printk("MII and no head!\n");
712 goto unlock;
715 if (mip->mii_func != NULL)
716 (*(mip->mii_func))(mii_reg, dev);
718 mii_head = mip->mii_next;
719 mip->mii_next = mii_free;
720 mii_free = mip;
722 if ((mip = mii_head) != NULL)
723 ep->fec_mii_data = mip->mii_regval;
725 unlock:
726 spin_unlock(&fep->lock);
729 static int
730 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
732 struct fec_enet_private *fep;
733 unsigned long flags;
734 mii_list_t *mip;
735 int retval;
737 /* Add PHY address to register command.
739 fep = netdev_priv(dev);
740 regval |= fep->phy_addr << 23;
742 retval = 0;
744 spin_lock_irqsave(&fep->lock,flags);
746 if ((mip = mii_free) != NULL) {
747 mii_free = mip->mii_next;
748 mip->mii_regval = regval;
749 mip->mii_func = func;
750 mip->mii_next = NULL;
751 if (mii_head) {
752 mii_tail->mii_next = mip;
753 mii_tail = mip;
755 else {
756 mii_head = mii_tail = mip;
757 fep->hwp->fec_mii_data = regval;
760 else {
761 retval = 1;
764 spin_unlock_irqrestore(&fep->lock,flags);
766 return(retval);
769 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
771 int k;
773 if(!c)
774 return;
776 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
777 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
781 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
783 struct fec_enet_private *fep = netdev_priv(dev);
784 volatile uint *s = &(fep->phy_status);
785 uint status;
787 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
789 if (mii_reg & 0x0004)
790 status |= PHY_STAT_LINK;
791 if (mii_reg & 0x0010)
792 status |= PHY_STAT_FAULT;
793 if (mii_reg & 0x0020)
794 status |= PHY_STAT_ANC;
796 *s = status;
799 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
801 struct fec_enet_private *fep = netdev_priv(dev);
802 volatile uint *s = &(fep->phy_status);
803 uint status;
805 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
807 if (mii_reg & 0x1000)
808 status |= PHY_CONF_ANE;
809 if (mii_reg & 0x4000)
810 status |= PHY_CONF_LOOP;
811 *s = status;
814 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
816 struct fec_enet_private *fep = netdev_priv(dev);
817 volatile uint *s = &(fep->phy_status);
818 uint status;
820 status = *s & ~(PHY_CONF_SPMASK);
822 if (mii_reg & 0x0020)
823 status |= PHY_CONF_10HDX;
824 if (mii_reg & 0x0040)
825 status |= PHY_CONF_10FDX;
826 if (mii_reg & 0x0080)
827 status |= PHY_CONF_100HDX;
828 if (mii_reg & 0x00100)
829 status |= PHY_CONF_100FDX;
830 *s = status;
833 /* ------------------------------------------------------------------------- */
834 /* The Level one LXT970 is used by many boards */
836 #define MII_LXT970_MIRROR 16 /* Mirror register */
837 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
838 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
839 #define MII_LXT970_CONFIG 19 /* Configuration Register */
840 #define MII_LXT970_CSR 20 /* Chip Status Register */
842 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
844 struct fec_enet_private *fep = netdev_priv(dev);
845 volatile uint *s = &(fep->phy_status);
846 uint status;
848 status = *s & ~(PHY_STAT_SPMASK);
849 if (mii_reg & 0x0800) {
850 if (mii_reg & 0x1000)
851 status |= PHY_STAT_100FDX;
852 else
853 status |= PHY_STAT_100HDX;
854 } else {
855 if (mii_reg & 0x1000)
856 status |= PHY_STAT_10FDX;
857 else
858 status |= PHY_STAT_10HDX;
860 *s = status;
863 static phy_cmd_t const phy_cmd_lxt970_config[] = {
864 { mk_mii_read(MII_REG_CR), mii_parse_cr },
865 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
866 { mk_mii_end, }
868 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
869 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
870 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
871 { mk_mii_end, }
873 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
874 /* read SR and ISR to acknowledge */
875 { mk_mii_read(MII_REG_SR), mii_parse_sr },
876 { mk_mii_read(MII_LXT970_ISR), NULL },
878 /* find out the current status */
879 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
880 { mk_mii_end, }
882 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
883 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
884 { mk_mii_end, }
886 static phy_info_t const phy_info_lxt970 = {
887 .id = 0x07810000,
888 .name = "LXT970",
889 .config = phy_cmd_lxt970_config,
890 .startup = phy_cmd_lxt970_startup,
891 .ack_int = phy_cmd_lxt970_ack_int,
892 .shutdown = phy_cmd_lxt970_shutdown
895 /* ------------------------------------------------------------------------- */
896 /* The Level one LXT971 is used on some of my custom boards */
898 /* register definitions for the 971 */
900 #define MII_LXT971_PCR 16 /* Port Control Register */
901 #define MII_LXT971_SR2 17 /* Status Register 2 */
902 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
903 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
904 #define MII_LXT971_LCR 20 /* LED Control Register */
905 #define MII_LXT971_TCR 30 /* Transmit Control Register */
908 * I had some nice ideas of running the MDIO faster...
909 * The 971 should support 8MHz and I tried it, but things acted really
910 * weird, so 2.5 MHz ought to be enough for anyone...
913 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
915 struct fec_enet_private *fep = netdev_priv(dev);
916 volatile uint *s = &(fep->phy_status);
917 uint status;
919 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
921 if (mii_reg & 0x0400) {
922 fep->link = 1;
923 status |= PHY_STAT_LINK;
924 } else {
925 fep->link = 0;
927 if (mii_reg & 0x0080)
928 status |= PHY_STAT_ANC;
929 if (mii_reg & 0x4000) {
930 if (mii_reg & 0x0200)
931 status |= PHY_STAT_100FDX;
932 else
933 status |= PHY_STAT_100HDX;
934 } else {
935 if (mii_reg & 0x0200)
936 status |= PHY_STAT_10FDX;
937 else
938 status |= PHY_STAT_10HDX;
940 if (mii_reg & 0x0008)
941 status |= PHY_STAT_FAULT;
943 *s = status;
946 static phy_cmd_t const phy_cmd_lxt971_config[] = {
947 /* limit to 10MBit because my prototype board
948 * doesn't work with 100. */
949 { mk_mii_read(MII_REG_CR), mii_parse_cr },
950 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
951 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
952 { mk_mii_end, }
954 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
955 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
956 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
957 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
958 /* Somehow does the 971 tell me that the link is down
959 * the first read after power-up.
960 * read here to get a valid value in ack_int */
961 { mk_mii_read(MII_REG_SR), mii_parse_sr },
962 { mk_mii_end, }
964 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
965 /* acknowledge the int before reading status ! */
966 { mk_mii_read(MII_LXT971_ISR), NULL },
967 /* find out the current status */
968 { mk_mii_read(MII_REG_SR), mii_parse_sr },
969 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
970 { mk_mii_end, }
972 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
973 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
974 { mk_mii_end, }
976 static phy_info_t const phy_info_lxt971 = {
977 .id = 0x0001378e,
978 .name = "LXT971",
979 .config = phy_cmd_lxt971_config,
980 .startup = phy_cmd_lxt971_startup,
981 .ack_int = phy_cmd_lxt971_ack_int,
982 .shutdown = phy_cmd_lxt971_shutdown
985 /* ------------------------------------------------------------------------- */
986 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
988 /* register definitions */
990 #define MII_QS6612_MCR 17 /* Mode Control Register */
991 #define MII_QS6612_FTR 27 /* Factory Test Register */
992 #define MII_QS6612_MCO 28 /* Misc. Control Register */
993 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
994 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
995 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
997 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
999 struct fec_enet_private *fep = netdev_priv(dev);
1000 volatile uint *s = &(fep->phy_status);
1001 uint status;
1003 status = *s & ~(PHY_STAT_SPMASK);
1005 switch((mii_reg >> 2) & 7) {
1006 case 1: status |= PHY_STAT_10HDX; break;
1007 case 2: status |= PHY_STAT_100HDX; break;
1008 case 5: status |= PHY_STAT_10FDX; break;
1009 case 6: status |= PHY_STAT_100FDX; break;
1012 *s = status;
1015 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1016 /* The PHY powers up isolated on the RPX,
1017 * so send a command to allow operation.
1019 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1021 /* parse cr and anar to get some info */
1022 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1023 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1024 { mk_mii_end, }
1026 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1027 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1028 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1029 { mk_mii_end, }
1031 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1032 /* we need to read ISR, SR and ANER to acknowledge */
1033 { mk_mii_read(MII_QS6612_ISR), NULL },
1034 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1035 { mk_mii_read(MII_REG_ANER), NULL },
1037 /* read pcr to get info */
1038 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1039 { mk_mii_end, }
1041 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1042 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1043 { mk_mii_end, }
1045 static phy_info_t const phy_info_qs6612 = {
1046 .id = 0x00181440,
1047 .name = "QS6612",
1048 .config = phy_cmd_qs6612_config,
1049 .startup = phy_cmd_qs6612_startup,
1050 .ack_int = phy_cmd_qs6612_ack_int,
1051 .shutdown = phy_cmd_qs6612_shutdown
1054 /* ------------------------------------------------------------------------- */
1055 /* AMD AM79C874 phy */
1057 /* register definitions for the 874 */
1059 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1060 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1061 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1062 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1063 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1064 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1065 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1067 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1069 struct fec_enet_private *fep = netdev_priv(dev);
1070 volatile uint *s = &(fep->phy_status);
1071 uint status;
1073 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1075 if (mii_reg & 0x0080)
1076 status |= PHY_STAT_ANC;
1077 if (mii_reg & 0x0400)
1078 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1079 else
1080 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1082 *s = status;
1085 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1086 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1087 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1088 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1089 { mk_mii_end, }
1091 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1092 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1093 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1094 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1095 { mk_mii_end, }
1097 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1098 /* find out the current status */
1099 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1100 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1101 /* we only need to read ISR to acknowledge */
1102 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1103 { mk_mii_end, }
1105 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1106 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1107 { mk_mii_end, }
1109 static phy_info_t const phy_info_am79c874 = {
1110 .id = 0x00022561,
1111 .name = "AM79C874",
1112 .config = phy_cmd_am79c874_config,
1113 .startup = phy_cmd_am79c874_startup,
1114 .ack_int = phy_cmd_am79c874_ack_int,
1115 .shutdown = phy_cmd_am79c874_shutdown
1119 /* ------------------------------------------------------------------------- */
1120 /* Kendin KS8721BL phy */
1122 /* register definitions for the 8721 */
1124 #define MII_KS8721BL_RXERCR 21
1125 #define MII_KS8721BL_ICSR 22
1126 #define MII_KS8721BL_PHYCR 31
1128 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1129 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1130 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1131 { mk_mii_end, }
1133 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1134 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1135 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1136 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1137 { mk_mii_end, }
1139 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1140 /* find out the current status */
1141 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1142 /* we only need to read ISR to acknowledge */
1143 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1144 { mk_mii_end, }
1146 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1147 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1148 { mk_mii_end, }
1150 static phy_info_t const phy_info_ks8721bl = {
1151 .id = 0x00022161,
1152 .name = "KS8721BL",
1153 .config = phy_cmd_ks8721bl_config,
1154 .startup = phy_cmd_ks8721bl_startup,
1155 .ack_int = phy_cmd_ks8721bl_ack_int,
1156 .shutdown = phy_cmd_ks8721bl_shutdown
1159 /* ------------------------------------------------------------------------- */
1160 /* register definitions for the DP83848 */
1162 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1164 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1166 struct fec_enet_private *fep = dev->priv;
1167 volatile uint *s = &(fep->phy_status);
1169 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1171 /* Link up */
1172 if (mii_reg & 0x0001) {
1173 fep->link = 1;
1174 *s |= PHY_STAT_LINK;
1175 } else
1176 fep->link = 0;
1177 /* Status of link */
1178 if (mii_reg & 0x0010) /* Autonegotioation complete */
1179 *s |= PHY_STAT_ANC;
1180 if (mii_reg & 0x0002) { /* 10MBps? */
1181 if (mii_reg & 0x0004) /* Full Duplex? */
1182 *s |= PHY_STAT_10FDX;
1183 else
1184 *s |= PHY_STAT_10HDX;
1185 } else { /* 100 Mbps? */
1186 if (mii_reg & 0x0004) /* Full Duplex? */
1187 *s |= PHY_STAT_100FDX;
1188 else
1189 *s |= PHY_STAT_100HDX;
1191 if (mii_reg & 0x0008)
1192 *s |= PHY_STAT_FAULT;
1195 static phy_info_t phy_info_dp83848= {
1196 0x020005c9,
1197 "DP83848",
1199 (const phy_cmd_t []) { /* config */
1200 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1201 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1202 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1203 { mk_mii_end, }
1205 (const phy_cmd_t []) { /* startup - enable interrupts */
1206 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1207 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1208 { mk_mii_end, }
1210 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1211 { mk_mii_end, }
1213 (const phy_cmd_t []) { /* shutdown */
1214 { mk_mii_end, }
1218 /* ------------------------------------------------------------------------- */
1220 static phy_info_t const * const phy_info[] = {
1221 &phy_info_lxt970,
1222 &phy_info_lxt971,
1223 &phy_info_qs6612,
1224 &phy_info_am79c874,
1225 &phy_info_ks8721bl,
1226 &phy_info_dp83848,
1227 NULL
1230 /* ------------------------------------------------------------------------- */
1231 #if !defined(CONFIG_M532x)
1232 #ifdef CONFIG_RPXCLASSIC
1233 static void
1234 mii_link_interrupt(void *dev_id);
1235 #else
1236 static irqreturn_t
1237 mii_link_interrupt(int irq, void * dev_id);
1238 #endif
1239 #endif
1241 #if defined(CONFIG_M5272)
1244 * Code specific to Coldfire 5272 setup.
1246 static void __inline__ fec_request_intrs(struct net_device *dev)
1248 volatile unsigned long *icrp;
1249 static const struct idesc {
1250 char *name;
1251 unsigned short irq;
1252 irq_handler_t handler;
1253 } *idp, id[] = {
1254 { "fec(RX)", 86, fec_enet_interrupt },
1255 { "fec(TX)", 87, fec_enet_interrupt },
1256 { "fec(OTHER)", 88, fec_enet_interrupt },
1257 { "fec(MII)", 66, mii_link_interrupt },
1258 { NULL },
1261 /* Setup interrupt handlers. */
1262 for (idp = id; idp->name; idp++) {
1263 if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
1264 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1267 /* Unmask interrupt at ColdFire 5272 SIM */
1268 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1269 *icrp = 0x00000ddd;
1270 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1271 *icrp = 0x0d000000;
1274 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1276 volatile fec_t *fecp;
1278 fecp = fep->hwp;
1279 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1280 fecp->fec_x_cntrl = 0x00;
1283 * Set MII speed to 2.5 MHz
1284 * See 5272 manual section 11.5.8: MSCR
1286 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1287 fecp->fec_mii_speed = fep->phy_speed;
1289 fec_restart(dev, 0);
1292 static void __inline__ fec_get_mac(struct net_device *dev)
1294 struct fec_enet_private *fep = netdev_priv(dev);
1295 volatile fec_t *fecp;
1296 unsigned char *iap, tmpaddr[ETH_ALEN];
1298 fecp = fep->hwp;
1300 if (FEC_FLASHMAC) {
1302 * Get MAC address from FLASH.
1303 * If it is all 1's or 0's, use the default.
1305 iap = (unsigned char *)FEC_FLASHMAC;
1306 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1307 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1308 iap = fec_mac_default;
1309 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1310 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1311 iap = fec_mac_default;
1312 } else {
1313 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1314 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1315 iap = &tmpaddr[0];
1318 memcpy(dev->dev_addr, iap, ETH_ALEN);
1320 /* Adjust MAC if using default MAC address */
1321 if (iap == fec_mac_default)
1322 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1325 static void __inline__ fec_enable_phy_intr(void)
1329 static void __inline__ fec_disable_phy_intr(void)
1331 volatile unsigned long *icrp;
1332 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1333 *icrp = 0x08000000;
1336 static void __inline__ fec_phy_ack_intr(void)
1338 volatile unsigned long *icrp;
1339 /* Acknowledge the interrupt */
1340 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1341 *icrp = 0x0d000000;
1344 static void __inline__ fec_localhw_setup(void)
1349 * Do not need to make region uncached on 5272.
1351 static void __inline__ fec_uncache(unsigned long addr)
1355 /* ------------------------------------------------------------------------- */
1357 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1360 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1361 * the 5270/5271/5274/5275 and 5280/5282 setups.
1363 static void __inline__ fec_request_intrs(struct net_device *dev)
1365 struct fec_enet_private *fep;
1366 int b;
1367 static const struct idesc {
1368 char *name;
1369 unsigned short irq;
1370 } *idp, id[] = {
1371 { "fec(TXF)", 23 },
1372 { "fec(TXB)", 24 },
1373 { "fec(TXFIFO)", 25 },
1374 { "fec(TXCR)", 26 },
1375 { "fec(RXF)", 27 },
1376 { "fec(RXB)", 28 },
1377 { "fec(MII)", 29 },
1378 { "fec(LC)", 30 },
1379 { "fec(HBERR)", 31 },
1380 { "fec(GRA)", 32 },
1381 { "fec(EBERR)", 33 },
1382 { "fec(BABT)", 34 },
1383 { "fec(BABR)", 35 },
1384 { NULL },
1387 fep = netdev_priv(dev);
1388 b = (fep->index) ? 128 : 64;
1390 /* Setup interrupt handlers. */
1391 for (idp = id; idp->name; idp++) {
1392 if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
1393 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1396 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1398 volatile unsigned char *icrp;
1399 volatile unsigned long *imrp;
1400 int i, ilip;
1402 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1403 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1404 MCFINTC_ICR0);
1405 for (i = 23, ilip = 0x28; (i < 36); i++)
1406 icrp[i] = ilip--;
1408 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1409 MCFINTC_IMRH);
1410 *imrp &= ~0x0000000f;
1411 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1412 MCFINTC_IMRL);
1413 *imrp &= ~0xff800001;
1416 #if defined(CONFIG_M528x)
1417 /* Set up gpio outputs for MII lines */
1419 volatile u16 *gpio_paspar;
1420 volatile u8 *gpio_pehlpar;
1422 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1423 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1424 *gpio_paspar |= 0x0f00;
1425 *gpio_pehlpar = 0xc0;
1427 #endif
1429 #if defined(CONFIG_M527x)
1430 /* Set up gpio outputs for MII lines */
1432 volatile u8 *gpio_par_fec;
1433 volatile u16 *gpio_par_feci2c;
1435 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1436 /* Set up gpio outputs for FEC0 MII lines */
1437 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1439 *gpio_par_feci2c |= 0x0f00;
1440 *gpio_par_fec |= 0xc0;
1442 #if defined(CONFIG_FEC2)
1443 /* Set up gpio outputs for FEC1 MII lines */
1444 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1446 *gpio_par_feci2c |= 0x00a0;
1447 *gpio_par_fec |= 0xc0;
1448 #endif /* CONFIG_FEC2 */
1450 #endif /* CONFIG_M527x */
1453 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1455 volatile fec_t *fecp;
1457 fecp = fep->hwp;
1458 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1459 fecp->fec_x_cntrl = 0x00;
1462 * Set MII speed to 2.5 MHz
1463 * See 5282 manual section 17.5.4.7: MSCR
1465 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1466 fecp->fec_mii_speed = fep->phy_speed;
1468 fec_restart(dev, 0);
1471 static void __inline__ fec_get_mac(struct net_device *dev)
1473 struct fec_enet_private *fep = netdev_priv(dev);
1474 volatile fec_t *fecp;
1475 unsigned char *iap, tmpaddr[ETH_ALEN];
1477 fecp = fep->hwp;
1479 if (FEC_FLASHMAC) {
1481 * Get MAC address from FLASH.
1482 * If it is all 1's or 0's, use the default.
1484 iap = FEC_FLASHMAC;
1485 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1486 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1487 iap = fec_mac_default;
1488 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1489 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1490 iap = fec_mac_default;
1491 } else {
1492 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1493 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1494 iap = &tmpaddr[0];
1497 memcpy(dev->dev_addr, iap, ETH_ALEN);
1499 /* Adjust MAC if using default MAC address */
1500 if (iap == fec_mac_default)
1501 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1504 static void __inline__ fec_enable_phy_intr(void)
1508 static void __inline__ fec_disable_phy_intr(void)
1512 static void __inline__ fec_phy_ack_intr(void)
1516 static void __inline__ fec_localhw_setup(void)
1521 * Do not need to make region uncached on 5272.
1523 static void __inline__ fec_uncache(unsigned long addr)
1527 /* ------------------------------------------------------------------------- */
1529 #elif defined(CONFIG_M520x)
1532 * Code specific to Coldfire 520x
1534 static void __inline__ fec_request_intrs(struct net_device *dev)
1536 struct fec_enet_private *fep;
1537 int b;
1538 static const struct idesc {
1539 char *name;
1540 unsigned short irq;
1541 } *idp, id[] = {
1542 { "fec(TXF)", 23 },
1543 { "fec(TXB)", 24 },
1544 { "fec(TXFIFO)", 25 },
1545 { "fec(TXCR)", 26 },
1546 { "fec(RXF)", 27 },
1547 { "fec(RXB)", 28 },
1548 { "fec(MII)", 29 },
1549 { "fec(LC)", 30 },
1550 { "fec(HBERR)", 31 },
1551 { "fec(GRA)", 32 },
1552 { "fec(EBERR)", 33 },
1553 { "fec(BABT)", 34 },
1554 { "fec(BABR)", 35 },
1555 { NULL },
1558 fep = netdev_priv(dev);
1559 b = 64 + 13;
1561 /* Setup interrupt handlers. */
1562 for (idp = id; idp->name; idp++) {
1563 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1564 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1567 /* Unmask interrupts at ColdFire interrupt controller */
1569 volatile unsigned char *icrp;
1570 volatile unsigned long *imrp;
1572 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1573 MCFINTC_ICR0);
1574 for (b = 36; (b < 49); b++)
1575 icrp[b] = 0x04;
1576 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1577 MCFINTC_IMRH);
1578 *imrp &= ~0x0001FFF0;
1580 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1581 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1584 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1586 volatile fec_t *fecp;
1588 fecp = fep->hwp;
1589 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1590 fecp->fec_x_cntrl = 0x00;
1593 * Set MII speed to 2.5 MHz
1594 * See 5282 manual section 17.5.4.7: MSCR
1596 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1597 fecp->fec_mii_speed = fep->phy_speed;
1599 fec_restart(dev, 0);
1602 static void __inline__ fec_get_mac(struct net_device *dev)
1604 struct fec_enet_private *fep = netdev_priv(dev);
1605 volatile fec_t *fecp;
1606 unsigned char *iap, tmpaddr[ETH_ALEN];
1608 fecp = fep->hwp;
1610 if (FEC_FLASHMAC) {
1612 * Get MAC address from FLASH.
1613 * If it is all 1's or 0's, use the default.
1615 iap = FEC_FLASHMAC;
1616 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1617 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1618 iap = fec_mac_default;
1619 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1620 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1621 iap = fec_mac_default;
1622 } else {
1623 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1624 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1625 iap = &tmpaddr[0];
1628 memcpy(dev->dev_addr, iap, ETH_ALEN);
1630 /* Adjust MAC if using default MAC address */
1631 if (iap == fec_mac_default)
1632 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1635 static void __inline__ fec_enable_phy_intr(void)
1639 static void __inline__ fec_disable_phy_intr(void)
1643 static void __inline__ fec_phy_ack_intr(void)
1647 static void __inline__ fec_localhw_setup(void)
1651 static void __inline__ fec_uncache(unsigned long addr)
1655 /* ------------------------------------------------------------------------- */
1657 #elif defined(CONFIG_M532x)
1659 * Code specific for M532x
1661 static void __inline__ fec_request_intrs(struct net_device *dev)
1663 struct fec_enet_private *fep;
1664 int b;
1665 static const struct idesc {
1666 char *name;
1667 unsigned short irq;
1668 } *idp, id[] = {
1669 { "fec(TXF)", 36 },
1670 { "fec(TXB)", 37 },
1671 { "fec(TXFIFO)", 38 },
1672 { "fec(TXCR)", 39 },
1673 { "fec(RXF)", 40 },
1674 { "fec(RXB)", 41 },
1675 { "fec(MII)", 42 },
1676 { "fec(LC)", 43 },
1677 { "fec(HBERR)", 44 },
1678 { "fec(GRA)", 45 },
1679 { "fec(EBERR)", 46 },
1680 { "fec(BABT)", 47 },
1681 { "fec(BABR)", 48 },
1682 { NULL },
1685 fep = netdev_priv(dev);
1686 b = (fep->index) ? 128 : 64;
1688 /* Setup interrupt handlers. */
1689 for (idp = id; idp->name; idp++) {
1690 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1691 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1692 idp->name, b+idp->irq);
1695 /* Unmask interrupts */
1696 MCF_INTC0_ICR36 = 0x2;
1697 MCF_INTC0_ICR37 = 0x2;
1698 MCF_INTC0_ICR38 = 0x2;
1699 MCF_INTC0_ICR39 = 0x2;
1700 MCF_INTC0_ICR40 = 0x2;
1701 MCF_INTC0_ICR41 = 0x2;
1702 MCF_INTC0_ICR42 = 0x2;
1703 MCF_INTC0_ICR43 = 0x2;
1704 MCF_INTC0_ICR44 = 0x2;
1705 MCF_INTC0_ICR45 = 0x2;
1706 MCF_INTC0_ICR46 = 0x2;
1707 MCF_INTC0_ICR47 = 0x2;
1708 MCF_INTC0_ICR48 = 0x2;
1710 MCF_INTC0_IMRH &= ~(
1711 MCF_INTC_IMRH_INT_MASK36 |
1712 MCF_INTC_IMRH_INT_MASK37 |
1713 MCF_INTC_IMRH_INT_MASK38 |
1714 MCF_INTC_IMRH_INT_MASK39 |
1715 MCF_INTC_IMRH_INT_MASK40 |
1716 MCF_INTC_IMRH_INT_MASK41 |
1717 MCF_INTC_IMRH_INT_MASK42 |
1718 MCF_INTC_IMRH_INT_MASK43 |
1719 MCF_INTC_IMRH_INT_MASK44 |
1720 MCF_INTC_IMRH_INT_MASK45 |
1721 MCF_INTC_IMRH_INT_MASK46 |
1722 MCF_INTC_IMRH_INT_MASK47 |
1723 MCF_INTC_IMRH_INT_MASK48 );
1725 /* Set up gpio outputs for MII lines */
1726 MCF_GPIO_PAR_FECI2C |= (0 |
1727 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1728 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1729 MCF_GPIO_PAR_FEC = (0 |
1730 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1731 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1734 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1736 volatile fec_t *fecp;
1738 fecp = fep->hwp;
1739 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1740 fecp->fec_x_cntrl = 0x00;
1743 * Set MII speed to 2.5 MHz
1745 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1746 fecp->fec_mii_speed = fep->phy_speed;
1748 fec_restart(dev, 0);
1751 static void __inline__ fec_get_mac(struct net_device *dev)
1753 struct fec_enet_private *fep = netdev_priv(dev);
1754 volatile fec_t *fecp;
1755 unsigned char *iap, tmpaddr[ETH_ALEN];
1757 fecp = fep->hwp;
1759 if (FEC_FLASHMAC) {
1761 * Get MAC address from FLASH.
1762 * If it is all 1's or 0's, use the default.
1764 iap = FEC_FLASHMAC;
1765 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1766 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1767 iap = fec_mac_default;
1768 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1769 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1770 iap = fec_mac_default;
1771 } else {
1772 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1773 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1774 iap = &tmpaddr[0];
1777 memcpy(dev->dev_addr, iap, ETH_ALEN);
1779 /* Adjust MAC if using default MAC address */
1780 if (iap == fec_mac_default)
1781 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1784 static void __inline__ fec_enable_phy_intr(void)
1788 static void __inline__ fec_disable_phy_intr(void)
1792 static void __inline__ fec_phy_ack_intr(void)
1796 static void __inline__ fec_localhw_setup(void)
1801 * Do not need to make region uncached on 532x.
1803 static void __inline__ fec_uncache(unsigned long addr)
1807 /* ------------------------------------------------------------------------- */
1810 #else
1813 * Code specific to the MPC860T setup.
1815 static void __inline__ fec_request_intrs(struct net_device *dev)
1817 volatile immap_t *immap;
1819 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1821 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1822 panic("Could not allocate FEC IRQ!");
1824 #ifdef CONFIG_RPXCLASSIC
1825 /* Make Port C, bit 15 an input that causes interrupts.
1827 immap->im_ioport.iop_pcpar &= ~0x0001;
1828 immap->im_ioport.iop_pcdir &= ~0x0001;
1829 immap->im_ioport.iop_pcso &= ~0x0001;
1830 immap->im_ioport.iop_pcint |= 0x0001;
1831 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1833 /* Make LEDS reflect Link status.
1835 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1836 #endif
1837 #ifdef CONFIG_FADS
1838 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1839 panic("Could not allocate MII IRQ!");
1840 #endif
1843 static void __inline__ fec_get_mac(struct net_device *dev)
1845 bd_t *bd;
1847 bd = (bd_t *)__res;
1848 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1850 #ifdef CONFIG_RPXCLASSIC
1851 /* The Embedded Planet boards have only one MAC address in
1852 * the EEPROM, but can have two Ethernet ports. For the
1853 * FEC port, we create another address by setting one of
1854 * the address bits above something that would have (up to
1855 * now) been allocated.
1857 dev->dev_adrd[3] |= 0x80;
1858 #endif
1861 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1863 extern uint _get_IMMR(void);
1864 volatile immap_t *immap;
1865 volatile fec_t *fecp;
1867 fecp = fep->hwp;
1868 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1870 /* Configure all of port D for MII.
1872 immap->im_ioport.iop_pdpar = 0x1fff;
1874 /* Bits moved from Rev. D onward.
1876 if ((_get_IMMR() & 0xffff) < 0x0501)
1877 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1878 else
1879 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1881 /* Set MII speed to 2.5 MHz
1883 fecp->fec_mii_speed = fep->phy_speed =
1884 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1887 static void __inline__ fec_enable_phy_intr(void)
1889 volatile fec_t *fecp;
1891 fecp = fep->hwp;
1893 /* Enable MII command finished interrupt
1895 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1898 static void __inline__ fec_disable_phy_intr(void)
1902 static void __inline__ fec_phy_ack_intr(void)
1906 static void __inline__ fec_localhw_setup(void)
1908 volatile fec_t *fecp;
1910 fecp = fep->hwp;
1911 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1912 /* Enable big endian and don't care about SDMA FC.
1914 fecp->fec_fun_code = 0x78000000;
1917 static void __inline__ fec_uncache(unsigned long addr)
1919 pte_t *pte;
1920 pte = va_to_pte(mem_addr);
1921 pte_val(*pte) |= _PAGE_NO_CACHE;
1922 flush_tlb_page(init_mm.mmap, mem_addr);
1925 #endif
1927 /* ------------------------------------------------------------------------- */
1929 static void mii_display_status(struct net_device *dev)
1931 struct fec_enet_private *fep = netdev_priv(dev);
1932 volatile uint *s = &(fep->phy_status);
1934 if (!fep->link && !fep->old_link) {
1935 /* Link is still down - don't print anything */
1936 return;
1939 printk("%s: status: ", dev->name);
1941 if (!fep->link) {
1942 printk("link down");
1943 } else {
1944 printk("link up");
1946 switch(*s & PHY_STAT_SPMASK) {
1947 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1948 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1949 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1950 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1951 default:
1952 printk(", Unknown speed/duplex");
1955 if (*s & PHY_STAT_ANC)
1956 printk(", auto-negotiation complete");
1959 if (*s & PHY_STAT_FAULT)
1960 printk(", remote fault");
1962 printk(".\n");
1965 static void mii_display_config(struct work_struct *work)
1967 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1968 struct net_device *dev = fep->netdev;
1969 uint status = fep->phy_status;
1972 ** When we get here, phy_task is already removed from
1973 ** the workqueue. It is thus safe to allow to reuse it.
1975 fep->mii_phy_task_queued = 0;
1976 printk("%s: config: auto-negotiation ", dev->name);
1978 if (status & PHY_CONF_ANE)
1979 printk("on");
1980 else
1981 printk("off");
1983 if (status & PHY_CONF_100FDX)
1984 printk(", 100FDX");
1985 if (status & PHY_CONF_100HDX)
1986 printk(", 100HDX");
1987 if (status & PHY_CONF_10FDX)
1988 printk(", 10FDX");
1989 if (status & PHY_CONF_10HDX)
1990 printk(", 10HDX");
1991 if (!(status & PHY_CONF_SPMASK))
1992 printk(", No speed/duplex selected?");
1994 if (status & PHY_CONF_LOOP)
1995 printk(", loopback enabled");
1997 printk(".\n");
1999 fep->sequence_done = 1;
2002 static void mii_relink(struct work_struct *work)
2004 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
2005 struct net_device *dev = fep->netdev;
2006 int duplex;
2009 ** When we get here, phy_task is already removed from
2010 ** the workqueue. It is thus safe to allow to reuse it.
2012 fep->mii_phy_task_queued = 0;
2013 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
2014 mii_display_status(dev);
2015 fep->old_link = fep->link;
2017 if (fep->link) {
2018 duplex = 0;
2019 if (fep->phy_status
2020 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
2021 duplex = 1;
2022 fec_restart(dev, duplex);
2024 else
2025 fec_stop(dev);
2027 #if 0
2028 enable_irq(fep->mii_irq);
2029 #endif
2033 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
2034 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2036 struct fec_enet_private *fep = netdev_priv(dev);
2039 ** We cannot queue phy_task twice in the workqueue. It
2040 ** would cause an endless loop in the workqueue.
2041 ** Fortunately, if the last mii_relink entry has not yet been
2042 ** executed now, it will do the job for the current interrupt,
2043 ** which is just what we want.
2045 if (fep->mii_phy_task_queued)
2046 return;
2048 fep->mii_phy_task_queued = 1;
2049 INIT_WORK(&fep->phy_task, mii_relink);
2050 schedule_work(&fep->phy_task);
2053 /* mii_queue_config is called in interrupt context from fec_enet_mii */
2054 static void mii_queue_config(uint mii_reg, struct net_device *dev)
2056 struct fec_enet_private *fep = netdev_priv(dev);
2058 if (fep->mii_phy_task_queued)
2059 return;
2061 fep->mii_phy_task_queued = 1;
2062 INIT_WORK(&fep->phy_task, mii_display_config);
2063 schedule_work(&fep->phy_task);
2066 phy_cmd_t const phy_cmd_relink[] = {
2067 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2068 { mk_mii_end, }
2070 phy_cmd_t const phy_cmd_config[] = {
2071 { mk_mii_read(MII_REG_CR), mii_queue_config },
2072 { mk_mii_end, }
2075 /* Read remainder of PHY ID.
2077 static void
2078 mii_discover_phy3(uint mii_reg, struct net_device *dev)
2080 struct fec_enet_private *fep;
2081 int i;
2083 fep = netdev_priv(dev);
2084 fep->phy_id |= (mii_reg & 0xffff);
2085 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2087 for(i = 0; phy_info[i]; i++) {
2088 if(phy_info[i]->id == (fep->phy_id >> 4))
2089 break;
2092 if (phy_info[i])
2093 printk(" -- %s\n", phy_info[i]->name);
2094 else
2095 printk(" -- unknown PHY!\n");
2097 fep->phy = phy_info[i];
2098 fep->phy_id_done = 1;
2101 /* Scan all of the MII PHY addresses looking for someone to respond
2102 * with a valid ID. This usually happens quickly.
2104 static void
2105 mii_discover_phy(uint mii_reg, struct net_device *dev)
2107 struct fec_enet_private *fep;
2108 volatile fec_t *fecp;
2109 uint phytype;
2111 fep = netdev_priv(dev);
2112 fecp = fep->hwp;
2114 if (fep->phy_addr < 32) {
2115 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
2117 /* Got first part of ID, now get remainder.
2119 fep->phy_id = phytype << 16;
2120 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2121 mii_discover_phy3);
2123 else {
2124 fep->phy_addr++;
2125 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2126 mii_discover_phy);
2128 } else {
2129 printk("FEC: No PHY device found.\n");
2130 /* Disable external MII interface */
2131 fecp->fec_mii_speed = fep->phy_speed = 0;
2132 fec_disable_phy_intr();
2136 /* This interrupt occurs when the PHY detects a link change.
2138 #ifdef CONFIG_RPXCLASSIC
2139 static void
2140 mii_link_interrupt(void *dev_id)
2141 #else
2142 static irqreturn_t
2143 mii_link_interrupt(int irq, void * dev_id)
2144 #endif
2146 struct net_device *dev = dev_id;
2147 struct fec_enet_private *fep = netdev_priv(dev);
2149 fec_phy_ack_intr();
2151 #if 0
2152 disable_irq(fep->mii_irq); /* disable now, enable later */
2153 #endif
2155 mii_do_cmd(dev, fep->phy->ack_int);
2156 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2158 return IRQ_HANDLED;
2161 static int
2162 fec_enet_open(struct net_device *dev)
2164 struct fec_enet_private *fep = netdev_priv(dev);
2166 /* I should reset the ring buffers here, but I don't yet know
2167 * a simple way to do that.
2169 fec_set_mac_address(dev);
2171 fep->sequence_done = 0;
2172 fep->link = 0;
2174 if (fep->phy) {
2175 mii_do_cmd(dev, fep->phy->ack_int);
2176 mii_do_cmd(dev, fep->phy->config);
2177 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2179 /* Poll until the PHY tells us its configuration
2180 * (not link state).
2181 * Request is initiated by mii_do_cmd above, but answer
2182 * comes by interrupt.
2183 * This should take about 25 usec per register at 2.5 MHz,
2184 * and we read approximately 5 registers.
2186 while(!fep->sequence_done)
2187 schedule();
2189 mii_do_cmd(dev, fep->phy->startup);
2191 /* Set the initial link state to true. A lot of hardware
2192 * based on this device does not implement a PHY interrupt,
2193 * so we are never notified of link change.
2195 fep->link = 1;
2196 } else {
2197 fep->link = 1; /* lets just try it and see */
2198 /* no phy, go full duplex, it's most likely a hub chip */
2199 fec_restart(dev, 1);
2202 netif_start_queue(dev);
2203 fep->opened = 1;
2204 return 0; /* Success */
2207 static int
2208 fec_enet_close(struct net_device *dev)
2210 struct fec_enet_private *fep = netdev_priv(dev);
2212 /* Don't know what to do yet.
2214 fep->opened = 0;
2215 netif_stop_queue(dev);
2216 fec_stop(dev);
2218 return 0;
2221 /* Set or clear the multicast filter for this adaptor.
2222 * Skeleton taken from sunlance driver.
2223 * The CPM Ethernet implementation allows Multicast as well as individual
2224 * MAC address filtering. Some of the drivers check to make sure it is
2225 * a group multicast address, and discard those that are not. I guess I
2226 * will do the same for now, but just remove the test if you want
2227 * individual filtering as well (do the upper net layers want or support
2228 * this kind of feature?).
2231 #define HASH_BITS 6 /* #bits in hash */
2232 #define CRC32_POLY 0xEDB88320
2234 static void set_multicast_list(struct net_device *dev)
2236 struct fec_enet_private *fep;
2237 volatile fec_t *ep;
2238 struct dev_mc_list *dmi;
2239 unsigned int i, j, bit, data, crc;
2240 unsigned char hash;
2242 fep = netdev_priv(dev);
2243 ep = fep->hwp;
2245 if (dev->flags&IFF_PROMISC) {
2246 ep->fec_r_cntrl |= 0x0008;
2247 } else {
2249 ep->fec_r_cntrl &= ~0x0008;
2251 if (dev->flags & IFF_ALLMULTI) {
2252 /* Catch all multicast addresses, so set the
2253 * filter to all 1's.
2255 ep->fec_hash_table_high = 0xffffffff;
2256 ep->fec_hash_table_low = 0xffffffff;
2257 } else {
2258 /* Clear filter and add the addresses in hash register.
2260 ep->fec_hash_table_high = 0;
2261 ep->fec_hash_table_low = 0;
2263 dmi = dev->mc_list;
2265 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2267 /* Only support group multicast for now.
2269 if (!(dmi->dmi_addr[0] & 1))
2270 continue;
2272 /* calculate crc32 value of mac address
2274 crc = 0xffffffff;
2276 for (i = 0; i < dmi->dmi_addrlen; i++)
2278 data = dmi->dmi_addr[i];
2279 for (bit = 0; bit < 8; bit++, data >>= 1)
2281 crc = (crc >> 1) ^
2282 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2286 /* only upper 6 bits (HASH_BITS) are used
2287 which point to specific bit in he hash registers
2289 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2291 if (hash > 31)
2292 ep->fec_hash_table_high |= 1 << (hash - 32);
2293 else
2294 ep->fec_hash_table_low |= 1 << hash;
2300 /* Set a MAC change in hardware.
2302 static void
2303 fec_set_mac_address(struct net_device *dev)
2305 volatile fec_t *fecp;
2307 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2309 /* Set station address. */
2310 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2311 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2312 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2313 (dev->dev_addr[4] << 24);
2317 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2320 * XXX: We need to clean up on failure exits here.
2322 int __init fec_enet_init(struct net_device *dev)
2324 struct fec_enet_private *fep = netdev_priv(dev);
2325 unsigned long mem_addr;
2326 volatile cbd_t *bdp;
2327 cbd_t *cbd_base;
2328 volatile fec_t *fecp;
2329 int i, j;
2330 static int index = 0;
2332 /* Only allow us to be probed once. */
2333 if (index >= FEC_MAX_PORTS)
2334 return -ENXIO;
2336 /* Allocate memory for buffer descriptors.
2338 mem_addr = __get_free_page(GFP_KERNEL);
2339 if (mem_addr == 0) {
2340 printk("FEC: allocate descriptor memory failed?\n");
2341 return -ENOMEM;
2344 /* Create an Ethernet device instance.
2346 fecp = (volatile fec_t *) fec_hw[index];
2348 fep->index = index;
2349 fep->hwp = fecp;
2350 fep->netdev = dev;
2352 /* Whack a reset. We should wait for this.
2354 fecp->fec_ecntrl = 1;
2355 udelay(10);
2357 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2358 * this needs some work to get unique addresses.
2360 * This is our default MAC address unless the user changes
2361 * it via eth_mac_addr (our dev->set_mac_addr handler).
2363 fec_get_mac(dev);
2365 cbd_base = (cbd_t *)mem_addr;
2366 /* XXX: missing check for allocation failure */
2368 fec_uncache(mem_addr);
2370 /* Set receive and transmit descriptor base.
2372 fep->rx_bd_base = cbd_base;
2373 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2375 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2376 fep->cur_rx = fep->rx_bd_base;
2378 fep->skb_cur = fep->skb_dirty = 0;
2380 /* Initialize the receive buffer descriptors.
2382 bdp = fep->rx_bd_base;
2383 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2385 /* Allocate a page.
2387 mem_addr = __get_free_page(GFP_KERNEL);
2388 /* XXX: missing check for allocation failure */
2390 fec_uncache(mem_addr);
2392 /* Initialize the BD for every fragment in the page.
2394 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2395 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2396 bdp->cbd_bufaddr = __pa(mem_addr);
2397 mem_addr += FEC_ENET_RX_FRSIZE;
2398 bdp++;
2402 /* Set the last buffer to wrap.
2404 bdp--;
2405 bdp->cbd_sc |= BD_SC_WRAP;
2407 /* ...and the same for transmmit.
2409 bdp = fep->tx_bd_base;
2410 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2411 if (j >= FEC_ENET_TX_FRPPG) {
2412 mem_addr = __get_free_page(GFP_KERNEL);
2413 j = 1;
2414 } else {
2415 mem_addr += FEC_ENET_TX_FRSIZE;
2416 j++;
2418 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2420 /* Initialize the BD for every fragment in the page.
2422 bdp->cbd_sc = 0;
2423 bdp->cbd_bufaddr = 0;
2424 bdp++;
2427 /* Set the last buffer to wrap.
2429 bdp--;
2430 bdp->cbd_sc |= BD_SC_WRAP;
2432 /* Set receive and transmit descriptor base.
2434 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2435 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2437 /* Install our interrupt handlers. This varies depending on
2438 * the architecture.
2440 fec_request_intrs(dev);
2442 fecp->fec_hash_table_high = 0;
2443 fecp->fec_hash_table_low = 0;
2444 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2445 fecp->fec_ecntrl = 2;
2446 fecp->fec_r_des_active = 0;
2448 dev->base_addr = (unsigned long)fecp;
2450 /* The FEC Ethernet specific entries in the device structure. */
2451 dev->open = fec_enet_open;
2452 dev->hard_start_xmit = fec_enet_start_xmit;
2453 dev->tx_timeout = fec_timeout;
2454 dev->watchdog_timeo = TX_TIMEOUT;
2455 dev->stop = fec_enet_close;
2456 dev->set_multicast_list = set_multicast_list;
2458 for (i=0; i<NMII-1; i++)
2459 mii_cmds[i].mii_next = &mii_cmds[i+1];
2460 mii_free = mii_cmds;
2462 /* setup MII interface */
2463 fec_set_mii(dev, fep);
2465 /* Clear and enable interrupts */
2466 fecp->fec_ievent = 0xffc00000;
2467 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2468 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2470 /* Queue up command to detect the PHY and initialize the
2471 * remainder of the interface.
2473 fep->phy_id_done = 0;
2474 fep->phy_addr = 0;
2475 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2477 index++;
2478 return 0;
2481 /* This function is called to start or restart the FEC during a link
2482 * change. This only happens when switching between half and full
2483 * duplex.
2485 static void
2486 fec_restart(struct net_device *dev, int duplex)
2488 struct fec_enet_private *fep;
2489 volatile cbd_t *bdp;
2490 volatile fec_t *fecp;
2491 int i;
2493 fep = netdev_priv(dev);
2494 fecp = fep->hwp;
2496 /* Whack a reset. We should wait for this.
2498 fecp->fec_ecntrl = 1;
2499 udelay(10);
2501 /* Clear any outstanding interrupt.
2503 fecp->fec_ievent = 0xffc00000;
2504 fec_enable_phy_intr();
2506 /* Set station address.
2508 fec_set_mac_address(dev);
2510 /* Reset all multicast.
2512 fecp->fec_hash_table_high = 0;
2513 fecp->fec_hash_table_low = 0;
2515 /* Set maximum receive buffer size.
2517 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2519 fec_localhw_setup();
2521 /* Set receive and transmit descriptor base.
2523 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2524 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2526 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2527 fep->cur_rx = fep->rx_bd_base;
2529 /* Reset SKB transmit buffers.
2531 fep->skb_cur = fep->skb_dirty = 0;
2532 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2533 if (fep->tx_skbuff[i] != NULL) {
2534 dev_kfree_skb_any(fep->tx_skbuff[i]);
2535 fep->tx_skbuff[i] = NULL;
2539 /* Initialize the receive buffer descriptors.
2541 bdp = fep->rx_bd_base;
2542 for (i=0; i<RX_RING_SIZE; i++) {
2544 /* Initialize the BD for every fragment in the page.
2546 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2547 bdp++;
2550 /* Set the last buffer to wrap.
2552 bdp--;
2553 bdp->cbd_sc |= BD_SC_WRAP;
2555 /* ...and the same for transmmit.
2557 bdp = fep->tx_bd_base;
2558 for (i=0; i<TX_RING_SIZE; i++) {
2560 /* Initialize the BD for every fragment in the page.
2562 bdp->cbd_sc = 0;
2563 bdp->cbd_bufaddr = 0;
2564 bdp++;
2567 /* Set the last buffer to wrap.
2569 bdp--;
2570 bdp->cbd_sc |= BD_SC_WRAP;
2572 /* Enable MII mode.
2574 if (duplex) {
2575 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2576 fecp->fec_x_cntrl = 0x04; /* FD enable */
2578 else {
2579 /* MII enable|No Rcv on Xmit */
2580 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2581 fecp->fec_x_cntrl = 0x00;
2583 fep->full_duplex = duplex;
2585 /* Set MII speed.
2587 fecp->fec_mii_speed = fep->phy_speed;
2589 /* And last, enable the transmit and receive processing.
2591 fecp->fec_ecntrl = 2;
2592 fecp->fec_r_des_active = 0;
2594 /* Enable interrupts we wish to service.
2596 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2597 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2600 static void
2601 fec_stop(struct net_device *dev)
2603 volatile fec_t *fecp;
2604 struct fec_enet_private *fep;
2606 fep = netdev_priv(dev);
2607 fecp = fep->hwp;
2610 ** We cannot expect a graceful transmit stop without link !!!
2612 if (fep->link)
2614 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2615 udelay(10);
2616 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2617 printk("fec_stop : Graceful transmit stop did not complete !\n");
2620 /* Whack a reset. We should wait for this.
2622 fecp->fec_ecntrl = 1;
2623 udelay(10);
2625 /* Clear outstanding MII command interrupts.
2627 fecp->fec_ievent = FEC_ENET_MII;
2628 fec_enable_phy_intr();
2630 fecp->fec_imask = FEC_ENET_MII;
2631 fecp->fec_mii_speed = fep->phy_speed;
2634 static int __init fec_enet_module_init(void)
2636 struct net_device *dev;
2637 int i, j, err;
2638 DECLARE_MAC_BUF(mac);
2640 printk("FEC ENET Version 0.2\n");
2642 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2643 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2644 if (!dev)
2645 return -ENOMEM;
2646 err = fec_enet_init(dev);
2647 if (err) {
2648 free_netdev(dev);
2649 continue;
2651 if (register_netdev(dev) != 0) {
2652 /* XXX: missing cleanup here */
2653 free_netdev(dev);
2654 return -EIO;
2657 printk("%s: ethernet %s\n",
2658 dev->name, print_mac(mac, dev->dev_addr));
2660 return 0;
2663 module_init(fec_enet_module_init);
2665 MODULE_LICENSE("GPL");