1 #include <linux/init.h>
2 #include <linux/bitops.h>
6 #include <asm/processor.h>
10 # include <asm/numa_64.h>
11 # include <asm/mmconfig.h>
12 # include <asm/cacheflush.h>
15 #include <mach_apic.h>
20 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
21 * misexecution of code under Linux. Owners of such processors should
22 * contact AMD for precise details and a CPU swap.
24 * See http://www.multimania.com/poulot/k6bug.html
25 * http://www.amd.com/K6/k6docs/revgd.html
27 * The following test is erm.. interesting. AMD neglected to up
28 * the chip setting when fixing the bug but they also tweaked some
29 * performance at the same time..
32 extern void vide(void);
33 __asm__(".align 4\nvide: ret");
35 static void __cpuinit
init_amd_k5(struct cpuinfo_x86
*c
)
38 * General Systems BIOSen alias the cpu frequency registers
39 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
40 * drivers subsequently pokes it, and changes the CPU speed.
41 * Workaround : Remove the unneeded alias.
43 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
44 #define CBAR_ENB (0x80000000)
45 #define CBAR_KEY (0X000000CB)
46 if (c
->x86_model
== 9 || c
->x86_model
== 10) {
47 if (inl (CBAR
) & CBAR_ENB
)
48 outl (0 | CBAR_KEY
, CBAR
);
53 static void __cpuinit
init_amd_k6(struct cpuinfo_x86
*c
)
56 int mbytes
= num_physpages
>> (20-PAGE_SHIFT
);
58 if (c
->x86_model
< 6) {
59 /* Based on AMD doc 20734R - June 2000 */
60 if (c
->x86_model
== 0) {
61 clear_cpu_cap(c
, X86_FEATURE_APIC
);
62 set_cpu_cap(c
, X86_FEATURE_PGE
);
67 if (c
->x86_model
== 6 && c
->x86_mask
== 1) {
68 const int K6_BUG_LOOP
= 1000000;
73 printk(KERN_INFO
"AMD K6 stepping B detected - ");
76 * It looks like AMD fixed the 2.6.2 bug and improved indirect
77 * calls at the same time.
88 if (d
> 20*K6_BUG_LOOP
)
89 printk("system stability may be impaired when more than 32 MB are used.\n");
91 printk("probably OK (after B9730xxxx).\n");
92 printk(KERN_INFO
"Please see http://membres.lycos.fr/poulot/k6bug.html\n");
95 /* K6 with old style WHCR */
96 if (c
->x86_model
< 8 ||
97 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
98 /* We can only write allocate on the low 508Mb */
102 rdmsr(MSR_K6_WHCR
, l
, h
);
103 if ((l
&0x0000FFFF) == 0) {
105 l
= (1<<0)|((mbytes
/4)<<1);
106 local_irq_save(flags
);
108 wrmsr(MSR_K6_WHCR
, l
, h
);
109 local_irq_restore(flags
);
110 printk(KERN_INFO
"Enabling old style K6 write allocation for %d Mb\n",
116 if ((c
->x86_model
== 8 && c
->x86_mask
> 7) ||
117 c
->x86_model
== 9 || c
->x86_model
== 13) {
118 /* The more serious chips .. */
123 rdmsr(MSR_K6_WHCR
, l
, h
);
124 if ((l
&0xFFFF0000) == 0) {
126 l
= ((mbytes
>>2)<<22)|(1<<16);
127 local_irq_save(flags
);
129 wrmsr(MSR_K6_WHCR
, l
, h
);
130 local_irq_restore(flags
);
131 printk(KERN_INFO
"Enabling new style K6 write allocation for %d Mb\n",
138 if (c
->x86_model
== 10) {
139 /* AMD Geode LX is model 10 */
140 /* placeholder for any needed mods */
145 static void __cpuinit
init_amd_k7(struct cpuinfo_x86
*c
)
150 * Bit 15 of Athlon specific MSR 15, needs to be 0
151 * to enable SSE on Palomino/Morgan/Barton CPU's.
152 * If the BIOS didn't enable it already, enable it here.
154 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
155 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
156 printk(KERN_INFO
"Enabling disabled K7/SSE Support.\n");
157 rdmsr(MSR_K7_HWCR
, l
, h
);
159 wrmsr(MSR_K7_HWCR
, l
, h
);
160 set_cpu_cap(c
, X86_FEATURE_XMM
);
165 * It's been determined by AMD that Athlons since model 8 stepping 1
166 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
167 * As per AMD technical note 27212 0.2
169 if ((c
->x86_model
== 8 && c
->x86_mask
>= 1) || (c
->x86_model
> 8)) {
170 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
171 if ((l
& 0xfff00000) != 0x20000000) {
172 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l
,
173 ((l
& 0x000fffff)|0x20000000));
174 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
178 set_cpu_cap(c
, X86_FEATURE_K7
);
182 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
183 * Assumes number of cores is a power of two.
185 static void __cpuinit
amd_detect_cmp(struct cpuinfo_x86
*c
)
190 bits
= c
->x86_coreid_bits
;
192 /* Low order bits define the core id (index of core in socket) */
193 c
->cpu_core_id
= c
->initial_apicid
& ((1 << bits
)-1);
194 /* Convert the initial APIC ID into the socket ID */
195 c
->phys_proc_id
= c
->initial_apicid
>> bits
;
199 static void __cpuinit
early_init_amd_mc(struct cpuinfo_x86
*c
)
204 /* Multi core CPU? */
205 if (c
->extended_cpuid_level
< 0x80000008)
208 ecx
= cpuid_ecx(0x80000008);
210 c
->x86_max_cores
= (ecx
& 0xff) + 1;
212 /* CPU telling us the core id bits shift? */
213 bits
= (ecx
>> 12) & 0xF;
215 /* Otherwise recompute */
217 while ((1 << bits
) < c
->x86_max_cores
)
221 c
->x86_coreid_bits
= bits
;
225 static void __cpuinit
early_init_amd(struct cpuinfo_x86
*c
)
227 early_init_amd_mc(c
);
229 if (c
->x86_power
& (1<<8))
230 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
232 /* Set MTRR capability flag if appropriate */
233 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
234 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
235 set_cpu_cap(c
, X86_FEATURE_K6_MTRR
);
238 static void __cpuinit
init_amd(struct cpuinfo_x86
*c
)
241 unsigned long long value
;
244 * Disable TLB flush filter by setting HWCR.FFDIS on K8
245 * bit 6 of msr C001_0015
247 * Errata 63 for SH-B3 steppings
248 * Errata 122 for all steppings (F+ have it disabled by default)
251 rdmsrl(MSR_K7_HWCR
, value
);
253 wrmsrl(MSR_K7_HWCR
, value
);
260 * FIXME: We should handle the K5 here. Set up the write
261 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
266 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
267 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
269 clear_cpu_cap(c
, 0*32+31);
278 case 6: /* An Athlon/Duron */
283 /* K6s reports MCEs but don't actually have all the MSRs */
285 clear_cpu_cap(c
, X86_FEATURE_MCE
);
288 set_cpu_cap(c
, X86_FEATURE_FXSAVE_LEAK
);
290 if (!c
->x86_model_id
[0]) {
293 /* Should distinguish Models here, but this is only
294 a fallback anyways. */
295 strcpy(c
->x86_model_id
, "Hammer");
300 display_cacheinfo(c
);
302 /* Multi core CPU? */
303 if (c
->extended_cpuid_level
>= 0x80000008)
308 if (c
->extended_cpuid_level
>= 0x80000006) {
309 if ((c
->x86
>= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
310 num_cache_leaves
= 4;
312 num_cache_leaves
= 3;
315 if (c
->x86
>= 0xf && c
->x86
<= 0x11)
316 set_cpu_cap(c
, X86_FEATURE_K8
);
319 /* MFENCE stops RDTSC speculation */
320 set_cpu_cap(c
, X86_FEATURE_MFENCE_RDTSC
);
324 static unsigned int __cpuinit
amd_size_cache(struct cpuinfo_x86
*c
, unsigned int size
)
326 /* AMD errata T13 (order #21922) */
328 if (c
->x86_model
== 3 && c
->x86_mask
== 0) /* Duron Rev A0 */
330 if (c
->x86_model
== 4 &&
331 (c
->x86_mask
== 0 || c
->x86_mask
== 1)) /* Tbird rev A1/A2 */
337 static struct cpu_dev amd_cpu_dev __cpuinitdata
= {
339 .c_ident
= { "AuthenticAMD" },
341 { .vendor
= X86_VENDOR_AMD
, .family
= 4, .model_names
=
352 .c_early_init
= early_init_amd
,
354 .c_size_cache
= amd_size_cache
,
355 .c_x86_vendor
= X86_VENDOR_AMD
,
358 cpu_dev_register(amd_cpu_dev
);