drivers/net/sfc/net_driver.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 /* Common definitions for all Efx net driver code */
  12
  13 #ifndef EFX_NET_DRIVER_H
  14 #define EFX_NET_DRIVER_H
  15
  16 #include <linux/version.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/timer.h>
  22 #include <linux/mii.h>
  23 #include <linux/list.h>
  24 #include <linux/pci.h>
  25 #include <linux/device.h>
  26 #include <linux/highmem.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/inet_lro.h>
  29
  30 #include "enum.h"
  31 #include "bitfield.h"
  32 #include "i2c-direct.h"
  33
  34 #define EFX_MAX_LRO_DESCRIPTORS 8
  35 #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
  36
  37 /**************************************************************************
  38  *
  39  * Build definitions
  40  *
  41  **************************************************************************/
  42 #ifndef EFX_DRIVER_NAME
  43 #define EFX_DRIVER_NAME "sfc"
  44 #endif
  45 #define EFX_DRIVER_VERSION      "2.2.0136"
  46
  47 #ifdef EFX_ENABLE_DEBUG
  48 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  49 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  50 #else
  51 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  52 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  53 #endif
  54
  55 #define NET_DEV_REGISTERED(efx)                                 \
  56         ((efx)->net_dev->reg_state == NETREG_REGISTERED)
  57
  58 /* Include net device name in log messages if it has been registered.
  59  * Use efx->name not efx->net_dev->name so that races with (un)registration
  60  * are harmless.
  61  */
  62 #define NET_DEV_NAME(efx) (NET_DEV_REGISTERED(efx) ? (efx)->name : "")
  63
  64 /* Un-rate-limited logging */
  65 #define EFX_ERR(efx, fmt, args...) \
  66 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, NET_DEV_NAME(efx), ##args)
  67
  68 #define EFX_INFO(efx, fmt, args...) \
  69 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, NET_DEV_NAME(efx), ##args)
  70
  71 #ifdef EFX_ENABLE_DEBUG
  72 #define EFX_LOG(efx, fmt, args...) \
  73 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
  74 #else
  75 #define EFX_LOG(efx, fmt, args...) \
  76 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
  77 #endif
  78
  79 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
  80
  81 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
  82
  83 /* Rate-limited logging */
  84 #define EFX_ERR_RL(efx, fmt, args...) \
  85 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
  86
  87 #define EFX_INFO_RL(efx, fmt, args...) \
  88 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
  89
  90 #define EFX_LOG_RL(efx, fmt, args...) \
  91 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
  92
  93 /* Kernel headers may redefine inline anyway */
  94 #ifndef inline
  95 #define inline inline __attribute__ ((always_inline))
  96 #endif
  97
  98 /**************************************************************************
  99  *
 100  * Efx data structures
 101  *
 102  **************************************************************************/
 103
 104 #define EFX_MAX_CHANNELS 32
 105 #define EFX_MAX_TX_QUEUES 1
 106 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
 107
 108 /**
 109  * struct efx_special_buffer - An Efx special buffer
 110  * @addr: CPU base address of the buffer
 111  * @dma_addr: DMA base address of the buffer
 112  * @len: Buffer length, in bytes
 113  * @index: Buffer index within controller;s buffer table
 114  * @entries: Number of buffer table entries
 115  *
 116  * Special buffers are used for the event queues and the TX and RX
 117  * descriptor queues for each channel.  They are *not* used for the
 118  * actual transmit and receive buffers.
 119  *
 120  * Note that for Falcon, TX and RX descriptor queues live in host memory.
 121  * Allocation and freeing procedures must take this into account.
 122  */
 123 struct efx_special_buffer {
 124         void *addr;
 125         dma_addr_t dma_addr;
 126         unsigned int len;
 127         int index;
 128         int entries;
 129 };
 130
 131 /**
 132  * struct efx_tx_buffer - An Efx TX buffer
 133  * @skb: The associated socket buffer.
 134  *      Set only on the final fragment of a packet; %NULL for all other
 135  *      fragments.  When this fragment completes, then we can free this
 136  *      skb.
 137  * @dma_addr: DMA address of the fragment.
 138  * @len: Length of this fragment.
 139  *      This field is zero when the queue slot is empty.
 140  * @continuation: True if this fragment is not the end of a packet.
 141  * @unmap_single: True if pci_unmap_single should be used.
 142  * @unmap_addr: DMA address to unmap
 143  * @unmap_len: Length of this fragment to unmap
 144  */
 145 struct efx_tx_buffer {
 146         const struct sk_buff *skb;
 147         dma_addr_t dma_addr;
 148         unsigned short len;
 149         unsigned char continuation;
 150         unsigned char unmap_single;
 151         dma_addr_t unmap_addr;
 152         unsigned short unmap_len;
 153 };
 154
 155 /**
 156  * struct efx_tx_queue - An Efx TX queue
 157  *
 158  * This is a ring buffer of TX fragments.
 159  * Since the TX completion path always executes on the same
 160  * CPU and the xmit path can operate on different CPUs,
 161  * performance is increased by ensuring that the completion
 162  * path and the xmit path operate on different cache lines.
 163  * This is particularly important if the xmit path is always
 164  * executing on one CPU which is different from the completion
 165  * path.  There is also a cache line for members which are
 166  * read but not written on the fast path.
 167  *
 168  * @efx: The associated Efx NIC
 169  * @queue: DMA queue number
 170  * @used: Queue is used by net driver
 171  * @channel: The associated channel
 172  * @buffer: The software buffer ring
 173  * @txd: The hardware descriptor ring
 174  * @read_count: Current read pointer.
 175  *      This is the number of buffers that have been removed from both rings.
 176  * @stopped: Stopped flag.
 177  *      Set if this TX queue is currently stopping its port.
 178  * @insert_count: Current insert pointer
 179  *      This is the number of buffers that have been added to the
 180  *      software ring.
 181  * @write_count: Current write pointer
 182  *      This is the number of buffers that have been added to the
 183  *      hardware ring.
 184  * @old_read_count: The value of read_count when last checked.
 185  *      This is here for performance reasons.  The xmit path will
 186  *      only get the up-to-date value of read_count if this
 187  *      variable indicates that the queue is full.  This is to
 188  *      avoid cache-line ping-pong between the xmit path and the
 189  *      completion path.
 190  */
 191 struct efx_tx_queue {
 192         /* Members which don't change on the fast path */
 193         struct efx_nic *efx ____cacheline_aligned_in_smp;
 194         int queue;
 195         int used;
 196         struct efx_channel *channel;
 197         struct efx_nic *nic;
 198         struct efx_tx_buffer *buffer;
 199         struct efx_special_buffer txd;
 200
 201         /* Members used mainly on the completion path */
 202         unsigned int read_count ____cacheline_aligned_in_smp;
 203         int stopped;
 204
 205         /* Members used only on the xmit path */
 206         unsigned int insert_count ____cacheline_aligned_in_smp;
 207         unsigned int write_count;
 208         unsigned int old_read_count;
 209 };
 210
 211 /**
 212  * struct efx_rx_buffer - An Efx RX data buffer
 213  * @dma_addr: DMA base address of the buffer
 214  * @skb: The associated socket buffer, if any.
 215  *      If both this and page are %NULL, the buffer slot is currently free.
 216  * @page: The associated page buffer, if any.
 217  *      If both this and skb are %NULL, the buffer slot is currently free.
 218  * @data: Pointer to ethernet header
 219  * @len: Buffer length, in bytes.
 220  * @unmap_addr: DMA address to unmap
 221  */
 222 struct efx_rx_buffer {
 223         dma_addr_t dma_addr;
 224         struct sk_buff *skb;
 225         struct page *page;
 226         char *data;
 227         unsigned int len;
 228         dma_addr_t unmap_addr;
 229 };
 230
 231 /**
 232  * struct efx_rx_queue - An Efx RX queue
 233  * @efx: The associated Efx NIC
 234  * @queue: DMA queue number
 235  * @used: Queue is used by net driver
 236  * @channel: The associated channel
 237  * @buffer: The software buffer ring
 238  * @rxd: The hardware descriptor ring
 239  * @added_count: Number of buffers added to the receive queue.
 240  * @notified_count: Number of buffers given to NIC (<= @added_count).
 241  * @removed_count: Number of buffers removed from the receive queue.
 242  * @add_lock: Receive queue descriptor add spin lock.
 243  *      This lock must be held in order to add buffers to the RX
 244  *      descriptor ring (rxd and buffer) and to update added_count (but
 245  *      not removed_count).
 246  * @max_fill: RX descriptor maximum fill level (<= ring size)
 247  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
 248  *      (<= @max_fill)
 249  * @fast_fill_limit: The level to which a fast fill will fill
 250  *      (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
 251  * @min_fill: RX descriptor minimum non-zero fill level.
 252  *      This records the minimum fill level observed when a ring
 253  *      refill was triggered.
 254  * @min_overfill: RX descriptor minimum overflow fill level.
 255  *      This records the minimum fill level at which RX queue
 256  *      overflow was observed.  It should never be set.
 257  * @alloc_page_count: RX allocation strategy counter.
 258  * @alloc_skb_count: RX allocation strategy counter.
 259  * @work: Descriptor push work thread
 260  * @buf_page: Page for next RX buffer.
 261  *      We can use a single page for multiple RX buffers. This tracks
 262  *      the remaining space in the allocation.
 263  * @buf_dma_addr: Page's DMA address.
 264  * @buf_data: Page's host address.
 265  */
 266 struct efx_rx_queue {
 267         struct efx_nic *efx;
 268         int queue;
 269         int used;
 270         struct efx_channel *channel;
 271         struct efx_rx_buffer *buffer;
 272         struct efx_special_buffer rxd;
 273
 274         int added_count;
 275         int notified_count;
 276         int removed_count;
 277         spinlock_t add_lock;
 278         unsigned int max_fill;
 279         unsigned int fast_fill_trigger;
 280         unsigned int fast_fill_limit;
 281         unsigned int min_fill;
 282         unsigned int min_overfill;
 283         unsigned int alloc_page_count;
 284         unsigned int alloc_skb_count;
 285         struct delayed_work work;
 286         unsigned int slow_fill_count;
 287
 288         struct page *buf_page;
 289         dma_addr_t buf_dma_addr;
 290         char *buf_data;
 291 };
 292
 293 /**
 294  * struct efx_buffer - An Efx general-purpose buffer
 295  * @addr: host base address of the buffer
 296  * @dma_addr: DMA base address of the buffer
 297  * @len: Buffer length, in bytes
 298  *
 299  * Falcon uses these buffers for its interrupt status registers and
 300  * MAC stats dumps.
 301  */
 302 struct efx_buffer {
 303         void *addr;
 304         dma_addr_t dma_addr;
 305         unsigned int len;
 306 };
 307
 308
 309 /* Flags for channel->used_flags */
 310 #define EFX_USED_BY_RX 1
 311 #define EFX_USED_BY_TX 2
 312 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
 313
 314 enum efx_rx_alloc_method {
 315         RX_ALLOC_METHOD_AUTO = 0,
 316         RX_ALLOC_METHOD_SKB = 1,
 317         RX_ALLOC_METHOD_PAGE = 2,
 318 };
 319
 320 /**
 321  * struct efx_channel - An Efx channel
 322  *
 323  * A channel comprises an event queue, at least one TX queue, at least
 324  * one RX queue, and an associated tasklet for processing the event
 325  * queue.
 326  *
 327  * @efx: Associated Efx NIC
 328  * @evqnum: Event queue number
 329  * @channel: Channel instance number
 330  * @used_flags: Channel is used by net driver
 331  * @enabled: Channel enabled indicator
 332  * @irq: IRQ number (MSI and MSI-X only)
 333  * @has_interrupt: Channel has an interrupt
 334  * @irq_moderation: IRQ moderation value (in us)
 335  * @napi_dev: Net device used with NAPI
 336  * @napi_str: NAPI control structure
 337  * @reset_work: Scheduled reset work thread
 338  * @work_pending: Is work pending via NAPI?
 339  * @eventq: Event queue buffer
 340  * @eventq_read_ptr: Event queue read pointer
 341  * @last_eventq_read_ptr: Last event queue read pointer value.
 342  * @eventq_magic: Event queue magic value for driver-generated test events
 343  * @lro_mgr: LRO state
 344  * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
 345  *      and diagnostic counters
 346  * @rx_alloc_push_pages: RX allocation method currently in use for pushing
 347  *      descriptors
 348  * @rx_alloc_pop_pages: RX allocation method currently in use for popping
 349  *      descriptors
 350  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
 351  * @n_rx_ip_frag_err: Count of RX IP fragment errors
 352  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
 353  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
 354  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
 355  * @n_rx_overlength: Count of RX_OVERLENGTH errors
 356  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
 357  */
 358 struct efx_channel {
 359         struct efx_nic *efx;
 360         int evqnum;
 361         int channel;
 362         int used_flags;
 363         int enabled;
 364         int irq;
 365         unsigned int has_interrupt;
 366         unsigned int irq_moderation;
 367         struct net_device *napi_dev;
 368         struct napi_struct napi_str;
 369         struct work_struct reset_work;
 370         int work_pending;
 371         struct efx_special_buffer eventq;
 372         unsigned int eventq_read_ptr;
 373         unsigned int last_eventq_read_ptr;
 374         unsigned int eventq_magic;
 375
 376         struct net_lro_mgr lro_mgr;
 377         int rx_alloc_level;
 378         int rx_alloc_push_pages;
 379         int rx_alloc_pop_pages;
 380
 381         unsigned n_rx_tobe_disc;
 382         unsigned n_rx_ip_frag_err;
 383         unsigned n_rx_ip_hdr_chksum_err;
 384         unsigned n_rx_tcp_udp_chksum_err;
 385         unsigned n_rx_frm_trunc;
 386         unsigned n_rx_overlength;
 387         unsigned n_skbuff_leaks;
 388
 389         /* Used to pipeline received packets in order to optimise memory
 390          * access with prefetches.
 391          */
 392         struct efx_rx_buffer *rx_pkt;
 393         int rx_pkt_csummed;
 394
 395 };
 396
 397 /**
 398  * struct efx_blinker - S/W LED blinking context
 399  * @led_num: LED ID (board-specific meaning)
 400  * @state: Current state - on or off
 401  * @resubmit: Timer resubmission flag
 402  * @timer: Control timer for blinking
 403  */
 404 struct efx_blinker {
 405         int led_num;
 406         int state;
 407         int resubmit;
 408         struct timer_list timer;
 409 };
 410
 411
 412 /**
 413  * struct efx_board - board information
 414  * @type: Board model type
 415  * @major: Major rev. ('A', 'B' ...)
 416  * @minor: Minor rev. (0, 1, ...)
 417  * @init: Initialisation function
 418  * @init_leds: Sets up board LEDs
 419  * @set_fault_led: Turns the fault LED on or off
 420  * @blink: Starts/stops blinking
 421  * @blinker: used to blink LEDs in software
 422  */
 423 struct efx_board {
 424         int type;
 425         int major;
 426         int minor;
 427         int (*init) (struct efx_nic *nic);
 428         /* As the LEDs are typically attached to the PHY, LEDs
 429          * have a separate init callback that happens later than
 430          * board init. */
 431         int (*init_leds)(struct efx_nic *efx);
 432         void (*set_fault_led) (struct efx_nic *efx, int state);
 433         void (*blink) (struct efx_nic *efx, int start);
 434         struct efx_blinker blinker;
 435 };
 436
 437 enum efx_int_mode {
 438         /* Be careful if altering to correct macro below */
 439         EFX_INT_MODE_MSIX = 0,
 440         EFX_INT_MODE_MSI = 1,
 441         EFX_INT_MODE_LEGACY = 2,
 442         EFX_INT_MODE_MAX        /* Insert any new items before this */
 443 };
 444 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
 445
 446 enum phy_type {
 447         PHY_TYPE_NONE = 0,
 448         PHY_TYPE_CX4_RTMR = 1,
 449         PHY_TYPE_1G_ALASKA = 2,
 450         PHY_TYPE_10XPRESS = 3,
 451         PHY_TYPE_XFP = 4,
 452         PHY_TYPE_PM8358 = 6,
 453         PHY_TYPE_MAX    /* Insert any new items before this */
 454 };
 455
 456 #define PHY_ADDR_INVALID 0xff
 457
 458 enum nic_state {
 459         STATE_INIT = 0,
 460         STATE_RUNNING = 1,
 461         STATE_FINI = 2,
 462         STATE_RESETTING = 3, /* rtnl_lock always held */
 463         STATE_DISABLED = 4,
 464         STATE_MAX,
 465 };
 466
 467 /*
 468  * Alignment of page-allocated RX buffers
 469  *
 470  * Controls the number of bytes inserted at the start of an RX buffer.
 471  * This is the equivalent of NET_IP_ALIGN [which controls the alignment
 472  * of the skb->head for hardware DMA].
 473  */
 474 #if defined(__i386__) || defined(__x86_64__)
 475 #define EFX_PAGE_IP_ALIGN 0
 476 #else
 477 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
 478 #endif
 479
 480 /*
 481  * Alignment of the skb->head which wraps a page-allocated RX buffer
 482  *
 483  * The skb allocated to wrap an rx_buffer can have this alignment. Since
 484  * the data is memcpy'd from the rx_buf, it does not need to be equal to
 485  * EFX_PAGE_IP_ALIGN.
 486  */
 487 #define EFX_PAGE_SKB_ALIGN 2
 488
 489 /* Forward declaration */
 490 struct efx_nic;
 491
 492 /* Pseudo bit-mask flow control field */
 493 enum efx_fc_type {
 494         EFX_FC_RX = 1,
 495         EFX_FC_TX = 2,
 496         EFX_FC_AUTO = 4,
 497 };
 498
 499 /**
 500  * struct efx_phy_operations - Efx PHY operations table
 501  * @init: Initialise PHY
 502  * @fini: Shut down PHY
 503  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
 504  * @clear_interrupt: Clear down interrupt
 505  * @blink: Blink LEDs
 506  * @check_hw: Check hardware
 507  * @reset_xaui: Reset XAUI side of PHY for (software sequenced reset)
 508  * @mmds: MMD presence mask
 509  */
 510 struct efx_phy_operations {
 511         int (*init) (struct efx_nic *efx);
 512         void (*fini) (struct efx_nic *efx);
 513         void (*reconfigure) (struct efx_nic *efx);
 514         void (*clear_interrupt) (struct efx_nic *efx);
 515         int (*check_hw) (struct efx_nic *efx);
 516         void (*reset_xaui) (struct efx_nic *efx);
 517         int mmds;
 518 };
 519
 520 /*
 521  * Efx extended statistics
 522  *
 523  * Not all statistics are provided by all supported MACs.  The purpose
 524  * is this structure is to contain the raw statistics provided by each
 525  * MAC.
 526  */
 527 struct efx_mac_stats {
 528         u64 tx_bytes;
 529         u64 tx_good_bytes;
 530         u64 tx_bad_bytes;
 531         unsigned long tx_packets;
 532         unsigned long tx_bad;
 533         unsigned long tx_pause;
 534         unsigned long tx_control;
 535         unsigned long tx_unicast;
 536         unsigned long tx_multicast;
 537         unsigned long tx_broadcast;
 538         unsigned long tx_lt64;
 539         unsigned long tx_64;
 540         unsigned long tx_65_to_127;
 541         unsigned long tx_128_to_255;
 542         unsigned long tx_256_to_511;
 543         unsigned long tx_512_to_1023;
 544         unsigned long tx_1024_to_15xx;
 545         unsigned long tx_15xx_to_jumbo;
 546         unsigned long tx_gtjumbo;
 547         unsigned long tx_collision;
 548         unsigned long tx_single_collision;
 549         unsigned long tx_multiple_collision;
 550         unsigned long tx_excessive_collision;
 551         unsigned long tx_deferred;
 552         unsigned long tx_late_collision;
 553         unsigned long tx_excessive_deferred;
 554         unsigned long tx_non_tcpudp;
 555         unsigned long tx_mac_src_error;
 556         unsigned long tx_ip_src_error;
 557         u64 rx_bytes;
 558         u64 rx_good_bytes;
 559         u64 rx_bad_bytes;
 560         unsigned long rx_packets;
 561         unsigned long rx_good;
 562         unsigned long rx_bad;
 563         unsigned long rx_pause;
 564         unsigned long rx_control;
 565         unsigned long rx_unicast;
 566         unsigned long rx_multicast;
 567         unsigned long rx_broadcast;
 568         unsigned long rx_lt64;
 569         unsigned long rx_64;
 570         unsigned long rx_65_to_127;
 571         unsigned long rx_128_to_255;
 572         unsigned long rx_256_to_511;
 573         unsigned long rx_512_to_1023;
 574         unsigned long rx_1024_to_15xx;
 575         unsigned long rx_15xx_to_jumbo;
 576         unsigned long rx_gtjumbo;
 577         unsigned long rx_bad_lt64;
 578         unsigned long rx_bad_64_to_15xx;
 579         unsigned long rx_bad_15xx_to_jumbo;
 580         unsigned long rx_bad_gtjumbo;
 581         unsigned long rx_overflow;
 582         unsigned long rx_missed;
 583         unsigned long rx_false_carrier;
 584         unsigned long rx_symbol_error;
 585         unsigned long rx_align_error;
 586         unsigned long rx_length_error;
 587         unsigned long rx_internal_error;
 588         unsigned long rx_good_lt64;
 589 };
 590
 591 /* Number of bits used in a multicast filter hash address */
 592 #define EFX_MCAST_HASH_BITS 8
 593
 594 /* Number of (single-bit) entries in a multicast filter hash */
 595 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
 596
 597 /* An Efx multicast filter hash */
 598 union efx_multicast_hash {
 599         u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
 600         efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
 601 };
 602
 603 /**
 604  * struct efx_nic - an Efx NIC
 605  * @name: Device name (net device name or bus id before net device registered)
 606  * @pci_dev: The PCI device
 607  * @type: Controller type attributes
 608  * @legacy_irq: IRQ number
 609  * @workqueue: Workqueue for resets, port reconfigures and the HW monitor
 610  * @reset_work: Scheduled reset workitem
 611  * @monitor_work: Hardware monitor workitem
 612  * @membase_phys: Memory BAR value as physical address
 613  * @membase: Memory BAR value
 614  * @biu_lock: BIU (bus interface unit) lock
 615  * @interrupt_mode: Interrupt mode
 616  * @i2c: I2C interface
 617  * @board_info: Board-level information
 618  * @state: Device state flag. Serialised by the rtnl_lock.
 619  * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
 620  * @tx_queue: TX DMA queues
 621  * @rx_queue: RX DMA queues
 622  * @channel: Channels
 623  * @rss_queues: Number of RSS queues
 624  * @rx_buffer_len: RX buffer length
 625  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
 626  * @irq_status: Interrupt status buffer
 627  * @last_irq_cpu: Last CPU to handle interrupt.
 628  *      This register is written with the SMP processor ID whenever an
 629  *      interrupt is handled.  It is used by falcon_test_interrupt()
 630  *      to verify that an interrupt has occurred.
 631  * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
 632  * @nic_data: Hardware dependant state
 633  * @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and
 634  *      efx_reconfigure_port()
 635  * @port_enabled: Port enabled indicator.
 636  *      Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
 637  *      efx_reconfigure_work with kernel interfaces. Safe to read under any
 638  *      one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
 639  *      be held to modify it.
 640  * @port_initialized: Port initialized?
 641  * @net_dev: Operating system network device. Consider holding the rtnl lock
 642  * @rx_checksum_enabled: RX checksumming enabled
 643  * @netif_stop_count: Port stop count
 644  * @netif_stop_lock: Port stop lock
 645  * @mac_stats: MAC statistics. These include all statistics the MACs
 646  *      can provide.  Generic code converts these into a standard
 647  *      &struct net_device_stats.
 648  * @stats_buffer: DMA buffer for statistics
 649  * @stats_lock: Statistics update lock
 650  * @mac_address: Permanent MAC address
 651  * @phy_type: PHY type
 652  * @phy_lock: PHY access lock
 653  * @phy_op: PHY interface
 654  * @phy_data: PHY private data (including PHY-specific stats)
 655  * @mii: PHY interface
 656  * @phy_powered: PHY power state
 657  * @tx_disabled: PHY transmitter turned off
 658  * @link_up: Link status
 659  * @link_options: Link options (MII/GMII format)
 660  * @n_link_state_changes: Number of times the link has changed state
 661  * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
 662  * @multicast_hash: Multicast hash table
 663  * @flow_control: Flow control flags - separate RX/TX so can't use link_options
 664  * @reconfigure_work: work item for dealing with PHY events
 665  *
 666  * The @priv field of the corresponding &struct net_device points to
 667  * this.
 668  */
 669 struct efx_nic {
 670         char name[IFNAMSIZ];
 671         struct pci_dev *pci_dev;
 672         const struct efx_nic_type *type;
 673         int legacy_irq;
 674         struct workqueue_struct *workqueue;
 675         struct work_struct reset_work;
 676         struct delayed_work monitor_work;
 677         unsigned long membase_phys;
 678         void __iomem *membase;
 679         spinlock_t biu_lock;
 680         enum efx_int_mode interrupt_mode;
 681
 682         struct efx_i2c_interface i2c;
 683         struct efx_board board_info;
 684
 685         enum nic_state state;
 686         enum reset_type reset_pending;
 687
 688         struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES];
 689         struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
 690         struct efx_channel channel[EFX_MAX_CHANNELS];
 691
 692         int rss_queues;
 693         unsigned int rx_buffer_len;
 694         unsigned int rx_buffer_order;
 695
 696         struct efx_buffer irq_status;
 697         volatile signed int last_irq_cpu;
 698
 699         unsigned n_rx_nodesc_drop_cnt;
 700
 701         void *nic_data;
 702
 703         struct mutex mac_lock;
 704         int port_enabled;
 705
 706         int port_initialized;
 707         struct net_device *net_dev;
 708         int rx_checksum_enabled;
 709
 710         atomic_t netif_stop_count;
 711         spinlock_t netif_stop_lock;
 712
 713         struct efx_mac_stats mac_stats;
 714         struct efx_buffer stats_buffer;
 715         spinlock_t stats_lock;
 716
 717         unsigned char mac_address[ETH_ALEN];
 718
 719         enum phy_type phy_type;
 720         spinlock_t phy_lock;
 721         struct efx_phy_operations *phy_op;
 722         void *phy_data;
 723         struct mii_if_info mii;
 724
 725         int link_up;
 726         unsigned int link_options;
 727         unsigned int n_link_state_changes;
 728
 729         int promiscuous;
 730         union efx_multicast_hash multicast_hash;
 731         enum efx_fc_type flow_control;
 732         struct work_struct reconfigure_work;
 733
 734         atomic_t rx_reset;
 735 };
 736
 737 /**
 738  * struct efx_nic_type - Efx device type definition
 739  * @mem_bar: Memory BAR number
 740  * @mem_map_size: Memory BAR mapped size
 741  * @txd_ptr_tbl_base: TX descriptor ring base address
 742  * @rxd_ptr_tbl_base: RX descriptor ring base address
 743  * @buf_tbl_base: Buffer table base address
 744  * @evq_ptr_tbl_base: Event queue pointer table base address
 745  * @evq_rptr_tbl_base: Event queue read-pointer table base address
 746  * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
 747  * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
 748  * @evq_size: Event queue size (must be a power of two)
 749  * @max_dma_mask: Maximum possible DMA mask
 750  * @tx_dma_mask: TX DMA mask
 751  * @bug5391_mask: Address mask for bug 5391 workaround
 752  * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
 753  * @rx_xon_thresh: RX FIFO XON watermark (bytes)
 754  * @rx_buffer_padding: Padding added to each RX buffer
 755  * @max_interrupt_mode: Highest capability interrupt mode supported
 756  *      from &enum efx_init_mode.
 757  * @phys_addr_channels: Number of channels with physically addressed
 758  *      descriptors
 759  */
 760 struct efx_nic_type {
 761         unsigned int mem_bar;
 762         unsigned int mem_map_size;
 763         unsigned int txd_ptr_tbl_base;
 764         unsigned int rxd_ptr_tbl_base;
 765         unsigned int buf_tbl_base;
 766         unsigned int evq_ptr_tbl_base;
 767         unsigned int evq_rptr_tbl_base;
 768
 769         unsigned int txd_ring_mask;
 770         unsigned int rxd_ring_mask;
 771         unsigned int evq_size;
 772         dma_addr_t max_dma_mask;
 773         unsigned int tx_dma_mask;
 774         unsigned bug5391_mask;
 775
 776         int rx_xoff_thresh;
 777         int rx_xon_thresh;
 778         unsigned int rx_buffer_padding;
 779         unsigned int max_interrupt_mode;
 780         unsigned int phys_addr_channels;
 781 };
 782
 783 /**************************************************************************
 784  *
 785  * Prototypes and inline functions
 786  *
 787  *************************************************************************/
 788
 789 /* Iterate over all used channels */
 790 #define efx_for_each_channel(_channel, _efx)                            \
 791         for (_channel = &_efx->channel[0];                              \
 792              _channel < &_efx->channel[EFX_MAX_CHANNELS];               \
 793              _channel++)                                                \
 794                 if (!_channel->used_flags)                              \
 795                         continue;                                       \
 796                 else
 797
 798 /* Iterate over all used channels with interrupts */
 799 #define efx_for_each_channel_with_interrupt(_channel, _efx)             \
 800         for (_channel = &_efx->channel[0];                              \
 801              _channel < &_efx->channel[EFX_MAX_CHANNELS];               \
 802              _channel++)                                                \
 803                 if (!(_channel->used_flags && _channel->has_interrupt)) \
 804                         continue;                                       \
 805                 else
 806
 807 /* Iterate over all used TX queues */
 808 #define efx_for_each_tx_queue(_tx_queue, _efx)                          \
 809         for (_tx_queue = &_efx->tx_queue[0];                            \
 810              _tx_queue < &_efx->tx_queue[EFX_MAX_TX_QUEUES];            \
 811              _tx_queue++)                                               \
 812                 if (!_tx_queue->used)                                   \
 813                         continue;                                       \
 814                 else
 815
 816 /* Iterate over all TX queues belonging to a channel */
 817 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)              \
 818         for (_tx_queue = &_channel->efx->tx_queue[0];                   \
 819              _tx_queue < &_channel->efx->tx_queue[EFX_MAX_TX_QUEUES];   \
 820              _tx_queue++)                                               \
 821                 if ((!_tx_queue->used) ||                               \
 822                     (_tx_queue->channel != _channel))                   \
 823                         continue;                                       \
 824                 else
 825
 826 /* Iterate over all used RX queues */
 827 #define efx_for_each_rx_queue(_rx_queue, _efx)                          \
 828         for (_rx_queue = &_efx->rx_queue[0];                            \
 829              _rx_queue < &_efx->rx_queue[EFX_MAX_RX_QUEUES];            \
 830              _rx_queue++)                                               \
 831                 if (!_rx_queue->used)                                   \
 832                         continue;                                       \
 833                 else
 834
 835 /* Iterate over all RX queues belonging to a channel */
 836 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)              \
 837         for (_rx_queue = &_channel->efx->rx_queue[0];                   \
 838              _rx_queue < &_channel->efx->rx_queue[EFX_MAX_RX_QUEUES];   \
 839              _rx_queue++)                                               \
 840                 if ((!_rx_queue->used) ||                               \
 841                     (_rx_queue->channel != _channel))                   \
 842                         continue;                                       \
 843                 else
 844
 845 /* Returns a pointer to the specified receive buffer in the RX
 846  * descriptor queue.
 847  */
 848 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
 849                                                   unsigned int index)
 850 {
 851         return (&rx_queue->buffer[index]);
 852 }
 853
 854 /* Set bit in a little-endian bitfield */
 855 static inline void set_bit_le(int nr, unsigned char *addr)
 856 {
 857         addr[nr / 8] |= (1 << (nr % 8));
 858 }
 859
 860 /* Clear bit in a little-endian bitfield */
 861 static inline void clear_bit_le(int nr, unsigned char *addr)
 862 {
 863         addr[nr / 8] &= ~(1 << (nr % 8));
 864 }
 865
 866
 867 /**
 868  * EFX_MAX_FRAME_LEN - calculate maximum frame length
 869  *
 870  * This calculates the maximum frame length that will be used for a
 871  * given MTU.  The frame length will be equal to the MTU plus a
 872  * constant amount of header space and padding.  This is the quantity
 873  * that the net driver will program into the MAC as the maximum frame
 874  * length.
 875  *
 876  * The 10G MAC used in Falcon requires 8-byte alignment on the frame
 877  * length, so we round up to the nearest 8.
 878  */
 879 #define EFX_MAX_FRAME_LEN(mtu) \
 880         ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
 881
 882
 883 #endif /* EFX_NET_DRIVER_H */