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drivers/misc/Makefile, Kconfig: cleanup
[linux-2.6/mini2440.git] / drivers / pci / probe.c
blob003a9b3c293fd6937682d061f2b4e242ab673adc
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
21
22
23 static int find_anything(struct device *dev, void *data)
24 {
25 return 1;
26 }
27
28 /*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33 int no_pci_devices(void)
34 {
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42 }
43 EXPORT_SYMBOL(no_pci_devices);
44
45 /*
46 * PCI Bus Class Devices
47 */
48 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
49 int type,
50 struct device_attribute *attr,
51 char *buf)
52 {
53 int ret;
54 cpumask_t cpumask;
55
56 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
57 ret = type?
58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
60 buf[ret++] = '\n';
61 buf[ret] = '\0';
62 return ret;
63 }
64
65 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
67 char *buf)
68 {
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
70 }
71
72 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
74 char *buf)
75 {
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
77 }
78
79 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
81
82 /*
83 * PCI Bus Class
84 */
85 static void release_pcibus_dev(struct device *dev)
86 {
87 struct pci_bus *pci_bus = to_pci_bus(dev);
88
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
91 kfree(pci_bus);
92 }
93
94 static struct class pcibus_class = {
95 .name = "pci_bus",
96 .dev_release = &release_pcibus_dev,
97 };
98
99 static int __init pcibus_class_init(void)
100 {
101 return class_register(&pcibus_class);
102 }
103 postcore_initcall(pcibus_class_init);
104
105 /*
106 * Translate the low bits of the PCI base
107 * to the resource type
108 */
109 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
110 {
111 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
112 return IORESOURCE_IO;
113
114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
115 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
116
117 return IORESOURCE_MEM;
118 }
119
120 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
121 {
122 u64 size = mask & maxbase; /* Find the significant bits */
123 if (!size)
124 return 0;
125
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size = (size & ~(size-1)) - 1;
129
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base == maxbase && ((base | size) & mask) != mask)
133 return 0;
134
135 return size;
136 }
137
138 enum pci_bar_type {
139 pci_bar_unknown, /* Standard PCI BAR probe */
140 pci_bar_io, /* An io port BAR */
141 pci_bar_mem32, /* A 32-bit memory BAR */
142 pci_bar_mem64, /* A 64-bit memory BAR */
143 };
144
145 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
146 {
147 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
148 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
149 return pci_bar_io;
150 }
151
152 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
153
154 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
155 return pci_bar_mem64;
156 return pci_bar_mem32;
157 }
158
159 /*
160 * If the type is not unknown, we assume that the lowest bit is 'enable'.
161 * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
162 */
163 static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
164 struct resource *res, unsigned int pos)
165 {
166 u32 l, sz, mask;
167
168 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
169
170 res->name = pci_name(dev);
171
172 pci_read_config_dword(dev, pos, &l);
173 pci_write_config_dword(dev, pos, mask);
174 pci_read_config_dword(dev, pos, &sz);
175 pci_write_config_dword(dev, pos, l);
176
177 /*
178 * All bits set in sz means the device isn't working properly.
179 * If the BAR isn't implemented, all bits must be 0. If it's a
180 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
181 * 1 must be clear.
182 */
183 if (!sz || sz == 0xffffffff)
184 goto fail;
185
186 /*
187 * I don't know how l can have all bits set. Copied from old code.
188 * Maybe it fixes a bug on some ancient platform.
189 */
190 if (l == 0xffffffff)
191 l = 0;
192
193 if (type == pci_bar_unknown) {
194 type = decode_bar(res, l);
195 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
196 if (type == pci_bar_io) {
197 l &= PCI_BASE_ADDRESS_IO_MASK;
198 mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
199 } else {
200 l &= PCI_BASE_ADDRESS_MEM_MASK;
201 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
202 }
203 } else {
204 res->flags |= (l & IORESOURCE_ROM_ENABLE);
205 l &= PCI_ROM_ADDRESS_MASK;
206 mask = (u32)PCI_ROM_ADDRESS_MASK;
207 }
208
209 if (type == pci_bar_mem64) {
210 u64 l64 = l;
211 u64 sz64 = sz;
212 u64 mask64 = mask | (u64)~0 << 32;
213
214 pci_read_config_dword(dev, pos + 4, &l);
215 pci_write_config_dword(dev, pos + 4, ~0);
216 pci_read_config_dword(dev, pos + 4, &sz);
217 pci_write_config_dword(dev, pos + 4, l);
218
219 l64 |= ((u64)l << 32);
220 sz64 |= ((u64)sz << 32);
221
222 sz64 = pci_size(l64, sz64, mask64);
223
224 if (!sz64)
225 goto fail;
226
227 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
228 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
229 goto fail;
230 } else if ((sizeof(resource_size_t) < 8) && l) {
231 /* Address above 32-bit boundary; disable the BAR */
232 pci_write_config_dword(dev, pos, 0);
233 pci_write_config_dword(dev, pos + 4, 0);
234 res->start = 0;
235 res->end = sz64;
236 } else {
237 res->start = l64;
238 res->end = l64 + sz64;
239 dev_printk(KERN_DEBUG, &dev->dev,
240 "reg %x 64bit mmio: %pR\n", pos, res);
241 }
242 } else {
243 sz = pci_size(l, sz, mask);
244
245 if (!sz)
246 goto fail;
247
248 res->start = l;
249 res->end = l + sz;
250
251 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos,
252 (res->flags & IORESOURCE_IO) ? "io port" : "32bit mmio",
253 res);
254 }
255
256 out:
257 return (type == pci_bar_mem64) ? 1 : 0;
258 fail:
259 res->flags = 0;
260 goto out;
261 }
262
263 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
264 {
265 unsigned int pos, reg;
266
267 for (pos = 0; pos < howmany; pos++) {
268 struct resource *res = &dev->resource[pos];
269 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
270 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
271 }
272
273 if (rom) {
274 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
275 dev->rom_base_reg = rom;
276 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
277 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
278 IORESOURCE_SIZEALIGN;
279 __pci_read_base(dev, pci_bar_mem32, res, rom);
280 }
281 }
282
283 void __devinit pci_read_bridge_bases(struct pci_bus *child)
284 {
285 struct pci_dev *dev = child->self;
286 u8 io_base_lo, io_limit_lo;
287 u16 mem_base_lo, mem_limit_lo;
288 unsigned long base, limit;
289 struct resource *res;
290 int i;
291
292 if (!dev) /* It's a host bus, nothing to read */
293 return;
294
295 if (dev->transparent) {
296 dev_info(&dev->dev, "transparent bridge\n");
297 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
298 child->resource[i] = child->parent->resource[i - 3];
299 }
300
301 res = child->resource[0];
302 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
303 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
304 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
305 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
306
307 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
308 u16 io_base_hi, io_limit_hi;
309 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
310 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
311 base |= (io_base_hi << 16);
312 limit |= (io_limit_hi << 16);
313 }
314
315 if (base <= limit) {
316 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
317 if (!res->start)
318 res->start = base;
319 if (!res->end)
320 res->end = limit + 0xfff;
321 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
322 }
323
324 res = child->resource[1];
325 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
326 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
327 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
328 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
329 if (base <= limit) {
330 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
331 res->start = base;
332 res->end = limit + 0xfffff;
333 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n",
334 res);
335 }
336
337 res = child->resource[2];
338 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
339 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
340 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
341 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
342
343 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
344 u32 mem_base_hi, mem_limit_hi;
345 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
346 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
347
348 /*
349 * Some bridges set the base > limit by default, and some
350 * (broken) BIOSes do not initialize them. If we find
351 * this, just assume they are not being used.
352 */
353 if (mem_base_hi <= mem_limit_hi) {
354 #if BITS_PER_LONG == 64
355 base |= ((long) mem_base_hi) << 32;
356 limit |= ((long) mem_limit_hi) << 32;
357 #else
358 if (mem_base_hi || mem_limit_hi) {
359 dev_err(&dev->dev, "can't handle 64-bit "
360 "address space for bridge\n");
361 return;
362 }
363 #endif
364 }
365 }
366 if (base <= limit) {
367 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
368 res->start = base;
369 res->end = limit + 0xfffff;
370 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
371 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
372 res);
373 }
374 }
375
376 static struct pci_bus * pci_alloc_bus(void)
377 {
378 struct pci_bus *b;
379
380 b = kzalloc(sizeof(*b), GFP_KERNEL);
381 if (b) {
382 INIT_LIST_HEAD(&b->node);
383 INIT_LIST_HEAD(&b->children);
384 INIT_LIST_HEAD(&b->devices);
385 INIT_LIST_HEAD(&b->slots);
386 }
387 return b;
388 }
389
390 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
391 struct pci_dev *bridge, int busnr)
392 {
393 struct pci_bus *child;
394 int i;
395
396 /*
397 * Allocate a new bus, and inherit stuff from the parent..
398 */
399 child = pci_alloc_bus();
400 if (!child)
401 return NULL;
402
403 child->self = bridge;
404 child->parent = parent;
405 child->ops = parent->ops;
406 child->sysdata = parent->sysdata;
407 child->bus_flags = parent->bus_flags;
408 child->bridge = get_device(&bridge->dev);
409
410 /* initialize some portions of the bus device, but don't register it
411 * now as the parent is not properly set up yet. This device will get
412 * registered later in pci_bus_add_devices()
413 */
414 child->dev.class = &pcibus_class;
415 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
416
417 /*
418 * Set up the primary, secondary and subordinate
419 * bus numbers.
420 */
421 child->number = child->secondary = busnr;
422 child->primary = parent->secondary;
423 child->subordinate = 0xff;
424
425 /* Set up default resource pointers and names.. */
426 for (i = 0; i < 4; i++) {
427 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
428 child->resource[i]->name = child->name;
429 }
430 bridge->subordinate = child;
431
432 return child;
433 }
434
435 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
436 {
437 struct pci_bus *child;
438
439 child = pci_alloc_child_bus(parent, dev, busnr);
440 if (child) {
441 down_write(&pci_bus_sem);
442 list_add_tail(&child->node, &parent->children);
443 up_write(&pci_bus_sem);
444 }
445 return child;
446 }
447
448 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
449 {
450 struct pci_bus *parent = child->parent;
451
452 /* Attempts to fix that up are really dangerous unless
453 we're going to re-assign all bus numbers. */
454 if (!pcibios_assign_all_busses())
455 return;
456
457 while (parent->parent && parent->subordinate < max) {
458 parent->subordinate = max;
459 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
460 parent = parent->parent;
461 }
462 }
463
464 /*
465 * If it's a bridge, configure it and scan the bus behind it.
466 * For CardBus bridges, we don't scan behind as the devices will
467 * be handled by the bridge driver itself.
468 *
469 * We need to process bridges in two passes -- first we scan those
470 * already configured by the BIOS and after we are done with all of
471 * them, we proceed to assigning numbers to the remaining buses in
472 * order to avoid overlaps between old and new bus numbers.
473 */
474 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
475 {
476 struct pci_bus *child;
477 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
478 u32 buses, i, j = 0;
479 u16 bctl;
480 int broken = 0;
481
482 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
483
484 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
485 buses & 0xffffff, pass);
486
487 /* Check if setup is sensible at all */
488 if (!pass &&
489 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
490 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
491 broken = 1;
492 }
493
494 /* Disable MasterAbortMode during probing to avoid reporting
495 of bus errors (in some architectures) */
496 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
497 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
498 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
499
500 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
501 unsigned int cmax, busnr;
502 /*
503 * Bus already configured by firmware, process it in the first
504 * pass and just note the configuration.
505 */
506 if (pass)
507 goto out;
508 busnr = (buses >> 8) & 0xFF;
509
510 /*
511 * If we already got to this bus through a different bridge,
512 * ignore it. This can happen with the i450NX chipset.
513 */
514 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
515 dev_info(&dev->dev, "bus %04x:%02x already known\n",
516 pci_domain_nr(bus), busnr);
517 goto out;
518 }
519
520 child = pci_add_new_bus(bus, dev, busnr);
521 if (!child)
522 goto out;
523 child->primary = buses & 0xFF;
524 child->subordinate = (buses >> 16) & 0xFF;
525 child->bridge_ctl = bctl;
526
527 cmax = pci_scan_child_bus(child);
528 if (cmax > max)
529 max = cmax;
530 if (child->subordinate > max)
531 max = child->subordinate;
532 } else {
533 /*
534 * We need to assign a number to this bus which we always
535 * do in the second pass.
536 */
537 if (!pass) {
538 if (pcibios_assign_all_busses() || broken)
539 /* Temporarily disable forwarding of the
540 configuration cycles on all bridges in
541 this bus segment to avoid possible
542 conflicts in the second pass between two
543 bridges programmed with overlapping
544 bus ranges. */
545 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
546 buses & ~0xffffff);
547 goto out;
548 }
549
550 /* Clear errors */
551 pci_write_config_word(dev, PCI_STATUS, 0xffff);
552
553 /* Prevent assigning a bus number that already exists.
554 * This can happen when a bridge is hot-plugged */
555 if (pci_find_bus(pci_domain_nr(bus), max+1))
556 goto out;
557 child = pci_add_new_bus(bus, dev, ++max);
558 buses = (buses & 0xff000000)
559 | ((unsigned int)(child->primary) << 0)
560 | ((unsigned int)(child->secondary) << 8)
561 | ((unsigned int)(child->subordinate) << 16);
562
563 /*
564 * yenta.c forces a secondary latency timer of 176.
565 * Copy that behaviour here.
566 */
567 if (is_cardbus) {
568 buses &= ~0xff000000;
569 buses |= CARDBUS_LATENCY_TIMER << 24;
570 }
571
572 /*
573 * We need to blast all three values with a single write.
574 */
575 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
576
577 if (!is_cardbus) {
578 child->bridge_ctl = bctl;
579 /*
580 * Adjust subordinate busnr in parent buses.
581 * We do this before scanning for children because
582 * some devices may not be detected if the bios
583 * was lazy.
584 */
585 pci_fixup_parent_subordinate_busnr(child, max);
586 /* Now we can scan all subordinate buses... */
587 max = pci_scan_child_bus(child);
588 /*
589 * now fix it up again since we have found
590 * the real value of max.
591 */
592 pci_fixup_parent_subordinate_busnr(child, max);
593 } else {
594 /*
595 * For CardBus bridges, we leave 4 bus numbers
596 * as cards with a PCI-to-PCI bridge can be
597 * inserted later.
598 */
599 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
600 struct pci_bus *parent = bus;
601 if (pci_find_bus(pci_domain_nr(bus),
602 max+i+1))
603 break;
604 while (parent->parent) {
605 if ((!pcibios_assign_all_busses()) &&
606 (parent->subordinate > max) &&
607 (parent->subordinate <= max+i)) {
608 j = 1;
609 }
610 parent = parent->parent;
611 }
612 if (j) {
613 /*
614 * Often, there are two cardbus bridges
615 * -- try to leave one valid bus number
616 * for each one.
617 */
618 i /= 2;
619 break;
620 }
621 }
622 max += i;
623 pci_fixup_parent_subordinate_busnr(child, max);
624 }
625 /*
626 * Set the subordinate bus number to its real value.
627 */
628 child->subordinate = max;
629 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
630 }
631
632 sprintf(child->name,
633 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
634 pci_domain_nr(bus), child->number);
635
636 /* Has only triggered on CardBus, fixup is in yenta_socket */
637 while (bus->parent) {
638 if ((child->subordinate > bus->subordinate) ||
639 (child->number > bus->subordinate) ||
640 (child->number < bus->number) ||
641 (child->subordinate < bus->number)) {
642 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
643 "hidden behind%s bridge #%02x (-#%02x)\n",
644 child->number, child->subordinate,
645 (bus->number > child->subordinate &&
646 bus->subordinate < child->number) ?
647 "wholly" : "partially",
648 bus->self->transparent ? " transparent" : "",
649 bus->number, bus->subordinate);
650 }
651 bus = bus->parent;
652 }
653
654 out:
655 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
656
657 return max;
658 }
659
660 /*
661 * Read interrupt line and base address registers.
662 * The architecture-dependent code can tweak these, of course.
663 */
664 static void pci_read_irq(struct pci_dev *dev)
665 {
666 unsigned char irq;
667
668 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
669 dev->pin = irq;
670 if (irq)
671 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
672 dev->irq = irq;
673 }
674
675 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
676
677 /**
678 * pci_setup_device - fill in class and map information of a device
679 * @dev: the device structure to fill
680 *
681 * Initialize the device structure with information about the device's
682 * vendor,class,memory and IO-space addresses,IRQ lines etc.
683 * Called at initialisation of the PCI subsystem and by CardBus services.
684 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
685 * or CardBus).
686 */
687 static int pci_setup_device(struct pci_dev * dev)
688 {
689 u32 class;
690
691 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
692 dev->bus->number, PCI_SLOT(dev->devfn),
693 PCI_FUNC(dev->devfn));
694
695 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
696 dev->revision = class & 0xff;
697 class >>= 8; /* upper 3 bytes */
698 dev->class = class;
699 class >>= 8;
700
701 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
702 dev->vendor, dev->device, class, dev->hdr_type);
703
704 /* "Unknown power state" */
705 dev->current_state = PCI_UNKNOWN;
706
707 /* Early fixups, before probing the BARs */
708 pci_fixup_device(pci_fixup_early, dev);
709 class = dev->class >> 8;
710
711 switch (dev->hdr_type) { /* header type */
712 case PCI_HEADER_TYPE_NORMAL: /* standard header */
713 if (class == PCI_CLASS_BRIDGE_PCI)
714 goto bad;
715 pci_read_irq(dev);
716 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
717 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
718 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
719
720 /*
721 * Do the ugly legacy mode stuff here rather than broken chip
722 * quirk code. Legacy mode ATA controllers have fixed
723 * addresses. These are not always echoed in BAR0-3, and
724 * BAR0-3 in a few cases contain junk!
725 */
726 if (class == PCI_CLASS_STORAGE_IDE) {
727 u8 progif;
728 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
729 if ((progif & 1) == 0) {
730 dev->resource[0].start = 0x1F0;
731 dev->resource[0].end = 0x1F7;
732 dev->resource[0].flags = LEGACY_IO_RESOURCE;
733 dev->resource[1].start = 0x3F6;
734 dev->resource[1].end = 0x3F6;
735 dev->resource[1].flags = LEGACY_IO_RESOURCE;
736 }
737 if ((progif & 4) == 0) {
738 dev->resource[2].start = 0x170;
739 dev->resource[2].end = 0x177;
740 dev->resource[2].flags = LEGACY_IO_RESOURCE;
741 dev->resource[3].start = 0x376;
742 dev->resource[3].end = 0x376;
743 dev->resource[3].flags = LEGACY_IO_RESOURCE;
744 }
745 }
746 break;
747
748 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
749 if (class != PCI_CLASS_BRIDGE_PCI)
750 goto bad;
751 /* The PCI-to-PCI bridge spec requires that subtractive
752 decoding (i.e. transparent) bridge must have programming
753 interface code of 0x01. */
754 pci_read_irq(dev);
755 dev->transparent = ((dev->class & 0xff) == 1);
756 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
757 break;
758
759 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
760 if (class != PCI_CLASS_BRIDGE_CARDBUS)
761 goto bad;
762 pci_read_irq(dev);
763 pci_read_bases(dev, 1, 0);
764 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
765 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
766 break;
767
768 default: /* unknown header */
769 dev_err(&dev->dev, "unknown header type %02x, "
770 "ignoring device\n", dev->hdr_type);
771 return -1;
772
773 bad:
774 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
775 "type %02x)\n", class, dev->hdr_type);
776 dev->class = PCI_CLASS_NOT_DEFINED;
777 }
778
779 /* We found a fine healthy device, go go go... */
780 return 0;
781 }
782
783 static void pci_release_capabilities(struct pci_dev *dev)
784 {
785 pci_vpd_release(dev);
786 }
787
788 /**
789 * pci_release_dev - free a pci device structure when all users of it are finished.
790 * @dev: device that's been disconnected
791 *
792 * Will be called only by the device core when all users of this pci device are
793 * done.
794 */
795 static void pci_release_dev(struct device *dev)
796 {
797 struct pci_dev *pci_dev;
798
799 pci_dev = to_pci_dev(dev);
800 pci_release_capabilities(pci_dev);
801 kfree(pci_dev);
802 }
803
804 static void set_pcie_port_type(struct pci_dev *pdev)
805 {
806 int pos;
807 u16 reg16;
808
809 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
810 if (!pos)
811 return;
812 pdev->is_pcie = 1;
813 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
814 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
815 }
816
817 /**
818 * pci_cfg_space_size - get the configuration space size of the PCI device.
819 * @dev: PCI device
820 *
821 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
822 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
823 * access it. Maybe we don't have a way to generate extended config space
824 * accesses, or the device is behind a reverse Express bridge. So we try
825 * reading the dword at 0x100 which must either be 0 or a valid extended
826 * capability header.
827 */
828 int pci_cfg_space_size_ext(struct pci_dev *dev)
829 {
830 u32 status;
831 int pos = PCI_CFG_SPACE_SIZE;
832
833 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
834 goto fail;
835 if (status == 0xffffffff)
836 goto fail;
837
838 return PCI_CFG_SPACE_EXP_SIZE;
839
840 fail:
841 return PCI_CFG_SPACE_SIZE;
842 }
843
844 int pci_cfg_space_size(struct pci_dev *dev)
845 {
846 int pos;
847 u32 status;
848
849 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
850 if (!pos) {
851 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
852 if (!pos)
853 goto fail;
854
855 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
856 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
857 goto fail;
858 }
859
860 return pci_cfg_space_size_ext(dev);
861
862 fail:
863 return PCI_CFG_SPACE_SIZE;
864 }
865
866 static void pci_release_bus_bridge_dev(struct device *dev)
867 {
868 kfree(dev);
869 }
870
871 struct pci_dev *alloc_pci_dev(void)
872 {
873 struct pci_dev *dev;
874
875 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
876 if (!dev)
877 return NULL;
878
879 INIT_LIST_HEAD(&dev->bus_list);
880
881 return dev;
882 }
883 EXPORT_SYMBOL(alloc_pci_dev);
884
885 /*
886 * Read the config data for a PCI device, sanity-check it
887 * and fill in the dev structure...
888 */
889 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
890 {
891 struct pci_dev *dev;
892 struct pci_slot *slot;
893 u32 l;
894 u8 hdr_type;
895 int delay = 1;
896
897 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
898 return NULL;
899
900 /* some broken boards return 0 or ~0 if a slot is empty: */
901 if (l == 0xffffffff || l == 0x00000000 ||
902 l == 0x0000ffff || l == 0xffff0000)
903 return NULL;
904
905 /* Configuration request Retry Status */
906 while (l == 0xffff0001) {
907 msleep(delay);
908 delay *= 2;
909 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
910 return NULL;
911 /* Card hasn't responded in 60 seconds? Must be stuck. */
912 if (delay > 60 * 1000) {
913 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
914 "responding\n", pci_domain_nr(bus),
915 bus->number, PCI_SLOT(devfn),
916 PCI_FUNC(devfn));
917 return NULL;
918 }
919 }
920
921 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
922 return NULL;
923
924 dev = alloc_pci_dev();
925 if (!dev)
926 return NULL;
927
928 dev->bus = bus;
929 dev->sysdata = bus->sysdata;
930 dev->dev.parent = bus->bridge;
931 dev->dev.bus = &pci_bus_type;
932 dev->devfn = devfn;
933 dev->hdr_type = hdr_type & 0x7f;
934 dev->multifunction = !!(hdr_type & 0x80);
935 dev->vendor = l & 0xffff;
936 dev->device = (l >> 16) & 0xffff;
937 dev->cfg_size = pci_cfg_space_size(dev);
938 dev->error_state = pci_channel_io_normal;
939 set_pcie_port_type(dev);
940
941 list_for_each_entry(slot, &bus->slots, list)
942 if (PCI_SLOT(devfn) == slot->number)
943 dev->slot = slot;
944
945 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
946 set this higher, assuming the system even supports it. */
947 dev->dma_mask = 0xffffffff;
948 if (pci_setup_device(dev) < 0) {
949 kfree(dev);
950 return NULL;
951 }
952
953 return dev;
954 }
955
956 static void pci_init_capabilities(struct pci_dev *dev)
957 {
958 /* MSI/MSI-X list */
959 pci_msi_init_pci_dev(dev);
960
961 /* Power Management */
962 pci_pm_init(dev);
963
964 /* Vital Product Data */
965 pci_vpd_pci22_init(dev);
966
967 /* Alternative Routing-ID Forwarding */
968 pci_enable_ari(dev);
969 }
970
971 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
972 {
973 device_initialize(&dev->dev);
974 dev->dev.release = pci_release_dev;
975 pci_dev_get(dev);
976
977 dev->dev.dma_mask = &dev->dma_mask;
978 dev->dev.dma_parms = &dev->dma_parms;
979 dev->dev.coherent_dma_mask = 0xffffffffull;
980
981 pci_set_dma_max_seg_size(dev, 65536);
982 pci_set_dma_seg_boundary(dev, 0xffffffff);
983
984 /* Fix up broken headers */
985 pci_fixup_device(pci_fixup_header, dev);
986
987 /* Initialize various capabilities */
988 pci_init_capabilities(dev);
989
990 /*
991 * Add the device to our list of discovered devices
992 * and the bus list for fixup functions, etc.
993 */
994 down_write(&pci_bus_sem);
995 list_add_tail(&dev->bus_list, &bus->devices);
996 up_write(&pci_bus_sem);
997 }
998
999 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1000 {
1001 struct pci_dev *dev;
1002
1003 dev = pci_scan_device(bus, devfn);
1004 if (!dev)
1005 return NULL;
1006
1007 pci_device_add(dev, bus);
1008
1009 return dev;
1010 }
1011 EXPORT_SYMBOL(pci_scan_single_device);
1012
1013 /**
1014 * pci_scan_slot - scan a PCI slot on a bus for devices.
1015 * @bus: PCI bus to scan
1016 * @devfn: slot number to scan (must have zero function.)
1017 *
1018 * Scan a PCI slot on the specified PCI bus for devices, adding
1019 * discovered devices to the @bus->devices list. New devices
1020 * will not have is_added set.
1021 */
1022 int pci_scan_slot(struct pci_bus *bus, int devfn)
1023 {
1024 int func, nr = 0;
1025 int scan_all_fns;
1026
1027 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
1028
1029 for (func = 0; func < 8; func++, devfn++) {
1030 struct pci_dev *dev;
1031
1032 dev = pci_scan_single_device(bus, devfn);
1033 if (dev) {
1034 nr++;
1035
1036 /*
1037 * If this is a single function device,
1038 * don't scan past the first function.
1039 */
1040 if (!dev->multifunction) {
1041 if (func > 0) {
1042 dev->multifunction = 1;
1043 } else {
1044 break;
1045 }
1046 }
1047 } else {
1048 if (func == 0 && !scan_all_fns)
1049 break;
1050 }
1051 }
1052
1053 /* only one slot has pcie device */
1054 if (bus->self && nr)
1055 pcie_aspm_init_link_state(bus->self);
1056
1057 return nr;
1058 }
1059
1060 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1061 {
1062 unsigned int devfn, pass, max = bus->secondary;
1063 struct pci_dev *dev;
1064
1065 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1066
1067 /* Go find them, Rover! */
1068 for (devfn = 0; devfn < 0x100; devfn += 8)
1069 pci_scan_slot(bus, devfn);
1070
1071 /*
1072 * After performing arch-dependent fixup of the bus, look behind
1073 * all PCI-to-PCI bridges on this bus.
1074 */
1075 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1076 pcibios_fixup_bus(bus);
1077 for (pass=0; pass < 2; pass++)
1078 list_for_each_entry(dev, &bus->devices, bus_list) {
1079 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1080 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1081 max = pci_scan_bridge(bus, dev, max, pass);
1082 }
1083
1084 /*
1085 * We've scanned the bus and so we know all about what's on
1086 * the other side of any bridges that may be on this bus plus
1087 * any devices.
1088 *
1089 * Return how far we've got finding sub-buses.
1090 */
1091 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1092 pci_domain_nr(bus), bus->number, max);
1093 return max;
1094 }
1095
1096 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
1097 {
1098 }
1099
1100 struct pci_bus * pci_create_bus(struct device *parent,
1101 int bus, struct pci_ops *ops, void *sysdata)
1102 {
1103 int error;
1104 struct pci_bus *b;
1105 struct device *dev;
1106
1107 b = pci_alloc_bus();
1108 if (!b)
1109 return NULL;
1110
1111 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1112 if (!dev){
1113 kfree(b);
1114 return NULL;
1115 }
1116
1117 b->sysdata = sysdata;
1118 b->ops = ops;
1119
1120 if (pci_find_bus(pci_domain_nr(b), bus)) {
1121 /* If we already got to this bus through a different bridge, ignore it */
1122 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1123 goto err_out;
1124 }
1125
1126 down_write(&pci_bus_sem);
1127 list_add_tail(&b->node, &pci_root_buses);
1128 up_write(&pci_bus_sem);
1129
1130 memset(dev, 0, sizeof(*dev));
1131 dev->parent = parent;
1132 dev->release = pci_release_bus_bridge_dev;
1133 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1134 error = device_register(dev);
1135 if (error)
1136 goto dev_reg_err;
1137 b->bridge = get_device(dev);
1138
1139 if (!parent)
1140 set_dev_node(b->bridge, pcibus_to_node(b));
1141
1142 b->dev.class = &pcibus_class;
1143 b->dev.parent = b->bridge;
1144 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1145 error = device_register(&b->dev);
1146 if (error)
1147 goto class_dev_reg_err;
1148 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1149 if (error)
1150 goto dev_create_file_err;
1151
1152 /* Create legacy_io and legacy_mem files for this bus */
1153 pci_create_legacy_files(b);
1154
1155 b->number = b->secondary = bus;
1156 b->resource[0] = &ioport_resource;
1157 b->resource[1] = &iomem_resource;
1158
1159 set_pci_bus_resources_arch_default(b);
1160
1161 return b;
1162
1163 dev_create_file_err:
1164 device_unregister(&b->dev);
1165 class_dev_reg_err:
1166 device_unregister(dev);
1167 dev_reg_err:
1168 down_write(&pci_bus_sem);
1169 list_del(&b->node);
1170 up_write(&pci_bus_sem);
1171 err_out:
1172 kfree(dev);
1173 kfree(b);
1174 return NULL;
1175 }
1176
1177 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1178 int bus, struct pci_ops *ops, void *sysdata)
1179 {
1180 struct pci_bus *b;
1181
1182 b = pci_create_bus(parent, bus, ops, sysdata);
1183 if (b)
1184 b->subordinate = pci_scan_child_bus(b);
1185 return b;
1186 }
1187 EXPORT_SYMBOL(pci_scan_bus_parented);
1188
1189 #ifdef CONFIG_HOTPLUG
1190 EXPORT_SYMBOL(pci_add_new_bus);
1191 EXPORT_SYMBOL(pci_scan_slot);
1192 EXPORT_SYMBOL(pci_scan_bridge);
1193 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1194 #endif
1195
1196 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1197 {
1198 const struct pci_dev *a = to_pci_dev(d_a);
1199 const struct pci_dev *b = to_pci_dev(d_b);
1200
1201 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1202 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1203
1204 if (a->bus->number < b->bus->number) return -1;
1205 else if (a->bus->number > b->bus->number) return 1;
1206
1207 if (a->devfn < b->devfn) return -1;
1208 else if (a->devfn > b->devfn) return 1;
1209
1210 return 0;
1211 }
1212
1213 void __init pci_sort_breadthfirst(void)
1214 {
1215 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1216 }
Support for the Chinese Samsung S3C2440 based development boards