drivers/net/sfc/mdio_10g.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2006-2008 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9 /*
  10  * Useful functions for working with MDIO clause 45 PHYs
  11  */
  12 #include <linux/types.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/delay.h>
  15 #include "net_driver.h"
  16 #include "mdio_10g.h"
  17 #include "boards.h"
  18 #include "workarounds.h"
  19
  20 int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd,
  21                             int spins, int spintime)
  22 {
  23         u32 ctrl;
  24         int phy_id = port->mii.phy_id;
  25
  26         /* Catch callers passing values in the wrong units (or just silly) */
  27         EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
  28
  29         mdio_clause45_write(port, phy_id, mmd, MDIO_MMDREG_CTRL1,
  30                             (1 << MDIO_MMDREG_CTRL1_RESET_LBN));
  31         /* Wait for the reset bit to clear. */
  32         do {
  33                 msleep(spintime);
  34                 ctrl = mdio_clause45_read(port, phy_id, mmd, MDIO_MMDREG_CTRL1);
  35                 spins--;
  36
  37         } while (spins && (ctrl & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)));
  38
  39         return spins ? spins : -ETIMEDOUT;
  40 }
  41
  42 static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
  43                                    int fault_fatal)
  44 {
  45         int status;
  46         int phy_id = efx->mii.phy_id;
  47
  48         if (LOOPBACK_INTERNAL(efx))
  49                 return 0;
  50
  51         if (mmd != MDIO_MMD_AN) {
  52                 /* Read MMD STATUS2 to check it is responding. */
  53                 status = mdio_clause45_read(efx, phy_id, mmd,
  54                                             MDIO_MMDREG_STAT2);
  55                 if (((status >> MDIO_MMDREG_STAT2_PRESENT_LBN) &
  56                      ((1 << MDIO_MMDREG_STAT2_PRESENT_WIDTH) - 1)) !=
  57                     MDIO_MMDREG_STAT2_PRESENT_VAL) {
  58                         EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
  59                         return -EIO;
  60                 }
  61         }
  62
  63         /* Read MMD STATUS 1 to check for fault. */
  64         status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT1);
  65         if ((status & (1 << MDIO_MMDREG_STAT1_FAULT_LBN)) != 0) {
  66                 if (fault_fatal) {
  67                         EFX_ERR(efx, "PHY MMD %d reporting fatal"
  68                                 " fault: status %x\n", mmd, status);
  69                         return -EIO;
  70                 } else {
  71                         EFX_LOG(efx, "PHY MMD %d reporting status"
  72                                 " %x (expected)\n", mmd, status);
  73                 }
  74         }
  75         return 0;
  76 }
  77
  78 /* This ought to be ridiculous overkill. We expect it to fail rarely */
  79 #define MDIO45_RESET_TIME       1000 /* ms */
  80 #define MDIO45_RESET_ITERS      100
  81
  82 int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
  83                                   unsigned int mmd_mask)
  84 {
  85         const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
  86         int tries = MDIO45_RESET_ITERS;
  87         int rc = 0;
  88         int in_reset;
  89
  90         while (tries) {
  91                 int mask = mmd_mask;
  92                 int mmd = 0;
  93                 int stat;
  94                 in_reset = 0;
  95                 while (mask) {
  96                         if (mask & 1) {
  97                                 stat = mdio_clause45_read(efx,
  98                                                           efx->mii.phy_id,
  99                                                           mmd,
 100                                                           MDIO_MMDREG_CTRL1);
 101                                 if (stat < 0) {
 102                                         EFX_ERR(efx, "failed to read status of"
 103                                                 " MMD %d\n", mmd);
 104                                         return -EIO;
 105                                 }
 106                                 if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
 107                                         in_reset |= (1 << mmd);
 108                         }
 109                         mask = mask >> 1;
 110                         mmd++;
 111                 }
 112                 if (!in_reset)
 113                         break;
 114                 tries--;
 115                 msleep(spintime);
 116         }
 117         if (in_reset != 0) {
 118                 EFX_ERR(efx, "not all MMDs came out of reset in time."
 119                         " MMDs still in reset: %x\n", in_reset);
 120                 rc = -ETIMEDOUT;
 121         }
 122         return rc;
 123 }
 124
 125 int mdio_clause45_check_mmds(struct efx_nic *efx,
 126                              unsigned int mmd_mask, unsigned int fatal_mask)
 127 {
 128         u32 devices;
 129         int mmd = 0, probe_mmd;
 130
 131         /* Historically we have probed the PHYXS to find out what devices are
 132          * present,but that doesn't work so well if the PHYXS isn't expected
 133          * to exist, if so just find the first item in the list supplied. */
 134         probe_mmd = (mmd_mask & MDIO_MMDREG_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
 135             __ffs(mmd_mask);
 136         devices = (mdio_clause45_read(efx, efx->mii.phy_id,
 137                                       probe_mmd, MDIO_MMDREG_DEVS0) |
 138                    mdio_clause45_read(efx, efx->mii.phy_id,
 139                                       probe_mmd, MDIO_MMDREG_DEVS1) << 16);
 140
 141         /* Check all the expected MMDs are present */
 142         if (devices < 0) {
 143                 EFX_ERR(efx, "failed to read devices present\n");
 144                 return -EIO;
 145         }
 146         if ((devices & mmd_mask) != mmd_mask) {
 147                 EFX_ERR(efx, "required MMDs not present: got %x, "
 148                         "wanted %x\n", devices, mmd_mask);
 149                 return -ENODEV;
 150         }
 151         EFX_TRACE(efx, "Devices present: %x\n", devices);
 152
 153         /* Check all required MMDs are responding and happy. */
 154         while (mmd_mask) {
 155                 if (mmd_mask & 1) {
 156                         int fault_fatal = fatal_mask & 1;
 157                         if (mdio_clause45_check_mmd(efx, mmd, fault_fatal))
 158                                 return -EIO;
 159                 }
 160                 mmd_mask = mmd_mask >> 1;
 161                 fatal_mask = fatal_mask >> 1;
 162                 mmd++;
 163         }
 164
 165         return 0;
 166 }
 167
 168 bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
 169 {
 170         int phy_id = efx->mii.phy_id;
 171         u32 reg;
 172         bool ok = true;
 173         int mmd = 0;
 174
 175         /* If the port is in loopback, then we should only consider a subset
 176          * of mmd's */
 177         if (LOOPBACK_INTERNAL(efx))
 178                 return true;
 179         else if (efx->loopback_mode == LOOPBACK_NETWORK)
 180                 return false;
 181         else if (efx_phy_mode_disabled(efx->phy_mode))
 182                 return false;
 183         else if (efx->loopback_mode == LOOPBACK_PHYXS) {
 184                 mmd_mask &= ~(MDIO_MMDREG_DEVS_PHYXS |
 185                               MDIO_MMDREG_DEVS_PCS |
 186                               MDIO_MMDREG_DEVS_PMAPMD |
 187                               MDIO_MMDREG_DEVS_AN);
 188                 if (!mmd_mask) {
 189                         reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
 190                                                  MDIO_PHYXS_STATUS2);
 191                         return !(reg & (1 << MDIO_PHYXS_STATUS2_RX_FAULT_LBN));
 192                 }
 193         } else if (efx->loopback_mode == LOOPBACK_PCS)
 194                 mmd_mask &= ~(MDIO_MMDREG_DEVS_PCS |
 195                               MDIO_MMDREG_DEVS_PMAPMD |
 196                               MDIO_MMDREG_DEVS_AN);
 197         else if (efx->loopback_mode == LOOPBACK_PMAPMD)
 198                 mmd_mask &= ~(MDIO_MMDREG_DEVS_PMAPMD |
 199                               MDIO_MMDREG_DEVS_AN);
 200
 201         while (mmd_mask) {
 202                 if (mmd_mask & 1) {
 203                         /* Double reads because link state is latched, and a
 204                          * read moves the current state into the register */
 205                         reg = mdio_clause45_read(efx, phy_id,
 206                                                  mmd, MDIO_MMDREG_STAT1);
 207                         reg = mdio_clause45_read(efx, phy_id,
 208                                                  mmd, MDIO_MMDREG_STAT1);
 209                         ok = ok && (reg & (1 << MDIO_MMDREG_STAT1_LINK_LBN));
 210                 }
 211                 mmd_mask = (mmd_mask >> 1);
 212                 mmd++;
 213         }
 214         return ok;
 215 }
 216
 217 void mdio_clause45_transmit_disable(struct efx_nic *efx)
 218 {
 219         mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
 220                                MDIO_MMDREG_TXDIS, MDIO_MMDREG_TXDIS_GLOBAL_LBN,
 221                                efx->phy_mode & PHY_MODE_TX_DISABLED);
 222 }
 223
 224 void mdio_clause45_phy_reconfigure(struct efx_nic *efx)
 225 {
 226         int phy_id = efx->mii.phy_id;
 227
 228         mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
 229                                MDIO_MMDREG_CTRL1, MDIO_PMAPMD_CTRL1_LBACK_LBN,
 230                                efx->loopback_mode == LOOPBACK_PMAPMD);
 231         mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PCS,
 232                                MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
 233                                efx->loopback_mode == LOOPBACK_PCS);
 234         mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
 235                                MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
 236                                efx->loopback_mode == LOOPBACK_NETWORK);
 237 }
 238
 239 static void mdio_clause45_set_mmd_lpower(struct efx_nic *efx,
 240                                          int lpower, int mmd)
 241 {
 242         int phy = efx->mii.phy_id;
 243         int stat = mdio_clause45_read(efx, phy, mmd, MDIO_MMDREG_STAT1);
 244
 245         EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n",
 246                   mmd, lpower);
 247
 248         if (stat & (1 << MDIO_MMDREG_STAT1_LPABLE_LBN)) {
 249                 mdio_clause45_set_flag(efx, phy, mmd, MDIO_MMDREG_CTRL1,
 250                                        MDIO_MMDREG_CTRL1_LPOWER_LBN, lpower);
 251         }
 252 }
 253
 254 void mdio_clause45_set_mmds_lpower(struct efx_nic *efx,
 255                                    int low_power, unsigned int mmd_mask)
 256 {
 257         int mmd = 0;
 258         mmd_mask &= ~MDIO_MMDREG_DEVS_AN;
 259         while (mmd_mask) {
 260                 if (mmd_mask & 1)
 261                         mdio_clause45_set_mmd_lpower(efx, low_power, mmd);
 262                 mmd_mask = (mmd_mask >> 1);
 263                 mmd++;
 264         }
 265 }
 266
 267 static u32 mdio_clause45_get_an(struct efx_nic *efx, u16 addr, u32 xnp)
 268 {
 269         int phy_id = efx->mii.phy_id;
 270         u32 result = 0;
 271         int reg;
 272
 273         reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, addr);
 274         if (reg & ADVERTISE_10HALF)
 275                 result |= ADVERTISED_10baseT_Half;
 276         if (reg & ADVERTISE_10FULL)
 277                 result |= ADVERTISED_10baseT_Full;
 278         if (reg & ADVERTISE_100HALF)
 279                 result |= ADVERTISED_100baseT_Half;
 280         if (reg & ADVERTISE_100FULL)
 281                 result |= ADVERTISED_100baseT_Full;
 282         if (reg & LPA_RESV)
 283                 result |= xnp;
 284
 285         return result;
 286 }
 287
 288 /**
 289  * mdio_clause45_get_settings - Read (some of) the PHY settings over MDIO.
 290  * @efx:                Efx NIC
 291  * @ecmd:               Buffer for settings
 292  *
 293  * On return the 'port', 'speed', 'supported' and 'advertising' fields of
 294  * ecmd have been filled out.
 295  */
 296 void mdio_clause45_get_settings(struct efx_nic *efx,
 297                                 struct ethtool_cmd *ecmd)
 298 {
 299         mdio_clause45_get_settings_ext(efx, ecmd, 0, 0);
 300 }
 301
 302 /**
 303  * mdio_clause45_get_settings_ext - Read (some of) the PHY settings over MDIO.
 304  * @efx:                Efx NIC
 305  * @ecmd:               Buffer for settings
 306  * @xnp:                Advertised Extended Next Page state
 307  * @xnp_lpa:            Link Partner's advertised XNP state
 308  *
 309  * On return the 'port', 'speed', 'supported' and 'advertising' fields of
 310  * ecmd have been filled out.
 311  */
 312 void mdio_clause45_get_settings_ext(struct efx_nic *efx,
 313                                     struct ethtool_cmd *ecmd,
 314                                     u32 xnp, u32 xnp_lpa)
 315 {
 316         int phy_id = efx->mii.phy_id;
 317         int reg;
 318
 319         ecmd->transceiver = XCVR_INTERNAL;
 320         ecmd->phy_address = phy_id;
 321
 322         reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 323                                  MDIO_MMDREG_CTRL2);
 324         switch (reg & MDIO_PMAPMD_CTRL2_TYPE_MASK) {
 325         case MDIO_PMAPMD_CTRL2_10G_BT:
 326         case MDIO_PMAPMD_CTRL2_1G_BT:
 327         case MDIO_PMAPMD_CTRL2_100_BT:
 328         case MDIO_PMAPMD_CTRL2_10_BT:
 329                 ecmd->port = PORT_TP;
 330                 ecmd->supported = SUPPORTED_TP;
 331                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 332                                          MDIO_MMDREG_SPEED);
 333                 if (reg & (1 << MDIO_MMDREG_SPEED_10G_LBN))
 334                         ecmd->supported |= SUPPORTED_10000baseT_Full;
 335                 if (reg & (1 << MDIO_MMDREG_SPEED_1000M_LBN))
 336                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
 337                                             SUPPORTED_1000baseT_Half);
 338                 if (reg & (1 << MDIO_MMDREG_SPEED_100M_LBN))
 339                         ecmd->supported |= (SUPPORTED_100baseT_Full |
 340                                             SUPPORTED_100baseT_Half);
 341                 if (reg & (1 << MDIO_MMDREG_SPEED_10M_LBN))
 342                         ecmd->supported |= (SUPPORTED_10baseT_Full |
 343                                             SUPPORTED_10baseT_Half);
 344                 ecmd->advertising = ADVERTISED_TP;
 345                 break;
 346
 347         /* We represent CX4 as fibre in the absence of anything better */
 348         case MDIO_PMAPMD_CTRL2_10G_CX4:
 349         /* All the other defined modes are flavours of optical */
 350         default:
 351                 ecmd->port = PORT_FIBRE;
 352                 ecmd->supported = SUPPORTED_FIBRE;
 353                 ecmd->advertising = ADVERTISED_FIBRE;
 354                 break;
 355         }
 356
 357         if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
 358                 ecmd->supported |= SUPPORTED_Autoneg;
 359                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 360                                          MDIO_MMDREG_CTRL1);
 361                 if (reg & BMCR_ANENABLE) {
 362                         ecmd->autoneg = AUTONEG_ENABLE;
 363                         ecmd->advertising |=
 364                                 ADVERTISED_Autoneg |
 365                                 mdio_clause45_get_an(efx,
 366                                                      MDIO_AN_ADVERTISE, xnp);
 367                 } else
 368                         ecmd->autoneg = AUTONEG_DISABLE;
 369         } else
 370                 ecmd->autoneg = AUTONEG_DISABLE;
 371
 372         if (ecmd->autoneg) {
 373                 /* If AN is complete, report best common mode,
 374                  * otherwise report best advertised mode. */
 375                 u32 common = ecmd->advertising;
 376                 if (mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 377                                        MDIO_MMDREG_STAT1) &
 378                     (1 << MDIO_AN_STATUS_AN_DONE_LBN)) {
 379                         common &= mdio_clause45_get_an(efx, MDIO_AN_LPA,
 380                                                        xnp_lpa);
 381                 }
 382                 if (common & ADVERTISED_10000baseT_Full) {
 383                         ecmd->speed = SPEED_10000;
 384                         ecmd->duplex = DUPLEX_FULL;
 385                 } else if (common & (ADVERTISED_1000baseT_Full |
 386                                      ADVERTISED_1000baseT_Half)) {
 387                         ecmd->speed = SPEED_1000;
 388                         ecmd->duplex = !!(common & ADVERTISED_1000baseT_Full);
 389                 } else if (common & (ADVERTISED_100baseT_Full |
 390                                      ADVERTISED_100baseT_Half)) {
 391                         ecmd->speed = SPEED_100;
 392                         ecmd->duplex = !!(common & ADVERTISED_100baseT_Full);
 393                 } else {
 394                         ecmd->speed = SPEED_10;
 395                         ecmd->duplex = !!(common & ADVERTISED_10baseT_Full);
 396                 }
 397         } else {
 398                 /* Report forced settings */
 399                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 400                                          MDIO_MMDREG_CTRL1);
 401                 ecmd->speed = (((reg & BMCR_SPEED1000) ? 100 : 1) *
 402                                ((reg & BMCR_SPEED100) ? 100 : 10));
 403                 ecmd->duplex = (reg & BMCR_FULLDPLX ||
 404                                 ecmd->speed == SPEED_10000);
 405         }
 406 }
 407
 408 /**
 409  * mdio_clause45_set_settings - Set (some of) the PHY settings over MDIO.
 410  * @efx:                Efx NIC
 411  * @ecmd:               New settings
 412  */
 413 int mdio_clause45_set_settings(struct efx_nic *efx,
 414                                struct ethtool_cmd *ecmd)
 415 {
 416         int phy_id = efx->mii.phy_id;
 417         struct ethtool_cmd prev;
 418         u32 required;
 419         int ctrl1_bits, reg;
 420
 421         efx->phy_op->get_settings(efx, &prev);
 422
 423         if (ecmd->advertising == prev.advertising &&
 424             ecmd->speed == prev.speed &&
 425             ecmd->duplex == prev.duplex &&
 426             ecmd->port == prev.port &&
 427             ecmd->autoneg == prev.autoneg)
 428                 return 0;
 429
 430         /* We can only change these settings for -T PHYs */
 431         if (prev.port != PORT_TP || ecmd->port != PORT_TP)
 432                 return -EINVAL;
 433
 434         /* Check that PHY supports these settings and work out the
 435          * basic control bits */
 436         if (ecmd->duplex) {
 437                 switch (ecmd->speed) {
 438                 case SPEED_10:
 439                         ctrl1_bits = BMCR_FULLDPLX;
 440                         required = SUPPORTED_10baseT_Full;
 441                         break;
 442                 case SPEED_100:
 443                         ctrl1_bits = BMCR_SPEED100 | BMCR_FULLDPLX;
 444                         required = SUPPORTED_100baseT_Full;
 445                         break;
 446                 case SPEED_1000:
 447                         ctrl1_bits = BMCR_SPEED1000 | BMCR_FULLDPLX;
 448                         required = SUPPORTED_1000baseT_Full;
 449                         break;
 450                 case SPEED_10000:
 451                         ctrl1_bits = (BMCR_SPEED1000 | BMCR_SPEED100 |
 452                                       BMCR_FULLDPLX);
 453                         required = SUPPORTED_10000baseT_Full;
 454                         break;
 455                 default:
 456                         return -EINVAL;
 457                 }
 458         } else {
 459                 switch (ecmd->speed) {
 460                 case SPEED_10:
 461                         ctrl1_bits = 0;
 462                         required = SUPPORTED_10baseT_Half;
 463                         break;
 464                 case SPEED_100:
 465                         ctrl1_bits = BMCR_SPEED100;
 466                         required = SUPPORTED_100baseT_Half;
 467                         break;
 468                 case SPEED_1000:
 469                         ctrl1_bits = BMCR_SPEED1000;
 470                         required = SUPPORTED_1000baseT_Half;
 471                         break;
 472                 default:
 473                         return -EINVAL;
 474                 }
 475         }
 476         if (ecmd->autoneg)
 477                 required |= SUPPORTED_Autoneg;
 478         required |= ecmd->advertising;
 479         if (required & ~prev.supported)
 480                 return -EINVAL;
 481
 482         /* Set the basic control bits */
 483         reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
 484                                  MDIO_MMDREG_CTRL1);
 485         reg &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX | 0x003c);
 486         reg |= ctrl1_bits;
 487         mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, MDIO_MMDREG_CTRL1,
 488                             reg);
 489
 490         /* Set the AN registers */
 491         if (ecmd->autoneg != prev.autoneg ||
 492             ecmd->advertising != prev.advertising) {
 493                 bool xnp = false;
 494
 495                 if (efx->phy_op->set_xnp_advertise)
 496                         xnp = efx->phy_op->set_xnp_advertise(efx,
 497                                                              ecmd->advertising);
 498
 499                 if (ecmd->autoneg) {
 500                         reg = 0;
 501                         if (ecmd->advertising & ADVERTISED_10baseT_Half)
 502                                 reg |= ADVERTISE_10HALF;
 503                         if (ecmd->advertising & ADVERTISED_10baseT_Full)
 504                                 reg |= ADVERTISE_10FULL;
 505                         if (ecmd->advertising & ADVERTISED_100baseT_Half)
 506                                 reg |= ADVERTISE_100HALF;
 507                         if (ecmd->advertising & ADVERTISED_100baseT_Full)
 508                                 reg |= ADVERTISE_100FULL;
 509                         if (xnp)
 510                                 reg |= ADVERTISE_RESV;
 511                         mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 512                                             MDIO_AN_ADVERTISE, reg);
 513                 }
 514
 515                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 516                                          MDIO_MMDREG_CTRL1);
 517                 if (ecmd->autoneg)
 518                         reg |= BMCR_ANENABLE | BMCR_ANRESTART;
 519                 else
 520                         reg &= ~BMCR_ANENABLE;
 521                 if (EFX_WORKAROUND_15195(efx)
 522                     && LOOPBACK_MASK(efx) & efx->phy_op->loopbacks)
 523                         reg &= ~BMCR_ANRESTART;
 524                 if (xnp)
 525                         reg |= 1 << MDIO_AN_CTRL_XNP_LBN;
 526                 else
 527                         reg &= ~(1 << MDIO_AN_CTRL_XNP_LBN);
 528                 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 529                                     MDIO_MMDREG_CTRL1, reg);
 530         }
 531
 532         return 0;
 533 }
 534
 535 void mdio_clause45_set_pause(struct efx_nic *efx)
 536 {
 537         int phy_id = efx->mii.phy_id;
 538         int reg;
 539
 540         if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
 541                 /* Set pause capability advertising */
 542                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 543                                          MDIO_AN_ADVERTISE);
 544                 reg &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 545                 reg |= efx_fc_advertise(efx->wanted_fc);
 546                 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 547                                     MDIO_AN_ADVERTISE, reg);
 548
 549                 /* Restart auto-negotiation */
 550                 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
 551                                          MDIO_MMDREG_CTRL1);
 552                 if (reg & BMCR_ANENABLE) {
 553                         reg |= BMCR_ANRESTART;
 554                         mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
 555                                             MDIO_MMDREG_CTRL1, reg);
 556                 }
 557         }
 558 }
 559
 560 enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx)
 561 {
 562         int phy_id = efx->mii.phy_id;
 563         int lpa;
 564
 565         if (!(efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)))
 566                 return efx->wanted_fc;
 567         lpa = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_LPA);
 568         return efx_fc_resolve(efx->wanted_fc, lpa);
 569 }
 570
 571 void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev,
 572                             u16 addr, int bit, bool sense)
 573 {
 574         int old_val = mdio_clause45_read(efx, prt, dev, addr);
 575         int new_val;
 576
 577         if (sense)
 578                 new_val = old_val | (1 << bit);
 579         else
 580                 new_val = old_val & ~(1 << bit);
 581         if (old_val != new_val)
 582                 mdio_clause45_write(efx, prt, dev, addr, new_val);
 583 }