2 * Standard Hot Plug Controller Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/sched.h> /* signal_pending(), struct timer_list */
36 #include <linux/mutex.h>
38 #include "pci_hotplug.h"
41 #define MY_NAME "shpchp"
43 #define MY_NAME THIS_MODULE->name
46 extern int shpchp_poll_mode
;
47 extern int shpchp_poll_time
;
48 extern int shpchp_debug
;
50 /*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
51 #define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
52 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
53 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
54 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
65 struct timer_list task_event
;
67 struct controller
*ctrl
;
68 struct hpc_ops
*hpc_ops
;
69 struct hotplug_slot
*hotplug_slot
;
70 struct list_head slot_list
;
79 struct list_head ctrl_list
;
80 struct mutex crit_sect
; /* critical section mutex */
81 struct mutex cmd_lock
; /* command lock */
82 struct php_ctlr_state_s
*hpc_ctlr_handle
; /* HPC controller handle */
83 int num_slots
; /* Number of slots on ctlr */
84 int slot_num_inc
; /* 1 or -1 */
85 struct pci_dev
*pci_dev
;
86 struct pci_bus
*pci_bus
;
87 struct event_info event_queue
[10];
88 struct list_head slot_list
;
89 struct hpc_ops
*hpc_ops
;
90 wait_queue_head_t queue
; /* sleep & wake process */
95 u8 slot_device_offset
;
97 u32 pcix_misc2_reg
; /* for amd pogo errata */
98 enum pci_bus_speed speed
;
99 u32 first_slot
; /* First physical slot number */
100 u8 slot_bus
; /* Bus where the slots handled by this controller sit */
102 unsigned long mmio_base
;
103 unsigned long mmio_size
;
104 volatile int cmd_busy
;
107 struct hotplug_params
{
114 /* Define AMD SHPC ID */
115 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
116 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
118 /* AMD PCIX bridge registers */
120 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
121 #define PCIX_MISCII_OFFSET 0x48
122 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
124 /* AMD PCIX_MISCII masks and offsets */
125 #define PERRNONFATALENABLE_MASK 0x00040000
126 #define PERRFATALENABLE_MASK 0x00080000
127 #define PERRFLOODENABLE_MASK 0x00100000
128 #define SERRNONFATALENABLE_MASK 0x00200000
129 #define SERRFATALENABLE_MASK 0x00400000
131 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
132 #define PERR_OBSERVED_MASK 0x00000001
134 /* AMD PCIX_MEM_BASE_LIMIT masks */
135 #define RSE_MASK 0x40000000
137 #define INT_BUTTON_IGNORE 0
138 #define INT_PRESENCE_ON 1
139 #define INT_PRESENCE_OFF 2
140 #define INT_SWITCH_CLOSE 3
141 #define INT_SWITCH_OPEN 4
142 #define INT_POWER_FAULT 5
143 #define INT_POWER_FAULT_CLEAR 6
144 #define INT_BUTTON_PRESS 7
145 #define INT_BUTTON_RELEASE 8
146 #define INT_BUTTON_CANCEL 9
148 #define STATIC_STATE 0
149 #define BLINKINGON_STATE 1
150 #define BLINKINGOFF_STATE 2
151 #define POWERON_STATE 3
152 #define POWEROFF_STATE 4
154 #define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
157 #define INTERLOCK_OPEN 0x00000002
158 #define ADD_NOT_SUPPORTED 0x00000003
159 #define CARD_FUNCTIONING 0x00000005
160 #define ADAPTER_NOT_SAME 0x00000006
161 #define NO_ADAPTER_PRESENT 0x00000009
162 #define NOT_ENOUGH_RESOURCES 0x0000000B
163 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
164 #define WRONG_BUS_FREQUENCY 0x0000000D
165 #define POWER_FAILURE 0x0000000E
167 #define REMOVE_NOT_SUPPORTED 0x00000003
169 #define DISABLE_CARD 1
174 #define msg_initialization_err "Initialization failure, error=%d\n"
175 #define msg_button_on "PCI slot #%d - powering on due to button press.\n"
176 #define msg_button_off "PCI slot #%d - powering off due to button press.\n"
177 #define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n"
179 /* sysfs functions for the hotplug controller info */
180 extern void shpchp_create_ctrl_files (struct controller
*ctrl
);
182 /* controller functions */
183 extern int shpchp_event_start_thread(void);
184 extern void shpchp_event_stop_thread(void);
185 extern int shpchp_enable_slot(struct slot
*slot
);
186 extern int shpchp_disable_slot(struct slot
*slot
);
188 extern u8
shpchp_handle_attention_button(u8 hp_slot
, void *inst_id
);
189 extern u8
shpchp_handle_switch_change(u8 hp_slot
, void *inst_id
);
190 extern u8
shpchp_handle_presence_change(u8 hp_slot
, void *inst_id
);
191 extern u8
shpchp_handle_power_fault(u8 hp_slot
, void *inst_id
);
194 extern int shpchp_save_config(struct controller
*ctrl
, int busnumber
, int num_ctlr_slots
, int first_device_num
);
195 extern int shpchp_configure_device(struct slot
*p_slot
);
196 extern int shpchp_unconfigure_device(struct slot
*p_slot
);
197 extern void get_hp_hw_control_from_firmware(struct pci_dev
*dev
);
198 extern void get_hp_params_from_firmware(struct pci_dev
*dev
,
199 struct hotplug_params
*hpp
);
200 extern int shpchprm_get_physical_slot_number(struct controller
*ctrl
,
201 u32
*sun
, u8 busnum
, u8 devnum
);
202 extern void shpchp_remove_ctrl_files(struct controller
*ctrl
);
205 /* Global variables */
206 extern struct list_head shpchp_ctrl_list
;
209 volatile u32 base_offset
;
210 volatile u32 slot_avail1
;
211 volatile u32 slot_avail2
;
212 volatile u32 slot_config
;
213 volatile u16 sec_bus_config
;
214 volatile u8 msi_ctrl
;
215 volatile u8 prog_interface
;
217 volatile u16 cmd_status
;
218 volatile u32 intr_loc
;
219 volatile u32 serr_loc
;
220 volatile u32 serr_intr_enable
;
233 } __attribute__ ((packed
));
235 /* offsets to the controller registers based on the above structure layout */
237 BASE_OFFSET
= offsetof(struct ctrl_reg
, base_offset
),
238 SLOT_AVAIL1
= offsetof(struct ctrl_reg
, slot_avail1
),
239 SLOT_AVAIL2
= offsetof(struct ctrl_reg
, slot_avail2
),
240 SLOT_CONFIG
= offsetof(struct ctrl_reg
, slot_config
),
241 SEC_BUS_CONFIG
= offsetof(struct ctrl_reg
, sec_bus_config
),
242 MSI_CTRL
= offsetof(struct ctrl_reg
, msi_ctrl
),
243 PROG_INTERFACE
= offsetof(struct ctrl_reg
, prog_interface
),
244 CMD
= offsetof(struct ctrl_reg
, cmd
),
245 CMD_STATUS
= offsetof(struct ctrl_reg
, cmd_status
),
246 INTR_LOC
= offsetof(struct ctrl_reg
, intr_loc
),
247 SERR_LOC
= offsetof(struct ctrl_reg
, serr_loc
),
248 SERR_INTR_ENABLE
= offsetof(struct ctrl_reg
, serr_intr_enable
),
249 SLOT1
= offsetof(struct ctrl_reg
, slot1
),
250 SLOT2
= offsetof(struct ctrl_reg
, slot2
),
251 SLOT3
= offsetof(struct ctrl_reg
, slot3
),
252 SLOT4
= offsetof(struct ctrl_reg
, slot4
),
253 SLOT5
= offsetof(struct ctrl_reg
, slot5
),
254 SLOT6
= offsetof(struct ctrl_reg
, slot6
),
255 SLOT7
= offsetof(struct ctrl_reg
, slot7
),
256 SLOT8
= offsetof(struct ctrl_reg
, slot8
),
257 SLOT9
= offsetof(struct ctrl_reg
, slot9
),
258 SLOT10
= offsetof(struct ctrl_reg
, slot10
),
259 SLOT11
= offsetof(struct ctrl_reg
, slot11
),
260 SLOT12
= offsetof(struct ctrl_reg
, slot12
),
262 typedef u8(*php_intr_callback_t
) (u8 hp_slot
, void *instance_id
);
263 struct php_ctlr_state_s
{
264 struct php_ctlr_state_s
*pnext
;
265 struct pci_dev
*pci_dev
;
267 unsigned long flags
; /* spinlock's */
268 u32 slot_device_offset
;
270 struct timer_list int_poll_timer
; /* Added for poll event */
271 php_intr_callback_t attention_button_callback
;
272 php_intr_callback_t switch_change_callback
;
273 php_intr_callback_t presence_change_callback
;
274 php_intr_callback_t power_fault_callback
;
275 void *callback_instance_id
;
276 void __iomem
*creg
; /* Ptr to controller register space */
278 /* Inline functions */
281 /* Inline functions to check the sanity of a pointer that is passed to us */
282 static inline int slot_paranoia_check (struct slot
*slot
, const char *function
)
285 dbg("%s - slot == NULL", function
);
288 if (!slot
->hotplug_slot
) {
289 dbg("%s - slot->hotplug_slot == NULL!", function
);
295 static inline struct slot
*get_slot (struct hotplug_slot
*hotplug_slot
, const char *function
)
300 dbg("%s - hotplug_slot == NULL\n", function
);
304 slot
= (struct slot
*)hotplug_slot
->private;
305 if (slot_paranoia_check (slot
, function
))
310 static inline struct slot
*shpchp_find_slot (struct controller
*ctrl
, u8 device
)
317 list_for_each_entry(slot
, &ctrl
->slot_list
, slot_list
) {
318 if (slot
->device
== device
)
322 err("%s: slot (device=0x%x) not found\n", __FUNCTION__
, device
);
327 static inline int wait_for_ctrl_irq (struct controller
*ctrl
)
329 DECLARE_WAITQUEUE(wait
, current
);
332 add_wait_queue(&ctrl
->queue
, &wait
);
334 if (!shpchp_poll_mode
) {
335 /* Sleep for up to 1 second */
336 msleep_interruptible(1000);
338 /* Sleep for up to 2 seconds */
339 msleep_interruptible(2000);
341 remove_wait_queue(&ctrl
->queue
, &wait
);
342 if (signal_pending(current
))
348 static inline void amd_pogo_errata_save_misc_reg(struct slot
*p_slot
)
352 /* save MiscII register */
353 pci_read_config_dword(p_slot
->ctrl
->pci_dev
, PCIX_MISCII_OFFSET
, &pcix_misc2_temp
);
355 p_slot
->ctrl
->pcix_misc2_reg
= pcix_misc2_temp
;
357 /* clear SERR/PERR enable bits */
358 pcix_misc2_temp
&= ~SERRFATALENABLE_MASK
;
359 pcix_misc2_temp
&= ~SERRNONFATALENABLE_MASK
;
360 pcix_misc2_temp
&= ~PERRFLOODENABLE_MASK
;
361 pcix_misc2_temp
&= ~PERRFATALENABLE_MASK
;
362 pcix_misc2_temp
&= ~PERRNONFATALENABLE_MASK
;
363 pci_write_config_dword(p_slot
->ctrl
->pci_dev
, PCIX_MISCII_OFFSET
, pcix_misc2_temp
);
366 static inline void amd_pogo_errata_restore_misc_reg(struct slot
*p_slot
)
369 u32 pcix_bridge_errors_reg
;
370 u32 pcix_mem_base_reg
;
374 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
375 pci_read_config_dword(p_slot
->ctrl
->pci_dev
, PCIX_MISC_BRIDGE_ERRORS_OFFSET
, &pcix_bridge_errors_reg
);
376 perr_set
= pcix_bridge_errors_reg
& PERR_OBSERVED_MASK
;
378 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__
, perr_set
);
380 pci_write_config_dword(p_slot
->ctrl
->pci_dev
, PCIX_MISC_BRIDGE_ERRORS_OFFSET
, perr_set
);
383 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
384 pci_read_config_dword(p_slot
->ctrl
->pci_dev
, PCIX_MEM_BASE_LIMIT_OFFSET
, &pcix_mem_base_reg
);
385 rse_set
= pcix_mem_base_reg
& RSE_MASK
;
387 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__
);
389 pci_write_config_dword(p_slot
->ctrl
->pci_dev
, PCIX_MEM_BASE_LIMIT_OFFSET
, rse_set
);
391 /* restore MiscII register */
392 pci_read_config_dword( p_slot
->ctrl
->pci_dev
, PCIX_MISCII_OFFSET
, &pcix_misc2_temp
);
394 if (p_slot
->ctrl
->pcix_misc2_reg
& SERRFATALENABLE_MASK
)
395 pcix_misc2_temp
|= SERRFATALENABLE_MASK
;
397 pcix_misc2_temp
&= ~SERRFATALENABLE_MASK
;
399 if (p_slot
->ctrl
->pcix_misc2_reg
& SERRNONFATALENABLE_MASK
)
400 pcix_misc2_temp
|= SERRNONFATALENABLE_MASK
;
402 pcix_misc2_temp
&= ~SERRNONFATALENABLE_MASK
;
404 if (p_slot
->ctrl
->pcix_misc2_reg
& PERRFLOODENABLE_MASK
)
405 pcix_misc2_temp
|= PERRFLOODENABLE_MASK
;
407 pcix_misc2_temp
&= ~PERRFLOODENABLE_MASK
;
409 if (p_slot
->ctrl
->pcix_misc2_reg
& PERRFATALENABLE_MASK
)
410 pcix_misc2_temp
|= PERRFATALENABLE_MASK
;
412 pcix_misc2_temp
&= ~PERRFATALENABLE_MASK
;
414 if (p_slot
->ctrl
->pcix_misc2_reg
& PERRNONFATALENABLE_MASK
)
415 pcix_misc2_temp
|= PERRNONFATALENABLE_MASK
;
417 pcix_misc2_temp
&= ~PERRNONFATALENABLE_MASK
;
418 pci_write_config_dword(p_slot
->ctrl
->pci_dev
, PCIX_MISCII_OFFSET
, pcix_misc2_temp
);
427 int shpc_init( struct controller
*ctrl
, struct pci_dev
*pdev
);
429 int shpc_get_ctlr_slot_config( struct controller
*ctrl
,
431 int *first_device_num
,
432 int *physical_slot_num
,
437 int (*power_on_slot
) (struct slot
*slot
);
438 int (*slot_enable
) (struct slot
*slot
);
439 int (*slot_disable
) (struct slot
*slot
);
440 int (*set_bus_speed_mode
) (struct slot
*slot
, enum pci_bus_speed speed
);
441 int (*get_power_status
) (struct slot
*slot
, u8
*status
);
442 int (*get_attention_status
) (struct slot
*slot
, u8
*status
);
443 int (*set_attention_status
) (struct slot
*slot
, u8 status
);
444 int (*get_latch_status
) (struct slot
*slot
, u8
*status
);
445 int (*get_adapter_status
) (struct slot
*slot
, u8
*status
);
447 int (*get_max_bus_speed
) (struct slot
*slot
, enum pci_bus_speed
*speed
);
448 int (*get_cur_bus_speed
) (struct slot
*slot
, enum pci_bus_speed
*speed
);
449 int (*get_adapter_speed
) (struct slot
*slot
, enum pci_bus_speed
*speed
);
450 int (*get_mode1_ECC_cap
) (struct slot
*slot
, u8
*mode
);
451 int (*get_prog_int
) (struct slot
*slot
, u8
*prog_int
);
453 int (*query_power_fault
) (struct slot
*slot
);
454 void (*green_led_on
) (struct slot
*slot
);
455 void (*green_led_off
) (struct slot
*slot
);
456 void (*green_led_blink
) (struct slot
*slot
);
457 void (*release_ctlr
) (struct controller
*ctrl
);
458 int (*check_cmd_status
) (struct controller
*ctrl
);
461 #endif /* _SHPCHP_H */